Maxim Integrated / Mbed OS MAX11410BOB_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester MAX11410 CmdLine USBDevice

Diff: MAX11410.h

Revision:
22:3e03687b7e95
Parent:
21:498357e216b0
Child:
23:e0c36767f98b
--- a/MAX11410.h	Thu Jul 25 02:48:42 2019 -0700
+++ b/MAX11410.h	Thu Jul 25 03:24:47 2019 -0700
@@ -1094,7 +1094,7 @@
     //----------------------------------------
     /// Write an 8-bit MAX11410 register
     ///
-    /// CMD_1xxx_xxx_REGISTER_READ bit is cleared 0.
+    /// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0.
     ///
     /// SPI 16-bit transfer
     ///
@@ -1108,7 +1108,7 @@
     //----------------------------------------
     /// Read an 8-bit MAX11410 register
     ///
-    /// CMD_1xxx_xxx_REGISTER_READ bit is set 1.
+    /// CMD_1aaa_aaaa_REGISTER_READ bit is set 1.
     ///
     /// SPI 16-bit transfer
     ///
@@ -1122,7 +1122,7 @@
     //----------------------------------------
     /// Write a 16-bit MAX11410 register
     ///
-    /// CMD_1xxx_xxx_REGISTER_READ bit is cleared 0.
+    /// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0.
     ///
     /// SPI 24-bit transfer
     ///
@@ -1136,7 +1136,7 @@
     //----------------------------------------
     /// Read a 16-bit MAX11410 register
     ///
-    /// CMD_1xxx_xxx_REGISTER_READ bit is set 1.
+    /// CMD_1aaa_aaaa_REGISTER_READ bit is set 1.
     ///
     /// SPI 24-bit transfer
     ///
@@ -1150,7 +1150,7 @@
     //----------------------------------------
     /// Write a 24-bit MAX11410 register
     ///
-    /// CMD_1xxx_xxx_REGISTER_READ bit is cleared 0.
+    /// CMD_1aaa_aaaa_REGISTER_READ bit is cleared 0.
     ///
     /// SPI 32-bit transfer
     ///
@@ -1164,7 +1164,7 @@
     //----------------------------------------
     /// Read a 24-bit MAX11410 register
     ///
-    /// CMD_1xxx_xxx_REGISTER_READ bit is set 1.
+    /// CMD_1aaa_aaaa_REGISTER_READ bit is set 1.
     ///
     /// SPI 32-bit transfer
     ///