Maxim Integrated / Mbed OS MAX11410BOB_Serial_Tester

Test program running on MAX32625MBED. Control through USB Serial commands using a terminal emulator such as teraterm or putty.

Dependencies:   MaximTinyTester MAX11410 CmdLine USBDevice

MAX11410.h@19:8f951e448ab1, 2019-07-24 (annotated)

Committer:
whismanoid
Date:
Wed Jul 24 23:16:08 2019 -0700
Revision:
19:8f951e448ab1
Child:
20:97dccb1c9b61
CodeGenerator MAX11410 WIP Configure_Voltage (not buildable yet)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 19:8f951e448ab1 1 // /*******************************************************************************
whismanoid 19:8f951e448ab1 2 // * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 19:8f951e448ab1 3 // *
whismanoid 19:8f951e448ab1 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 19:8f951e448ab1 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 19:8f951e448ab1 6 // * to deal in the Software without restriction, including without limitation
whismanoid 19:8f951e448ab1 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 19:8f951e448ab1 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 19:8f951e448ab1 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 19:8f951e448ab1 10 // *
whismanoid 19:8f951e448ab1 11 // * The above copyright notice and this permission notice shall be included
whismanoid 19:8f951e448ab1 12 // * in all copies or substantial portions of the Software.
whismanoid 19:8f951e448ab1 13 // *
whismanoid 19:8f951e448ab1 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 19:8f951e448ab1 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 19:8f951e448ab1 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 19:8f951e448ab1 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 19:8f951e448ab1 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 19:8f951e448ab1 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 19:8f951e448ab1 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 19:8f951e448ab1 21 // *
whismanoid 19:8f951e448ab1 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 19:8f951e448ab1 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 19:8f951e448ab1 24 // * Products, Inc. Branding Policy.
whismanoid 19:8f951e448ab1 25 // *
whismanoid 19:8f951e448ab1 26 // * The mere transfer of this software does not imply any licenses
whismanoid 19:8f951e448ab1 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 19:8f951e448ab1 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 19:8f951e448ab1 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 19:8f951e448ab1 30 // * ownership rights.
whismanoid 19:8f951e448ab1 31 // *******************************************************************************
whismanoid 19:8f951e448ab1 32 // */
whismanoid 19:8f951e448ab1 33 // *********************************************************************
whismanoid 19:8f951e448ab1 34 // @file MAX11410.h
whismanoid 19:8f951e448ab1 35 // *********************************************************************
whismanoid 19:8f951e448ab1 36 // Header file
whismanoid 19:8f951e448ab1 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 19:8f951e448ab1 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 19:8f951e448ab1 39 // System Name = ExampleSystem
whismanoid 19:8f951e448ab1 40 // System Description = Device driver example
whismanoid 19:8f951e448ab1 41 // Device Name = MAX11410
whismanoid 19:8f951e448ab1 42 // Device Description = 1.9ksps, Low-Power, Serial SPI 24-Bit, 10-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid 19:8f951e448ab1 43 // Device Manufacturer = Maxim Integrated
whismanoid 19:8f951e448ab1 44 // Device PartNumber = MAX11410ATI+
whismanoid 19:8f951e448ab1 45 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 19:8f951e448ab1 46 //
whismanoid 19:8f951e448ab1 47 // SPI CS = ActiveLow
whismanoid 19:8f951e448ab1 48 // SPI FrameStart = CS
whismanoid 19:8f951e448ab1 49 // SPI CPOL = 0
whismanoid 19:8f951e448ab1 50 // SPI CPHA = 0
whismanoid 19:8f951e448ab1 51 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 19:8f951e448ab1 52 // SPI SCLK Idle Low
whismanoid 19:8f951e448ab1 53 // SPI SCLKMaxMHz = 8
whismanoid 19:8f951e448ab1 54 // SPI SCLKMinMHz = 0
whismanoid 19:8f951e448ab1 55 //
whismanoid 19:8f951e448ab1 56
whismanoid 19:8f951e448ab1 57
whismanoid 19:8f951e448ab1 58 // Prevent multiple declaration
whismanoid 19:8f951e448ab1 59 #ifndef __MAX11410_H__
whismanoid 19:8f951e448ab1 60 #define __MAX11410_H__
whismanoid 19:8f951e448ab1 61
whismanoid 19:8f951e448ab1 62 // standard include for target platform
whismanoid 19:8f951e448ab1 63 #include "mbed.h"
whismanoid 19:8f951e448ab1 64
whismanoid 19:8f951e448ab1 65 // CODE GENERATOR: conditional defines
whismanoid 19:8f951e448ab1 66 // CODE GENERATOR: class declaration and docstrings
whismanoid 19:8f951e448ab1 67 /**
whismanoid 19:8f951e448ab1 68 * @brief MAX11410 1.9ksps, Low-Power, Serial SPI 24-Bit, 10-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid 19:8f951e448ab1 69 *
whismanoid 19:8f951e448ab1 70 *
whismanoid 19:8f951e448ab1 71 *
whismanoid 19:8f951e448ab1 72 * Datasheet: https://www.maximintegrated.com/MAX11410
whismanoid 19:8f951e448ab1 73 *
whismanoid 19:8f951e448ab1 74 *
whismanoid 19:8f951e448ab1 75 *
whismanoid 19:8f951e448ab1 76 * //---------- CODE GENERATOR: helloCppCodeList
whismanoid 19:8f951e448ab1 77 * @code
whismanoid 19:8f951e448ab1 78 * // CODE GENERATOR: example code includes
whismanoid 19:8f951e448ab1 79 * // example code includes
whismanoid 19:8f951e448ab1 80 * // standard include for target platform
whismanoid 19:8f951e448ab1 81 * #include "mbed.h"
whismanoid 19:8f951e448ab1 82 * //#include "max32625.h"
whismanoid 19:8f951e448ab1 83 * #include "MAX11410.h"
whismanoid 19:8f951e448ab1 84 *
whismanoid 19:8f951e448ab1 85 * // example code board support
whismanoid 19:8f951e448ab1 86 * //MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
whismanoid 19:8f951e448ab1 87 * //DigitalOut rLED(LED1);
whismanoid 19:8f951e448ab1 88 * //DigitalOut gLED(LED2);
whismanoid 19:8f951e448ab1 89 * //DigitalOut bLED(LED3);
whismanoid 19:8f951e448ab1 90 * //
whismanoid 19:8f951e448ab1 91 * // Arduino "shield" connector port definitions (MAX32625MBED shown)
whismanoid 19:8f951e448ab1 92 * #if defined(TARGET_MAX32625MBED)
whismanoid 19:8f951e448ab1 93 * #define A0 AIN_0
whismanoid 19:8f951e448ab1 94 * #define A1 AIN_1
whismanoid 19:8f951e448ab1 95 * #define A2 AIN_2
whismanoid 19:8f951e448ab1 96 * #define A3 AIN_3
whismanoid 19:8f951e448ab1 97 * #define D0 P0_0
whismanoid 19:8f951e448ab1 98 * #define D1 P0_1
whismanoid 19:8f951e448ab1 99 * #define D2 P0_2
whismanoid 19:8f951e448ab1 100 * #define D3 P0_3
whismanoid 19:8f951e448ab1 101 * #define D4 P0_4
whismanoid 19:8f951e448ab1 102 * #define D5 P0_5
whismanoid 19:8f951e448ab1 103 * #define D6 P0_6
whismanoid 19:8f951e448ab1 104 * #define D7 P0_7
whismanoid 19:8f951e448ab1 105 * #define D8 P1_4
whismanoid 19:8f951e448ab1 106 * #define D9 P1_5
whismanoid 19:8f951e448ab1 107 * #define D10 P1_3
whismanoid 19:8f951e448ab1 108 * #define D11 P1_1
whismanoid 19:8f951e448ab1 109 * #define D12 P1_2
whismanoid 19:8f951e448ab1 110 * #define D13 P1_0
whismanoid 19:8f951e448ab1 111 * #endif
whismanoid 19:8f951e448ab1 112 *
whismanoid 19:8f951e448ab1 113 * // example code declare SPI interface
whismanoid 19:8f951e448ab1 114 * #if defined(TARGET_MAX32625MBED)
whismanoid 19:8f951e448ab1 115 * SPI spi(SPI1_MOSI, SPI1_MISO, SPI1_SCK); // mosi, miso, sclk spi1 TARGET_MAX32625MBED: P1_1 P1_2 P1_0 Arduino 10-pin header D11 D12 D13
whismanoid 19:8f951e448ab1 116 * DigitalOut spi_cs(SPI1_SS); // TARGET_MAX32625MBED: P1_3 Arduino 10-pin header D10
whismanoid 19:8f951e448ab1 117 * #elif defined(TARGET_MAX32600MBED)
whismanoid 19:8f951e448ab1 118 * SPI spi(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13
whismanoid 19:8f951e448ab1 119 * DigitalOut spi_cs(SPI2_SS); // Generic: Arduino 10-pin header D10
whismanoid 19:8f951e448ab1 120 * #else
whismanoid 19:8f951e448ab1 121 * SPI spi(D11, D12, D13); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13
whismanoid 19:8f951e448ab1 122 * DigitalOut spi_cs(D10); // Generic: Arduino 10-pin header D10
whismanoid 19:8f951e448ab1 123 * #endif
whismanoid 19:8f951e448ab1 124 *
whismanoid 19:8f951e448ab1 125 * // example code declare GPIO interface pins
whismanoid 19:8f951e448ab1 126 * // example code declare device instance
whismanoid 19:8f951e448ab1 127 * MAX11410 g_MAX11410_device(spi, spi_cs, MAX11410::MAX11410_IC);
whismanoid 19:8f951e448ab1 128 *
whismanoid 19:8f951e448ab1 129 * // example code main function
whismanoid 19:8f951e448ab1 130 * int main()
whismanoid 19:8f951e448ab1 131 * {
whismanoid 19:8f951e448ab1 132 * while (1)
whismanoid 19:8f951e448ab1 133 * {
whismanoid 19:8f951e448ab1 134 * // CODE GENERATOR: example code: member function Init
whismanoid 19:8f951e448ab1 135 * g_MAX11410_device.Init();
whismanoid 19:8f951e448ab1 136 *
whismanoid 19:8f951e448ab1 137 * // CODE GENERATOR: example code: has no member function REF
whismanoid 19:8f951e448ab1 138 * // CODE GENERATOR: example code: has no member function CODE_LOAD
whismanoid 19:8f951e448ab1 139 * // CODE GENERATOR: example code: has no member function CODEallLOADall
whismanoid 19:8f951e448ab1 140 * // CODE GENERATOR: example code: has no member function CODEnLOADn
whismanoid 19:8f951e448ab1 141 * // CODE GENERATOR: example code: has no member function ScanManual
whismanoid 19:8f951e448ab1 142 * // CODE GENERATOR: example code: has no member function ReadAINcode
whismanoid 19:8f951e448ab1 143 * wait(3.0);
whismanoid 19:8f951e448ab1 144 * }
whismanoid 19:8f951e448ab1 145 * }
whismanoid 19:8f951e448ab1 146 * @endcode
whismanoid 19:8f951e448ab1 147 * //---------- CODE GENERATOR: end helloCppCodeList
whismanoid 19:8f951e448ab1 148 */
whismanoid 19:8f951e448ab1 149 class MAX11410 {
whismanoid 19:8f951e448ab1 150 public:
whismanoid 19:8f951e448ab1 151 // CODE GENERATOR: TypedefEnum EnumItem declarations
whismanoid 19:8f951e448ab1 152 // CODE GENERATOR: TypedefEnum MAX11410_CMD_enum_t
whismanoid 19:8f951e448ab1 153 //----------------------------------------
whismanoid 19:8f951e448ab1 154 /// Register Addresses
whismanoid 19:8f951e448ab1 155 ///
whismanoid 19:8f951e448ab1 156 /// Naming convention is CMD_bitstream_FUNCTION_NAME
whismanoid 19:8f951e448ab1 157 /// - r = read/write bit (1=read, 0=write)
whismanoid 19:8f951e448ab1 158 /// - xaaa_aaaa = 7-bit register address field
whismanoid 19:8f951e448ab1 159 /// - dddd_dddd = 8-bit register data field
whismanoid 19:8f951e448ab1 160 /// - dddd_dddd_dddd_dddd = 16-bit register data field
whismanoid 19:8f951e448ab1 161 /// - dddd_dddd_dddd_dddd_dddd_dddd = 24-bit register data field
whismanoid 19:8f951e448ab1 162 /// - xxxx = don't care
whismanoid 19:8f951e448ab1 163 typedef enum MAX11410_CMD_enum_t {
whismanoid 19:8f951e448ab1 164 CMD_r000_0000_xxxx_xxdd_PD = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 165 CMD_r000_0001_xddd_xxdd_CONV_START = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 166 CMD_r000_0010_xddd_dddd_SEQ_START = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 167 CMD_r000_0011_xxxx_xddd_CAL_START = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 168 CMD_r000_0100_dddd_xddd_GP0_CTRL = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 169 CMD_r000_0101_dddd_xddd_GP1_CTRL = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 170 CMD_r000_0110_xddd_xxdd_GP_CONV = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 171 CMD_r000_0111_xddd_dddd_GP_SEQ_ADDR = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 172 CMD_r000_1000_x0dd_dddd_FILTER = 0x08, //!< 8'b00001000
whismanoid 19:8f951e448ab1 173 CMD_r000_1001_dddd_dddd_CTRL = 0x09, //!< 8'b00001001
whismanoid 19:8f951e448ab1 174 CMD_r000_1010_dddd_dddd_SOURCE = 0x0a, //!< 8'b00001010
whismanoid 19:8f951e448ab1 175 CMD_r000_1011_dddd_dddd_MUX_CTRL0 = 0x0b, //!< 8'b00001011
whismanoid 19:8f951e448ab1 176 CMD_r000_1100_dddd_dddd_MUX_CTRL1 = 0x0c, //!< 8'b00001100
whismanoid 19:8f951e448ab1 177 CMD_r000_1101_dddd_dddd_MUX_CTRL2 = 0x0d, //!< 8'b00001101
whismanoid 19:8f951e448ab1 178 CMD_r000_1110_xxdd_xddd_PGA = 0x0e, //!< 8'b00001110
whismanoid 19:8f951e448ab1 179 CMD_r000_1111_dddd_dddd_WAIT_EXT = 0x0f, //!< 8'b00001111
whismanoid 19:8f951e448ab1 180 CMD_r001_0000_xxxx_xxxx_WAIT_START = 0x10, //!< 8'b00010000
whismanoid 19:8f951e448ab1 181 CMD_r001_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xddd_PART_ID = 0x11, //!< 8'b00010001
whismanoid 19:8f951e448ab1 182 CMD_r001_0010_xxxx_xxxx_dddd_xxdd_dddd_dddd_SYSC_SEL = 0x12, //!< 8'b00010010
whismanoid 19:8f951e448ab1 183 CMD_r001_0011_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_A = 0x13, //!< 8'b00010011
whismanoid 19:8f951e448ab1 184 CMD_r001_0100_dddd_dddd_dddd_dddd_dddd_dddd_SYS_OFF_B = 0x14, //!< 8'b00010100
whismanoid 19:8f951e448ab1 185 CMD_r001_0101_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_A = 0x15, //!< 8'b00010101
whismanoid 19:8f951e448ab1 186 CMD_r001_0110_dddd_dddd_dddd_dddd_dddd_dddd_SYS_GAIN_B = 0x16, //!< 8'b00010110
whismanoid 19:8f951e448ab1 187 CMD_r001_0111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_OFF = 0x17, //!< 8'b00010111
whismanoid 19:8f951e448ab1 188 CMD_r001_1000_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_1 = 0x18, //!< 8'b00011000
whismanoid 19:8f951e448ab1 189 CMD_r001_1001_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_2 = 0x19, //!< 8'b00011001
whismanoid 19:8f951e448ab1 190 CMD_r001_1010_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_4 = 0x1a, //!< 8'b00011010
whismanoid 19:8f951e448ab1 191 CMD_r001_1011_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_8 = 0x1b, //!< 8'b00011011
whismanoid 19:8f951e448ab1 192 CMD_r001_1100_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_16 = 0x1c, //!< 8'b00011100
whismanoid 19:8f951e448ab1 193 CMD_r001_1101_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_32 = 0x1d, //!< 8'b00011101
whismanoid 19:8f951e448ab1 194 CMD_r001_1110_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_64 = 0x1e, //!< 8'b00011110
whismanoid 19:8f951e448ab1 195 CMD_r001_1111_dddd_dddd_dddd_dddd_dddd_dddd_SELF_GAIN_128 = 0x1f, //!< 8'b00011111
whismanoid 19:8f951e448ab1 196 CMD_r010_0000_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH0 = 0x20, //!< 8'b00100000
whismanoid 19:8f951e448ab1 197 CMD_r010_0001_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH1 = 0x21, //!< 8'b00100001
whismanoid 19:8f951e448ab1 198 CMD_r010_0010_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH2 = 0x22, //!< 8'b00100010
whismanoid 19:8f951e448ab1 199 CMD_r010_0011_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH3 = 0x23, //!< 8'b00100011
whismanoid 19:8f951e448ab1 200 CMD_r010_0100_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH4 = 0x24, //!< 8'b00100100
whismanoid 19:8f951e448ab1 201 CMD_r010_0101_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH5 = 0x25, //!< 8'b00100101
whismanoid 19:8f951e448ab1 202 CMD_r010_0110_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH6 = 0x26, //!< 8'b00100110
whismanoid 19:8f951e448ab1 203 CMD_r010_0111_dddd_dddd_dddd_dddd_dddd_dddd_LTHRESH7 = 0x27, //!< 8'b00100111
whismanoid 19:8f951e448ab1 204 CMD_r010_1000_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH0 = 0x28, //!< 8'b00101000
whismanoid 19:8f951e448ab1 205 CMD_r010_1001_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH1 = 0x29, //!< 8'b00101001
whismanoid 19:8f951e448ab1 206 CMD_r010_1010_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH2 = 0x2a, //!< 8'b00101010
whismanoid 19:8f951e448ab1 207 CMD_r010_1011_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH3 = 0x2b, //!< 8'b00101011
whismanoid 19:8f951e448ab1 208 CMD_r010_1100_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH4 = 0x2c, //!< 8'b00101100
whismanoid 19:8f951e448ab1 209 CMD_r010_1101_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH5 = 0x2d, //!< 8'b00101101
whismanoid 19:8f951e448ab1 210 CMD_r010_1110_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH6 = 0x2e, //!< 8'b00101110
whismanoid 19:8f951e448ab1 211 CMD_r010_1111_dddd_dddd_dddd_dddd_dddd_dddd_UTHRESH7 = 0x2f, //!< 8'b00101111
whismanoid 19:8f951e448ab1 212 CMD_r011_0000_dddd_dddd_dddd_dddd_dddd_dddd_DATA0 = 0x30, //!< 8'b00110000
whismanoid 19:8f951e448ab1 213 CMD_r011_0001_dddd_dddd_dddd_dddd_dddd_dddd_DATA1 = 0x31, //!< 8'b00110001
whismanoid 19:8f951e448ab1 214 CMD_r011_0010_dddd_dddd_dddd_dddd_dddd_dddd_DATA2 = 0x32, //!< 8'b00110010
whismanoid 19:8f951e448ab1 215 CMD_r011_0011_dddd_dddd_dddd_dddd_dddd_dddd_DATA3 = 0x33, //!< 8'b00110011
whismanoid 19:8f951e448ab1 216 CMD_r011_0100_dddd_dddd_dddd_dddd_dddd_dddd_DATA4 = 0x34, //!< 8'b00110100
whismanoid 19:8f951e448ab1 217 CMD_r011_0101_dddd_dddd_dddd_dddd_dddd_dddd_DATA5 = 0x35, //!< 8'b00110101
whismanoid 19:8f951e448ab1 218 CMD_r011_0110_dddd_dddd_dddd_dddd_dddd_dddd_DATA6 = 0x36, //!< 8'b00110110
whismanoid 19:8f951e448ab1 219 CMD_r011_0111_dddd_dddd_dddd_dddd_dddd_dddd_DATA7 = 0x37, //!< 8'b00110111
whismanoid 19:8f951e448ab1 220 CMD_r011_1000_dddd_dddd_dddd_dddd_dxxx_dddd_STATUS = 0x38, //!< 8'b00111000
whismanoid 19:8f951e448ab1 221 CMD_r011_1001_dddd_dddd_dddd_dddd_dxxd_dddd_STATUS_IE = 0x39, //!< 8'b00111001
whismanoid 19:8f951e448ab1 222 CMD_r011_1010_xaaa_aaaa_dddd_dddd_UC_0 = 0x3a, //!< 8'b00111010
whismanoid 19:8f951e448ab1 223 CMD_r011_1011_xaaa_aaaa_dddd_dddd_UC_1 = 0x3b, //!< 8'b00111011
whismanoid 19:8f951e448ab1 224 CMD_r011_1100_xaaa_aaaa_dddd_dddd_UC_2 = 0x3c, //!< 8'b00111100
whismanoid 19:8f951e448ab1 225 CMD_r011_1101_xaaa_aaaa_dddd_dddd_UC_3 = 0x3d, //!< 8'b00111101
whismanoid 19:8f951e448ab1 226 CMD_r011_1110_xaaa_aaaa_dddd_dddd_UC_4 = 0x3e, //!< 8'b00111110
whismanoid 19:8f951e448ab1 227 CMD_r011_1111_xaaa_aaaa_dddd_dddd_UC_5 = 0x3f, //!< 8'b00111111
whismanoid 19:8f951e448ab1 228 CMD_r100_0000_xaaa_aaaa_dddd_dddd_UC_6 = 0x40, //!< 8'b01000000
whismanoid 19:8f951e448ab1 229 CMD_r100_0001_xaaa_aaaa_dddd_dddd_UC_7 = 0x41, //!< 8'b01000001
whismanoid 19:8f951e448ab1 230 CMD_r100_0010_xaaa_aaaa_dddd_dddd_UC_8 = 0x42, //!< 8'b01000010
whismanoid 19:8f951e448ab1 231 CMD_r100_0011_xaaa_aaaa_dddd_dddd_UC_9 = 0x43, //!< 8'b01000011
whismanoid 19:8f951e448ab1 232 CMD_r100_0100_xaaa_aaaa_dddd_dddd_UC_10 = 0x44, //!< 8'b01000100
whismanoid 19:8f951e448ab1 233 CMD_r100_0101_xaaa_aaaa_dddd_dddd_UC_11 = 0x45, //!< 8'b01000101
whismanoid 19:8f951e448ab1 234 CMD_r100_0110_xaaa_aaaa_dddd_dddd_UC_12 = 0x46, //!< 8'b01000110
whismanoid 19:8f951e448ab1 235 CMD_r100_0111_xaaa_aaaa_dddd_dddd_UC_13 = 0x47, //!< 8'b01000111
whismanoid 19:8f951e448ab1 236 CMD_r100_1000_xaaa_aaaa_dddd_dddd_UC_14 = 0x48, //!< 8'b01001000
whismanoid 19:8f951e448ab1 237 CMD_r100_1001_xaaa_aaaa_dddd_dddd_UC_15 = 0x49, //!< 8'b01001001
whismanoid 19:8f951e448ab1 238 CMD_r100_1010_xaaa_aaaa_dddd_dddd_UC_16 = 0x4a, //!< 8'b01001010
whismanoid 19:8f951e448ab1 239 CMD_r100_1011_xaaa_aaaa_dddd_dddd_UC_17 = 0x4b, //!< 8'b01001011
whismanoid 19:8f951e448ab1 240 CMD_r100_1100_xaaa_aaaa_dddd_dddd_UC_18 = 0x4c, //!< 8'b01001100
whismanoid 19:8f951e448ab1 241 CMD_r100_1101_xaaa_aaaa_dddd_dddd_UC_19 = 0x4d, //!< 8'b01001101
whismanoid 19:8f951e448ab1 242 CMD_r100_1110_xaaa_aaaa_dddd_dddd_UC_20 = 0x4e, //!< 8'b01001110
whismanoid 19:8f951e448ab1 243 CMD_r100_1111_xaaa_aaaa_dddd_dddd_UC_21 = 0x4f, //!< 8'b01001111
whismanoid 19:8f951e448ab1 244 CMD_r101_0000_xaaa_aaaa_dddd_dddd_UC_22 = 0x50, //!< 8'b01010000
whismanoid 19:8f951e448ab1 245 CMD_r101_0001_xaaa_aaaa_dddd_dddd_UC_23 = 0x51, //!< 8'b01010001
whismanoid 19:8f951e448ab1 246 CMD_r101_0010_xaaa_aaaa_dddd_dddd_UC_24 = 0x52, //!< 8'b01010010
whismanoid 19:8f951e448ab1 247 CMD_r101_0011_xaaa_aaaa_dddd_dddd_UC_25 = 0x53, //!< 8'b01010011
whismanoid 19:8f951e448ab1 248 CMD_r101_0100_xaaa_aaaa_dddd_dddd_UC_26 = 0x54, //!< 8'b01010100
whismanoid 19:8f951e448ab1 249 CMD_r101_0101_xaaa_aaaa_dddd_dddd_UC_27 = 0x55, //!< 8'b01010101
whismanoid 19:8f951e448ab1 250 CMD_r101_0110_xaaa_aaaa_dddd_dddd_UC_28 = 0x56, //!< 8'b01010110
whismanoid 19:8f951e448ab1 251 CMD_r101_0111_xaaa_aaaa_dddd_dddd_UC_29 = 0x57, //!< 8'b01010111
whismanoid 19:8f951e448ab1 252 CMD_r101_1000_xaaa_aaaa_dddd_dddd_UC_30 = 0x58, //!< 8'b01011000
whismanoid 19:8f951e448ab1 253 CMD_r101_1001_xaaa_aaaa_dddd_dddd_UC_31 = 0x59, //!< 8'b01011001
whismanoid 19:8f951e448ab1 254 CMD_r101_1010_xaaa_aaaa_dddd_dddd_UC_32 = 0x5a, //!< 8'b01011010
whismanoid 19:8f951e448ab1 255 CMD_r101_1011_xaaa_aaaa_dddd_dddd_UC_33 = 0x5b, //!< 8'b01011011
whismanoid 19:8f951e448ab1 256 CMD_r101_1100_xaaa_aaaa_dddd_dddd_UC_34 = 0x5c, //!< 8'b01011100
whismanoid 19:8f951e448ab1 257 CMD_r101_1101_xaaa_aaaa_dddd_dddd_UC_35 = 0x5d, //!< 8'b01011101
whismanoid 19:8f951e448ab1 258 CMD_r101_1110_xaaa_aaaa_dddd_dddd_UC_36 = 0x5e, //!< 8'b01011110
whismanoid 19:8f951e448ab1 259 CMD_r101_1111_xaaa_aaaa_dddd_dddd_UC_37 = 0x5f, //!< 8'b01011111
whismanoid 19:8f951e448ab1 260 CMD_r110_0000_xaaa_aaaa_dddd_dddd_UC_38 = 0x60, //!< 8'b01100000
whismanoid 19:8f951e448ab1 261 CMD_r110_0001_xaaa_aaaa_dddd_dddd_UC_39 = 0x61, //!< 8'b01100001
whismanoid 19:8f951e448ab1 262 CMD_r110_0010_xaaa_aaaa_dddd_dddd_UC_40 = 0x62, //!< 8'b01100010
whismanoid 19:8f951e448ab1 263 CMD_r110_0011_xaaa_aaaa_dddd_dddd_UC_41 = 0x63, //!< 8'b01100011
whismanoid 19:8f951e448ab1 264 CMD_r110_0100_xaaa_aaaa_dddd_dddd_UC_42 = 0x64, //!< 8'b01100100
whismanoid 19:8f951e448ab1 265 CMD_r110_0101_xaaa_aaaa_dddd_dddd_UC_43 = 0x65, //!< 8'b01100101
whismanoid 19:8f951e448ab1 266 CMD_r110_0110_xaaa_aaaa_dddd_dddd_UC_44 = 0x66, //!< 8'b01100110
whismanoid 19:8f951e448ab1 267 CMD_r110_0111_xaaa_aaaa_dddd_dddd_UC_45 = 0x67, //!< 8'b01100111
whismanoid 19:8f951e448ab1 268 CMD_r110_1000_xaaa_aaaa_dddd_dddd_UC_46 = 0x68, //!< 8'b01101000
whismanoid 19:8f951e448ab1 269 CMD_r110_1001_xaaa_aaaa_dddd_dddd_UC_47 = 0x69, //!< 8'b01101001
whismanoid 19:8f951e448ab1 270 CMD_r110_1010_xaaa_aaaa_dddd_dddd_UC_48 = 0x6a, //!< 8'b01101010
whismanoid 19:8f951e448ab1 271 CMD_r110_1011_xaaa_aaaa_dddd_dddd_UC_49 = 0x6b, //!< 8'b01101011
whismanoid 19:8f951e448ab1 272 CMD_r110_1100_xaaa_aaaa_dddd_dddd_UC_50 = 0x6c, //!< 8'b01101100
whismanoid 19:8f951e448ab1 273 CMD_r110_1101_xaaa_aaaa_dddd_dddd_UC_51 = 0x6d, //!< 8'b01101101
whismanoid 19:8f951e448ab1 274 CMD_r110_1110_xaaa_aaaa_dddd_dddd_UC_52 = 0x6e, //!< 8'b01101110
whismanoid 19:8f951e448ab1 275 CMD_r110_1111_xxxx_xxxx_xaaa_aaaa_UCADDR = 0x6f, //!< 8'b01101111
whismanoid 19:8f951e448ab1 276 CMD_1aaa_aaaa_REGISTER_READ = 0x80, //!< 8'b10000000
whismanoid 19:8f951e448ab1 277 } MAX11410_CMD_enum_t;
whismanoid 19:8f951e448ab1 278
whismanoid 19:8f951e448ab1 279 // CODE GENERATOR: TypedefEnum MAX11410_SEQ_ADDR_enum_t
whismanoid 19:8f951e448ab1 280 //----------------------------------------
whismanoid 19:8f951e448ab1 281 /// Microcode Sequencer Addresses.
whismanoid 19:8f951e448ab1 282 /// CMD_r000_0010_xddd_dddd_SEQ_START
whismanoid 19:8f951e448ab1 283 /// CMD_r000_0111_xddd_dddd_GP_SEQ_ADDR
whismanoid 19:8f951e448ab1 284 ///
whismanoid 19:8f951e448ab1 285 /// Naming convention is CMD_bitstream_FUNCTION_NAME
whismanoid 19:8f951e448ab1 286 /// - xaaa_aaaa = 7-bit register address field
whismanoid 19:8f951e448ab1 287 /// - dddd_dddd = 8-bit register data field
whismanoid 19:8f951e448ab1 288 /// - xxxx = don't care
whismanoid 19:8f951e448ab1 289 typedef enum MAX11410_SEQ_ADDR_enum_t {
whismanoid 19:8f951e448ab1 290 SEQ_ADDR_r011_1010_xaaa_aaaa_dddd_dddd_UC_0 = 0x3a, //!< 8'b00111010
whismanoid 19:8f951e448ab1 291 SEQ_ADDR_r011_1011_xaaa_aaaa_dddd_dddd_UC_1 = 0x3b, //!< 8'b00111011
whismanoid 19:8f951e448ab1 292 SEQ_ADDR_r011_1100_xaaa_aaaa_dddd_dddd_UC_2 = 0x3c, //!< 8'b00111100
whismanoid 19:8f951e448ab1 293 SEQ_ADDR_r011_1101_xaaa_aaaa_dddd_dddd_UC_3 = 0x3d, //!< 8'b00111101
whismanoid 19:8f951e448ab1 294 SEQ_ADDR_r011_1110_xaaa_aaaa_dddd_dddd_UC_4 = 0x3e, //!< 8'b00111110
whismanoid 19:8f951e448ab1 295 SEQ_ADDR_r011_1111_xaaa_aaaa_dddd_dddd_UC_5 = 0x3f, //!< 8'b00111111
whismanoid 19:8f951e448ab1 296 SEQ_ADDR_r100_0000_xaaa_aaaa_dddd_dddd_UC_6 = 0x40, //!< 8'b01000000
whismanoid 19:8f951e448ab1 297 SEQ_ADDR_r100_0001_xaaa_aaaa_dddd_dddd_UC_7 = 0x41, //!< 8'b01000001
whismanoid 19:8f951e448ab1 298 SEQ_ADDR_r100_0010_xaaa_aaaa_dddd_dddd_UC_8 = 0x42, //!< 8'b01000010
whismanoid 19:8f951e448ab1 299 SEQ_ADDR_r100_0011_xaaa_aaaa_dddd_dddd_UC_9 = 0x43, //!< 8'b01000011
whismanoid 19:8f951e448ab1 300 SEQ_ADDR_r100_0100_xaaa_aaaa_dddd_dddd_UC_10 = 0x44, //!< 8'b01000100
whismanoid 19:8f951e448ab1 301 SEQ_ADDR_r100_0101_xaaa_aaaa_dddd_dddd_UC_11 = 0x45, //!< 8'b01000101
whismanoid 19:8f951e448ab1 302 SEQ_ADDR_r100_0110_xaaa_aaaa_dddd_dddd_UC_12 = 0x46, //!< 8'b01000110
whismanoid 19:8f951e448ab1 303 SEQ_ADDR_r100_0111_xaaa_aaaa_dddd_dddd_UC_13 = 0x47, //!< 8'b01000111
whismanoid 19:8f951e448ab1 304 SEQ_ADDR_r100_1000_xaaa_aaaa_dddd_dddd_UC_14 = 0x48, //!< 8'b01001000
whismanoid 19:8f951e448ab1 305 SEQ_ADDR_r100_1001_xaaa_aaaa_dddd_dddd_UC_15 = 0x49, //!< 8'b01001001
whismanoid 19:8f951e448ab1 306 SEQ_ADDR_r100_1010_xaaa_aaaa_dddd_dddd_UC_16 = 0x4a, //!< 8'b01001010
whismanoid 19:8f951e448ab1 307 SEQ_ADDR_r100_1011_xaaa_aaaa_dddd_dddd_UC_17 = 0x4b, //!< 8'b01001011
whismanoid 19:8f951e448ab1 308 SEQ_ADDR_r100_1100_xaaa_aaaa_dddd_dddd_UC_18 = 0x4c, //!< 8'b01001100
whismanoid 19:8f951e448ab1 309 SEQ_ADDR_r100_1101_xaaa_aaaa_dddd_dddd_UC_19 = 0x4d, //!< 8'b01001101
whismanoid 19:8f951e448ab1 310 SEQ_ADDR_r100_1110_xaaa_aaaa_dddd_dddd_UC_20 = 0x4e, //!< 8'b01001110
whismanoid 19:8f951e448ab1 311 SEQ_ADDR_r100_1111_xaaa_aaaa_dddd_dddd_UC_21 = 0x4f, //!< 8'b01001111
whismanoid 19:8f951e448ab1 312 SEQ_ADDR_r101_0000_xaaa_aaaa_dddd_dddd_UC_22 = 0x50, //!< 8'b01010000
whismanoid 19:8f951e448ab1 313 SEQ_ADDR_r101_0001_xaaa_aaaa_dddd_dddd_UC_23 = 0x51, //!< 8'b01010001
whismanoid 19:8f951e448ab1 314 SEQ_ADDR_r101_0010_xaaa_aaaa_dddd_dddd_UC_24 = 0x52, //!< 8'b01010010
whismanoid 19:8f951e448ab1 315 SEQ_ADDR_r101_0011_xaaa_aaaa_dddd_dddd_UC_25 = 0x53, //!< 8'b01010011
whismanoid 19:8f951e448ab1 316 SEQ_ADDR_r101_0100_xaaa_aaaa_dddd_dddd_UC_26 = 0x54, //!< 8'b01010100
whismanoid 19:8f951e448ab1 317 SEQ_ADDR_r101_0101_xaaa_aaaa_dddd_dddd_UC_27 = 0x55, //!< 8'b01010101
whismanoid 19:8f951e448ab1 318 SEQ_ADDR_r101_0110_xaaa_aaaa_dddd_dddd_UC_28 = 0x56, //!< 8'b01010110
whismanoid 19:8f951e448ab1 319 SEQ_ADDR_r101_0111_xaaa_aaaa_dddd_dddd_UC_29 = 0x57, //!< 8'b01010111
whismanoid 19:8f951e448ab1 320 SEQ_ADDR_r101_1000_xaaa_aaaa_dddd_dddd_UC_30 = 0x58, //!< 8'b01011000
whismanoid 19:8f951e448ab1 321 SEQ_ADDR_r101_1001_xaaa_aaaa_dddd_dddd_UC_31 = 0x59, //!< 8'b01011001
whismanoid 19:8f951e448ab1 322 SEQ_ADDR_r101_1010_xaaa_aaaa_dddd_dddd_UC_32 = 0x5a, //!< 8'b01011010
whismanoid 19:8f951e448ab1 323 SEQ_ADDR_r101_1011_xaaa_aaaa_dddd_dddd_UC_33 = 0x5b, //!< 8'b01011011
whismanoid 19:8f951e448ab1 324 SEQ_ADDR_r101_1100_xaaa_aaaa_dddd_dddd_UC_34 = 0x5c, //!< 8'b01011100
whismanoid 19:8f951e448ab1 325 SEQ_ADDR_r101_1101_xaaa_aaaa_dddd_dddd_UC_35 = 0x5d, //!< 8'b01011101
whismanoid 19:8f951e448ab1 326 SEQ_ADDR_r101_1110_xaaa_aaaa_dddd_dddd_UC_36 = 0x5e, //!< 8'b01011110
whismanoid 19:8f951e448ab1 327 SEQ_ADDR_r101_1111_xaaa_aaaa_dddd_dddd_UC_37 = 0x5f, //!< 8'b01011111
whismanoid 19:8f951e448ab1 328 SEQ_ADDR_r110_0000_xaaa_aaaa_dddd_dddd_UC_38 = 0x60, //!< 8'b01100000
whismanoid 19:8f951e448ab1 329 SEQ_ADDR_r110_0001_xaaa_aaaa_dddd_dddd_UC_39 = 0x61, //!< 8'b01100001
whismanoid 19:8f951e448ab1 330 SEQ_ADDR_r110_0010_xaaa_aaaa_dddd_dddd_UC_40 = 0x62, //!< 8'b01100010
whismanoid 19:8f951e448ab1 331 SEQ_ADDR_r110_0011_xaaa_aaaa_dddd_dddd_UC_41 = 0x63, //!< 8'b01100011
whismanoid 19:8f951e448ab1 332 SEQ_ADDR_r110_0100_xaaa_aaaa_dddd_dddd_UC_42 = 0x64, //!< 8'b01100100
whismanoid 19:8f951e448ab1 333 SEQ_ADDR_r110_0101_xaaa_aaaa_dddd_dddd_UC_43 = 0x65, //!< 8'b01100101
whismanoid 19:8f951e448ab1 334 SEQ_ADDR_r110_0110_xaaa_aaaa_dddd_dddd_UC_44 = 0x66, //!< 8'b01100110
whismanoid 19:8f951e448ab1 335 SEQ_ADDR_r110_0111_xaaa_aaaa_dddd_dddd_UC_45 = 0x67, //!< 8'b01100111
whismanoid 19:8f951e448ab1 336 SEQ_ADDR_r110_1000_xaaa_aaaa_dddd_dddd_UC_46 = 0x68, //!< 8'b01101000
whismanoid 19:8f951e448ab1 337 SEQ_ADDR_r110_1001_xaaa_aaaa_dddd_dddd_UC_47 = 0x69, //!< 8'b01101001
whismanoid 19:8f951e448ab1 338 SEQ_ADDR_r110_1010_xaaa_aaaa_dddd_dddd_UC_48 = 0x6a, //!< 8'b01101010
whismanoid 19:8f951e448ab1 339 SEQ_ADDR_r110_1011_xaaa_aaaa_dddd_dddd_UC_49 = 0x6b, //!< 8'b01101011
whismanoid 19:8f951e448ab1 340 SEQ_ADDR_r110_1100_xaaa_aaaa_dddd_dddd_UC_50 = 0x6c, //!< 8'b01101100
whismanoid 19:8f951e448ab1 341 SEQ_ADDR_r110_1101_xaaa_aaaa_dddd_dddd_UC_51 = 0x6d, //!< 8'b01101101
whismanoid 19:8f951e448ab1 342 SEQ_ADDR_r110_1110_xaaa_aaaa_dddd_dddd_UC_52 = 0x6e, //!< 8'b01101110
whismanoid 19:8f951e448ab1 343 } MAX11410_SEQ_ADDR_enum_t;
whismanoid 19:8f951e448ab1 344
whismanoid 19:8f951e448ab1 345 // CODE GENERATOR: TypedefEnum MAX11410_PD_enum_t
whismanoid 19:8f951e448ab1 346 //----------------------------------------
whismanoid 19:8f951e448ab1 347 /// Power-down state command
whismanoid 19:8f951e448ab1 348 /// CMD_r000_0000_xxxx_xxdd_PD PD[1:0] field
whismanoid 19:8f951e448ab1 349 ///
whismanoid 19:8f951e448ab1 350 /// - 00: Normal mode
whismanoid 19:8f951e448ab1 351 /// - 01: Standby mode -- Powers down all analog circuity, but not the internal voltage regulator
whismanoid 19:8f951e448ab1 352 /// - 10: Sleep mode -- Powers down all analog circuitry including the internal voltage regulator
whismanoid 19:8f951e448ab1 353 /// - 11: Reset -- all registers reset to POR state (Self Clearing to 01 Standby mode)
whismanoid 19:8f951e448ab1 354 typedef enum MAX11410_PD_enum_t {
whismanoid 19:8f951e448ab1 355 PD_00_Normal = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 356 PD_01_Standby = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 357 PD_10_Sleep = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 358 PD_11_Reset = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 359 } MAX11410_PD_enum_t;
whismanoid 19:8f951e448ab1 360
whismanoid 19:8f951e448ab1 361 // CODE GENERATOR: TypedefEnum MAX11410_DEST_enum_t
whismanoid 19:8f951e448ab1 362 //----------------------------------------
whismanoid 19:8f951e448ab1 363 /// Conversion / seqeuncer start command
whismanoid 19:8f951e448ab1 364 /// CMD_r000_0001_xddd_xxdd_CONV_START DEST[2:0] field.
whismanoid 19:8f951e448ab1 365 /// CMD_r000_0110_xddd_xxdd_GP_CONV GP_DEST[2:0] field.
whismanoid 19:8f951e448ab1 366 ///
whismanoid 19:8f951e448ab1 367 /// - 000: Store result in DATA0
whismanoid 19:8f951e448ab1 368 /// - 001: Store result in DATA1
whismanoid 19:8f951e448ab1 369 /// - 010: Store result in DATA2
whismanoid 19:8f951e448ab1 370 /// - 011: Store result in DATA3
whismanoid 19:8f951e448ab1 371 /// - 100: Store result in DATA4
whismanoid 19:8f951e448ab1 372 /// - 101: Store result in DATA5
whismanoid 19:8f951e448ab1 373 /// - 110: Store result in DATA6
whismanoid 19:8f951e448ab1 374 /// - 111: Store result in DATA7
whismanoid 19:8f951e448ab1 375 typedef enum MAX11410_DEST_enum_t {
whismanoid 19:8f951e448ab1 376 DEST_000_DATA0 = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 377 DEST_001_DATA1 = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 378 DEST_010_DATA2 = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 379 DEST_011_DATA3 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 380 DEST_100_DATA4 = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 381 DEST_101_DATA5 = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 382 DEST_110_DATA6 = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 383 DEST_111_DATA7 = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 384 } MAX11410_DEST_enum_t;
whismanoid 19:8f951e448ab1 385
whismanoid 19:8f951e448ab1 386 // CODE GENERATOR: TypedefEnum MAX11410_CONV_TYPE_enum_t
whismanoid 19:8f951e448ab1 387 //----------------------------------------
whismanoid 19:8f951e448ab1 388 /// Conversion / seqeuncer start command
whismanoid 19:8f951e448ab1 389 /// CMD_r000_0001_xddd_xxdd_CONV_START CONV_TYPE[1:0] field.
whismanoid 19:8f951e448ab1 390 /// CMD_r000_0110_xddd_xxdd_GP_CONV GP_CONV_TYPE[2:0] field.
whismanoid 19:8f951e448ab1 391 ///
whismanoid 19:8f951e448ab1 392 /// - 00: Single conversion
whismanoid 19:8f951e448ab1 393 /// - 01: Continuous conversions
whismanoid 19:8f951e448ab1 394 /// - 10, 11: 1:4 Duty cycled conversions (modulator low-power mode)
whismanoid 19:8f951e448ab1 395 typedef enum MAX11410_CONV_TYPE_enum_t {
whismanoid 19:8f951e448ab1 396 CONV_TYPE_00_Single = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 397 CONV_TYPE_01_Continuous = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 398 CONV_TYPE_10_DutyCycle_1_4 = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 399 CONV_TYPE_11_DutyCycle_1_4 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 400 } MAX11410_CONV_TYPE_enum_t;
whismanoid 19:8f951e448ab1 401
whismanoid 19:8f951e448ab1 402 // CODE GENERATOR: TypedefEnum MAX11410_CAL_TYPE_enum_t
whismanoid 19:8f951e448ab1 403 //----------------------------------------
whismanoid 19:8f951e448ab1 404 /// Calbration command
whismanoid 19:8f951e448ab1 405 /// CMD_r000_0011_xxxx_xddd_CAL_START CAL_TYPE[2:0] field
whismanoid 19:8f951e448ab1 406 ///
whismanoid 19:8f951e448ab1 407 /// - 000: Performs a self-calibration. Resulting offset calibration value is stored in the SELF_OFF register, and the 1x gain calibration value is stored in the SELF_GAIN_1 register.
whismanoid 19:8f951e448ab1 408 /// - 001: Performs a PGA gain calibration at the currently programmed PGA gain. A 'No Op' will result if PGA Gain calibration is executed with the PGA disabled via the SIG_PATH register, or with the GAIN register set to 1x.The resulting gain calibration value is stored in the SELF_GAIN_[2-128] register corresponding to the currently programmed PGA GAIN setting.
whismanoid 19:8f951e448ab1 409 /// - 010: Reserved
whismanoid 19:8f951e448ab1 410 /// - 011: Reserved
whismanoid 19:8f951e448ab1 411 /// - 100: Performs a system offset calibration. The resulting calibration value is stored in the SYS_OFF_A register.
whismanoid 19:8f951e448ab1 412 /// - 101: Performs a system gain calibration. The resulting calibration value is stored in the SYS_GAIN_A register.
whismanoid 19:8f951e448ab1 413 /// - 110: Performs a system offset calibration. The resulting calibration value is stored in the SYS_OFF_B register.
whismanoid 19:8f951e448ab1 414 /// - 111: Performs a system gain calibration. The resulting calibration value is stored in the SYS_GAIN_B register.
whismanoid 19:8f951e448ab1 415 typedef enum MAX11410_CAL_TYPE_enum_t {
whismanoid 19:8f951e448ab1 416 CAL_TYPE_000_SELF_CAL = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 417 CAL_TYPE_001_PGA_GAIN = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 418 CAL_TYPE_010_reserved = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 419 CAL_TYPE_011_reserved = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 420 CAL_TYPE_100_SYS_OFF_A = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 421 CAL_TYPE_101_SYS_GAIN_A = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 422 CAL_TYPE_110_SYS_OFF_B = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 423 CAL_TYPE_111_SYS_GAIN_B = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 424 } MAX11410_CAL_TYPE_enum_t;
whismanoid 19:8f951e448ab1 425
whismanoid 19:8f951e448ab1 426 // CODE GENERATOR: TypedefEnum MAX11410_GP0_DIR_enum_t
whismanoid 19:8f951e448ab1 427 //----------------------------------------
whismanoid 19:8f951e448ab1 428 /// GPIO0 pin command
whismanoid 19:8f951e448ab1 429 /// CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_DIR[1:0] field
whismanoid 19:8f951e448ab1 430 ///
whismanoid 19:8f951e448ab1 431 /// - 00: Input mode, reference to VDDIO (default)
whismanoid 19:8f951e448ab1 432 /// - 01: Reserved
whismanoid 19:8f951e448ab1 433 /// - 10: Output mode, open-drain output
whismanoid 19:8f951e448ab1 434 /// - 11: Output mode, CMOS output
whismanoid 19:8f951e448ab1 435 typedef enum MAX11410_GP0_DIR_enum_t {
whismanoid 19:8f951e448ab1 436 GP0_DIR_000_Input = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 437 GP0_DIR_001_reserved = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 438 GP0_DIR_010_OutputOpenDrain = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 439 GP0_DIR_011_Output = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 440 } MAX11410_GP0_DIR_enum_t;
whismanoid 19:8f951e448ab1 441
whismanoid 19:8f951e448ab1 442 // CODE GENERATOR: TypedefEnum MAX11410_GP0_ISEL_enum_t
whismanoid 19:8f951e448ab1 443 //----------------------------------------
whismanoid 19:8f951e448ab1 444 /// GPIO0 pin command
whismanoid 19:8f951e448ab1 445 /// CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_ISEL[1:0] field
whismanoid 19:8f951e448ab1 446 ///
whismanoid 19:8f951e448ab1 447 /// - 00: GPIO_0 input disabled (default)
whismanoid 19:8f951e448ab1 448 /// - 01: GPIO_0 input configured as rising-edge-triggered conversion start
whismanoid 19:8f951e448ab1 449 /// - 10: GPIO_0 input configured as rising-edge-triggered sequence start from GP_SEQ_ADDR
whismanoid 19:8f951e448ab1 450 /// - 11: Reserved
whismanoid 19:8f951e448ab1 451 typedef enum MAX11410_GP0_ISEL_enum_t {
whismanoid 19:8f951e448ab1 452 GP0_ISEL_000_disabled = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 453 GP0_ISEL_001_TRIGGER_CONV_START = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 454 GP0_ISEL_010_TRIGGER_SEQ_START = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 455 GP0_ISEL_011_reserved = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 456 } MAX11410_GP0_ISEL_enum_t;
whismanoid 19:8f951e448ab1 457
whismanoid 19:8f951e448ab1 458 // CODE GENERATOR: TypedefEnum MAX11410_GP0_OSEL_enum_t
whismanoid 19:8f951e448ab1 459 //----------------------------------------
whismanoid 19:8f951e448ab1 460 /// GPIO0 pin command
whismanoid 19:8f951e448ab1 461 /// CMD_r000_0100_dddd_xddd_GP0_CTRL GP0_OSEL[2:0] field
whismanoid 19:8f951e448ab1 462 ///
whismanoid 19:8f951e448ab1 463 /// - 000: GPIO_0 output disabled, high Z (default)
whismanoid 19:8f951e448ab1 464 /// - 001: GPIO_0 output is configured as INTRB (active low)
whismanoid 19:8f951e448ab1 465 /// - 010: GPIO_0 output is configured as INTR (active high)
whismanoid 19:8f951e448ab1 466 /// - 011: GPIO_0 output is configured as state Logic 0
whismanoid 19:8f951e448ab1 467 /// - 100: GPIO_0 output is configured as state Logic 1
whismanoid 19:8f951e448ab1 468 /// - 101: GPIO_0 output is configured as automatic low-side switch operation (CMOS output mode overridden)
whismanoid 19:8f951e448ab1 469 /// - 110: GPIO_0 output is configured as modulator active status
whismanoid 19:8f951e448ab1 470 /// - 111: GPIO_0 output is configured as system clock (2.456Mhz Nominal)
whismanoid 19:8f951e448ab1 471 typedef enum MAX11410_GP0_OSEL_enum_t {
whismanoid 19:8f951e448ab1 472 GP0_OSEL_000_disabled = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 473 GP0_OSEL_001_INTRB = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 474 GP0_OSEL_010_INTR = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 475 GP0_OSEL_011_LOGIC_0 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 476 GP0_OSEL_100_LOGIC_1 = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 477 GP0_OSEL_101_AUTO_LOWSIDE_SWITCH = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 478 GP0_OSEL_110_MODULATOR_ACTIVE_STATUS = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 479 GP0_OSEL_111_CLOCK_2M456 = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 480 } MAX11410_GP0_OSEL_enum_t;
whismanoid 19:8f951e448ab1 481
whismanoid 19:8f951e448ab1 482 // CODE GENERATOR: TypedefEnum MAX11410_GP1_DIR_enum_t
whismanoid 19:8f951e448ab1 483 //----------------------------------------
whismanoid 19:8f951e448ab1 484 /// GPIO1 pin command
whismanoid 19:8f951e448ab1 485 /// CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_DIR[1:0] field
whismanoid 19:8f951e448ab1 486 ///
whismanoid 19:8f951e448ab1 487 /// - 00: Input mode, reference to VDDIO (default)
whismanoid 19:8f951e448ab1 488 /// - 01: Reserved
whismanoid 19:8f951e448ab1 489 /// - 10: Output mode, open-drain output
whismanoid 19:8f951e448ab1 490 /// - 11: Output mode, CMOS output
whismanoid 19:8f951e448ab1 491 typedef enum MAX11410_GP1_DIR_enum_t {
whismanoid 19:8f951e448ab1 492 GP1_DIR_000_Input = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 493 GP1_DIR_001_reserved = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 494 GP1_DIR_010_OutputOpenDrain = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 495 GP1_DIR_011_Output = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 496 } MAX11410_GP1_DIR_enum_t;
whismanoid 19:8f951e448ab1 497
whismanoid 19:8f951e448ab1 498 // CODE GENERATOR: TypedefEnum MAX11410_GP1_ISEL_enum_t
whismanoid 19:8f951e448ab1 499 //----------------------------------------
whismanoid 19:8f951e448ab1 500 /// GPIO1 pin command
whismanoid 19:8f951e448ab1 501 /// CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_ISEL[1:0] field
whismanoid 19:8f951e448ab1 502 ///
whismanoid 19:8f951e448ab1 503 /// - 00: GPIO_1 input disabled (default)
whismanoid 19:8f951e448ab1 504 /// - 01: GPIO_1 input configured as rising-edge-triggered conversion start
whismanoid 19:8f951e448ab1 505 /// - 10: GPIO_1 input configured as rising-edge-triggered sequence start from GP_SEQ_ADDR
whismanoid 19:8f951e448ab1 506 /// - 11: Reserved
whismanoid 19:8f951e448ab1 507 typedef enum MAX11410_GP1_ISEL_enum_t {
whismanoid 19:8f951e448ab1 508 GP1_ISEL_000_disabled = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 509 GP1_ISEL_001_TRIGGER_CONV_START = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 510 GP1_ISEL_010_TRIGGER_SEQ_START = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 511 GP1_ISEL_011_reserved = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 512 } MAX11410_GP1_ISEL_enum_t;
whismanoid 19:8f951e448ab1 513
whismanoid 19:8f951e448ab1 514 // CODE GENERATOR: TypedefEnum MAX11410_GP1_OSEL_enum_t
whismanoid 19:8f951e448ab1 515 //----------------------------------------
whismanoid 19:8f951e448ab1 516 /// GPIO1 pin command
whismanoid 19:8f951e448ab1 517 /// CMD_r000_0101_dddd_xddd_GP1_CTRL GP1_OSEL[2:0] field
whismanoid 19:8f951e448ab1 518 ///
whismanoid 19:8f951e448ab1 519 /// - 000: GPIO_1 output disabled, high Z (default)
whismanoid 19:8f951e448ab1 520 /// - 001: GPIO_1 output is configured as INTRB (active low)
whismanoid 19:8f951e448ab1 521 /// - 010: GPIO_1 output is configured as INTR (active high)
whismanoid 19:8f951e448ab1 522 /// - 011: GPIO_1 output is configured as state Logic 0
whismanoid 19:8f951e448ab1 523 /// - 100: GPIO_1 output is configured as state Logic 1
whismanoid 19:8f951e448ab1 524 /// - 101: GPIO_1 output is configured as system clock (2.456Mhz Nominal)
whismanoid 19:8f951e448ab1 525 /// - 110: GPIO_1 output is configured as modulator active status
whismanoid 19:8f951e448ab1 526 /// - 111: GPIO_1 output is configured as automatic low-side switch operation (CMOS output mode overridden)
whismanoid 19:8f951e448ab1 527 typedef enum MAX11410_GP1_OSEL_enum_t {
whismanoid 19:8f951e448ab1 528 GP1_OSEL_000_disabled = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 529 GP1_OSEL_001_INTRB = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 530 GP1_OSEL_010_INTR = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 531 GP1_OSEL_011_LOGIC_0 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 532 GP1_OSEL_100_LOGIC_1 = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 533 GP1_OSEL_101_AUTO_LOWSIDE_SWITCH = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 534 GP1_OSEL_110_MODULATOR_ACTIVE_STATUS = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 535 GP1_OSEL_111_CLOCK_2M456 = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 536 } MAX11410_GP1_OSEL_enum_t;
whismanoid 19:8f951e448ab1 537
whismanoid 19:8f951e448ab1 538 // CODE GENERATOR: TypedefEnum MAX11410_LINEF_enum_t
whismanoid 19:8f951e448ab1 539 //----------------------------------------
whismanoid 19:8f951e448ab1 540 /// Filter command
whismanoid 19:8f951e448ab1 541 /// CMD_r000_1000_x0dd_dddd_FILTER LINEF[1:0] field
whismanoid 19:8f951e448ab1 542 ///
whismanoid 19:8f951e448ab1 543 /// - 00: Simultaneous 50/60Hz FIR rejection (default)
whismanoid 19:8f951e448ab1 544 /// - 01: 50Hz FIR rejection
whismanoid 19:8f951e448ab1 545 /// - 10: 60Hz FIR rejection
whismanoid 19:8f951e448ab1 546 /// - 11: SINC4
whismanoid 19:8f951e448ab1 547 typedef enum MAX11410_LINEF_enum_t {
whismanoid 19:8f951e448ab1 548 LINEF_00_50Hz_60Hz_FIR = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 549 LINEF_01_50Hz_FIR = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 550 LINEF_10_60Hz_FIR = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 551 LINEF_11_SINC4 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 552 } MAX11410_LINEF_enum_t;
whismanoid 19:8f951e448ab1 553
whismanoid 19:8f951e448ab1 554 // CODE GENERATOR: TypedefEnum MAX11410_RATE_enum_t
whismanoid 19:8f951e448ab1 555 //----------------------------------------
whismanoid 19:8f951e448ab1 556 /// Filter command
whismanoid 19:8f951e448ab1 557 /// CMD_r000_1000_x0dd_dddd_FILTER RATE[3:0] field
whismanoid 19:8f951e448ab1 558 ///
whismanoid 19:8f951e448ab1 559 /// Sets conversion rate based on LINEF value. See Table 9a through Table 9d for details.
whismanoid 19:8f951e448ab1 560 ///
whismanoid 19:8f951e448ab1 561 /// Table 9a. LINEF = 00 Data Rate and Filter Rejection Settings
whismanoid 19:8f951e448ab1 562 ///
whismanoid 19:8f951e448ab1 563 /// Rate | LINEF | CONV_TYPE | Rate
whismanoid 19:8f951e448ab1 564 /// -----------|------------------------|----------------------------|----------
whismanoid 19:8f951e448ab1 565 /// RATE_0000 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 1.0SPS
whismanoid 19:8f951e448ab1 566 /// RATE_0001 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 2.0SPS
whismanoid 19:8f951e448ab1 567 /// RATE_0010 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 4.0SPS
whismanoid 19:8f951e448ab1 568 /// RATE_0011 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 8.0SPS
whismanoid 19:8f951e448ab1 569 /// RATE_0100 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_00_Single | 16.0SPS
whismanoid 19:8f951e448ab1 570 /// RATE_0000 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 1.1SPS
whismanoid 19:8f951e448ab1 571 /// RATE_0001 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 2.1SPS
whismanoid 19:8f951e448ab1 572 /// RATE_0010 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 4.2SPS
whismanoid 19:8f951e448ab1 573 /// RATE_0011 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 8.4SPS
whismanoid 19:8f951e448ab1 574 /// RATE_0100 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_01_Continuous | 16.8SPS
whismanoid 19:8f951e448ab1 575 /// RATE_0000 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.3SPS
whismanoid 19:8f951e448ab1 576 /// RATE_0001 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.5SPS
whismanoid 19:8f951e448ab1 577 /// RATE_0010 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 1.1SPS
whismanoid 19:8f951e448ab1 578 /// RATE_0011 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 2.1SPS
whismanoid 19:8f951e448ab1 579 /// RATE_0100 | LINEF_00_50Hz_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 4.2SPS
whismanoid 19:8f951e448ab1 580 ///
whismanoid 19:8f951e448ab1 581 /// Table 9b. LINEF = 01 Data Rate and Filter Rejection Settings
whismanoid 19:8f951e448ab1 582 ///
whismanoid 19:8f951e448ab1 583 /// Rate | LINEF | CONV_TYPE | Rate
whismanoid 19:8f951e448ab1 584 /// ----------|------------------------|----------------------------|----------
whismanoid 19:8f951e448ab1 585 /// RATE_0000 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 1.3SPS
whismanoid 19:8f951e448ab1 586 /// RATE_0001 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 2.5SPS
whismanoid 19:8f951e448ab1 587 /// RATE_0010 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 5.0SPS
whismanoid 19:8f951e448ab1 588 /// RATE_0011 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 10.0SPS
whismanoid 19:8f951e448ab1 589 /// RATE_0100 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 20.0SPS
whismanoid 19:8f951e448ab1 590 /// RATE_0101 | LINEF_01_50Hz_FIR | CONV_TYPE_00_Single | 35.6SPS
whismanoid 19:8f951e448ab1 591 /// RATE_0000 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 1.3SPS
whismanoid 19:8f951e448ab1 592 /// RATE_0001 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 2.7SPS
whismanoid 19:8f951e448ab1 593 /// RATE_0010 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 5.3SPS
whismanoid 19:8f951e448ab1 594 /// RATE_0011 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 10.7SPS
whismanoid 19:8f951e448ab1 595 /// RATE_0100 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 21.3SPS
whismanoid 19:8f951e448ab1 596 /// RATE_0101 | LINEF_01_50Hz_FIR | CONV_TYPE_01_Continuous | 40.0SPS
whismanoid 19:8f951e448ab1 597 /// RATE_0000 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.3SPS
whismanoid 19:8f951e448ab1 598 /// RATE_0001 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.7SPS
whismanoid 19:8f951e448ab1 599 /// RATE_0010 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 1.3SPS
whismanoid 19:8f951e448ab1 600 /// RATE_0011 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 2.7SPS
whismanoid 19:8f951e448ab1 601 /// RATE_0100 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 5.3SPS
whismanoid 19:8f951e448ab1 602 /// RATE_0101 | LINEF_01_50Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 10.0SPS
whismanoid 19:8f951e448ab1 603 ///
whismanoid 19:8f951e448ab1 604 /// Table 9c. LINEF = 10 Data Rate and Filter Rejection Settings
whismanoid 19:8f951e448ab1 605 ///
whismanoid 19:8f951e448ab1 606 /// Rate | LINEF | CONV_TYPE | Rate
whismanoid 19:8f951e448ab1 607 /// ----------|------------------------|----------------------------|----------
whismanoid 19:8f951e448ab1 608 /// RATE_0000 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 1.3SPS
whismanoid 19:8f951e448ab1 609 /// RATE_0001 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 2.5SPS
whismanoid 19:8f951e448ab1 610 /// RATE_0010 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 5.0SPS
whismanoid 19:8f951e448ab1 611 /// RATE_0011 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 10.0SPS
whismanoid 19:8f951e448ab1 612 /// RATE_0100 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 20.0SPS
whismanoid 19:8f951e448ab1 613 /// RATE_0101 | LINEF_10_60Hz_FIR | CONV_TYPE_00_Single | 35.6SPS
whismanoid 19:8f951e448ab1 614 /// RATE_0000 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 1.3SPS
whismanoid 19:8f951e448ab1 615 /// RATE_0001 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 2.7SPS
whismanoid 19:8f951e448ab1 616 /// RATE_0010 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 5.3SPS
whismanoid 19:8f951e448ab1 617 /// RATE_0011 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 10.7SPS
whismanoid 19:8f951e448ab1 618 /// RATE_0100 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 21.3SPS
whismanoid 19:8f951e448ab1 619 /// RATE_0101 | LINEF_10_60Hz_FIR | CONV_TYPE_01_Continuous | 40.0SPS
whismanoid 19:8f951e448ab1 620 /// RATE_0000 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.3SPS
whismanoid 19:8f951e448ab1 621 /// RATE_0001 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 0.7SPS
whismanoid 19:8f951e448ab1 622 /// RATE_0010 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 1.3SPS
whismanoid 19:8f951e448ab1 623 /// RATE_0011 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 2.7SPS
whismanoid 19:8f951e448ab1 624 /// RATE_0100 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 5.3SPS
whismanoid 19:8f951e448ab1 625 /// RATE_0101 | LINEF_10_60Hz_FIR | CONV_TYPE_10_DutyCycle_1_4 | 10.0SPS
whismanoid 19:8f951e448ab1 626 ///
whismanoid 19:8f951e448ab1 627 /// Table 9d. LINEF = 11 Data Rate and Filter Rejection Settings
whismanoid 19:8f951e448ab1 628 ///
whismanoid 19:8f951e448ab1 629 /// Rate | LINEF | CONV_TYPE | Rate
whismanoid 19:8f951e448ab1 630 /// ----------|------------------------|----------------------------|----------
whismanoid 19:8f951e448ab1 631 /// RATE_0000 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 1SPS
whismanoid 19:8f951e448ab1 632 /// RATE_0001 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 2.5SPS
whismanoid 19:8f951e448ab1 633 /// RATE_0010 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 5SPS
whismanoid 19:8f951e448ab1 634 /// RATE_0011 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 10SPS
whismanoid 19:8f951e448ab1 635 /// RATE_0100 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 15SPS
whismanoid 19:8f951e448ab1 636 /// RATE_0101 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 30SPS
whismanoid 19:8f951e448ab1 637 /// RATE_0110 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 60SPS
whismanoid 19:8f951e448ab1 638 /// RATE_0111 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 120SPS
whismanoid 19:8f951e448ab1 639 /// RATE_1000 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 240SPS
whismanoid 19:8f951e448ab1 640 /// RATE_1001 | LINEF_11_SINC4 | CONV_TYPE_00_Single | 480SPS
whismanoid 19:8f951e448ab1 641 /// RATE_0000 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 4SPS
whismanoid 19:8f951e448ab1 642 /// RATE_0001 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 10SPS
whismanoid 19:8f951e448ab1 643 /// RATE_0010 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 20SPS
whismanoid 19:8f951e448ab1 644 /// RATE_0011 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 40SPS
whismanoid 19:8f951e448ab1 645 /// RATE_0100 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 60SPS
whismanoid 19:8f951e448ab1 646 /// RATE_0101 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 120SPS
whismanoid 19:8f951e448ab1 647 /// RATE_0110 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 240SPS
whismanoid 19:8f951e448ab1 648 /// RATE_0111 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 480SPS
whismanoid 19:8f951e448ab1 649 /// RATE_1000 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 960SPS
whismanoid 19:8f951e448ab1 650 /// RATE_1001 | LINEF_11_SINC4 | CONV_TYPE_01_Continuous | 1920SPS
whismanoid 19:8f951e448ab1 651 /// RATE_0000 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 1SPS
whismanoid 19:8f951e448ab1 652 /// RATE_0001 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 2.5SPS
whismanoid 19:8f951e448ab1 653 /// RATE_0010 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 5SPS
whismanoid 19:8f951e448ab1 654 /// RATE_0011 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 10SPS
whismanoid 19:8f951e448ab1 655 /// RATE_0100 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 15SPS
whismanoid 19:8f951e448ab1 656 /// RATE_0101 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 30SPS
whismanoid 19:8f951e448ab1 657 /// RATE_0110 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 60SPS
whismanoid 19:8f951e448ab1 658 /// RATE_0111 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 120SPS
whismanoid 19:8f951e448ab1 659 /// RATE_1000 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 240SPS
whismanoid 19:8f951e448ab1 660 /// RATE_1001 | LINEF_11_SINC4 | CONV_TYPE_10_DutyCycle_1_4 | 480SPS
whismanoid 19:8f951e448ab1 661 ///
whismanoid 19:8f951e448ab1 662 typedef enum MAX11410_RATE_enum_t {
whismanoid 19:8f951e448ab1 663 RATE_0000 = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 664 RATE_0001 = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 665 RATE_0010 = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 666 RATE_0011 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 667 RATE_0100 = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 668 RATE_0101 = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 669 RATE_0110 = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 670 RATE_0111 = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 671 RATE_1000 = 0x08, //!< 8'b00001000
whismanoid 19:8f951e448ab1 672 RATE_1001 = 0x09, //!< 8'b00001001
whismanoid 19:8f951e448ab1 673 RATE_1010 = 0x0a, //!< 8'b00001010
whismanoid 19:8f951e448ab1 674 RATE_1011 = 0x0b, //!< 8'b00001011
whismanoid 19:8f951e448ab1 675 RATE_1100 = 0x0c, //!< 8'b00001100
whismanoid 19:8f951e448ab1 676 RATE_1101 = 0x0d, //!< 8'b00001101
whismanoid 19:8f951e448ab1 677 RATE_1110 = 0x0e, //!< 8'b00001110
whismanoid 19:8f951e448ab1 678 RATE_1111 = 0x0f, //!< 8'b00001111
whismanoid 19:8f951e448ab1 679 } MAX11410_RATE_enum_t;
whismanoid 19:8f951e448ab1 680
whismanoid 19:8f951e448ab1 681 // CODE GENERATOR: TypedefEnum MAX11410_REF_SEL_enum_t
whismanoid 19:8f951e448ab1 682 //----------------------------------------
whismanoid 19:8f951e448ab1 683 /// Filter command
whismanoid 19:8f951e448ab1 684 /// CMD_r000_1001_dddd_dddd_CTRL REF_SEL[2:0] field
whismanoid 19:8f951e448ab1 685 ///
whismanoid 19:8f951e448ab1 686 /// - 000: AIN0(REF0P)/AIN1(REF0N)
whismanoid 19:8f951e448ab1 687 /// - 001: REF1P/REF1N (default)
whismanoid 19:8f951e448ab1 688 /// - 010: REF2P/REF2N
whismanoid 19:8f951e448ab1 689 /// - 011: AVDD/AGND
whismanoid 19:8f951e448ab1 690 /// - 100: AIN0(REF0P)/AGND (single-ended mode)
whismanoid 19:8f951e448ab1 691 /// - 101: REF1P/AGND (single-ended mode)
whismanoid 19:8f951e448ab1 692 /// - 110: REF2P/AGND (single-ended mode)
whismanoid 19:8f951e448ab1 693 /// - 111: AVDD/AGND
whismanoid 19:8f951e448ab1 694 typedef enum MAX11410_REF_SEL_enum_t {
whismanoid 19:8f951e448ab1 695 REF_SEL_000_AIN0_AIN1 = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 696 REF_SEL_001_REF1P_REF1N = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 697 REF_SEL_010_REF2P_REF2N = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 698 REF_SEL_011_AVDD_AGND = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 699 REF_SEL_100_AIN0_AGND = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 700 REF_SEL_101_REF1P_AGND = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 701 REF_SEL_110_REF2P_AGND = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 702 REF_SEL_111_AVDD_AGND = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 703 } MAX11410_REF_SEL_enum_t;
whismanoid 19:8f951e448ab1 704
whismanoid 19:8f951e448ab1 705 // CODE GENERATOR: TypedefEnum MAX11410_VBIAS_MODE_enum_t
whismanoid 19:8f951e448ab1 706 //----------------------------------------
whismanoid 19:8f951e448ab1 707 /// Source command
whismanoid 19:8f951e448ab1 708 /// CMD_r000_1010_dddd_dddd_SOURCE VBIAS_MODE[1:0] field
whismanoid 19:8f951e448ab1 709 ///
whismanoid 19:8f951e448ab1 710 /// - 00: Active mode (default)
whismanoid 19:8f951e448ab1 711 /// - 01: High impedance; 125kOhm output impedance
whismanoid 19:8f951e448ab1 712 /// - 10: Low impedance; 20kOhm output impedance
whismanoid 19:8f951e448ab1 713 /// - 11: Low impedance; 20kOhm output impedance
whismanoid 19:8f951e448ab1 714 typedef enum MAX11410_VBIAS_MODE_enum_t {
whismanoid 19:8f951e448ab1 715 VBIAS_MODE_00_Active = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 716 VBIAS_MODE_01_125kOhm = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 717 VBIAS_MODE_10_20kOhm = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 718 VBIAS_MODE_11_20kOhm = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 719 } MAX11410_VBIAS_MODE_enum_t;
whismanoid 19:8f951e448ab1 720
whismanoid 19:8f951e448ab1 721 // CODE GENERATOR: TypedefEnum MAX11410_BRN_MODE_enum_t
whismanoid 19:8f951e448ab1 722 //----------------------------------------
whismanoid 19:8f951e448ab1 723 /// Source command
whismanoid 19:8f951e448ab1 724 /// CMD_r000_1010_dddd_dddd_SOURCE BRN_MODE[1:0] field
whismanoid 19:8f951e448ab1 725 ///
whismanoid 19:8f951e448ab1 726 /// - 00: Powered down, burnout sources disabled (default)
whismanoid 19:8f951e448ab1 727 /// - 01: 0.5uA burnout current sources enabled
whismanoid 19:8f951e448ab1 728 /// - 10: 1uA burnout current sources enabled
whismanoid 19:8f951e448ab1 729 /// - 11: 10uA burnout current sources enabled
whismanoid 19:8f951e448ab1 730 typedef enum MAX11410_BRN_MODE_enum_t {
whismanoid 19:8f951e448ab1 731 BRN_MODE_00_disabled = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 732 BRN_MODE_01_0u5A = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 733 BRN_MODE_10_1uA = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 734 BRN_MODE_11_10uA = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 735 } MAX11410_BRN_MODE_enum_t;
whismanoid 19:8f951e448ab1 736
whismanoid 19:8f951e448ab1 737 // CODE GENERATOR: TypedefEnum MAX11410_IDAC_MODE_enum_t
whismanoid 19:8f951e448ab1 738 //----------------------------------------
whismanoid 19:8f951e448ab1 739 /// Source command
whismanoid 19:8f951e448ab1 740 /// CMD_r000_1010_dddd_dddd_SOURCE IDAC_MODE[3:0] field
whismanoid 19:8f951e448ab1 741 ///
whismanoid 19:8f951e448ab1 742 /// - 0000: 10uA (default)
whismanoid 19:8f951e448ab1 743 /// - 0001: 50uA
whismanoid 19:8f951e448ab1 744 /// - 0010: 75uA
whismanoid 19:8f951e448ab1 745 /// - 0011: 100uA
whismanoid 19:8f951e448ab1 746 /// - 0100: 125uA
whismanoid 19:8f951e448ab1 747 /// - 0101: 150uA
whismanoid 19:8f951e448ab1 748 /// - 0110: 175uA
whismanoid 19:8f951e448ab1 749 /// - 0111: 200uA
whismanoid 19:8f951e448ab1 750 /// - 1000: 225uA
whismanoid 19:8f951e448ab1 751 /// - 1001: 250uA
whismanoid 19:8f951e448ab1 752 /// - 1010: 300uA
whismanoid 19:8f951e448ab1 753 /// - 1011: 400uA
whismanoid 19:8f951e448ab1 754 /// - 1100: 600uA
whismanoid 19:8f951e448ab1 755 /// - 1101: 800uA
whismanoid 19:8f951e448ab1 756 /// - 1110: 1200uA
whismanoid 19:8f951e448ab1 757 /// - 1111: 1600uA
whismanoid 19:8f951e448ab1 758 typedef enum MAX11410_IDAC_MODE_enum_t {
whismanoid 19:8f951e448ab1 759 IDAC_MODE_0000_10uA = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 760 IDAC_MODE_0001_50uA = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 761 IDAC_MODE_0010_75uA = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 762 IDAC_MODE_0011_100uA = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 763 IDAC_MODE_0100_125uA = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 764 IDAC_MODE_0101_150uA = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 765 IDAC_MODE_0110_175uA = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 766 IDAC_MODE_0111_200uA = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 767 IDAC_MODE_1000_225uA = 0x08, //!< 8'b00001000
whismanoid 19:8f951e448ab1 768 IDAC_MODE_1001_250uA = 0x09, //!< 8'b00001001
whismanoid 19:8f951e448ab1 769 IDAC_MODE_1010_300uA = 0x0a, //!< 8'b00001010
whismanoid 19:8f951e448ab1 770 IDAC_MODE_1011_400uA = 0x0b, //!< 8'b00001011
whismanoid 19:8f951e448ab1 771 IDAC_MODE_1100_600uA = 0x0c, //!< 8'b00001100
whismanoid 19:8f951e448ab1 772 IDAC_MODE_1101_800uA = 0x0d, //!< 8'b00001101
whismanoid 19:8f951e448ab1 773 IDAC_MODE_1110_1200uA = 0x0e, //!< 8'b00001110
whismanoid 19:8f951e448ab1 774 IDAC_MODE_1111_1600uA = 0x0f, //!< 8'b00001111
whismanoid 19:8f951e448ab1 775 } MAX11410_IDAC_MODE_enum_t;
whismanoid 19:8f951e448ab1 776
whismanoid 19:8f951e448ab1 777 // CODE GENERATOR: TypedefEnum MAX11410_AINP_SEL_enum_t
whismanoid 19:8f951e448ab1 778 //----------------------------------------
whismanoid 19:8f951e448ab1 779 /// Input multiplexer channel selection
whismanoid 19:8f951e448ab1 780 /// CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINP_SEL[3:0]
whismanoid 19:8f951e448ab1 781 ///
whismanoid 19:8f951e448ab1 782 /// - 0000: AINP = AIN0
whismanoid 19:8f951e448ab1 783 /// - 0001: AINP = AIN1
whismanoid 19:8f951e448ab1 784 /// - 0010: AINP = AIN2
whismanoid 19:8f951e448ab1 785 /// - 0011: AINP = AIN3
whismanoid 19:8f951e448ab1 786 /// - 0100: AINP = AIN4
whismanoid 19:8f951e448ab1 787 /// - 0101: AINP = AIN5
whismanoid 19:8f951e448ab1 788 /// - 0110: AINP = AIN6
whismanoid 19:8f951e448ab1 789 /// - 0111: AINP = AIN7
whismanoid 19:8f951e448ab1 790 /// - 1000: AINP = AIN8
whismanoid 19:8f951e448ab1 791 /// - 1001: AINP = AIN9
whismanoid 19:8f951e448ab1 792 /// - 1010: AINP = AVDD
whismanoid 19:8f951e448ab1 793 /// - 1011: AINN = Unconnected
whismanoid 19:8f951e448ab1 794 /// - 1100: AINN = Unconnected
whismanoid 19:8f951e448ab1 795 /// - 1101: AINN = Unconnected
whismanoid 19:8f951e448ab1 796 /// - 1110: AINN = Unconnected
whismanoid 19:8f951e448ab1 797 /// - 1111: AINN = Unconnected (default)
whismanoid 19:8f951e448ab1 798 typedef enum MAX11410_AINP_SEL_enum_t {
whismanoid 19:8f951e448ab1 799 AINP_SEL_0000_AIN0 = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 800 AINP_SEL_0001_AIN1 = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 801 AINP_SEL_0010_AIN2 = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 802 AINP_SEL_0011_AIN3 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 803 AINP_SEL_0100_AIN4 = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 804 AINP_SEL_0101_AIN5 = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 805 AINP_SEL_0110_AIN6 = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 806 AINP_SEL_0111_AIN7 = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 807 AINP_SEL_1000_AIN8 = 0x08, //!< 8'b00001000
whismanoid 19:8f951e448ab1 808 AINP_SEL_1001_AIN9 = 0x09, //!< 8'b00001001
whismanoid 19:8f951e448ab1 809 AINP_SEL_1010_AVDD = 0x0a, //!< 8'b00001010
whismanoid 19:8f951e448ab1 810 AINP_SEL_1011_unconnected = 0x0b, //!< 8'b00001011
whismanoid 19:8f951e448ab1 811 AINP_SEL_1100_unconnected = 0x0c, //!< 8'b00001100
whismanoid 19:8f951e448ab1 812 AINP_SEL_1101_unconnected = 0x0d, //!< 8'b00001101
whismanoid 19:8f951e448ab1 813 AINP_SEL_1110_unconnected = 0x0e, //!< 8'b00001110
whismanoid 19:8f951e448ab1 814 AINP_SEL_1111_unconnected = 0x0f, //!< 8'b00001111
whismanoid 19:8f951e448ab1 815 } MAX11410_AINP_SEL_enum_t;
whismanoid 19:8f951e448ab1 816
whismanoid 19:8f951e448ab1 817 // CODE GENERATOR: TypedefEnum MAX11410_AINN_SEL_enum_t
whismanoid 19:8f951e448ab1 818 //----------------------------------------
whismanoid 19:8f951e448ab1 819 /// Input multiplexer channel selection
whismanoid 19:8f951e448ab1 820 /// CMD_r000_1011_dddd_dddd_MUX_CTRL0 field AINP_SEL[3:0]
whismanoid 19:8f951e448ab1 821 ///
whismanoid 19:8f951e448ab1 822 /// - 0000: AINN = AIN0
whismanoid 19:8f951e448ab1 823 /// - 0001: AINN = AIN1
whismanoid 19:8f951e448ab1 824 /// - 0010: AINN = AIN2
whismanoid 19:8f951e448ab1 825 /// - 0011: AINN = AIN3
whismanoid 19:8f951e448ab1 826 /// - 0100: AINN = AIN4
whismanoid 19:8f951e448ab1 827 /// - 0101: AINN = AIN5
whismanoid 19:8f951e448ab1 828 /// - 0110: AINN = AIN6
whismanoid 19:8f951e448ab1 829 /// - 0111: AINN = AIN7
whismanoid 19:8f951e448ab1 830 /// - 1000: AINN = AIN8
whismanoid 19:8f951e448ab1 831 /// - 1001: AINN = AIN9
whismanoid 19:8f951e448ab1 832 /// - 1010: AINN = GND
whismanoid 19:8f951e448ab1 833 /// - 1011: AINN = Unconnected
whismanoid 19:8f951e448ab1 834 /// - 1100: AINN = Unconnected
whismanoid 19:8f951e448ab1 835 /// - 1101: AINN = Unconnected
whismanoid 19:8f951e448ab1 836 /// - 1110: AINN = Unconnected
whismanoid 19:8f951e448ab1 837 /// - 1111: AINN = Unconnected (default)
whismanoid 19:8f951e448ab1 838 typedef enum MAX11410_AINN_SEL_enum_t {
whismanoid 19:8f951e448ab1 839 AINN_SEL_0000_AIN0 = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 840 AINN_SEL_0001_AIN1 = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 841 AINN_SEL_0010_AIN2 = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 842 AINN_SEL_0011_AIN3 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 843 AINN_SEL_0100_AIN4 = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 844 AINN_SEL_0101_AIN5 = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 845 AINN_SEL_0110_AIN6 = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 846 AINN_SEL_0111_AIN7 = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 847 AINN_SEL_1000_AIN8 = 0x08, //!< 8'b00001000
whismanoid 19:8f951e448ab1 848 AINN_SEL_1001_AIN9 = 0x09, //!< 8'b00001001
whismanoid 19:8f951e448ab1 849 AINN_SEL_1010_GND = 0x0a, //!< 8'b00001010
whismanoid 19:8f951e448ab1 850 AINN_SEL_1011_unconnected = 0x0b, //!< 8'b00001011
whismanoid 19:8f951e448ab1 851 AINN_SEL_1100_unconnected = 0x0c, //!< 8'b00001100
whismanoid 19:8f951e448ab1 852 AINN_SEL_1101_unconnected = 0x0d, //!< 8'b00001101
whismanoid 19:8f951e448ab1 853 AINN_SEL_1110_unconnected = 0x0e, //!< 8'b00001110
whismanoid 19:8f951e448ab1 854 AINN_SEL_1111_unconnected = 0x0f, //!< 8'b00001111
whismanoid 19:8f951e448ab1 855 } MAX11410_AINN_SEL_enum_t;
whismanoid 19:8f951e448ab1 856
whismanoid 19:8f951e448ab1 857 // CODE GENERATOR: TypedefEnum MAX11410_IDAC1_SEL_enum_t
whismanoid 19:8f951e448ab1 858 //----------------------------------------
whismanoid 19:8f951e448ab1 859 /// Input multiplexer channel selection
whismanoid 19:8f951e448ab1 860 /// CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC1_SEL[3:0]
whismanoid 19:8f951e448ab1 861 ///
whismanoid 19:8f951e448ab1 862 /// - 0000: AIN0
whismanoid 19:8f951e448ab1 863 /// - 0001: AIN1
whismanoid 19:8f951e448ab1 864 /// - 0010: AIN2
whismanoid 19:8f951e448ab1 865 /// - 0011: AIN3
whismanoid 19:8f951e448ab1 866 /// - 0100: AIN4
whismanoid 19:8f951e448ab1 867 /// - 0101: AIN5
whismanoid 19:8f951e448ab1 868 /// - 0110: AIN6
whismanoid 19:8f951e448ab1 869 /// - 0111: AIN7
whismanoid 19:8f951e448ab1 870 /// - 1000: AIN8
whismanoid 19:8f951e448ab1 871 /// - 1001: AIN9
whismanoid 19:8f951e448ab1 872 /// - 1010: Unconnected; IDAC1 powered down.
whismanoid 19:8f951e448ab1 873 /// - 1011: Unconnected; IDAC1 powered down.
whismanoid 19:8f951e448ab1 874 /// - 1100: Unconnected; IDAC1 powered down.
whismanoid 19:8f951e448ab1 875 /// - 1101: Unconnected; IDAC1 powered down.
whismanoid 19:8f951e448ab1 876 /// - 1110: Unconnected; IDAC1 powered down.
whismanoid 19:8f951e448ab1 877 /// - 1111: Unconnected; IDAC1 powered down.(Default)
whismanoid 19:8f951e448ab1 878 typedef enum MAX11410_IDAC1_SEL_enum_t {
whismanoid 19:8f951e448ab1 879 IDAC1_SEL_0000_AIN0 = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 880 IDAC1_SEL_0001_AIN1 = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 881 IDAC1_SEL_0010_AIN2 = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 882 IDAC1_SEL_0011_AIN3 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 883 IDAC1_SEL_0100_AIN4 = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 884 IDAC1_SEL_0101_AIN5 = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 885 IDAC1_SEL_0110_AIN6 = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 886 IDAC1_SEL_0111_AIN7 = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 887 IDAC1_SEL_1000_AIN8 = 0x08, //!< 8'b00001000
whismanoid 19:8f951e448ab1 888 IDAC1_SEL_1001_AIN9 = 0x09, //!< 8'b00001001
whismanoid 19:8f951e448ab1 889 IDAC1_SEL_1010_unconnected = 0x0a, //!< 8'b00001010
whismanoid 19:8f951e448ab1 890 IDAC1_SEL_1011_unconnected = 0x0b, //!< 8'b00001011
whismanoid 19:8f951e448ab1 891 IDAC1_SEL_1100_unconnected = 0x0c, //!< 8'b00001100
whismanoid 19:8f951e448ab1 892 IDAC1_SEL_1101_unconnected = 0x0d, //!< 8'b00001101
whismanoid 19:8f951e448ab1 893 IDAC1_SEL_1110_unconnected = 0x0e, //!< 8'b00001110
whismanoid 19:8f951e448ab1 894 IDAC1_SEL_1111_unconnected = 0x0f, //!< 8'b00001111
whismanoid 19:8f951e448ab1 895 } MAX11410_IDAC1_SEL_enum_t;
whismanoid 19:8f951e448ab1 896
whismanoid 19:8f951e448ab1 897 // CODE GENERATOR: TypedefEnum MAX11410_IDAC0_SEL_enum_t
whismanoid 19:8f951e448ab1 898 //----------------------------------------
whismanoid 19:8f951e448ab1 899 /// Input multiplexer channel selection
whismanoid 19:8f951e448ab1 900 /// CMD_r000_1100_dddd_dddd_MUX_CTRL1 field IDAC0_SEL[3:0]
whismanoid 19:8f951e448ab1 901 ///
whismanoid 19:8f951e448ab1 902 /// - 0000: AIN0
whismanoid 19:8f951e448ab1 903 /// - 0001: AIN1
whismanoid 19:8f951e448ab1 904 /// - 0010: AIN2
whismanoid 19:8f951e448ab1 905 /// - 0011: AIN3
whismanoid 19:8f951e448ab1 906 /// - 0100: AIN4
whismanoid 19:8f951e448ab1 907 /// - 0101: AIN5
whismanoid 19:8f951e448ab1 908 /// - 0110: AIN6
whismanoid 19:8f951e448ab1 909 /// - 0111: AIN7
whismanoid 19:8f951e448ab1 910 /// - 1000: AIN8
whismanoid 19:8f951e448ab1 911 /// - 1001: AIN9
whismanoid 19:8f951e448ab1 912 /// - 1010: Unconnected; IDAC0 powered down.
whismanoid 19:8f951e448ab1 913 /// - 1011: Unconnected; IDAC0 powered down.
whismanoid 19:8f951e448ab1 914 /// - 1100: Unconnected; IDAC0 powered down.
whismanoid 19:8f951e448ab1 915 /// - 1101: Unconnected; IDAC0 powered down.
whismanoid 19:8f951e448ab1 916 /// - 1110: Unconnected; IDAC0 powered down.
whismanoid 19:8f951e448ab1 917 /// - 1111: Unconnected; IDAC0 powered down.(Default)
whismanoid 19:8f951e448ab1 918 typedef enum MAX11410_IDAC0_SEL_enum_t {
whismanoid 19:8f951e448ab1 919 IDAC0_SEL_0000_AIN0 = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 920 IDAC0_SEL_0001_AIN1 = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 921 IDAC0_SEL_0010_AIN2 = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 922 IDAC0_SEL_0011_AIN3 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 923 IDAC0_SEL_0100_AIN4 = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 924 IDAC0_SEL_0101_AIN5 = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 925 IDAC0_SEL_0110_AIN6 = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 926 IDAC0_SEL_0111_AIN7 = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 927 IDAC0_SEL_1000_AIN8 = 0x08, //!< 8'b00001000
whismanoid 19:8f951e448ab1 928 IDAC0_SEL_1001_AIN9 = 0x09, //!< 8'b00001001
whismanoid 19:8f951e448ab1 929 IDAC0_SEL_1010_unconnected = 0x0a, //!< 8'b00001010
whismanoid 19:8f951e448ab1 930 IDAC0_SEL_1011_unconnected = 0x0b, //!< 8'b00001011
whismanoid 19:8f951e448ab1 931 IDAC0_SEL_1100_unconnected = 0x0c, //!< 8'b00001100
whismanoid 19:8f951e448ab1 932 IDAC0_SEL_1101_unconnected = 0x0d, //!< 8'b00001101
whismanoid 19:8f951e448ab1 933 IDAC0_SEL_1110_unconnected = 0x0e, //!< 8'b00001110
whismanoid 19:8f951e448ab1 934 IDAC0_SEL_1111_unconnected = 0x0f, //!< 8'b00001111
whismanoid 19:8f951e448ab1 935 } MAX11410_IDAC0_SEL_enum_t;
whismanoid 19:8f951e448ab1 936
whismanoid 19:8f951e448ab1 937 // CODE GENERATOR: TypedefEnum MAX11410_SIG_PATH_enum_t
whismanoid 19:8f951e448ab1 938 //----------------------------------------
whismanoid 19:8f951e448ab1 939 /// Input multiplexer channel selection
whismanoid 19:8f951e448ab1 940 /// CMD_r000_1110_xxdd_xddd_PGA field SIG_PATH[1:0]
whismanoid 19:8f951e448ab1 941 ///
whismanoid 19:8f951e448ab1 942 /// - 00: Buffered, low-power, unity-gain path (PGA disabled, digital gain) [default]
whismanoid 19:8f951e448ab1 943 /// - 01: Bypass path (signal buffer disabled,PGA disabled, digital gain)
whismanoid 19:8f951e448ab1 944 /// - 10: PGA path (signal buffer disabled, analog gain)
whismanoid 19:8f951e448ab1 945 /// - 11: Reserved
whismanoid 19:8f951e448ab1 946 typedef enum MAX11410_SIG_PATH_enum_t {
whismanoid 19:8f951e448ab1 947 SIG_PATH_00_BUFFERED = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 948 SIG_PATH_01_BYPASS = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 949 SIG_PATH_10_PGA = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 950 SIG_PATH_11_reserved = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 951 } MAX11410_SIG_PATH_enum_t;
whismanoid 19:8f951e448ab1 952
whismanoid 19:8f951e448ab1 953 // CODE GENERATOR: TypedefEnum MAX11410_GAIN_enum_t
whismanoid 19:8f951e448ab1 954 //----------------------------------------
whismanoid 19:8f951e448ab1 955 /// Input multiplexer channel selection
whismanoid 19:8f951e448ab1 956 /// CMD_r000_1110_xxdd_xddd_PGA field GAIN[2:0]
whismanoid 19:8f951e448ab1 957 ///
whismanoid 19:8f951e448ab1 958 /// - 000: 1 (default)
whismanoid 19:8f951e448ab1 959 /// - 001: 2
whismanoid 19:8f951e448ab1 960 /// - 010: 4
whismanoid 19:8f951e448ab1 961 /// - 011: 8
whismanoid 19:8f951e448ab1 962 /// - 100: 16
whismanoid 19:8f951e448ab1 963 /// - 101: 32
whismanoid 19:8f951e448ab1 964 /// - 110: 64
whismanoid 19:8f951e448ab1 965 /// - 111: 128
whismanoid 19:8f951e448ab1 966 typedef enum MAX11410_GAIN_enum_t {
whismanoid 19:8f951e448ab1 967 GAIN_000_1 = 0x00, //!< 8'b00000000
whismanoid 19:8f951e448ab1 968 GAIN_001_2 = 0x01, //!< 8'b00000001
whismanoid 19:8f951e448ab1 969 GAIN_010_4 = 0x02, //!< 8'b00000010
whismanoid 19:8f951e448ab1 970 GAIN_011_8 = 0x03, //!< 8'b00000011
whismanoid 19:8f951e448ab1 971 GAIN_100_16 = 0x04, //!< 8'b00000100
whismanoid 19:8f951e448ab1 972 GAIN_101_32 = 0x05, //!< 8'b00000101
whismanoid 19:8f951e448ab1 973 GAIN_110_64 = 0x06, //!< 8'b00000110
whismanoid 19:8f951e448ab1 974 GAIN_111_128 = 0x07, //!< 8'b00000111
whismanoid 19:8f951e448ab1 975 } MAX11410_GAIN_enum_t;
whismanoid 19:8f951e448ab1 976
whismanoid 19:8f951e448ab1 977 // TODO1: CODE GENERATOR: ic_variant -- IC's supported with this driver
whismanoid 19:8f951e448ab1 978 /**
whismanoid 19:8f951e448ab1 979 * @brief IC's supported with this driver
whismanoid 19:8f951e448ab1 980 * @details MAX11410
whismanoid 19:8f951e448ab1 981 */
whismanoid 19:8f951e448ab1 982 typedef enum
whismanoid 19:8f951e448ab1 983 {
whismanoid 19:8f951e448ab1 984 MAX11410_IC = 0,
whismanoid 19:8f951e448ab1 985 //MAX11410_IC = 1
whismanoid 19:8f951e448ab1 986 } MAX11410_ic_t;
whismanoid 19:8f951e448ab1 987
whismanoid 19:8f951e448ab1 988 // TODO1: CODE GENERATOR: class constructor declaration
whismanoid 19:8f951e448ab1 989 /**********************************************************//**
whismanoid 19:8f951e448ab1 990 * @brief Constructor for MAX11410 Class.
whismanoid 19:8f951e448ab1 991 *
whismanoid 19:8f951e448ab1 992 * @details Requires an existing SPI object as well as a DigitalOut object.
whismanoid 19:8f951e448ab1 993 * The DigitalOut object is used for a chip enable signal
whismanoid 19:8f951e448ab1 994 *
whismanoid 19:8f951e448ab1 995 * On Entry:
whismanoid 19:8f951e448ab1 996 * @param[in] spi - pointer to existing SPI object
whismanoid 19:8f951e448ab1 997 * @param[in] cs_pin - pointer to a DigitalOut pin object
whismanoid 19:8f951e448ab1 998 * CODE GENERATOR: class constructor docstrings gpio InputPin pins
whismanoid 19:8f951e448ab1 999 * CODE GENERATOR: class constructor docstrings gpio OutputPin pins
whismanoid 19:8f951e448ab1 1000 * @param[in] ic_variant - which type of MAX11410 is used
whismanoid 19:8f951e448ab1 1001 *
whismanoid 19:8f951e448ab1 1002 * On Exit:
whismanoid 19:8f951e448ab1 1003 *
whismanoid 19:8f951e448ab1 1004 * @return None
whismanoid 19:8f951e448ab1 1005 **************************************************************/
whismanoid 19:8f951e448ab1 1006 MAX11410(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 19:8f951e448ab1 1007 // CODE GENERATOR: class constructor declaration gpio InputPin pins
whismanoid 19:8f951e448ab1 1008 // CODE GENERATOR: class constructor declaration gpio OutputPin pins
whismanoid 19:8f951e448ab1 1009 MAX11410_ic_t ic_variant);
whismanoid 19:8f951e448ab1 1010
whismanoid 19:8f951e448ab1 1011 // CODE GENERATOR: class destructor declaration
whismanoid 19:8f951e448ab1 1012 /************************************************************
whismanoid 19:8f951e448ab1 1013 * @brief Default destructor for MAX11410 Class.
whismanoid 19:8f951e448ab1 1014 *
whismanoid 19:8f951e448ab1 1015 * @details Destroys SPI object if owner
whismanoid 19:8f951e448ab1 1016 *
whismanoid 19:8f951e448ab1 1017 * On Entry:
whismanoid 19:8f951e448ab1 1018 *
whismanoid 19:8f951e448ab1 1019 * On Exit:
whismanoid 19:8f951e448ab1 1020 *
whismanoid 19:8f951e448ab1 1021 * @return None
whismanoid 19:8f951e448ab1 1022 **************************************************************/
whismanoid 19:8f951e448ab1 1023 ~MAX11410();
whismanoid 19:8f951e448ab1 1024
whismanoid 19:8f951e448ab1 1025 // CODE GENERATOR: spi_frequency setter declaration
whismanoid 19:8f951e448ab1 1026 /// set SPI SCLK frequency
whismanoid 19:8f951e448ab1 1027 void spi_frequency(int spi_sclk_Hz);
whismanoid 19:8f951e448ab1 1028
whismanoid 19:8f951e448ab1 1029 //----------------------------------------
whismanoid 19:8f951e448ab1 1030 // CODE GENERATOR: omit typedef enum MAX11410_device_t, class members instead of global device object
whismanoid 19:8f951e448ab1 1031 public:
whismanoid 19:8f951e448ab1 1032
whismanoid 19:8f951e448ab1 1033 /// reference voltage, in Volts
whismanoid 19:8f951e448ab1 1034 double VRef;
whismanoid 19:8f951e448ab1 1035
whismanoid 19:8f951e448ab1 1036 // CODE GENERATOR: omit global g_MAX11410_device
whismanoid 19:8f951e448ab1 1037
whismanoid 19:8f951e448ab1 1038 // CODE GENERATOR: extern function declarations
whismanoid 19:8f951e448ab1 1039 // CODE GENERATOR: extern function declaration SPIoutputCS
whismanoid 19:8f951e448ab1 1040 //----------------------------------------
whismanoid 19:8f951e448ab1 1041 // Assert SPI Chip Select
whismanoid 19:8f951e448ab1 1042 // SPI chip-select for MAX11410
whismanoid 19:8f951e448ab1 1043 //
whismanoid 19:8f951e448ab1 1044 void SPIoutputCS(int isLogicHigh);
whismanoid 19:8f951e448ab1 1045
whismanoid 19:8f951e448ab1 1046 // CODE GENERATOR: extern function declaration SPIwrite16bits
whismanoid 19:8f951e448ab1 1047 //----------------------------------------
whismanoid 19:8f951e448ab1 1048 // SPI write 16 bits
whismanoid 19:8f951e448ab1 1049 // SPI interface to MAX11410 shift 16 bits mosiData into MAX11410 DIN
whismanoid 19:8f951e448ab1 1050 //
whismanoid 19:8f951e448ab1 1051 void SPIwrite16bits(int16_t mosiData16);
whismanoid 19:8f951e448ab1 1052
whismanoid 19:8f951e448ab1 1053 // CODE GENERATOR: class member data
whismanoid 19:8f951e448ab1 1054 private:
whismanoid 19:8f951e448ab1 1055 // CODE GENERATOR: class member data for SPI interface
whismanoid 19:8f951e448ab1 1056 // SPI object
whismanoid 19:8f951e448ab1 1057 SPI &m_spi;
whismanoid 19:8f951e448ab1 1058 int m_SPI_SCLK_Hz;
whismanoid 19:8f951e448ab1 1059 int m_SPI_dataMode;
whismanoid 19:8f951e448ab1 1060 int m_SPI_cs_state;
whismanoid 19:8f951e448ab1 1061
whismanoid 19:8f951e448ab1 1062 // Selector pin object
whismanoid 19:8f951e448ab1 1063 DigitalOut &m_cs_pin;
whismanoid 19:8f951e448ab1 1064
whismanoid 19:8f951e448ab1 1065 // CODE GENERATOR: class member data for gpio InputPin pins
whismanoid 19:8f951e448ab1 1066 // CODE GENERATOR: class member data for gpio OutputPin pins
whismanoid 19:8f951e448ab1 1067
whismanoid 19:8f951e448ab1 1068 // Identifies which IC variant is being used
whismanoid 19:8f951e448ab1 1069 MAX11410_ic_t m_ic_variant;
whismanoid 19:8f951e448ab1 1070
whismanoid 19:8f951e448ab1 1071 public:
whismanoid 19:8f951e448ab1 1072
whismanoid 19:8f951e448ab1 1073 // CODE GENERATOR: class member function declarations
whismanoid 19:8f951e448ab1 1074 //----------------------------------------
whismanoid 19:8f951e448ab1 1075 /// Initialize device
whismanoid 19:8f951e448ab1 1076 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1077 uint8_t Init(void);
whismanoid 19:8f951e448ab1 1078
whismanoid 19:8f951e448ab1 1079 //----------------------------------------
whismanoid 19:8f951e448ab1 1080 /// Return the physical voltage corresponding to DAC register.
whismanoid 19:8f951e448ab1 1081 /// Does not perform any offset or gain correction.
whismanoid 19:8f951e448ab1 1082 ///
whismanoid 19:8f951e448ab1 1083 /// @pre g_MAX11410_device.VRef = Voltage of REF input, in Volts
whismanoid 19:8f951e448ab1 1084 /// @param[in] value_u24: raw 24-bit MAX11410 code (right justified).
whismanoid 19:8f951e448ab1 1085 /// @return physical voltage corresponding to MAX11410 code.
whismanoid 19:8f951e448ab1 1086 double VoltageOfCode(uint16_t value_u24);
whismanoid 19:8f951e448ab1 1087
whismanoid 19:8f951e448ab1 1088 //----------------------------------------
whismanoid 19:8f951e448ab1 1089 /// Write an 8-bit MAX11410 register
whismanoid 19:8f951e448ab1 1090 ///
whismanoid 19:8f951e448ab1 1091 /// CMD_1xxx_xxx_REGISTER_READ bit is cleared 0.
whismanoid 19:8f951e448ab1 1092 ///
whismanoid 19:8f951e448ab1 1093 /// SPI 16-bit transfer
whismanoid 19:8f951e448ab1 1094 ///
whismanoid 19:8f951e448ab1 1095 /// SPI MOSI = 0aaa_aaaa_dddd_dddd
whismanoid 19:8f951e448ab1 1096 ///
whismanoid 19:8f951e448ab1 1097 /// SPI MISO = xxxx_xxxx_xxxx_xxxx
whismanoid 19:8f951e448ab1 1098 ///
whismanoid 19:8f951e448ab1 1099 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1100 uint8_t Write_8bit(MAX11410_CMD_enum_t regAddress, uint8_t regData);
whismanoid 19:8f951e448ab1 1101
whismanoid 19:8f951e448ab1 1102 //----------------------------------------
whismanoid 19:8f951e448ab1 1103 /// Read an 8-bit MAX11410 register
whismanoid 19:8f951e448ab1 1104 ///
whismanoid 19:8f951e448ab1 1105 /// CMD_1xxx_xxx_REGISTER_READ bit is set 1.
whismanoid 19:8f951e448ab1 1106 ///
whismanoid 19:8f951e448ab1 1107 /// SPI 16-bit transfer
whismanoid 19:8f951e448ab1 1108 ///
whismanoid 19:8f951e448ab1 1109 /// SPI MOSI = 1aaa_aaaa_0000_0000
whismanoid 19:8f951e448ab1 1110 ///
whismanoid 19:8f951e448ab1 1111 /// SPI MISO = xxxx_xxxx_dddd_dddd
whismanoid 19:8f951e448ab1 1112 ///
whismanoid 19:8f951e448ab1 1113 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1114 uint8_t Read_8bit(MAX11410_CMD_enum_t regAddress, uint8_t* ptrRegData);
whismanoid 19:8f951e448ab1 1115
whismanoid 19:8f951e448ab1 1116 //----------------------------------------
whismanoid 19:8f951e448ab1 1117 /// Write a 16-bit MAX11410 register
whismanoid 19:8f951e448ab1 1118 ///
whismanoid 19:8f951e448ab1 1119 /// CMD_1xxx_xxx_REGISTER_READ bit is cleared 0.
whismanoid 19:8f951e448ab1 1120 ///
whismanoid 19:8f951e448ab1 1121 /// SPI 24-bit transfer
whismanoid 19:8f951e448ab1 1122 ///
whismanoid 19:8f951e448ab1 1123 /// SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd
whismanoid 19:8f951e448ab1 1124 ///
whismanoid 19:8f951e448ab1 1125 /// SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 19:8f951e448ab1 1126 ///
whismanoid 19:8f951e448ab1 1127 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1128 uint8_t Write_16bit(MAX11410_CMD_enum_t regAddress, uint16_t regData);
whismanoid 19:8f951e448ab1 1129
whismanoid 19:8f951e448ab1 1130 //----------------------------------------
whismanoid 19:8f951e448ab1 1131 /// Read a 16-bit MAX11410 register
whismanoid 19:8f951e448ab1 1132 ///
whismanoid 19:8f951e448ab1 1133 /// CMD_1xxx_xxx_REGISTER_READ bit is set 1.
whismanoid 19:8f951e448ab1 1134 ///
whismanoid 19:8f951e448ab1 1135 /// SPI 24-bit transfer
whismanoid 19:8f951e448ab1 1136 ///
whismanoid 19:8f951e448ab1 1137 /// SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000
whismanoid 19:8f951e448ab1 1138 ///
whismanoid 19:8f951e448ab1 1139 /// SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd
whismanoid 19:8f951e448ab1 1140 ///
whismanoid 19:8f951e448ab1 1141 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1142 uint8_t Read_16bit(MAX11410_CMD_enum_t regAddress, uint16_t* ptrRegData);
whismanoid 19:8f951e448ab1 1143
whismanoid 19:8f951e448ab1 1144 //----------------------------------------
whismanoid 19:8f951e448ab1 1145 /// Write a 24-bit MAX11410 register
whismanoid 19:8f951e448ab1 1146 ///
whismanoid 19:8f951e448ab1 1147 /// CMD_1xxx_xxx_REGISTER_READ bit is cleared 0.
whismanoid 19:8f951e448ab1 1148 ///
whismanoid 19:8f951e448ab1 1149 /// SPI 32-bit transfer
whismanoid 19:8f951e448ab1 1150 ///
whismanoid 19:8f951e448ab1 1151 /// SPI MOSI = 0aaa_aaaa_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 19:8f951e448ab1 1152 ///
whismanoid 19:8f951e448ab1 1153 /// SPI MISO = xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx
whismanoid 19:8f951e448ab1 1154 ///
whismanoid 19:8f951e448ab1 1155 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1156 uint8_t Write_24bit(MAX11410_CMD_enum_t regAddress, uint32_t regData);
whismanoid 19:8f951e448ab1 1157
whismanoid 19:8f951e448ab1 1158 //----------------------------------------
whismanoid 19:8f951e448ab1 1159 /// Read a 24-bit MAX11410 register
whismanoid 19:8f951e448ab1 1160 ///
whismanoid 19:8f951e448ab1 1161 /// CMD_1xxx_xxx_REGISTER_READ bit is set 1.
whismanoid 19:8f951e448ab1 1162 ///
whismanoid 19:8f951e448ab1 1163 /// SPI 32-bit transfer
whismanoid 19:8f951e448ab1 1164 ///
whismanoid 19:8f951e448ab1 1165 /// SPI MOSI = 1aaa_aaaa_0000_0000_0000_0000_0000_0000
whismanoid 19:8f951e448ab1 1166 ///
whismanoid 19:8f951e448ab1 1167 /// SPI MISO = xxxx_xxxx_dddd_dddd_dddd_dddd_dddd_dddd
whismanoid 19:8f951e448ab1 1168 ///
whismanoid 19:8f951e448ab1 1169 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1170 uint8_t Read_24bit(MAX11410_CMD_enum_t regAddress, uint32_t* ptrRegData);
whismanoid 19:8f951e448ab1 1171
whismanoid 19:8f951e448ab1 1172 //----------------------------------------
whismanoid 19:8f951e448ab1 1173 /// Configure Measurement for voltage input.
whismanoid 19:8f951e448ab1 1174 ///
whismanoid 19:8f951e448ab1 1175 /// Example code for typical voltage measurement.
whismanoid 19:8f951e448ab1 1176 ///
whismanoid 19:8f951e448ab1 1177 /// SPI register write sequence test AIN0-AGND voltage input using REF2=2.5V
whismanoid 19:8f951e448ab1 1178 /// write8 0x00 PD = 0x03 (Reset Registers; enter Standby mode)
whismanoid 19:8f951e448ab1 1179 /// write8 0x00 PD = 0x00 (NOP)
whismanoid 19:8f951e448ab1 1180 /// write8 0x08 FILTER = 0x34 to select RATE_0100, LINEF_11_SINC4 60SPS (given CONV_TYPE_01_Continuous )
whismanoid 19:8f951e448ab1 1181 /// write8 0x0B MUX_CTRL0 = 0x0A to select AINP=AIN0 and AINN=GND
whismanoid 19:8f951e448ab1 1182 /// write8 0x09 CTRL = 0x02 to select reference REF2P/REF2N; or CTRL = 0x1A to select reference REF2P/REF2N with reference input buffers enabled; Data Format = Bipolar 2's Complement
whismanoid 19:8f951e448ab1 1183 /// write8 0x0E PGA = 0x00 to select input path = Buffers, digital gain = 1V/V
whismanoid 19:8f951e448ab1 1184 /// write8 0x01 CONV_START = 0x01 to set Conversion Mode = Continuous
whismanoid 19:8f951e448ab1 1185 /// read24 0x80|0x38 STATUS (%SW 0xB8 0 0 0)
whismanoid 19:8f951e448ab1 1186 /// read24 0x80|0x30 DATA0 (%SW 0xB0 0 0 0)
whismanoid 19:8f951e448ab1 1187 ///
whismanoid 19:8f951e448ab1 1188 /// @param[in] channel_hi = channel high side
whismanoid 19:8f951e448ab1 1189 /// @param[in] channel_lo = channel low side
whismanoid 19:8f951e448ab1 1190 ///
whismanoid 19:8f951e448ab1 1191 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1192 uint8_t Configure_Voltage(MAX11410_AINP_SEL_enum_t channel_hi, MAX11410_AINN_SEL_enum_t channel_lo);
whismanoid 19:8f951e448ab1 1193
whismanoid 19:8f951e448ab1 1194 //----------------------------------------
whismanoid 19:8f951e448ab1 1195 /// Trigger Measurement for voltage input.
whismanoid 19:8f951e448ab1 1196 ///
whismanoid 19:8f951e448ab1 1197 /// Example code for typical voltage measurement.
whismanoid 19:8f951e448ab1 1198 ///
whismanoid 19:8f951e448ab1 1199 /// @param[in] channel_hi = channel high side
whismanoid 19:8f951e448ab1 1200 /// @param[in] channel_lo = channel low side
whismanoid 19:8f951e448ab1 1201 /// @post TODO: where does the measurement go? struct member?
whismanoid 19:8f951e448ab1 1202 ///
whismanoid 19:8f951e448ab1 1203 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1204 uint8_t Measure_Voltage(MAX11410_AINP_SEL_enum_t channel_hi, MAX11410_AINN_SEL_enum_t channel_lo);
whismanoid 19:8f951e448ab1 1205
whismanoid 19:8f951e448ab1 1206 //----------------------------------------
whismanoid 19:8f951e448ab1 1207 /// Configure Measurement for Resistive Temperature Device (RTD).
whismanoid 19:8f951e448ab1 1208 ///
whismanoid 19:8f951e448ab1 1209 /// Example code for typical RTD measurement.
whismanoid 19:8f951e448ab1 1210 ///
whismanoid 19:8f951e448ab1 1211 /// @param[in] channel_RTD_Force = channel RTD high side force
whismanoid 19:8f951e448ab1 1212 /// @param[in] channel_RTD_Hi = channel RTD high side sense
whismanoid 19:8f951e448ab1 1213 /// @param[in] channel_RTD_Lo = channel RTD low side
whismanoid 19:8f951e448ab1 1214 ///
whismanoid 19:8f951e448ab1 1215 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1216 uint8_t Configure_RTD(MAX11410_AINP_SEL_enum_t channel_RTD_Force, MAX11410_AINP_SEL_enum_t channel_RTD_Hi, MAX11410_AINN_SEL_enum_t channel_RTD_Lo);
whismanoid 19:8f951e448ab1 1217
whismanoid 19:8f951e448ab1 1218 //----------------------------------------
whismanoid 19:8f951e448ab1 1219 /// Trigger Measurement for Resistive Temperature Device (RTD).
whismanoid 19:8f951e448ab1 1220 ///
whismanoid 19:8f951e448ab1 1221 /// Example code for typical RTD measurement.
whismanoid 19:8f951e448ab1 1222 ///
whismanoid 19:8f951e448ab1 1223 /// @param[in] channel_RTD_Force = channel RTD high side force
whismanoid 19:8f951e448ab1 1224 /// @param[in] channel_RTD_Hi = channel RTD high side sense
whismanoid 19:8f951e448ab1 1225 /// @param[in] channel_RTD_Lo = channel RTD low side
whismanoid 19:8f951e448ab1 1226 /// @post TODO: where does the measurement go? struct member?
whismanoid 19:8f951e448ab1 1227 ///
whismanoid 19:8f951e448ab1 1228 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1229 uint8_t Measure_RTD(MAX11410_AINP_SEL_enum_t channel_RTD_Force, MAX11410_AINP_SEL_enum_t channel_RTD_Hi, MAX11410_AINN_SEL_enum_t channel_RTD_Lo);
whismanoid 19:8f951e448ab1 1230
whismanoid 19:8f951e448ab1 1231 //----------------------------------------
whismanoid 19:8f951e448ab1 1232 /// Configure Measurement for Thermocouple
whismanoid 19:8f951e448ab1 1233 ///
whismanoid 19:8f951e448ab1 1234 /// Example code for typical Thermocouple measurement.
whismanoid 19:8f951e448ab1 1235 ///
whismanoid 19:8f951e448ab1 1236 /// @param[in] channel_TC_Hi = channel of Thermocouple high side
whismanoid 19:8f951e448ab1 1237 /// @param[in] channel_TC_Lo = channel of Thermocouple low side
whismanoid 19:8f951e448ab1 1238 /// @param[in] channel_RTD_Hi = channel of cold junction RTD high side
whismanoid 19:8f951e448ab1 1239 /// @param[in] channel_RTD_Lo = channel of cold junction RTD low side
whismanoid 19:8f951e448ab1 1240 ///
whismanoid 19:8f951e448ab1 1241 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1242 uint8_t Configure_Thermocouple(MAX11410_AINP_SEL_enum_t channel_TC_Hi, MAX11410_AINN_SEL_enum_t channel_TC_Lo, MAX11410_AINP_SEL_enum_t channel_RTD_Hi, MAX11410_AINP_SEL_enum_t channel_RTD_Lo);
whismanoid 19:8f951e448ab1 1243
whismanoid 19:8f951e448ab1 1244 //----------------------------------------
whismanoid 19:8f951e448ab1 1245 /// Trigger Measurement for Thermocouple
whismanoid 19:8f951e448ab1 1246 ///
whismanoid 19:8f951e448ab1 1247 /// Example code for typical Thermocouple measurement.
whismanoid 19:8f951e448ab1 1248 ///
whismanoid 19:8f951e448ab1 1249 /// @param[in] channel_TC_Hi = channel of Thermocouple high side
whismanoid 19:8f951e448ab1 1250 /// @param[in] channel_TC_Lo = channel of Thermocouple low side
whismanoid 19:8f951e448ab1 1251 /// @param[in] channel_RTD_Hi = channel of cold junction RTD high side
whismanoid 19:8f951e448ab1 1252 /// @param[in] channel_RTD_Lo = channel of cold junction RTD low side
whismanoid 19:8f951e448ab1 1253 /// @post TODO: where does the measurement go? struct member?
whismanoid 19:8f951e448ab1 1254 ///
whismanoid 19:8f951e448ab1 1255 /// @return 1 on success; 0 on failure
whismanoid 19:8f951e448ab1 1256 uint8_t Measure_Thermocouple(MAX11410_AINP_SEL_enum_t channel_TC_Hi, MAX11410_AINN_SEL_enum_t channel_TC_Lo, MAX11410_AINP_SEL_enum_t channel_RTD_Hi, MAX11410_AINP_SEL_enum_t channel_RTD_Lo);
whismanoid 19:8f951e448ab1 1257
whismanoid 19:8f951e448ab1 1258 }; // end of class MAX11410
whismanoid 19:8f951e448ab1 1259
whismanoid 19:8f951e448ab1 1260 #endif // __MAX11410_H__
whismanoid 19:8f951e448ab1 1261
whismanoid 19:8f951e448ab1 1262 // End of file