Maxim Integrated / MAX11131

Maxim Integrated MAX11131 SPI 12-bit 16-channel ADC with SampleSet

Dependents:   MAX11131BOB_Tester MAX11131BOB_12bit_16ch_SampleSet_SPI_ADC MAX11131BOB_Serial_Tester

MAX11131.h@5:6ef046dbe77e, 2019-08-04 (annotated)

Committer:
whismanoid
Date:
Sun Aug 04 01:16:46 2019 -0700
Revision:
5:6ef046dbe77e
Parent:
4:8a0ae95546fa
Child:
6:cb7bdeb185d0
CodeGenerator MAX11131 ifndef guards sorted

Who changed what in which revision?

UserRevisionLine numberNew contents of line
whismanoid 1:77f1ee332e4a 1 // /*******************************************************************************
whismanoid 0:f7d706d2904d 2 // * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid 0:f7d706d2904d 3 // *
whismanoid 0:f7d706d2904d 4 // * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid 0:f7d706d2904d 5 // * copy of this software and associated documentation files (the "Software"),
whismanoid 0:f7d706d2904d 6 // * to deal in the Software without restriction, including without limitation
whismanoid 0:f7d706d2904d 7 // * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid 0:f7d706d2904d 8 // * and/or sell copies of the Software, and to permit persons to whom the
whismanoid 0:f7d706d2904d 9 // * Software is furnished to do so, subject to the following conditions:
whismanoid 0:f7d706d2904d 10 // *
whismanoid 0:f7d706d2904d 11 // * The above copyright notice and this permission notice shall be included
whismanoid 0:f7d706d2904d 12 // * in all copies or substantial portions of the Software.
whismanoid 0:f7d706d2904d 13 // *
whismanoid 0:f7d706d2904d 14 // * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid 0:f7d706d2904d 15 // * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid 0:f7d706d2904d 16 // * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid 0:f7d706d2904d 17 // * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid 0:f7d706d2904d 18 // * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid 0:f7d706d2904d 19 // * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid 0:f7d706d2904d 20 // * OTHER DEALINGS IN THE SOFTWARE.
whismanoid 0:f7d706d2904d 21 // *
whismanoid 0:f7d706d2904d 22 // * Except as contained in this notice, the name of Maxim Integrated
whismanoid 0:f7d706d2904d 23 // * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid 0:f7d706d2904d 24 // * Products, Inc. Branding Policy.
whismanoid 0:f7d706d2904d 25 // *
whismanoid 0:f7d706d2904d 26 // * The mere transfer of this software does not imply any licenses
whismanoid 0:f7d706d2904d 27 // * of trade secrets, proprietary technology, copyrights, patents,
whismanoid 0:f7d706d2904d 28 // * trademarks, maskwork rights, or any other form of intellectual
whismanoid 0:f7d706d2904d 29 // * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid 0:f7d706d2904d 30 // * ownership rights.
whismanoid 0:f7d706d2904d 31 // *******************************************************************************
whismanoid 0:f7d706d2904d 32 // */
whismanoid 0:f7d706d2904d 33 // *********************************************************************
whismanoid 0:f7d706d2904d 34 // @file MAX11131.h
whismanoid 0:f7d706d2904d 35 // *********************************************************************
whismanoid 0:f7d706d2904d 36 // Header file
whismanoid 0:f7d706d2904d 37 // DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid 0:f7d706d2904d 38 // generated by XMLSystemOfDevicesToMBED.py
whismanoid 0:f7d706d2904d 39 // System Name = ExampleSystem
whismanoid 0:f7d706d2904d 40 // System Description = Device driver example
whismanoid 0:f7d706d2904d 41 // Device Name = MAX11131
whismanoid 0:f7d706d2904d 42 // Device Description = 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid 0:f7d706d2904d 43 // Device Manufacturer = Maxim Integrated
whismanoid 0:f7d706d2904d 44 // Device PartNumber = MAX11131ATI+
whismanoid 0:f7d706d2904d 45 // Device RegValue_Width = DataWidth16bit_HL
whismanoid 0:f7d706d2904d 46 //
whismanoid 0:f7d706d2904d 47 // ADC MaxOutputDataRate = 3Msps
whismanoid 0:f7d706d2904d 48 // ADC NumChannels = 16
whismanoid 0:f7d706d2904d 49 // ADC ResolutionBits = 12
whismanoid 0:f7d706d2904d 50 //
whismanoid 0:f7d706d2904d 51 // SPI CS = ActiveLow
whismanoid 0:f7d706d2904d 52 // SPI FrameStart = CS
whismanoid 0:f7d706d2904d 53 // SPI CPOL = 1
whismanoid 0:f7d706d2904d 54 // SPI CPHA = 1
whismanoid 0:f7d706d2904d 55 // SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid 0:f7d706d2904d 56 // SPI SCLK Idle High
whismanoid 0:f7d706d2904d 57 // SPI SCLKMaxMHz = 48
whismanoid 0:f7d706d2904d 58 // SPI SCLKMinMHz = 0.48
whismanoid 0:f7d706d2904d 59 //
whismanoid 0:f7d706d2904d 60
whismanoid 0:f7d706d2904d 61
whismanoid 0:f7d706d2904d 62 // Prevent multiple declaration
whismanoid 0:f7d706d2904d 63 #ifndef __MAX11131_H__
whismanoid 0:f7d706d2904d 64 #define __MAX11131_H__
whismanoid 0:f7d706d2904d 65
whismanoid 5:6ef046dbe77e 66 // standard include for target platform
whismanoid 0:f7d706d2904d 67 #include "mbed.h"
whismanoid 0:f7d706d2904d 68
whismanoid 0:f7d706d2904d 69 // CODE GENERATOR: conditional defines
whismanoid 0:f7d706d2904d 70 //----------------------------------------
whismanoid 0:f7d706d2904d 71 // Global setting for all channels: ADC_CONFIGURATION.REFSEL
whismanoid 0:f7d706d2904d 72 //
whismanoid 0:f7d706d2904d 73 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 74 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 75 //--------------------
whismanoid 0:f7d706d2904d 76 // external single-ended reference
whismanoid 0:f7d706d2904d 77 //~ #define REFSEL_0 1
whismanoid 0:f7d706d2904d 78 //
whismanoid 0:f7d706d2904d 79 //--------------------
whismanoid 0:f7d706d2904d 80 // external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid 0:f7d706d2904d 81 //~ #define REFSEL_1 1
whismanoid 0:f7d706d2904d 82 //
whismanoid 0:f7d706d2904d 83 //--------------------
whismanoid 0:f7d706d2904d 84 //
whismanoid 0:f7d706d2904d 85 // Default settings if not defined at project level
whismanoid 0:f7d706d2904d 86 #ifndef REFSEL_0
whismanoid 0:f7d706d2904d 87 # ifndef REFSEL_1
whismanoid 0:f7d706d2904d 88 # define REFSEL_0 1
whismanoid 0:f7d706d2904d 89 # define REFSEL_1 0
whismanoid 0:f7d706d2904d 90 # endif // REFSEL_1
whismanoid 0:f7d706d2904d 91 #endif // REFSEL_0
whismanoid 0:f7d706d2904d 92 //
whismanoid 0:f7d706d2904d 93 // (optional diagnostic) pragma message the active setting
whismanoid 0:f7d706d2904d 94 #if REFSEL_0
whismanoid 0:f7d706d2904d 95 //~ # pragma message("REFSEL_0: external single-ended reference")
whismanoid 0:f7d706d2904d 96 #endif // REFSEL_0
whismanoid 0:f7d706d2904d 97 #if REFSEL_1
whismanoid 0:f7d706d2904d 98 //~ # pragma message("REFSEL_1: external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)")
whismanoid 0:f7d706d2904d 99 #endif // REFSEL_1
whismanoid 0:f7d706d2904d 100 //
whismanoid 0:f7d706d2904d 101 // Validate the REFSEL_0 setting
whismanoid 0:f7d706d2904d 102 #if REFSEL_0
whismanoid 0:f7d706d2904d 103 # if REFSEL_1
whismanoid 0:f7d706d2904d 104 # error("cannot have both REFSEL_0 and REFSEL_1; choose one")
whismanoid 0:f7d706d2904d 105 # endif // REFSEL_1
whismanoid 0:f7d706d2904d 106 #endif // REFSEL_0
whismanoid 0:f7d706d2904d 107
whismanoid 0:f7d706d2904d 108 //----------------------------------------
whismanoid 0:f7d706d2904d 109 // Global setting for all channels: UNIPOLAR.PDIFF_COMM
whismanoid 0:f7d706d2904d 110 //
whismanoid 0:f7d706d2904d 111 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 112 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 113 //--------------------
whismanoid 5:6ef046dbe77e 114 // all single-ended channels use GND as common
whismanoid 5:6ef046dbe77e 115 //~ #define PDIFF_COMM_0 1
whismanoid 5:6ef046dbe77e 116 //
whismanoid 5:6ef046dbe77e 117 //--------------------
whismanoid 0:f7d706d2904d 118 // all single-ended channels are pseudo-differential with REF- as common
whismanoid 0:f7d706d2904d 119 //~ #define PDIFF_COMM_1 1
whismanoid 0:f7d706d2904d 120 //
whismanoid 0:f7d706d2904d 121 //--------------------
whismanoid 0:f7d706d2904d 122 //
whismanoid 0:f7d706d2904d 123 // Default settings if not defined at project level
whismanoid 5:6ef046dbe77e 124 #ifndef PDIFF_COMM_0
whismanoid 5:6ef046dbe77e 125 # ifndef PDIFF_COMM_1
whismanoid 5:6ef046dbe77e 126 # define PDIFF_COMM_0 1
whismanoid 0:f7d706d2904d 127 # define PDIFF_COMM_1 0
whismanoid 5:6ef046dbe77e 128 # endif // PDIFF_COMM_1
whismanoid 5:6ef046dbe77e 129 #endif // PDIFF_COMM_0
whismanoid 0:f7d706d2904d 130 //
whismanoid 0:f7d706d2904d 131 // (optional diagnostic) pragma message the active setting
whismanoid 5:6ef046dbe77e 132 #if PDIFF_COMM_0
whismanoid 5:6ef046dbe77e 133 //~ # pragma message("PDIFF_COMM_0: all single-ended channels use GND as common")
whismanoid 5:6ef046dbe77e 134 #endif // PDIFF_COMM_0
whismanoid 0:f7d706d2904d 135 #if PDIFF_COMM_1
whismanoid 0:f7d706d2904d 136 //~ # pragma message("PDIFF_COMM_1: all single-ended channels are pseudo-differential with REF- as common")
whismanoid 0:f7d706d2904d 137 #endif // PDIFF_COMM_1
whismanoid 5:6ef046dbe77e 138 //
whismanoid 5:6ef046dbe77e 139 // Validate the PDIFF_COMM_0 setting
whismanoid 0:f7d706d2904d 140 #if PDIFF_COMM_0
whismanoid 5:6ef046dbe77e 141 # if PDIFF_COMM_1
whismanoid 5:6ef046dbe77e 142 # error("cannot have both PDIFF_COMM_0 and PDIFF_COMM_1; choose one")
whismanoid 5:6ef046dbe77e 143 # endif // PDIFF_COMM_1
whismanoid 0:f7d706d2904d 144 #endif // PDIFF_COMM_0
whismanoid 0:f7d706d2904d 145
whismanoid 0:f7d706d2904d 146 //----------------------------------------
whismanoid 0:f7d706d2904d 147 // ADC Channels AIN0, AIN1
whismanoid 0:f7d706d2904d 148 //
whismanoid 0:f7d706d2904d 149 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 150 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 151 //--------------------
whismanoid 5:6ef046dbe77e 152 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 5:6ef046dbe77e 153 // Full Scale = 2 * VREF
whismanoid 0:f7d706d2904d 154 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 155 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 0:f7d706d2904d 156 // AIN0 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 157 // AIN1 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 158 //
whismanoid 5:6ef046dbe77e 159 //~ #define AIN_0_1_DifferentialBipolarFS2Vref 1
whismanoid 0:f7d706d2904d 160 //
whismanoid 0:f7d706d2904d 161 //--------------------
whismanoid 0:f7d706d2904d 162 // ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid 0:f7d706d2904d 163 // Full Scale = VREF
whismanoid 0:f7d706d2904d 164 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 165 // AIN0, AIN1 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 0:f7d706d2904d 166 // AIN0 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 167 // AIN1 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 168 //
whismanoid 0:f7d706d2904d 169 //~ #define AIN_0_1_DifferentialBipolarFSVref 1
whismanoid 0:f7d706d2904d 170 //
whismanoid 0:f7d706d2904d 171 //--------------------
whismanoid 5:6ef046dbe77e 172 // ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)
whismanoid 5:6ef046dbe77e 173 // Full Scale = VREF
whismanoid 0:f7d706d2904d 174 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 175 // AIN0, AIN1 are a Differential pair using Unipolar transfer function.
whismanoid 0:f7d706d2904d 176 // AIN0 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 177 // AIN1 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 178 //
whismanoid 5:6ef046dbe77e 179 //~ #define AIN_0_1_DifferentialUnipolar 1
whismanoid 0:f7d706d2904d 180 //
whismanoid 0:f7d706d2904d 181 //--------------------
whismanoid 0:f7d706d2904d 182 // ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar
whismanoid 0:f7d706d2904d 183 // Full Scale = VREF
whismanoid 0:f7d706d2904d 184 // Voltage per LSB count = VREF/2048
whismanoid 0:f7d706d2904d 185 // AIN0 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 186 // AIN1 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 187 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 0:f7d706d2904d 188 // AIN0 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 189 // AIN1 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 190 //
whismanoid 0:f7d706d2904d 191 //~ #define AIN_0_1_SingleEnded 1
whismanoid 0:f7d706d2904d 192 //
whismanoid 0:f7d706d2904d 193 //--------------------
whismanoid 0:f7d706d2904d 194 //
whismanoid 0:f7d706d2904d 195 // Default settings if not defined at project level
whismanoid 5:6ef046dbe77e 196 #ifndef AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 197 # ifndef AIN_0_1_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 198 # ifndef AIN_0_1_DifferentialUnipolar
whismanoid 0:f7d706d2904d 199 # ifndef AIN_0_1_SingleEnded
whismanoid 5:6ef046dbe77e 200 # define AIN_0_1_DifferentialBipolarFS2Vref 0
whismanoid 5:6ef046dbe77e 201 # define AIN_0_1_DifferentialBipolarFSVref 0
whismanoid 0:f7d706d2904d 202 # define AIN_0_1_DifferentialUnipolar 0
whismanoid 0:f7d706d2904d 203 # define AIN_0_1_SingleEnded 1
whismanoid 0:f7d706d2904d 204 # endif // AIN_0_1_SingleEnded
whismanoid 5:6ef046dbe77e 205 # endif // AIN_0_1_DifferentialUnipolar
whismanoid 0:f7d706d2904d 206 # endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 207 #endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 208 //
whismanoid 0:f7d706d2904d 209 // (optional diagnostic) pragma message the active setting
whismanoid 5:6ef046dbe77e 210 #if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 211 //~ # pragma message("AIN_0_1_DifferentialBipolarFS2Vref: ADC Channels AIN0, AIN1 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 212 #endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 213 #if AIN_0_1_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 214 //~ # pragma message("AIN_0_1_DifferentialBipolarFSVref: ADC Channels AIN0, AIN1 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 215 #endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 216 #if AIN_0_1_DifferentialUnipolar
whismanoid 0:f7d706d2904d 217 //~ # pragma message("AIN_0_1_DifferentialUnipolar: ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)")
whismanoid 0:f7d706d2904d 218 #endif // AIN_0_1_DifferentialUnipolar
whismanoid 0:f7d706d2904d 219 #if AIN_0_1_SingleEnded
whismanoid 0:f7d706d2904d 220 //~ # pragma message("AIN_0_1_SingleEnded: ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar")
whismanoid 0:f7d706d2904d 221 #endif // AIN_0_1_SingleEnded
whismanoid 0:f7d706d2904d 222 //
whismanoid 5:6ef046dbe77e 223 // Validate the AIN_0_1_DifferentialBipolarFS2Vref setting
whismanoid 5:6ef046dbe77e 224 #if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 225 # if AIN_0_1_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 226 # error("cannot have both AIN_0_1_DifferentialBipolarFS2Vref and AIN_0_1_DifferentialBipolarFSVref; choose one")
whismanoid 0:f7d706d2904d 227 # endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 228 # if AIN_0_1_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 229 # error("cannot have both AIN_0_1_DifferentialBipolarFS2Vref and AIN_0_1_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 230 # endif // AIN_0_1_DifferentialUnipolar
whismanoid 0:f7d706d2904d 231 # if AIN_0_1_SingleEnded
whismanoid 5:6ef046dbe77e 232 # error("cannot have both AIN_0_1_DifferentialBipolarFS2Vref and AIN_0_1_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 233 # endif // AIN_0_1_SingleEnded
whismanoid 5:6ef046dbe77e 234 #endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 235 //
whismanoid 0:f7d706d2904d 236 // Validate the AIN_0_1_DifferentialBipolarFSVref setting
whismanoid 0:f7d706d2904d 237 #if AIN_0_1_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 238 # if AIN_0_1_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 239 # error("cannot have both AIN_0_1_DifferentialBipolarFSVref and AIN_0_1_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 240 # endif // AIN_0_1_DifferentialUnipolar
whismanoid 0:f7d706d2904d 241 # if AIN_0_1_SingleEnded
whismanoid 0:f7d706d2904d 242 # error("cannot have both AIN_0_1_DifferentialBipolarFSVref and AIN_0_1_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 243 # endif // AIN_0_1_SingleEnded
whismanoid 0:f7d706d2904d 244 #endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 245 //
whismanoid 5:6ef046dbe77e 246 // Validate the AIN_0_1_DifferentialUnipolar setting
whismanoid 5:6ef046dbe77e 247 #if AIN_0_1_DifferentialUnipolar
whismanoid 0:f7d706d2904d 248 # if AIN_0_1_SingleEnded
whismanoid 5:6ef046dbe77e 249 # error("cannot have both AIN_0_1_DifferentialUnipolar and AIN_0_1_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 250 # endif // AIN_0_1_SingleEnded
whismanoid 5:6ef046dbe77e 251 #endif // AIN_0_1_DifferentialUnipolar
whismanoid 0:f7d706d2904d 252
whismanoid 0:f7d706d2904d 253 //----------------------------------------
whismanoid 0:f7d706d2904d 254 // ADC Channels AIN2, AIN3
whismanoid 0:f7d706d2904d 255 //
whismanoid 0:f7d706d2904d 256 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 257 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 258 //--------------------
whismanoid 0:f7d706d2904d 259 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 5:6ef046dbe77e 260 // Full Scale = 2 * VREF
whismanoid 5:6ef046dbe77e 261 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 262 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 5:6ef046dbe77e 263 // AIN2 voltage must always be between 0 and VREF.
whismanoid 5:6ef046dbe77e 264 // AIN3 voltage must always be between 0 and VREF.
whismanoid 5:6ef046dbe77e 265 //
whismanoid 5:6ef046dbe77e 266 //~ #define AIN_2_3_DifferentialBipolarFS2Vref 1
whismanoid 5:6ef046dbe77e 267 //
whismanoid 5:6ef046dbe77e 268 //--------------------
whismanoid 5:6ef046dbe77e 269 // ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid 0:f7d706d2904d 270 // Full Scale = VREF
whismanoid 0:f7d706d2904d 271 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 272 // AIN2, AIN3 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 0:f7d706d2904d 273 // AIN2 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 274 // AIN3 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 275 //
whismanoid 0:f7d706d2904d 276 //~ #define AIN_2_3_DifferentialBipolarFSVref 1
whismanoid 0:f7d706d2904d 277 //
whismanoid 0:f7d706d2904d 278 //--------------------
whismanoid 5:6ef046dbe77e 279 // ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)
whismanoid 5:6ef046dbe77e 280 // Full Scale = VREF
whismanoid 0:f7d706d2904d 281 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 282 // AIN2, AIN3 are a Differential pair using Unipolar transfer function.
whismanoid 0:f7d706d2904d 283 // AIN2 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 284 // AIN3 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 285 //
whismanoid 5:6ef046dbe77e 286 //~ #define AIN_2_3_DifferentialUnipolar 1
whismanoid 0:f7d706d2904d 287 //
whismanoid 0:f7d706d2904d 288 //--------------------
whismanoid 0:f7d706d2904d 289 // ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar
whismanoid 0:f7d706d2904d 290 // Full Scale = VREF
whismanoid 0:f7d706d2904d 291 // Voltage per LSB count = VREF/2048
whismanoid 0:f7d706d2904d 292 // AIN2 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 293 // AIN3 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 294 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 0:f7d706d2904d 295 // AIN2 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 296 // AIN3 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 297 //
whismanoid 0:f7d706d2904d 298 //~ #define AIN_2_3_SingleEnded 1
whismanoid 0:f7d706d2904d 299 //
whismanoid 0:f7d706d2904d 300 //--------------------
whismanoid 0:f7d706d2904d 301 //
whismanoid 0:f7d706d2904d 302 // Default settings if not defined at project level
whismanoid 5:6ef046dbe77e 303 #ifndef AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 304 # ifndef AIN_2_3_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 305 # ifndef AIN_2_3_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 306 # ifndef AIN_2_3_SingleEnded
whismanoid 5:6ef046dbe77e 307 # define AIN_2_3_DifferentialBipolarFS2Vref 0
whismanoid 0:f7d706d2904d 308 # define AIN_2_3_DifferentialBipolarFSVref 0
whismanoid 5:6ef046dbe77e 309 # define AIN_2_3_DifferentialUnipolar 0
whismanoid 0:f7d706d2904d 310 # define AIN_2_3_SingleEnded 1
whismanoid 5:6ef046dbe77e 311 # endif // AIN_2_3_SingleEnded
whismanoid 5:6ef046dbe77e 312 # endif // AIN_2_3_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 313 # endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 314 #endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 315 //
whismanoid 0:f7d706d2904d 316 // (optional diagnostic) pragma message the active setting
whismanoid 5:6ef046dbe77e 317 #if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 318 //~ # pragma message("AIN_2_3_DifferentialBipolarFS2Vref: ADC Channels AIN2, AIN3 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 319 #endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 320 #if AIN_2_3_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 321 //~ # pragma message("AIN_2_3_DifferentialBipolarFSVref: ADC Channels AIN2, AIN3 = Differential Bipolar")
whismanoid 0:f7d706d2904d 322 #endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 323 #if AIN_2_3_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 324 //~ # pragma message("AIN_2_3_DifferentialUnipolar: ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)")
whismanoid 5:6ef046dbe77e 325 #endif // AIN_2_3_DifferentialUnipolar
whismanoid 0:f7d706d2904d 326 #if AIN_2_3_SingleEnded
whismanoid 0:f7d706d2904d 327 //~ # pragma message("AIN_2_3_SingleEnded: ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar")
whismanoid 0:f7d706d2904d 328 #endif // AIN_2_3_SingleEnded
whismanoid 5:6ef046dbe77e 329 //
whismanoid 5:6ef046dbe77e 330 // Validate the AIN_2_3_DifferentialBipolarFS2Vref setting
whismanoid 5:6ef046dbe77e 331 #if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 332 # if AIN_2_3_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 333 # error("cannot have both AIN_2_3_DifferentialBipolarFS2Vref and AIN_2_3_DifferentialBipolarFSVref; choose one")
whismanoid 5:6ef046dbe77e 334 # endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 335 # if AIN_2_3_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 336 # error("cannot have both AIN_2_3_DifferentialBipolarFS2Vref and AIN_2_3_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 337 # endif // AIN_2_3_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 338 # if AIN_2_3_SingleEnded
whismanoid 5:6ef046dbe77e 339 # error("cannot have both AIN_2_3_DifferentialBipolarFS2Vref and AIN_2_3_SingleEnded; choose one")
whismanoid 5:6ef046dbe77e 340 # endif // AIN_2_3_SingleEnded
whismanoid 5:6ef046dbe77e 341 #endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 342 //
whismanoid 0:f7d706d2904d 343 // Validate the AIN_2_3_DifferentialBipolarFSVref setting
whismanoid 0:f7d706d2904d 344 #if AIN_2_3_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 345 # if AIN_2_3_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 346 # error("cannot have both AIN_2_3_DifferentialBipolarFSVref and AIN_2_3_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 347 # endif // AIN_2_3_DifferentialUnipolar
whismanoid 0:f7d706d2904d 348 # if AIN_2_3_SingleEnded
whismanoid 0:f7d706d2904d 349 # error("cannot have both AIN_2_3_DifferentialBipolarFSVref and AIN_2_3_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 350 # endif // AIN_2_3_SingleEnded
whismanoid 0:f7d706d2904d 351 #endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 352 //
whismanoid 5:6ef046dbe77e 353 // Validate the AIN_2_3_DifferentialUnipolar setting
whismanoid 5:6ef046dbe77e 354 #if AIN_2_3_DifferentialUnipolar
whismanoid 0:f7d706d2904d 355 # if AIN_2_3_SingleEnded
whismanoid 5:6ef046dbe77e 356 # error("cannot have both AIN_2_3_DifferentialUnipolar and AIN_2_3_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 357 # endif // AIN_2_3_SingleEnded
whismanoid 5:6ef046dbe77e 358 #endif // AIN_2_3_DifferentialUnipolar
whismanoid 0:f7d706d2904d 359
whismanoid 0:f7d706d2904d 360 //----------------------------------------
whismanoid 0:f7d706d2904d 361 // ADC Channels AIN4, AIN5
whismanoid 0:f7d706d2904d 362 //
whismanoid 0:f7d706d2904d 363 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 364 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 365 //--------------------
whismanoid 5:6ef046dbe77e 366 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 5:6ef046dbe77e 367 // Full Scale = 2 * VREF
whismanoid 0:f7d706d2904d 368 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 369 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 0:f7d706d2904d 370 // AIN4 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 371 // AIN5 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 372 //
whismanoid 5:6ef046dbe77e 373 //~ #define AIN_4_5_DifferentialBipolarFS2Vref 1
whismanoid 0:f7d706d2904d 374 //
whismanoid 0:f7d706d2904d 375 //--------------------
whismanoid 0:f7d706d2904d 376 // ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid 0:f7d706d2904d 377 // Full Scale = VREF
whismanoid 0:f7d706d2904d 378 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 379 // AIN4, AIN5 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 0:f7d706d2904d 380 // AIN4 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 381 // AIN5 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 382 //
whismanoid 0:f7d706d2904d 383 //~ #define AIN_4_5_DifferentialBipolarFSVref 1
whismanoid 0:f7d706d2904d 384 //
whismanoid 0:f7d706d2904d 385 //--------------------
whismanoid 5:6ef046dbe77e 386 // ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)
whismanoid 5:6ef046dbe77e 387 // Full Scale = VREF
whismanoid 0:f7d706d2904d 388 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 389 // AIN4, AIN5 are a Differential pair using Unipolar transfer function.
whismanoid 0:f7d706d2904d 390 // AIN4 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 391 // AIN5 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 392 //
whismanoid 5:6ef046dbe77e 393 //~ #define AIN_4_5_DifferentialUnipolar 1
whismanoid 0:f7d706d2904d 394 //
whismanoid 0:f7d706d2904d 395 //--------------------
whismanoid 0:f7d706d2904d 396 // ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar
whismanoid 0:f7d706d2904d 397 // Full Scale = VREF
whismanoid 0:f7d706d2904d 398 // Voltage per LSB count = VREF/2048
whismanoid 0:f7d706d2904d 399 // AIN4 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 400 // AIN5 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 401 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 0:f7d706d2904d 402 // AIN4 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 403 // AIN5 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 404 //
whismanoid 0:f7d706d2904d 405 //~ #define AIN_4_5_SingleEnded 1
whismanoid 0:f7d706d2904d 406 //
whismanoid 0:f7d706d2904d 407 //--------------------
whismanoid 0:f7d706d2904d 408 //
whismanoid 0:f7d706d2904d 409 // Default settings if not defined at project level
whismanoid 5:6ef046dbe77e 410 #ifndef AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 411 # ifndef AIN_4_5_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 412 # ifndef AIN_4_5_DifferentialUnipolar
whismanoid 0:f7d706d2904d 413 # ifndef AIN_4_5_SingleEnded
whismanoid 5:6ef046dbe77e 414 # define AIN_4_5_DifferentialBipolarFS2Vref 0
whismanoid 5:6ef046dbe77e 415 # define AIN_4_5_DifferentialBipolarFSVref 0
whismanoid 0:f7d706d2904d 416 # define AIN_4_5_DifferentialUnipolar 0
whismanoid 0:f7d706d2904d 417 # define AIN_4_5_SingleEnded 1
whismanoid 0:f7d706d2904d 418 # endif // AIN_4_5_SingleEnded
whismanoid 5:6ef046dbe77e 419 # endif // AIN_4_5_DifferentialUnipolar
whismanoid 0:f7d706d2904d 420 # endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 421 #endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 422 //
whismanoid 0:f7d706d2904d 423 // (optional diagnostic) pragma message the active setting
whismanoid 5:6ef046dbe77e 424 #if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 425 //~ # pragma message("AIN_4_5_DifferentialBipolarFS2Vref: ADC Channels AIN4, AIN5 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 426 #endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 427 #if AIN_4_5_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 428 //~ # pragma message("AIN_4_5_DifferentialBipolarFSVref: ADC Channels AIN4, AIN5 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 429 #endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 430 #if AIN_4_5_DifferentialUnipolar
whismanoid 0:f7d706d2904d 431 //~ # pragma message("AIN_4_5_DifferentialUnipolar: ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)")
whismanoid 0:f7d706d2904d 432 #endif // AIN_4_5_DifferentialUnipolar
whismanoid 0:f7d706d2904d 433 #if AIN_4_5_SingleEnded
whismanoid 0:f7d706d2904d 434 //~ # pragma message("AIN_4_5_SingleEnded: ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar")
whismanoid 0:f7d706d2904d 435 #endif // AIN_4_5_SingleEnded
whismanoid 0:f7d706d2904d 436 //
whismanoid 5:6ef046dbe77e 437 // Validate the AIN_4_5_DifferentialBipolarFS2Vref setting
whismanoid 5:6ef046dbe77e 438 #if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 439 # if AIN_4_5_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 440 # error("cannot have both AIN_4_5_DifferentialBipolarFS2Vref and AIN_4_5_DifferentialBipolarFSVref; choose one")
whismanoid 0:f7d706d2904d 441 # endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 442 # if AIN_4_5_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 443 # error("cannot have both AIN_4_5_DifferentialBipolarFS2Vref and AIN_4_5_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 444 # endif // AIN_4_5_DifferentialUnipolar
whismanoid 0:f7d706d2904d 445 # if AIN_4_5_SingleEnded
whismanoid 5:6ef046dbe77e 446 # error("cannot have both AIN_4_5_DifferentialBipolarFS2Vref and AIN_4_5_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 447 # endif // AIN_4_5_SingleEnded
whismanoid 5:6ef046dbe77e 448 #endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 449 //
whismanoid 0:f7d706d2904d 450 // Validate the AIN_4_5_DifferentialBipolarFSVref setting
whismanoid 0:f7d706d2904d 451 #if AIN_4_5_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 452 # if AIN_4_5_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 453 # error("cannot have both AIN_4_5_DifferentialBipolarFSVref and AIN_4_5_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 454 # endif // AIN_4_5_DifferentialUnipolar
whismanoid 0:f7d706d2904d 455 # if AIN_4_5_SingleEnded
whismanoid 0:f7d706d2904d 456 # error("cannot have both AIN_4_5_DifferentialBipolarFSVref and AIN_4_5_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 457 # endif // AIN_4_5_SingleEnded
whismanoid 0:f7d706d2904d 458 #endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 459 //
whismanoid 5:6ef046dbe77e 460 // Validate the AIN_4_5_DifferentialUnipolar setting
whismanoid 5:6ef046dbe77e 461 #if AIN_4_5_DifferentialUnipolar
whismanoid 0:f7d706d2904d 462 # if AIN_4_5_SingleEnded
whismanoid 5:6ef046dbe77e 463 # error("cannot have both AIN_4_5_DifferentialUnipolar and AIN_4_5_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 464 # endif // AIN_4_5_SingleEnded
whismanoid 5:6ef046dbe77e 465 #endif // AIN_4_5_DifferentialUnipolar
whismanoid 0:f7d706d2904d 466
whismanoid 0:f7d706d2904d 467 //----------------------------------------
whismanoid 0:f7d706d2904d 468 // ADC Channels AIN6, AIN7
whismanoid 0:f7d706d2904d 469 //
whismanoid 0:f7d706d2904d 470 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 471 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 472 //--------------------
whismanoid 0:f7d706d2904d 473 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 5:6ef046dbe77e 474 // Full Scale = 2 * VREF
whismanoid 5:6ef046dbe77e 475 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 476 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 5:6ef046dbe77e 477 // AIN6 voltage must always be between 0 and VREF.
whismanoid 5:6ef046dbe77e 478 // AIN7 voltage must always be between 0 and VREF.
whismanoid 5:6ef046dbe77e 479 //
whismanoid 5:6ef046dbe77e 480 //~ #define AIN_6_7_DifferentialBipolarFS2Vref 1
whismanoid 5:6ef046dbe77e 481 //
whismanoid 5:6ef046dbe77e 482 //--------------------
whismanoid 5:6ef046dbe77e 483 // ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid 0:f7d706d2904d 484 // Full Scale = VREF
whismanoid 0:f7d706d2904d 485 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 486 // AIN6, AIN7 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 0:f7d706d2904d 487 // AIN6 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 488 // AIN7 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 489 //
whismanoid 0:f7d706d2904d 490 //~ #define AIN_6_7_DifferentialBipolarFSVref 1
whismanoid 0:f7d706d2904d 491 //
whismanoid 0:f7d706d2904d 492 //--------------------
whismanoid 5:6ef046dbe77e 493 // ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)
whismanoid 5:6ef046dbe77e 494 // Full Scale = VREF
whismanoid 0:f7d706d2904d 495 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 496 // AIN6, AIN7 are a Differential pair using Unipolar transfer function.
whismanoid 0:f7d706d2904d 497 // AIN6 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 498 // AIN7 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 499 //
whismanoid 5:6ef046dbe77e 500 //~ #define AIN_6_7_DifferentialUnipolar 1
whismanoid 0:f7d706d2904d 501 //
whismanoid 0:f7d706d2904d 502 //--------------------
whismanoid 0:f7d706d2904d 503 // ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar
whismanoid 0:f7d706d2904d 504 // Full Scale = VREF
whismanoid 0:f7d706d2904d 505 // Voltage per LSB count = VREF/2048
whismanoid 0:f7d706d2904d 506 // AIN6 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 507 // AIN7 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 508 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 0:f7d706d2904d 509 // AIN6 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 510 // AIN7 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 511 //
whismanoid 0:f7d706d2904d 512 //~ #define AIN_6_7_SingleEnded 1
whismanoid 0:f7d706d2904d 513 //
whismanoid 0:f7d706d2904d 514 //--------------------
whismanoid 0:f7d706d2904d 515 //
whismanoid 0:f7d706d2904d 516 // Default settings if not defined at project level
whismanoid 5:6ef046dbe77e 517 #ifndef AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 518 # ifndef AIN_6_7_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 519 # ifndef AIN_6_7_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 520 # ifndef AIN_6_7_SingleEnded
whismanoid 5:6ef046dbe77e 521 # define AIN_6_7_DifferentialBipolarFS2Vref 0
whismanoid 0:f7d706d2904d 522 # define AIN_6_7_DifferentialBipolarFSVref 0
whismanoid 5:6ef046dbe77e 523 # define AIN_6_7_DifferentialUnipolar 0
whismanoid 0:f7d706d2904d 524 # define AIN_6_7_SingleEnded 1
whismanoid 5:6ef046dbe77e 525 # endif // AIN_6_7_SingleEnded
whismanoid 5:6ef046dbe77e 526 # endif // AIN_6_7_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 527 # endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 528 #endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 529 //
whismanoid 0:f7d706d2904d 530 // (optional diagnostic) pragma message the active setting
whismanoid 5:6ef046dbe77e 531 #if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 532 //~ # pragma message("AIN_6_7_DifferentialBipolarFS2Vref: ADC Channels AIN6, AIN7 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 533 #endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 534 #if AIN_6_7_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 535 //~ # pragma message("AIN_6_7_DifferentialBipolarFSVref: ADC Channels AIN6, AIN7 = Differential Bipolar")
whismanoid 0:f7d706d2904d 536 #endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 537 #if AIN_6_7_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 538 //~ # pragma message("AIN_6_7_DifferentialUnipolar: ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)")
whismanoid 5:6ef046dbe77e 539 #endif // AIN_6_7_DifferentialUnipolar
whismanoid 0:f7d706d2904d 540 #if AIN_6_7_SingleEnded
whismanoid 0:f7d706d2904d 541 //~ # pragma message("AIN_6_7_SingleEnded: ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar")
whismanoid 0:f7d706d2904d 542 #endif // AIN_6_7_SingleEnded
whismanoid 5:6ef046dbe77e 543 //
whismanoid 5:6ef046dbe77e 544 // Validate the AIN_6_7_DifferentialBipolarFS2Vref setting
whismanoid 5:6ef046dbe77e 545 #if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 546 # if AIN_6_7_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 547 # error("cannot have both AIN_6_7_DifferentialBipolarFS2Vref and AIN_6_7_DifferentialBipolarFSVref; choose one")
whismanoid 5:6ef046dbe77e 548 # endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 549 # if AIN_6_7_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 550 # error("cannot have both AIN_6_7_DifferentialBipolarFS2Vref and AIN_6_7_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 551 # endif // AIN_6_7_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 552 # if AIN_6_7_SingleEnded
whismanoid 5:6ef046dbe77e 553 # error("cannot have both AIN_6_7_DifferentialBipolarFS2Vref and AIN_6_7_SingleEnded; choose one")
whismanoid 5:6ef046dbe77e 554 # endif // AIN_6_7_SingleEnded
whismanoid 5:6ef046dbe77e 555 #endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 556 //
whismanoid 0:f7d706d2904d 557 // Validate the AIN_6_7_DifferentialBipolarFSVref setting
whismanoid 0:f7d706d2904d 558 #if AIN_6_7_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 559 # if AIN_6_7_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 560 # error("cannot have both AIN_6_7_DifferentialBipolarFSVref and AIN_6_7_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 561 # endif // AIN_6_7_DifferentialUnipolar
whismanoid 0:f7d706d2904d 562 # if AIN_6_7_SingleEnded
whismanoid 0:f7d706d2904d 563 # error("cannot have both AIN_6_7_DifferentialBipolarFSVref and AIN_6_7_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 564 # endif // AIN_6_7_SingleEnded
whismanoid 0:f7d706d2904d 565 #endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 566 //
whismanoid 5:6ef046dbe77e 567 // Validate the AIN_6_7_DifferentialUnipolar setting
whismanoid 5:6ef046dbe77e 568 #if AIN_6_7_DifferentialUnipolar
whismanoid 0:f7d706d2904d 569 # if AIN_6_7_SingleEnded
whismanoid 5:6ef046dbe77e 570 # error("cannot have both AIN_6_7_DifferentialUnipolar and AIN_6_7_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 571 # endif // AIN_6_7_SingleEnded
whismanoid 5:6ef046dbe77e 572 #endif // AIN_6_7_DifferentialUnipolar
whismanoid 0:f7d706d2904d 573
whismanoid 0:f7d706d2904d 574 //----------------------------------------
whismanoid 0:f7d706d2904d 575 // ADC Channels AIN8, AIN9
whismanoid 0:f7d706d2904d 576 //
whismanoid 0:f7d706d2904d 577 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 578 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 579 //--------------------
whismanoid 5:6ef046dbe77e 580 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 5:6ef046dbe77e 581 // Full Scale = 2 * VREF
whismanoid 0:f7d706d2904d 582 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 583 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 0:f7d706d2904d 584 // AIN8 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 585 // AIN9 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 586 //
whismanoid 5:6ef046dbe77e 587 //~ #define AIN_8_9_DifferentialBipolarFS2Vref 1
whismanoid 0:f7d706d2904d 588 //
whismanoid 0:f7d706d2904d 589 //--------------------
whismanoid 0:f7d706d2904d 590 // ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid 0:f7d706d2904d 591 // Full Scale = VREF
whismanoid 0:f7d706d2904d 592 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 593 // AIN8, AIN9 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 0:f7d706d2904d 594 // AIN8 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 595 // AIN9 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 596 //
whismanoid 0:f7d706d2904d 597 //~ #define AIN_8_9_DifferentialBipolarFSVref 1
whismanoid 0:f7d706d2904d 598 //
whismanoid 0:f7d706d2904d 599 //--------------------
whismanoid 5:6ef046dbe77e 600 // ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)
whismanoid 5:6ef046dbe77e 601 // Full Scale = VREF
whismanoid 0:f7d706d2904d 602 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 603 // AIN8, AIN9 are a Differential pair using Unipolar transfer function.
whismanoid 0:f7d706d2904d 604 // AIN8 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 605 // AIN9 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 606 //
whismanoid 5:6ef046dbe77e 607 //~ #define AIN_8_9_DifferentialUnipolar 1
whismanoid 0:f7d706d2904d 608 //
whismanoid 0:f7d706d2904d 609 //--------------------
whismanoid 0:f7d706d2904d 610 // ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar
whismanoid 0:f7d706d2904d 611 // Full Scale = VREF
whismanoid 0:f7d706d2904d 612 // Voltage per LSB count = VREF/2048
whismanoid 0:f7d706d2904d 613 // AIN8 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 614 // AIN9 is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 615 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 0:f7d706d2904d 616 // AIN8 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 617 // AIN9 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 618 //
whismanoid 0:f7d706d2904d 619 //~ #define AIN_8_9_SingleEnded 1
whismanoid 0:f7d706d2904d 620 //
whismanoid 0:f7d706d2904d 621 //--------------------
whismanoid 0:f7d706d2904d 622 //
whismanoid 0:f7d706d2904d 623 // Default settings if not defined at project level
whismanoid 5:6ef046dbe77e 624 #ifndef AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 625 # ifndef AIN_8_9_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 626 # ifndef AIN_8_9_DifferentialUnipolar
whismanoid 0:f7d706d2904d 627 # ifndef AIN_8_9_SingleEnded
whismanoid 5:6ef046dbe77e 628 # define AIN_8_9_DifferentialBipolarFS2Vref 0
whismanoid 5:6ef046dbe77e 629 # define AIN_8_9_DifferentialBipolarFSVref 0
whismanoid 0:f7d706d2904d 630 # define AIN_8_9_DifferentialUnipolar 0
whismanoid 0:f7d706d2904d 631 # define AIN_8_9_SingleEnded 1
whismanoid 0:f7d706d2904d 632 # endif // AIN_8_9_SingleEnded
whismanoid 5:6ef046dbe77e 633 # endif // AIN_8_9_DifferentialUnipolar
whismanoid 0:f7d706d2904d 634 # endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 635 #endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 636 //
whismanoid 0:f7d706d2904d 637 // (optional diagnostic) pragma message the active setting
whismanoid 5:6ef046dbe77e 638 #if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 639 //~ # pragma message("AIN_8_9_DifferentialBipolarFS2Vref: ADC Channels AIN8, AIN9 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 640 #endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 641 #if AIN_8_9_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 642 //~ # pragma message("AIN_8_9_DifferentialBipolarFSVref: ADC Channels AIN8, AIN9 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 643 #endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 644 #if AIN_8_9_DifferentialUnipolar
whismanoid 0:f7d706d2904d 645 //~ # pragma message("AIN_8_9_DifferentialUnipolar: ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)")
whismanoid 0:f7d706d2904d 646 #endif // AIN_8_9_DifferentialUnipolar
whismanoid 0:f7d706d2904d 647 #if AIN_8_9_SingleEnded
whismanoid 0:f7d706d2904d 648 //~ # pragma message("AIN_8_9_SingleEnded: ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar")
whismanoid 0:f7d706d2904d 649 #endif // AIN_8_9_SingleEnded
whismanoid 0:f7d706d2904d 650 //
whismanoid 5:6ef046dbe77e 651 // Validate the AIN_8_9_DifferentialBipolarFS2Vref setting
whismanoid 5:6ef046dbe77e 652 #if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 653 # if AIN_8_9_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 654 # error("cannot have both AIN_8_9_DifferentialBipolarFS2Vref and AIN_8_9_DifferentialBipolarFSVref; choose one")
whismanoid 0:f7d706d2904d 655 # endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 656 # if AIN_8_9_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 657 # error("cannot have both AIN_8_9_DifferentialBipolarFS2Vref and AIN_8_9_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 658 # endif // AIN_8_9_DifferentialUnipolar
whismanoid 0:f7d706d2904d 659 # if AIN_8_9_SingleEnded
whismanoid 5:6ef046dbe77e 660 # error("cannot have both AIN_8_9_DifferentialBipolarFS2Vref and AIN_8_9_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 661 # endif // AIN_8_9_SingleEnded
whismanoid 5:6ef046dbe77e 662 #endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 663 //
whismanoid 0:f7d706d2904d 664 // Validate the AIN_8_9_DifferentialBipolarFSVref setting
whismanoid 0:f7d706d2904d 665 #if AIN_8_9_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 666 # if AIN_8_9_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 667 # error("cannot have both AIN_8_9_DifferentialBipolarFSVref and AIN_8_9_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 668 # endif // AIN_8_9_DifferentialUnipolar
whismanoid 0:f7d706d2904d 669 # if AIN_8_9_SingleEnded
whismanoid 0:f7d706d2904d 670 # error("cannot have both AIN_8_9_DifferentialBipolarFSVref and AIN_8_9_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 671 # endif // AIN_8_9_SingleEnded
whismanoid 0:f7d706d2904d 672 #endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 673 //
whismanoid 5:6ef046dbe77e 674 // Validate the AIN_8_9_DifferentialUnipolar setting
whismanoid 5:6ef046dbe77e 675 #if AIN_8_9_DifferentialUnipolar
whismanoid 0:f7d706d2904d 676 # if AIN_8_9_SingleEnded
whismanoid 5:6ef046dbe77e 677 # error("cannot have both AIN_8_9_DifferentialUnipolar and AIN_8_9_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 678 # endif // AIN_8_9_SingleEnded
whismanoid 5:6ef046dbe77e 679 #endif // AIN_8_9_DifferentialUnipolar
whismanoid 0:f7d706d2904d 680
whismanoid 0:f7d706d2904d 681 //----------------------------------------
whismanoid 0:f7d706d2904d 682 // ADC Channels AIN10, AIN11
whismanoid 0:f7d706d2904d 683 //
whismanoid 0:f7d706d2904d 684 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 685 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 686 //--------------------
whismanoid 0:f7d706d2904d 687 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 0:f7d706d2904d 688 // Full Scale = 2 * VREF
whismanoid 0:f7d706d2904d 689 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 690 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 0:f7d706d2904d 691 // AIN10 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 692 // AIN11 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 693 //
whismanoid 0:f7d706d2904d 694 //~ #define AIN_10_11_DifferentialBipolarFS2Vref 1
whismanoid 0:f7d706d2904d 695 //
whismanoid 0:f7d706d2904d 696 //--------------------
whismanoid 5:6ef046dbe77e 697 // ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid 0:f7d706d2904d 698 // Full Scale = VREF
whismanoid 0:f7d706d2904d 699 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 700 // AIN10, AIN11 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 0:f7d706d2904d 701 // AIN10 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 702 // AIN11 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 703 //
whismanoid 5:6ef046dbe77e 704 //~ #define AIN_10_11_DifferentialBipolarFSVref 1
whismanoid 0:f7d706d2904d 705 //
whismanoid 0:f7d706d2904d 706 //--------------------
whismanoid 0:f7d706d2904d 707 // ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)
whismanoid 0:f7d706d2904d 708 // Full Scale = VREF
whismanoid 0:f7d706d2904d 709 // Voltage per LSB count = VREF/2048
whismanoid 0:f7d706d2904d 710 // AIN10, AIN11 are a Differential pair using Unipolar transfer function.
whismanoid 0:f7d706d2904d 711 // AIN10 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 712 // AIN11 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 713 //
whismanoid 0:f7d706d2904d 714 //~ #define AIN_10_11_DifferentialUnipolar 1
whismanoid 0:f7d706d2904d 715 //
whismanoid 0:f7d706d2904d 716 //--------------------
whismanoid 5:6ef046dbe77e 717 // ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar
whismanoid 0:f7d706d2904d 718 // Full Scale = VREF
whismanoid 0:f7d706d2904d 719 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 720 // AIN10 is a Single-Ended input using Unipolar transfer function.
whismanoid 5:6ef046dbe77e 721 // AIN11 is a Single-Ended input using Unipolar transfer function.
whismanoid 5:6ef046dbe77e 722 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 0:f7d706d2904d 723 // AIN10 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 724 // AIN11 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 725 //
whismanoid 5:6ef046dbe77e 726 //~ #define AIN_10_11_SingleEnded 1
whismanoid 0:f7d706d2904d 727 //
whismanoid 0:f7d706d2904d 728 //--------------------
whismanoid 0:f7d706d2904d 729 //
whismanoid 0:f7d706d2904d 730 // Default settings if not defined at project level
whismanoid 0:f7d706d2904d 731 #ifndef AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 732 # ifndef AIN_10_11_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 733 # ifndef AIN_10_11_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 734 # ifndef AIN_10_11_SingleEnded
whismanoid 0:f7d706d2904d 735 # define AIN_10_11_DifferentialBipolarFS2Vref 0
whismanoid 5:6ef046dbe77e 736 # define AIN_10_11_DifferentialBipolarFSVref 0
whismanoid 5:6ef046dbe77e 737 # define AIN_10_11_DifferentialUnipolar 0
whismanoid 0:f7d706d2904d 738 # define AIN_10_11_SingleEnded 1
whismanoid 5:6ef046dbe77e 739 # endif // AIN_10_11_SingleEnded
whismanoid 0:f7d706d2904d 740 # endif // AIN_10_11_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 741 # endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 742 #endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 743 //
whismanoid 0:f7d706d2904d 744 // (optional diagnostic) pragma message the active setting
whismanoid 0:f7d706d2904d 745 #if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 746 //~ # pragma message("AIN_10_11_DifferentialBipolarFS2Vref: ADC Channels AIN10, AIN11 = Differential Bipolar")
whismanoid 0:f7d706d2904d 747 #endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 748 #if AIN_10_11_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 749 //~ # pragma message("AIN_10_11_DifferentialBipolarFSVref: ADC Channels AIN10, AIN11 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 750 #endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 751 #if AIN_10_11_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 752 //~ # pragma message("AIN_10_11_DifferentialUnipolar: ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)")
whismanoid 5:6ef046dbe77e 753 #endif // AIN_10_11_DifferentialUnipolar
whismanoid 0:f7d706d2904d 754 #if AIN_10_11_SingleEnded
whismanoid 0:f7d706d2904d 755 //~ # pragma message("AIN_10_11_SingleEnded: ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar")
whismanoid 0:f7d706d2904d 756 #endif // AIN_10_11_SingleEnded
whismanoid 0:f7d706d2904d 757 //
whismanoid 0:f7d706d2904d 758 // Validate the AIN_10_11_DifferentialBipolarFS2Vref setting
whismanoid 0:f7d706d2904d 759 #if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 760 # if AIN_10_11_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 761 # error("cannot have both AIN_10_11_DifferentialBipolarFS2Vref and AIN_10_11_DifferentialBipolarFSVref; choose one")
whismanoid 5:6ef046dbe77e 762 # endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 763 # if AIN_10_11_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 764 # error("cannot have both AIN_10_11_DifferentialBipolarFS2Vref and AIN_10_11_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 765 # endif // AIN_10_11_DifferentialUnipolar
whismanoid 0:f7d706d2904d 766 # if AIN_10_11_SingleEnded
whismanoid 0:f7d706d2904d 767 # error("cannot have both AIN_10_11_DifferentialBipolarFS2Vref and AIN_10_11_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 768 # endif // AIN_10_11_SingleEnded
whismanoid 0:f7d706d2904d 769 #endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 770 //
whismanoid 5:6ef046dbe77e 771 // Validate the AIN_10_11_DifferentialBipolarFSVref setting
whismanoid 5:6ef046dbe77e 772 #if AIN_10_11_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 773 # if AIN_10_11_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 774 # error("cannot have both AIN_10_11_DifferentialBipolarFSVref and AIN_10_11_DifferentialUnipolar; choose one")
whismanoid 0:f7d706d2904d 775 # endif // AIN_10_11_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 776 # if AIN_10_11_SingleEnded
whismanoid 5:6ef046dbe77e 777 # error("cannot have both AIN_10_11_DifferentialBipolarFSVref and AIN_10_11_SingleEnded; choose one")
whismanoid 5:6ef046dbe77e 778 # endif // AIN_10_11_SingleEnded
whismanoid 5:6ef046dbe77e 779 #endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 780 //
whismanoid 0:f7d706d2904d 781 // Validate the AIN_10_11_DifferentialUnipolar setting
whismanoid 0:f7d706d2904d 782 #if AIN_10_11_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 783 # if AIN_10_11_SingleEnded
whismanoid 5:6ef046dbe77e 784 # error("cannot have both AIN_10_11_DifferentialUnipolar and AIN_10_11_SingleEnded; choose one")
whismanoid 5:6ef046dbe77e 785 # endif // AIN_10_11_SingleEnded
whismanoid 0:f7d706d2904d 786 #endif // AIN_10_11_DifferentialUnipolar
whismanoid 0:f7d706d2904d 787
whismanoid 0:f7d706d2904d 788 //----------------------------------------
whismanoid 0:f7d706d2904d 789 // ADC Channels AIN12, AIN13
whismanoid 0:f7d706d2904d 790 //
whismanoid 0:f7d706d2904d 791 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 792 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 793 //--------------------
whismanoid 0:f7d706d2904d 794 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 0:f7d706d2904d 795 // Full Scale = 2 * VREF
whismanoid 0:f7d706d2904d 796 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 797 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 0:f7d706d2904d 798 // AIN12 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 799 // AIN13 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 800 //
whismanoid 0:f7d706d2904d 801 //~ #define AIN_12_13_DifferentialBipolarFS2Vref 1
whismanoid 0:f7d706d2904d 802 //
whismanoid 0:f7d706d2904d 803 //--------------------
whismanoid 5:6ef046dbe77e 804 // ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid 0:f7d706d2904d 805 // Full Scale = VREF
whismanoid 0:f7d706d2904d 806 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 807 // AIN12, AIN13 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 0:f7d706d2904d 808 // AIN12 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 809 // AIN13 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 810 //
whismanoid 5:6ef046dbe77e 811 //~ #define AIN_12_13_DifferentialBipolarFSVref 1
whismanoid 0:f7d706d2904d 812 //
whismanoid 0:f7d706d2904d 813 //--------------------
whismanoid 0:f7d706d2904d 814 // ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)
whismanoid 0:f7d706d2904d 815 // Full Scale = VREF
whismanoid 0:f7d706d2904d 816 // Voltage per LSB count = VREF/2048
whismanoid 0:f7d706d2904d 817 // AIN12, AIN13 are a Differential pair using Unipolar transfer function.
whismanoid 0:f7d706d2904d 818 // AIN12 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 819 // AIN13 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 820 //
whismanoid 0:f7d706d2904d 821 //~ #define AIN_12_13_DifferentialUnipolar 1
whismanoid 0:f7d706d2904d 822 //
whismanoid 0:f7d706d2904d 823 //--------------------
whismanoid 5:6ef046dbe77e 824 // ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar
whismanoid 0:f7d706d2904d 825 // Full Scale = VREF
whismanoid 0:f7d706d2904d 826 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 827 // AIN12 is a Single-Ended input using Unipolar transfer function.
whismanoid 5:6ef046dbe77e 828 // AIN13 is a Single-Ended input using Unipolar transfer function.
whismanoid 5:6ef046dbe77e 829 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 0:f7d706d2904d 830 // AIN12 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 831 // AIN13 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 832 //
whismanoid 5:6ef046dbe77e 833 //~ #define AIN_12_13_SingleEnded 1
whismanoid 0:f7d706d2904d 834 //
whismanoid 0:f7d706d2904d 835 //--------------------
whismanoid 0:f7d706d2904d 836 //
whismanoid 0:f7d706d2904d 837 // Default settings if not defined at project level
whismanoid 0:f7d706d2904d 838 #ifndef AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 839 # ifndef AIN_12_13_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 840 # ifndef AIN_12_13_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 841 # ifndef AIN_12_13_SingleEnded
whismanoid 0:f7d706d2904d 842 # define AIN_12_13_DifferentialBipolarFS2Vref 0
whismanoid 5:6ef046dbe77e 843 # define AIN_12_13_DifferentialBipolarFSVref 0
whismanoid 5:6ef046dbe77e 844 # define AIN_12_13_DifferentialUnipolar 0
whismanoid 0:f7d706d2904d 845 # define AIN_12_13_SingleEnded 1
whismanoid 5:6ef046dbe77e 846 # endif // AIN_12_13_SingleEnded
whismanoid 0:f7d706d2904d 847 # endif // AIN_12_13_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 848 # endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 849 #endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 850 //
whismanoid 0:f7d706d2904d 851 // (optional diagnostic) pragma message the active setting
whismanoid 0:f7d706d2904d 852 #if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 853 //~ # pragma message("AIN_12_13_DifferentialBipolarFS2Vref: ADC Channels AIN12, AIN13 = Differential Bipolar")
whismanoid 0:f7d706d2904d 854 #endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 855 #if AIN_12_13_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 856 //~ # pragma message("AIN_12_13_DifferentialBipolarFSVref: ADC Channels AIN12, AIN13 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 857 #endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 858 #if AIN_12_13_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 859 //~ # pragma message("AIN_12_13_DifferentialUnipolar: ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)")
whismanoid 5:6ef046dbe77e 860 #endif // AIN_12_13_DifferentialUnipolar
whismanoid 0:f7d706d2904d 861 #if AIN_12_13_SingleEnded
whismanoid 0:f7d706d2904d 862 //~ # pragma message("AIN_12_13_SingleEnded: ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar")
whismanoid 0:f7d706d2904d 863 #endif // AIN_12_13_SingleEnded
whismanoid 0:f7d706d2904d 864 //
whismanoid 0:f7d706d2904d 865 // Validate the AIN_12_13_DifferentialBipolarFS2Vref setting
whismanoid 0:f7d706d2904d 866 #if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 867 # if AIN_12_13_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 868 # error("cannot have both AIN_12_13_DifferentialBipolarFS2Vref and AIN_12_13_DifferentialBipolarFSVref; choose one")
whismanoid 5:6ef046dbe77e 869 # endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 870 # if AIN_12_13_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 871 # error("cannot have both AIN_12_13_DifferentialBipolarFS2Vref and AIN_12_13_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 872 # endif // AIN_12_13_DifferentialUnipolar
whismanoid 0:f7d706d2904d 873 # if AIN_12_13_SingleEnded
whismanoid 0:f7d706d2904d 874 # error("cannot have both AIN_12_13_DifferentialBipolarFS2Vref and AIN_12_13_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 875 # endif // AIN_12_13_SingleEnded
whismanoid 0:f7d706d2904d 876 #endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 877 //
whismanoid 5:6ef046dbe77e 878 // Validate the AIN_12_13_DifferentialBipolarFSVref setting
whismanoid 5:6ef046dbe77e 879 #if AIN_12_13_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 880 # if AIN_12_13_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 881 # error("cannot have both AIN_12_13_DifferentialBipolarFSVref and AIN_12_13_DifferentialUnipolar; choose one")
whismanoid 0:f7d706d2904d 882 # endif // AIN_12_13_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 883 # if AIN_12_13_SingleEnded
whismanoid 5:6ef046dbe77e 884 # error("cannot have both AIN_12_13_DifferentialBipolarFSVref and AIN_12_13_SingleEnded; choose one")
whismanoid 5:6ef046dbe77e 885 # endif // AIN_12_13_SingleEnded
whismanoid 5:6ef046dbe77e 886 #endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 887 //
whismanoid 0:f7d706d2904d 888 // Validate the AIN_12_13_DifferentialUnipolar setting
whismanoid 0:f7d706d2904d 889 #if AIN_12_13_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 890 # if AIN_12_13_SingleEnded
whismanoid 5:6ef046dbe77e 891 # error("cannot have both AIN_12_13_DifferentialUnipolar and AIN_12_13_SingleEnded; choose one")
whismanoid 5:6ef046dbe77e 892 # endif // AIN_12_13_SingleEnded
whismanoid 0:f7d706d2904d 893 #endif // AIN_12_13_DifferentialUnipolar
whismanoid 0:f7d706d2904d 894
whismanoid 0:f7d706d2904d 895 //----------------------------------------
whismanoid 0:f7d706d2904d 896 // ADC Channels AIN14, AIN15
whismanoid 0:f7d706d2904d 897 //
whismanoid 0:f7d706d2904d 898 // CUSTOMIZE: select one of the following options
whismanoid 0:f7d706d2904d 899 // either by uncommenting in this file or define at the project level
whismanoid 0:f7d706d2904d 900 //--------------------
whismanoid 0:f7d706d2904d 901 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 0:f7d706d2904d 902 // Full Scale = 2 * VREF
whismanoid 0:f7d706d2904d 903 // Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 904 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 0:f7d706d2904d 905 // AIN14 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 906 // AIN15 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 907 //
whismanoid 0:f7d706d2904d 908 //~ #define AIN_14_15_DifferentialBipolarFS2Vref 1
whismanoid 0:f7d706d2904d 909 //
whismanoid 0:f7d706d2904d 910 //--------------------
whismanoid 5:6ef046dbe77e 911 // ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid 0:f7d706d2904d 912 // Full Scale = VREF
whismanoid 0:f7d706d2904d 913 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 914 // AIN14, AIN15 are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 0:f7d706d2904d 915 // AIN14 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 916 // AIN15 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 917 //
whismanoid 5:6ef046dbe77e 918 //~ #define AIN_14_15_DifferentialBipolarFSVref 1
whismanoid 0:f7d706d2904d 919 //
whismanoid 0:f7d706d2904d 920 //--------------------
whismanoid 0:f7d706d2904d 921 // ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)
whismanoid 0:f7d706d2904d 922 // Full Scale = VREF
whismanoid 0:f7d706d2904d 923 // Voltage per LSB count = VREF/2048
whismanoid 0:f7d706d2904d 924 // AIN14, AIN15 are a Differential pair using Unipolar transfer function.
whismanoid 0:f7d706d2904d 925 // AIN14 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 926 // AIN15 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 927 //
whismanoid 0:f7d706d2904d 928 //~ #define AIN_14_15_DifferentialUnipolar 1
whismanoid 0:f7d706d2904d 929 //
whismanoid 0:f7d706d2904d 930 //--------------------
whismanoid 5:6ef046dbe77e 931 // ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar
whismanoid 0:f7d706d2904d 932 // Full Scale = VREF
whismanoid 0:f7d706d2904d 933 // Voltage per LSB count = VREF/2048
whismanoid 5:6ef046dbe77e 934 // AIN14 is a Single-Ended input using Unipolar transfer function.
whismanoid 5:6ef046dbe77e 935 // AIN15 is a Single-Ended input using Unipolar transfer function.
whismanoid 5:6ef046dbe77e 936 // If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 0:f7d706d2904d 937 // AIN14 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 938 // AIN15 voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 939 //
whismanoid 5:6ef046dbe77e 940 //~ #define AIN_14_15_SingleEnded 1
whismanoid 0:f7d706d2904d 941 //
whismanoid 0:f7d706d2904d 942 //--------------------
whismanoid 0:f7d706d2904d 943 //
whismanoid 0:f7d706d2904d 944 // Default settings if not defined at project level
whismanoid 0:f7d706d2904d 945 #ifndef AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 946 # ifndef AIN_14_15_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 947 # ifndef AIN_14_15_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 948 # ifndef AIN_14_15_SingleEnded
whismanoid 0:f7d706d2904d 949 # define AIN_14_15_DifferentialBipolarFS2Vref 0
whismanoid 5:6ef046dbe77e 950 # define AIN_14_15_DifferentialBipolarFSVref 0
whismanoid 5:6ef046dbe77e 951 # define AIN_14_15_DifferentialUnipolar 0
whismanoid 0:f7d706d2904d 952 # define AIN_14_15_SingleEnded 1
whismanoid 5:6ef046dbe77e 953 # endif // AIN_14_15_SingleEnded
whismanoid 0:f7d706d2904d 954 # endif // AIN_14_15_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 955 # endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 956 #endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 957 //
whismanoid 0:f7d706d2904d 958 // (optional diagnostic) pragma message the active setting
whismanoid 0:f7d706d2904d 959 #if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 960 //~ # pragma message("AIN_14_15_DifferentialBipolarFS2Vref: ADC Channels AIN14, AIN15 = Differential Bipolar")
whismanoid 0:f7d706d2904d 961 #endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 962 #if AIN_14_15_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 963 //~ # pragma message("AIN_14_15_DifferentialBipolarFSVref: ADC Channels AIN14, AIN15 = Differential Bipolar")
whismanoid 5:6ef046dbe77e 964 #endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 965 #if AIN_14_15_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 966 //~ # pragma message("AIN_14_15_DifferentialUnipolar: ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)")
whismanoid 5:6ef046dbe77e 967 #endif // AIN_14_15_DifferentialUnipolar
whismanoid 0:f7d706d2904d 968 #if AIN_14_15_SingleEnded
whismanoid 0:f7d706d2904d 969 //~ # pragma message("AIN_14_15_SingleEnded: ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar")
whismanoid 0:f7d706d2904d 970 #endif // AIN_14_15_SingleEnded
whismanoid 0:f7d706d2904d 971 //
whismanoid 0:f7d706d2904d 972 // Validate the AIN_14_15_DifferentialBipolarFS2Vref setting
whismanoid 0:f7d706d2904d 973 #if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 5:6ef046dbe77e 974 # if AIN_14_15_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 975 # error("cannot have both AIN_14_15_DifferentialBipolarFS2Vref and AIN_14_15_DifferentialBipolarFSVref; choose one")
whismanoid 5:6ef046dbe77e 976 # endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid 5:6ef046dbe77e 977 # if AIN_14_15_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 978 # error("cannot have both AIN_14_15_DifferentialBipolarFS2Vref and AIN_14_15_DifferentialUnipolar; choose one")
whismanoid 5:6ef046dbe77e 979 # endif // AIN_14_15_DifferentialUnipolar
whismanoid 0:f7d706d2904d 980 # if AIN_14_15_SingleEnded
whismanoid 0:f7d706d2904d 981 # error("cannot have both AIN_14_15_DifferentialBipolarFS2Vref and AIN_14_15_SingleEnded; choose one")
whismanoid 0:f7d706d2904d 982 # endif // AIN_14_15_SingleEnded
whismanoid 0:f7d706d2904d 983 #endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid 0:f7d706d2904d 984 //
whismanoid 5:6ef046dbe77e 985 // Validate the AIN_14_15_DifferentialBipolarFSVref setting
whismanoid 5:6ef046dbe77e 986 #if AIN_14_15_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 987 # if AIN_14_15_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 988 # error("cannot have both AIN_14_15_DifferentialBipolarFSVref and AIN_14_15_DifferentialUnipolar; choose one")
whismanoid 0:f7d706d2904d 989 # endif // AIN_14_15_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 990 # if AIN_14_15_SingleEnded
whismanoid 5:6ef046dbe77e 991 # error("cannot have both AIN_14_15_DifferentialBipolarFSVref and AIN_14_15_SingleEnded; choose one")
whismanoid 5:6ef046dbe77e 992 # endif // AIN_14_15_SingleEnded
whismanoid 5:6ef046dbe77e 993 #endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid 0:f7d706d2904d 994 //
whismanoid 0:f7d706d2904d 995 // Validate the AIN_14_15_DifferentialUnipolar setting
whismanoid 0:f7d706d2904d 996 #if AIN_14_15_DifferentialUnipolar
whismanoid 5:6ef046dbe77e 997 # if AIN_14_15_SingleEnded
whismanoid 5:6ef046dbe77e 998 # error("cannot have both AIN_14_15_DifferentialUnipolar and AIN_14_15_SingleEnded; choose one")
whismanoid 5:6ef046dbe77e 999 # endif // AIN_14_15_SingleEnded
whismanoid 0:f7d706d2904d 1000 #endif // AIN_14_15_DifferentialUnipolar
whismanoid 0:f7d706d2904d 1001
whismanoid 0:f7d706d2904d 1002 // CODE GENERATOR: class declaration and docstrings
whismanoid 0:f7d706d2904d 1003 /**
whismanoid 0:f7d706d2904d 1004 * @brief MAX11131 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid 0:f7d706d2904d 1005 *
whismanoid 0:f7d706d2904d 1006 *
whismanoid 0:f7d706d2904d 1007 *
whismanoid 0:f7d706d2904d 1008 * Datasheet: https://www.maximintegrated.com/MAX11131
whismanoid 0:f7d706d2904d 1009 *
whismanoid 0:f7d706d2904d 1010 *
whismanoid 0:f7d706d2904d 1011 *
whismanoid 1:77f1ee332e4a 1012 * //---------- CODE GENERATOR: helloCppCodeList
whismanoid 0:f7d706d2904d 1013 * @code
whismanoid 0:f7d706d2904d 1014 * // CODE GENERATOR: example code includes
whismanoid 0:f7d706d2904d 1015 * // example code includes
whismanoid 5:6ef046dbe77e 1016 * // standard include for target platform
whismanoid 0:f7d706d2904d 1017 * #include "mbed.h"
whismanoid 0:f7d706d2904d 1018 * //#include "max32625.h"
whismanoid 0:f7d706d2904d 1019 * #include "MAX11131.h"
whismanoid 0:f7d706d2904d 1020 *
whismanoid 0:f7d706d2904d 1021 * // example code board support
whismanoid 0:f7d706d2904d 1022 * //MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
whismanoid 0:f7d706d2904d 1023 * //DigitalOut rLED(LED1);
whismanoid 0:f7d706d2904d 1024 * //DigitalOut gLED(LED2);
whismanoid 0:f7d706d2904d 1025 * //DigitalOut bLED(LED3);
whismanoid 0:f7d706d2904d 1026 * //
whismanoid 0:f7d706d2904d 1027 * // Arduino "shield" connector port definitions (MAX32625MBED shown)
whismanoid 0:f7d706d2904d 1028 * #if defined(TARGET_MAX32625MBED)
whismanoid 0:f7d706d2904d 1029 * #define A0 AIN_0
whismanoid 0:f7d706d2904d 1030 * #define A1 AIN_1
whismanoid 0:f7d706d2904d 1031 * #define A2 AIN_2
whismanoid 0:f7d706d2904d 1032 * #define A3 AIN_3
whismanoid 0:f7d706d2904d 1033 * #define D0 P0_0
whismanoid 0:f7d706d2904d 1034 * #define D1 P0_1
whismanoid 0:f7d706d2904d 1035 * #define D2 P0_2
whismanoid 0:f7d706d2904d 1036 * #define D3 P0_3
whismanoid 0:f7d706d2904d 1037 * #define D4 P0_4
whismanoid 0:f7d706d2904d 1038 * #define D5 P0_5
whismanoid 0:f7d706d2904d 1039 * #define D6 P0_6
whismanoid 0:f7d706d2904d 1040 * #define D7 P0_7
whismanoid 0:f7d706d2904d 1041 * #define D8 P1_4
whismanoid 0:f7d706d2904d 1042 * #define D9 P1_5
whismanoid 0:f7d706d2904d 1043 * #define D10 P1_3
whismanoid 0:f7d706d2904d 1044 * #define D11 P1_1
whismanoid 0:f7d706d2904d 1045 * #define D12 P1_2
whismanoid 0:f7d706d2904d 1046 * #define D13 P1_0
whismanoid 0:f7d706d2904d 1047 * #endif
whismanoid 0:f7d706d2904d 1048 *
whismanoid 0:f7d706d2904d 1049 * // example code declare SPI interface
whismanoid 0:f7d706d2904d 1050 * #if defined(TARGET_MAX32625MBED)
whismanoid 0:f7d706d2904d 1051 * SPI spi(SPI1_MOSI, SPI1_MISO, SPI1_SCK); // mosi, miso, sclk spi1 TARGET_MAX32625MBED: P1_1 P1_2 P1_0 Arduino 10-pin header D11 D12 D13
whismanoid 0:f7d706d2904d 1052 * DigitalOut spi_cs(SPI1_SS); // TARGET_MAX32625MBED: P1_3 Arduino 10-pin header D10
whismanoid 0:f7d706d2904d 1053 * #elif defined(TARGET_MAX32600MBED)
whismanoid 0:f7d706d2904d 1054 * SPI spi(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13
whismanoid 0:f7d706d2904d 1055 * DigitalOut spi_cs(SPI2_SS); // Generic: Arduino 10-pin header D10
whismanoid 0:f7d706d2904d 1056 * #else
whismanoid 0:f7d706d2904d 1057 * SPI spi(D11, D12, D13); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13
whismanoid 0:f7d706d2904d 1058 * DigitalOut spi_cs(D10); // Generic: Arduino 10-pin header D10
whismanoid 0:f7d706d2904d 1059 * #endif
whismanoid 0:f7d706d2904d 1060 *
whismanoid 0:f7d706d2904d 1061 * // example code declare GPIO interface pins
whismanoid 0:f7d706d2904d 1062 * DigitalOut CNVST_pin(D9); // Digital Trigger Input to MAX11131 device
whismanoid 0:f7d706d2904d 1063 * // AnalogOut REF__pin(Px_x_PortName_To_Be_Determined); // Reference Input to MAX11131 device
whismanoid 0:f7d706d2904d 1064 * // AnalogOut REF__AIN15_pin(Px_x_PortName_To_Be_Determined); // Reference Input to MAX11131 device
whismanoid 0:f7d706d2904d 1065 * DigitalIn EOC_pin(D2); // Digital Event Output from MAX11131 device
whismanoid 0:f7d706d2904d 1066 * // example code declare device instance
whismanoid 0:f7d706d2904d 1067 * MAX11131 g_MAX11131_device(spi, spi_cs, CNVST_pin, EOC_pin, MAX11131::MAX11131_IC);
whismanoid 0:f7d706d2904d 1068 *
whismanoid 0:f7d706d2904d 1069 * // example code main function
whismanoid 0:f7d706d2904d 1070 * int main()
whismanoid 0:f7d706d2904d 1071 * {
whismanoid 0:f7d706d2904d 1072 * while (1)
whismanoid 0:f7d706d2904d 1073 * {
whismanoid 0:f7d706d2904d 1074 * // CODE GENERATOR: example code: member function Init
whismanoid 0:f7d706d2904d 1075 * g_MAX11131_device.Init();
whismanoid 0:f7d706d2904d 1076 *
whismanoid 0:f7d706d2904d 1077 * // CODE GENERATOR: example code: has no member function REF
whismanoid 0:f7d706d2904d 1078 * // CODE GENERATOR: example code: has no member function CODE_LOAD
whismanoid 0:f7d706d2904d 1079 * // CODE GENERATOR: example code: has no member function CODEallLOADall
whismanoid 0:f7d706d2904d 1080 * // CODE GENERATOR: example code: has no member function CODEnLOADn
whismanoid 0:f7d706d2904d 1081 * // CODE GENERATOR: example code: member function ScanManual
whismanoid 0:f7d706d2904d 1082 * // @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid 0:f7d706d2904d 1083 * // @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1084 * // @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 0:f7d706d2904d 1085 * int channelId_0_15 = 3;
whismanoid 0:f7d706d2904d 1086 * g_MAX11131_device.channelNumber_0_15 = channelId_0_15;
whismanoid 0:f7d706d2904d 1087 * g_MAX11131_device.PowerManagement_0_2 = 0;
whismanoid 0:f7d706d2904d 1088 * g_MAX11131_device.chan_id_0_1 = 1;
whismanoid 0:f7d706d2904d 1089 * g_MAX11131_device.NumWords = g_MAX11131_device.ScanManual();
whismanoid 0:f7d706d2904d 1090 *
whismanoid 0:f7d706d2904d 1091 * // CODE GENERATOR: example code: member function ReadAINcode
whismanoid 0:f7d706d2904d 1092 * // TODO1: CODE GENERATOR: example code: member function ReadAINcode
whismanoid 0:f7d706d2904d 1093 * // Read raw ADC codes from device into AINcode[] and RAW_misoData16[]
whismanoid 0:f7d706d2904d 1094 * // @pre one of the MAX11311_Scan functions was called, setting g_MAX11131_device.NumWords
whismanoid 0:f7d706d2904d 1095 * g_MAX11131_device.ReadAINcode();
whismanoid 0:f7d706d2904d 1096 * // @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid 0:f7d706d2904d 1097 * // @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid 0:f7d706d2904d 1098 *
whismanoid 0:f7d706d2904d 1099 * wait(3.0);
whismanoid 0:f7d706d2904d 1100 * }
whismanoid 0:f7d706d2904d 1101 * }
whismanoid 0:f7d706d2904d 1102 * @endcode
whismanoid 1:77f1ee332e4a 1103 * //---------- CODE GENERATOR: end helloCppCodeList
whismanoid 0:f7d706d2904d 1104 */
whismanoid 0:f7d706d2904d 1105 class MAX11131 {
whismanoid 0:f7d706d2904d 1106 public:
whismanoid 0:f7d706d2904d 1107 // CODE GENERATOR: TypedefEnum EnumItem declarations
whismanoid 0:f7d706d2904d 1108 // CODE GENERATOR: TypedefEnum MAX11131_SCAN_enum_t
whismanoid 0:f7d706d2904d 1109 //----------------------------------------
whismanoid 0:f7d706d2904d 1110 /// ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid 0:f7d706d2904d 1111 typedef enum MAX11131_SCAN_enum_t {
whismanoid 0:f7d706d2904d 1112 SCAN_0000_NOP = 0x00, //!< 8'b00000000
whismanoid 0:f7d706d2904d 1113 SCAN_0001_Manual = 0x01, //!< 8'b00000001
whismanoid 0:f7d706d2904d 1114 SCAN_0010_Repeat = 0x02, //!< 8'b00000010
whismanoid 0:f7d706d2904d 1115 SCAN_0011_StandardInternalClock = 0x03, //!< 8'b00000011
whismanoid 0:f7d706d2904d 1116 SCAN_0100_StandardExternalClock = 0x04, //!< 8'b00000100
whismanoid 0:f7d706d2904d 1117 SCAN_0101_UpperInternalClock = 0x05, //!< 8'b00000101
whismanoid 0:f7d706d2904d 1118 SCAN_0110_UpperExternalClock = 0x06, //!< 8'b00000110
whismanoid 0:f7d706d2904d 1119 SCAN_0111_CustomInternalClock = 0x07, //!< 8'b00000111
whismanoid 0:f7d706d2904d 1120 SCAN_1000_CustomExternalClock = 0x08, //!< 8'b00001000
whismanoid 0:f7d706d2904d 1121 SCAN_1001_SampleSetExternalClock = 0x09, //!< 8'b00001001
whismanoid 0:f7d706d2904d 1122 } MAX11131_SCAN_enum_t;
whismanoid 0:f7d706d2904d 1123
whismanoid 0:f7d706d2904d 1124 // CODE GENERATOR: TypedefEnum MAX11131_RESET_enum_t
whismanoid 0:f7d706d2904d 1125 //----------------------------------------
whismanoid 0:f7d706d2904d 1126 /// ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid 0:f7d706d2904d 1127 typedef enum MAX11131_RESET_enum_t {
whismanoid 0:f7d706d2904d 1128 RESET_00_Normal = 0x00, //!< 8'b00000000
whismanoid 0:f7d706d2904d 1129 RESET_01_ResetFIFO = 0x01, //!< 8'b00000001
whismanoid 0:f7d706d2904d 1130 RESET_10_ResetAllRegisters = 0x02, //!< 8'b00000010
whismanoid 0:f7d706d2904d 1131 } MAX11131_RESET_enum_t;
whismanoid 0:f7d706d2904d 1132
whismanoid 0:f7d706d2904d 1133 // CODE GENERATOR: TypedefEnum MAX11131_PM_enum_t
whismanoid 0:f7d706d2904d 1134 //----------------------------------------
whismanoid 0:f7d706d2904d 1135 /// ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid 0:f7d706d2904d 1136 typedef enum MAX11131_PM_enum_t {
whismanoid 0:f7d706d2904d 1137 PM_00_Normal = 0x00, //!< 8'b00000000
whismanoid 0:f7d706d2904d 1138 PM_01_AutoShutdown = 0x01, //!< 8'b00000001
whismanoid 0:f7d706d2904d 1139 PM_10_AutoStandby = 0x02, //!< 8'b00000010
whismanoid 0:f7d706d2904d 1140 } MAX11131_PM_enum_t;
whismanoid 0:f7d706d2904d 1141
whismanoid 0:f7d706d2904d 1142 // TODO1: CODE GENERATOR: ic_variant -- IC's supported with this driver
whismanoid 0:f7d706d2904d 1143 /**
whismanoid 0:f7d706d2904d 1144 * @brief IC's supported with this driver
whismanoid 0:f7d706d2904d 1145 * @details MAX11131
whismanoid 0:f7d706d2904d 1146 */
whismanoid 0:f7d706d2904d 1147 typedef enum
whismanoid 0:f7d706d2904d 1148 {
whismanoid 0:f7d706d2904d 1149 MAX11131_IC = 0,
whismanoid 0:f7d706d2904d 1150 //MAX11131_IC = 1
whismanoid 0:f7d706d2904d 1151 } MAX11131_ic_t;
whismanoid 0:f7d706d2904d 1152
whismanoid 0:f7d706d2904d 1153 // TODO1: CODE GENERATOR: class constructor declaration
whismanoid 0:f7d706d2904d 1154 /**********************************************************//**
whismanoid 0:f7d706d2904d 1155 * @brief Constructor for MAX11131 Class.
whismanoid 0:f7d706d2904d 1156 *
whismanoid 0:f7d706d2904d 1157 * @details Requires an existing SPI object as well as a DigitalOut object.
whismanoid 0:f7d706d2904d 1158 * The DigitalOut object is used for a chip enable signal
whismanoid 0:f7d706d2904d 1159 *
whismanoid 0:f7d706d2904d 1160 * On Entry:
whismanoid 0:f7d706d2904d 1161 * @param[in] spi - pointer to existing SPI object
whismanoid 0:f7d706d2904d 1162 * @param[in] cs_pin - pointer to a DigitalOut pin object
whismanoid 0:f7d706d2904d 1163 * CODE GENERATOR: class constructor docstrings gpio InputPin pins
whismanoid 0:f7d706d2904d 1164 * @param[in] CNVST_pin - pointer to a DigitalOut pin object
whismanoid 0:f7d706d2904d 1165 * CODE GENERATOR: class constructor docstrings gpio OutputPin pins
whismanoid 0:f7d706d2904d 1166 * @param[in] EOC_pin - pointer to a DigitalIn pin object
whismanoid 0:f7d706d2904d 1167 * @param[in] ic_variant - which type of MAX11131 is used
whismanoid 0:f7d706d2904d 1168 *
whismanoid 0:f7d706d2904d 1169 * On Exit:
whismanoid 0:f7d706d2904d 1170 *
whismanoid 0:f7d706d2904d 1171 * @return None
whismanoid 0:f7d706d2904d 1172 **************************************************************/
whismanoid 0:f7d706d2904d 1173 MAX11131(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid 0:f7d706d2904d 1174 // CODE GENERATOR: class constructor declaration gpio InputPin pins
whismanoid 0:f7d706d2904d 1175 DigitalOut &CNVST_pin, // Digital Trigger Input to MAX11131 device
whismanoid 0:f7d706d2904d 1176 // AnalogOut &REF__pin, // Reference Input to MAX11131 device
whismanoid 0:f7d706d2904d 1177 // AnalogOut &REF__AIN15_pin, // Reference Input to MAX11131 device
whismanoid 0:f7d706d2904d 1178 // CODE GENERATOR: class constructor declaration gpio OutputPin pins
whismanoid 0:f7d706d2904d 1179 DigitalIn &EOC_pin, // Digital Event Output from MAX11131 device
whismanoid 0:f7d706d2904d 1180 MAX11131_ic_t ic_variant);
whismanoid 0:f7d706d2904d 1181
whismanoid 0:f7d706d2904d 1182 // CODE GENERATOR: class destructor declaration
whismanoid 0:f7d706d2904d 1183 /************************************************************
whismanoid 0:f7d706d2904d 1184 * @brief Default destructor for MAX11131 Class.
whismanoid 0:f7d706d2904d 1185 *
whismanoid 0:f7d706d2904d 1186 * @details Destroys SPI object if owner
whismanoid 0:f7d706d2904d 1187 *
whismanoid 0:f7d706d2904d 1188 * On Entry:
whismanoid 0:f7d706d2904d 1189 *
whismanoid 0:f7d706d2904d 1190 * On Exit:
whismanoid 0:f7d706d2904d 1191 *
whismanoid 0:f7d706d2904d 1192 * @return None
whismanoid 0:f7d706d2904d 1193 **************************************************************/
whismanoid 0:f7d706d2904d 1194 ~MAX11131();
whismanoid 0:f7d706d2904d 1195
whismanoid 0:f7d706d2904d 1196 // CODE GENERATOR: spi_frequency setter declaration
whismanoid 5:6ef046dbe77e 1197 /// set SPI SCLK frequency
whismanoid 0:f7d706d2904d 1198 void spi_frequency(int spi_sclk_Hz);
whismanoid 0:f7d706d2904d 1199
whismanoid 0:f7d706d2904d 1200 //----------------------------------------
whismanoid 0:f7d706d2904d 1201 // CODE GENERATOR: omit typedef enum MAX11131_device_t, class members instead of global device object
whismanoid 0:f7d706d2904d 1202 public:
whismanoid 0:f7d706d2904d 1203
whismanoid 0:f7d706d2904d 1204 /// shadow of write-only register ADC_MODE_CONTROL
whismanoid 0:f7d706d2904d 1205 /// mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid 0:f7d706d2904d 1206 int16_t ADC_MODE_CONTROL;
whismanoid 0:f7d706d2904d 1207
whismanoid 0:f7d706d2904d 1208 /// shadow of write-only register ADC_CONFIGURATION
whismanoid 0:f7d706d2904d 1209 /// mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid 0:f7d706d2904d 1210 int16_t ADC_CONFIGURATION;
whismanoid 0:f7d706d2904d 1211
whismanoid 0:f7d706d2904d 1212 /// shadow of write-only register UNIPOLAR
whismanoid 0:f7d706d2904d 1213 /// mosiData16 0x8800..0x8FFF format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid 0:f7d706d2904d 1214 int16_t UNIPOLAR;
whismanoid 0:f7d706d2904d 1215
whismanoid 0:f7d706d2904d 1216 /// shadow of write-only register BIPOLAR
whismanoid 0:f7d706d2904d 1217 /// mosiData16 0x9000..0x97FF format: 1 0 0 1 0 BCH0/1 BCH2/3 BCH4/5 BCH6/7 BCH8/9 BCH10/11 BCH12/13 BCH14/15 x x x
whismanoid 0:f7d706d2904d 1218 int16_t BIPOLAR;
whismanoid 0:f7d706d2904d 1219
whismanoid 0:f7d706d2904d 1220 /// shadow of write-only register RANGE
whismanoid 0:f7d706d2904d 1221 /// mosiData16 0x9800..0x9FFF format: 1 0 0 1 1 RANGE0/1 RANGE2/3 RANGE4/5 RANGE6/7 RANGE8/9 RANGE10/11 RANGE12/13 RANGE14/15 x x x
whismanoid 0:f7d706d2904d 1222 int16_t RANGE;
whismanoid 0:f7d706d2904d 1223
whismanoid 0:f7d706d2904d 1224 /// shadow of write-only register CSCAN0
whismanoid 0:f7d706d2904d 1225 /// mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid 0:f7d706d2904d 1226 int16_t CSCAN0;
whismanoid 0:f7d706d2904d 1227
whismanoid 0:f7d706d2904d 1228 /// shadow of write-only register CSCAN1
whismanoid 0:f7d706d2904d 1229 /// mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid 0:f7d706d2904d 1230 int16_t CSCAN1;
whismanoid 0:f7d706d2904d 1231
whismanoid 0:f7d706d2904d 1232 /// shadow of write-only register SAMPLESET
whismanoid 0:f7d706d2904d 1233 /// mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x followed by enabledChannelsPattern.
whismanoid 0:f7d706d2904d 1234 /// NOTE: Send the sampleset pattern, with 4 entries packed into each 16-bit SPI word. Pad unused entries with 0.
whismanoid 0:f7d706d2904d 1235 /// NOTE: Keep CS low during the entire enabledChannelsPattern entry.
whismanoid 0:f7d706d2904d 1236 int16_t SAMPLESET;
whismanoid 0:f7d706d2904d 1237
whismanoid 0:f7d706d2904d 1238 /// unpacked SAMPLESET.SEQ_LENGTH[7:0] determines length of pattern
whismanoid 0:f7d706d2904d 1239 /// NOTE: SAMPLESET.SEQ_LENGTH[7:0] is the number of channel entries in the pattern.
whismanoid 0:f7d706d2904d 1240 /// NOTE: Each channel entry is 4 bits. The first 4 bits are the first channel in the sequence.
whismanoid 0:f7d706d2904d 1241 /// NOTE: Channels can be repeated in any arbitrary order.
whismanoid 0:f7d706d2904d 1242 /// NOTE: The channel entry pattern is sent immediately after writing SAMPLESET.
whismanoid 0:f7d706d2904d 1243 uint8_t enabledChannelsPatternLength_1_256;
whismanoid 0:f7d706d2904d 1244
whismanoid 0:f7d706d2904d 1245 /// unpacked shadow of write-only register SAMPLESET enabledChannelsPattern.
whismanoid 0:f7d706d2904d 1246 /// Each entry is a channel number between 0 and 15.
whismanoid 0:f7d706d2904d 1247 uint8_t enabledChannelsPattern[256];
whismanoid 0:f7d706d2904d 1248
whismanoid 0:f7d706d2904d 1249 /// Diagnostic: what is the meaning of SPI Master Out data.
whismanoid 0:f7d706d2904d 1250 /// 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid 0:f7d706d2904d 1251 uint8_t SPI_MOSI_Semantic;
whismanoid 0:f7d706d2904d 1252
whismanoid 0:f7d706d2904d 1253 /// number of ScanRead() words needed to retrieve all measurements.
whismanoid 0:f7d706d2904d 1254 uint16_t NumWords;
whismanoid 0:f7d706d2904d 1255
whismanoid 0:f7d706d2904d 1256 /// Is the currently configured mode external or internal clock. 1:External Clock 0:Internal Clock
whismanoid 0:f7d706d2904d 1257 uint8_t isExternalClock;
whismanoid 0:f7d706d2904d 1258
whismanoid 0:f7d706d2904d 1259 /// unpacked ADC_MODE_CONTROL.SCAN[3:0] Scan Mode MAX11131_SCAN_enum_t
whismanoid 0:f7d706d2904d 1260 uint8_t ScanMode;
whismanoid 0:f7d706d2904d 1261
whismanoid 0:f7d706d2904d 1262 /// unpacked ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select
whismanoid 0:f7d706d2904d 1263 uint8_t channelNumber_0_15;
whismanoid 0:f7d706d2904d 1264
whismanoid 0:f7d706d2904d 1265 /// unpacked ADC_MODE_CONTROL.PM[1:0] Power Management MAX11131_PM_enum_t
whismanoid 0:f7d706d2904d 1266 uint8_t PowerManagement_0_2;
whismanoid 0:f7d706d2904d 1267
whismanoid 0:f7d706d2904d 1268 /// unpacked ADC_MODE_CONTROL.CHAN_ID
whismanoid 0:f7d706d2904d 1269 uint8_t chan_id_0_1;
whismanoid 0:f7d706d2904d 1270
whismanoid 0:f7d706d2904d 1271 /// unpacked ADC_CONFIGURATION.AVG and ADC_CONFIGURATION.NAVG[1:0] may be 0, 4, 8, 16, or 32
whismanoid 0:f7d706d2904d 1272 uint8_t average_0_4_8_16_32;
whismanoid 0:f7d706d2904d 1273
whismanoid 0:f7d706d2904d 1274 /// unpacked ADC_CONFIGURATION.NSCAN[1:0] may be 4, 8, 12, or 16
whismanoid 0:f7d706d2904d 1275 uint8_t nscan_4_8_12_16;
whismanoid 0:f7d706d2904d 1276
whismanoid 0:f7d706d2904d 1277 /// unpacked ADC_MODE_CONTROL.SWCNV
whismanoid 0:f7d706d2904d 1278 uint8_t swcnv_0_1;
whismanoid 0:f7d706d2904d 1279
whismanoid 0:f7d706d2904d 1280 /// unpacked CSCAN0 and CSCAN1
whismanoid 0:f7d706d2904d 1281 int16_t enabledChannelsMask;
whismanoid 0:f7d706d2904d 1282
whismanoid 0:f7d706d2904d 1283 /// Each channel's most recent value in LSBs.
whismanoid 0:f7d706d2904d 1284 /// Updated by ReadAINcode function.
whismanoid 0:f7d706d2904d 1285 /// Use VoltageOfCode function to convert LSBs to physical voltage.
whismanoid 0:f7d706d2904d 1286 uint16_t AINcode[16];
whismanoid 0:f7d706d2904d 1287
whismanoid 0:f7d706d2904d 1288 /// SPI master-in slave-out data.
whismanoid 0:f7d706d2904d 1289 /// Updated by ReadAINcode function.
whismanoid 0:f7d706d2904d 1290 /// SampleSet mode allows up to 256 channel entry selections.
whismanoid 0:f7d706d2904d 1291 int16_t RAW_misoData16[256];
whismanoid 0:f7d706d2904d 1292
whismanoid 0:f7d706d2904d 1293 /// reference voltage, in Volts
whismanoid 0:f7d706d2904d 1294 double VRef;
whismanoid 0:f7d706d2904d 1295
whismanoid 0:f7d706d2904d 1296 // CODE GENERATOR: omit global g_MAX11131_device
whismanoid 0:f7d706d2904d 1297
whismanoid 0:f7d706d2904d 1298 // CODE GENERATOR: extern function declarations
whismanoid 0:f7d706d2904d 1299 // CODE GENERATOR: extern function declaration SPIoutputCS
whismanoid 0:f7d706d2904d 1300 //----------------------------------------
whismanoid 0:f7d706d2904d 1301 // Assert SPI Chip Select
whismanoid 0:f7d706d2904d 1302 // SPI chip-select for MAX11131
whismanoid 0:f7d706d2904d 1303 //
whismanoid 0:f7d706d2904d 1304 void SPIoutputCS(int isLogicHigh);
whismanoid 0:f7d706d2904d 1305
whismanoid 0:f7d706d2904d 1306 // CODE GENERATOR: extern function declaration SPIwrite16bits
whismanoid 0:f7d706d2904d 1307 //----------------------------------------
whismanoid 0:f7d706d2904d 1308 // SPI write 16 bits
whismanoid 0:f7d706d2904d 1309 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 0:f7d706d2904d 1310 // ignoring MAX11131 DOUT
whismanoid 0:f7d706d2904d 1311 //
whismanoid 0:f7d706d2904d 1312 void SPIwrite16bits(int16_t mosiData16);
whismanoid 0:f7d706d2904d 1313
whismanoid 0:f7d706d2904d 1314 // CODE GENERATOR: extern function declaration SPIwrite24bits
whismanoid 0:f7d706d2904d 1315 //----------------------------------------
whismanoid 0:f7d706d2904d 1316 // SPI write 17-24 bits
whismanoid 0:f7d706d2904d 1317 // SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid 0:f7d706d2904d 1318 // followed by one additional SCLK byte.
whismanoid 0:f7d706d2904d 1319 // ignoring MAX11131 DOUT
whismanoid 0:f7d706d2904d 1320 //
whismanoid 0:f7d706d2904d 1321 void SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF);
whismanoid 0:f7d706d2904d 1322
whismanoid 0:f7d706d2904d 1323 // CODE GENERATOR: extern function declaration SPIread16bits
whismanoid 0:f7d706d2904d 1324 //----------------------------------------
whismanoid 0:f7d706d2904d 1325 // SPI read 16 bits while MOSI (MAX11131 DIN) is 0
whismanoid 0:f7d706d2904d 1326 // SPI interface to capture 16 bits miso data from MAX11131 DOUT
whismanoid 0:f7d706d2904d 1327 //
whismanoid 0:f7d706d2904d 1328 int16_t SPIread16bits();
whismanoid 0:f7d706d2904d 1329
whismanoid 0:f7d706d2904d 1330 // CODE GENERATOR: extern function declaration CNVSToutputPulseLow
whismanoid 0:f7d706d2904d 1331 //----------------------------------------
whismanoid 0:f7d706d2904d 1332 // Assert MAX11131 CNVST convert start.
whismanoid 0:f7d706d2904d 1333 // Required when using any of the InternalClock modes with SWCNV 0.
whismanoid 0:f7d706d2904d 1334 // Trigger measurement by driving CNVST/AIN14 pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 0:f7d706d2904d 1335 //
whismanoid 0:f7d706d2904d 1336 void CNVSToutputPulseLow();
whismanoid 0:f7d706d2904d 1337
whismanoid 0:f7d706d2904d 1338 // CODE GENERATOR: extern function declaration EOCinputWaitUntilLow
whismanoid 0:f7d706d2904d 1339 //----------------------------------------
whismanoid 0:f7d706d2904d 1340 // Wait for MAX11131 EOC pin low, indicating end of conversion.
whismanoid 0:f7d706d2904d 1341 // Required when using any of the InternalClock modes.
whismanoid 0:f7d706d2904d 1342 //
whismanoid 0:f7d706d2904d 1343 void EOCinputWaitUntilLow();
whismanoid 0:f7d706d2904d 1344
whismanoid 0:f7d706d2904d 1345 // CODE GENERATOR: extern function declaration EOCinputValue
whismanoid 0:f7d706d2904d 1346 //----------------------------------------
whismanoid 0:f7d706d2904d 1347 // Return the status of the MAX11131 EOC pin.
whismanoid 0:f7d706d2904d 1348 //
whismanoid 0:f7d706d2904d 1349 int EOCinputValue();
whismanoid 0:f7d706d2904d 1350
whismanoid 0:f7d706d2904d 1351 // CODE GENERATOR: class member data
whismanoid 0:f7d706d2904d 1352 private:
whismanoid 0:f7d706d2904d 1353 // CODE GENERATOR: class member data for SPI interface
whismanoid 0:f7d706d2904d 1354 // SPI object
whismanoid 0:f7d706d2904d 1355 SPI &m_spi;
whismanoid 0:f7d706d2904d 1356 int m_SPI_SCLK_Hz;
whismanoid 0:f7d706d2904d 1357 int m_SPI_dataMode;
whismanoid 0:f7d706d2904d 1358 int m_SPI_cs_state;
whismanoid 0:f7d706d2904d 1359
whismanoid 0:f7d706d2904d 1360 // Selector pin object
whismanoid 0:f7d706d2904d 1361 DigitalOut &m_cs_pin;
whismanoid 0:f7d706d2904d 1362
whismanoid 0:f7d706d2904d 1363 // CODE GENERATOR: class member data for gpio InputPin pins
whismanoid 0:f7d706d2904d 1364 // InputPin Name = CNVST
whismanoid 0:f7d706d2904d 1365 // InputPin Description = Active-Low Conversion Start Input/Analog Input 14
whismanoid 0:f7d706d2904d 1366 // InputPin Function = Trigger
whismanoid 0:f7d706d2904d 1367 DigitalOut &m_CNVST_pin;
whismanoid 0:f7d706d2904d 1368 //
whismanoid 0:f7d706d2904d 1369 // InputPin Name = REF+
whismanoid 0:f7d706d2904d 1370 // InputPin Description = External Positive Reference Input. Apply a reference voltage at REF+. Bypass to GND with a 0.47uF capacitor.
whismanoid 0:f7d706d2904d 1371 // InputPin Function = Reference
whismanoid 0:f7d706d2904d 1372 // AnalogOut &m_REF__pin;
whismanoid 0:f7d706d2904d 1373 //
whismanoid 0:f7d706d2904d 1374 // InputPin Name = REF-/AIN15
whismanoid 0:f7d706d2904d 1375 // InputPin Description = External Differential Reference Negative Input/Analog Input 15
whismanoid 0:f7d706d2904d 1376 // InputPin Function = Reference
whismanoid 0:f7d706d2904d 1377 // AnalogOut &m_REF__AIN15_pin;
whismanoid 0:f7d706d2904d 1378 //
whismanoid 0:f7d706d2904d 1379 // CODE GENERATOR: class member data for gpio OutputPin pins
whismanoid 0:f7d706d2904d 1380 // OutputPin Name = EOC
whismanoid 0:f7d706d2904d 1381 // OutputPin Description = End of Conversion Output. Data is valid after EOC pulls low (Internal clock mode only).
whismanoid 0:f7d706d2904d 1382 // OutputPin Function = Event
whismanoid 0:f7d706d2904d 1383 DigitalIn &m_EOC_pin;
whismanoid 0:f7d706d2904d 1384 //
whismanoid 0:f7d706d2904d 1385
whismanoid 0:f7d706d2904d 1386 // Identifies which IC variant is being used
whismanoid 0:f7d706d2904d 1387 MAX11131_ic_t m_ic_variant;
whismanoid 0:f7d706d2904d 1388
whismanoid 0:f7d706d2904d 1389 public:
whismanoid 0:f7d706d2904d 1390
whismanoid 0:f7d706d2904d 1391 // CODE GENERATOR: class member function declarations
whismanoid 0:f7d706d2904d 1392 //----------------------------------------
whismanoid 0:f7d706d2904d 1393 /// Initialize device
whismanoid 0:f7d706d2904d 1394 void Init(void);
whismanoid 0:f7d706d2904d 1395
whismanoid 0:f7d706d2904d 1396 //----------------------------------------
whismanoid 0:f7d706d2904d 1397 /// ADC Channels AIN(channelId), AIN(channelId+1) = Both Single-Ended, Unipolar
whismanoid 0:f7d706d2904d 1398 /// Full Scale = VREF
whismanoid 0:f7d706d2904d 1399 /// Voltage per LSB count = VREF/4096
whismanoid 0:f7d706d2904d 1400 /// AIN(channelId) is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 1401 /// AIN(channelId+1) is a Single-Ended input using Unipolar transfer function.
whismanoid 0:f7d706d2904d 1402 /// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid 0:f7d706d2904d 1403 /// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 1404 /// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 1405 ///
whismanoid 0:f7d706d2904d 1406 void Reconfigure_SingleEnded(int channelNumber_0_15);
whismanoid 0:f7d706d2904d 1407
whismanoid 0:f7d706d2904d 1408 //----------------------------------------
whismanoid 0:f7d706d2904d 1409 /// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Unipolar (AIN(channelId) > AIN(channelId+1))
whismanoid 0:f7d706d2904d 1410 /// Full Scale = VREF
whismanoid 0:f7d706d2904d 1411 /// Voltage per LSB count = VREF/4096
whismanoid 0:f7d706d2904d 1412 /// AIN(channelId), AIN(channelId+1) are a Differential pair using Unipolar transfer function.
whismanoid 0:f7d706d2904d 1413 /// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 1414 /// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 1415 ///
whismanoid 0:f7d706d2904d 1416 void Reconfigure_DifferentialUnipolar(int channelNumber_0_15);
whismanoid 0:f7d706d2904d 1417
whismanoid 0:f7d706d2904d 1418 //----------------------------------------
whismanoid 0:f7d706d2904d 1419 /// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 0:f7d706d2904d 1420 /// Full Scale = VREF
whismanoid 0:f7d706d2904d 1421 /// Voltage per LSB count = VREF/4096
whismanoid 4:8a0ae95546fa 1422 /// AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)(1/2)Vref
whismanoid 0:f7d706d2904d 1423 /// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 1424 /// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 1425 ///
whismanoid 0:f7d706d2904d 1426 void Reconfigure_DifferentialBipolarFSVref(int channelNumber_0_15);
whismanoid 0:f7d706d2904d 1427
whismanoid 0:f7d706d2904d 1428 //----------------------------------------
whismanoid 0:f7d706d2904d 1429 /// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid 0:f7d706d2904d 1430 /// Full Scale = 2 * VREF
whismanoid 0:f7d706d2904d 1431 /// Voltage per LSB count = VREF/2048
whismanoid 4:8a0ae95546fa 1432 /// AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range (+/-)Vref
whismanoid 0:f7d706d2904d 1433 /// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 1434 /// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid 0:f7d706d2904d 1435 ///
whismanoid 0:f7d706d2904d 1436 void Reconfigure_DifferentialBipolarFS2Vref(int channelNumber_0_15);
whismanoid 0:f7d706d2904d 1437
whismanoid 0:f7d706d2904d 1438 //----------------------------------------
whismanoid 0:f7d706d2904d 1439 /// SCAN_0000_NOP
whismanoid 0:f7d706d2904d 1440 ///
whismanoid 0:f7d706d2904d 1441 /// Shift 16 bits out of ADC, without changing configuration.
whismanoid 0:f7d706d2904d 1442 /// Note: @return data format depends on CHAN_ID bit:
whismanoid 0:f7d706d2904d 1443 /// "CH[3:0] DATA[11:0]" when CHAN_ID = 1, or
whismanoid 0:f7d706d2904d 1444 /// "0 DATA[11:0] x x x" when CHAN_ID = 0.
whismanoid 0:f7d706d2904d 1445 int16_t ScanRead(void);
whismanoid 0:f7d706d2904d 1446
whismanoid 0:f7d706d2904d 1447 //----------------------------------------
whismanoid 0:f7d706d2904d 1448 /// SCAN_0000_NOP
whismanoid 0:f7d706d2904d 1449 ///
whismanoid 0:f7d706d2904d 1450 /// Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid 0:f7d706d2904d 1451 /// If internal clock mode with SWCNV=0, measurements will be triggered using CNVST pin.
whismanoid 0:f7d706d2904d 1452 ///
whismanoid 0:f7d706d2904d 1453 /// @pre one of the Scan functions was called, setting g_MAX11131_device.NumWords
whismanoid 0:f7d706d2904d 1454 /// @post g_MAX11131_device.RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid 0:f7d706d2904d 1455 /// @post g_MAX11131_device.AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid 0:f7d706d2904d 1456 ///
whismanoid 0:f7d706d2904d 1457 void ReadAINcode(void);
whismanoid 0:f7d706d2904d 1458
whismanoid 0:f7d706d2904d 1459 //----------------------------------------
whismanoid 0:f7d706d2904d 1460 /// Sign-Extend a right-aligned MAX11131 code into a signed 2's complement value.
whismanoid 0:f7d706d2904d 1461 /// Supports the bipolar transfer functions.
whismanoid 0:f7d706d2904d 1462 /// @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 0:f7d706d2904d 1463 /// @return sign-extended 2's complement value.
whismanoid 0:f7d706d2904d 1464 ///
whismanoid 0:f7d706d2904d 1465 int32_t TwosComplementValue(uint32_t regValue);
whismanoid 0:f7d706d2904d 1466
whismanoid 0:f7d706d2904d 1467 //----------------------------------------
whismanoid 0:f7d706d2904d 1468 /// Return the physical voltage corresponding to MAX11131 code.
whismanoid 0:f7d706d2904d 1469 /// Does not perform any offset or gain correction.
whismanoid 0:f7d706d2904d 1470 /// @pre g_MAX11131_device.VRef = Voltage of REF input, in Volts
whismanoid 0:f7d706d2904d 1471 /// @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid 0:f7d706d2904d 1472 /// @param[in] channelId: AIN channel number.
whismanoid 0:f7d706d2904d 1473 /// @return physical voltage corresponding to MAX11131 code.
whismanoid 0:f7d706d2904d 1474 ///
whismanoid 0:f7d706d2904d 1475 double VoltageOfCode(int16_t value_u12, int channelId);
whismanoid 0:f7d706d2904d 1476
whismanoid 0:f7d706d2904d 1477 //----------------------------------------
whismanoid 0:f7d706d2904d 1478 /// SCAN_0001_Manual
whismanoid 0:f7d706d2904d 1479 ///
whismanoid 0:f7d706d2904d 1480 /// Measure ADC channel channelNumber_0_15 once.
whismanoid 0:f7d706d2904d 1481 /// External clock mode.
whismanoid 0:f7d706d2904d 1482 /// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid 0:f7d706d2904d 1483 /// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1484 /// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 0:f7d706d2904d 1485 /// @return number of ScanRead() words needed to retrieve the data.
whismanoid 0:f7d706d2904d 1486 /// For external clock modes, the data format depends on CHAN_ID.
whismanoid 0:f7d706d2904d 1487 /// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 0:f7d706d2904d 1488 /// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 0:f7d706d2904d 1489 ///
whismanoid 0:f7d706d2904d 1490 int ScanManual(void);
whismanoid 0:f7d706d2904d 1491
whismanoid 0:f7d706d2904d 1492 //----------------------------------------
whismanoid 0:f7d706d2904d 1493 /// SCAN_0010_Repeat
whismanoid 0:f7d706d2904d 1494 ///
whismanoid 0:f7d706d2904d 1495 /// Measure ADC channel channelNumber_0_15 repeatedly with averaging.
whismanoid 0:f7d706d2904d 1496 /// Internal clock mode.
whismanoid 0:f7d706d2904d 1497 /// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid 0:f7d706d2904d 1498 /// @param[in] g_MAX11131_device.average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 0:f7d706d2904d 1499 /// average_0_4_8_16_32=0 to disable averaging.
whismanoid 0:f7d706d2904d 1500 /// @param[in] g_MAX11131_device.nscan_4_8_12_16: Number of ScanRead() words to report.
whismanoid 0:f7d706d2904d 1501 /// @param[in] g_MAX11131_device.swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 0:f7d706d2904d 1502 /// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 0:f7d706d2904d 1503 /// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 0:f7d706d2904d 1504 /// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 0:f7d706d2904d 1505 /// CS must be held low for minimum of 17 SCLK cycles.
whismanoid 0:f7d706d2904d 1506 /// CNVST pin is not used. (AIN14 is available)
whismanoid 0:f7d706d2904d 1507 /// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1508 /// @return number of ScanRead() words needed to retrieve the data.
whismanoid 0:f7d706d2904d 1509 /// For internal clock modes, the data format always includes the channel address.
whismanoid 0:f7d706d2904d 1510 /// misoData16 = CH[3:0] DATA[11:0]
whismanoid 0:f7d706d2904d 1511 ///
whismanoid 0:f7d706d2904d 1512 int ScanRepeat(void);
whismanoid 0:f7d706d2904d 1513
whismanoid 0:f7d706d2904d 1514 //----------------------------------------
whismanoid 0:f7d706d2904d 1515 /// SCAN_0011_StandardInternalClock
whismanoid 0:f7d706d2904d 1516 ///
whismanoid 0:f7d706d2904d 1517 /// Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 0:f7d706d2904d 1518 /// Internal clock mode.
whismanoid 0:f7d706d2904d 1519 /// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid 0:f7d706d2904d 1520 /// @param[in] g_MAX11131_device.average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 0:f7d706d2904d 1521 /// average_0_4_8_16_32=0 to disable averaging.
whismanoid 0:f7d706d2904d 1522 /// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1523 /// @param[in] g_MAX11131_device.swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 0:f7d706d2904d 1524 /// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 0:f7d706d2904d 1525 /// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 0:f7d706d2904d 1526 /// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 0:f7d706d2904d 1527 /// CS must be held low for minimum of 17 SCLK cycles.
whismanoid 0:f7d706d2904d 1528 /// CNVST pin is not used. (AIN14 is available)
whismanoid 0:f7d706d2904d 1529 /// @return number of ScanRead() words needed to retrieve the data.
whismanoid 0:f7d706d2904d 1530 /// For internal clock modes, the data format always includes the channel address.
whismanoid 0:f7d706d2904d 1531 /// misoData16 = CH[3:0] DATA[11:0]
whismanoid 0:f7d706d2904d 1532 ///
whismanoid 0:f7d706d2904d 1533 int ScanStandardInternalClock(void);
whismanoid 0:f7d706d2904d 1534
whismanoid 0:f7d706d2904d 1535 //----------------------------------------
whismanoid 0:f7d706d2904d 1536 /// SCAN_0100_StandardExternalClock
whismanoid 0:f7d706d2904d 1537 ///
whismanoid 0:f7d706d2904d 1538 /// Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid 0:f7d706d2904d 1539 /// External clock mode.
whismanoid 0:f7d706d2904d 1540 /// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid 0:f7d706d2904d 1541 /// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1542 /// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 0:f7d706d2904d 1543 /// @return number of ScanRead() words needed to retrieve the data.
whismanoid 0:f7d706d2904d 1544 /// For external clock modes, the data format depends on CHAN_ID.
whismanoid 0:f7d706d2904d 1545 /// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 0:f7d706d2904d 1546 /// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 0:f7d706d2904d 1547 ///
whismanoid 0:f7d706d2904d 1548 int ScanStandardExternalClock(void);
whismanoid 0:f7d706d2904d 1549
whismanoid 0:f7d706d2904d 1550 //----------------------------------------
whismanoid 0:f7d706d2904d 1551 /// SCAN_0101_UpperInternalClock
whismanoid 0:f7d706d2904d 1552 ///
whismanoid 0:f7d706d2904d 1553 /// Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 0:f7d706d2904d 1554 /// Internal clock mode.
whismanoid 0:f7d706d2904d 1555 /// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid 0:f7d706d2904d 1556 /// @param[in] g_MAX11131_device.average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 0:f7d706d2904d 1557 /// average_0_4_8_16_32=0 to disable averaging.
whismanoid 0:f7d706d2904d 1558 /// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1559 /// @param[in] g_MAX11131_device.swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 0:f7d706d2904d 1560 /// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 0:f7d706d2904d 1561 /// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 0:f7d706d2904d 1562 /// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 0:f7d706d2904d 1563 /// CS must be held low for minimum of 17 SCLK cycles.
whismanoid 0:f7d706d2904d 1564 /// CNVST pin is not used. (AIN14 is available)
whismanoid 0:f7d706d2904d 1565 /// @return number of ScanRead() words needed to retrieve the data.
whismanoid 0:f7d706d2904d 1566 /// For internal clock modes, the data format always includes the channel address.
whismanoid 0:f7d706d2904d 1567 /// misoData16 = CH[3:0] DATA[11:0]
whismanoid 0:f7d706d2904d 1568 ///
whismanoid 0:f7d706d2904d 1569 int ScanUpperInternalClock(void);
whismanoid 0:f7d706d2904d 1570
whismanoid 0:f7d706d2904d 1571 //----------------------------------------
whismanoid 0:f7d706d2904d 1572 /// SCAN_0110_UpperExternalClock
whismanoid 0:f7d706d2904d 1573 ///
whismanoid 0:f7d706d2904d 1574 /// Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid 0:f7d706d2904d 1575 /// External clock mode.
whismanoid 0:f7d706d2904d 1576 /// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid 0:f7d706d2904d 1577 /// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1578 /// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 0:f7d706d2904d 1579 /// @return number of ScanRead() words needed to retrieve the data.
whismanoid 0:f7d706d2904d 1580 /// For external clock modes, the data format depends on CHAN_ID.
whismanoid 0:f7d706d2904d 1581 /// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 0:f7d706d2904d 1582 /// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 0:f7d706d2904d 1583 ///
whismanoid 0:f7d706d2904d 1584 int ScanUpperExternalClock(void);
whismanoid 0:f7d706d2904d 1585
whismanoid 0:f7d706d2904d 1586 //----------------------------------------
whismanoid 0:f7d706d2904d 1587 /// SCAN_0111_CustomInternalClock
whismanoid 0:f7d706d2904d 1588 ///
whismanoid 0:f7d706d2904d 1589 /// Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 0:f7d706d2904d 1590 /// using only the channels enabled by enabledChannelsMask.
whismanoid 0:f7d706d2904d 1591 /// Bit 0x0001 enables AIN0.
whismanoid 0:f7d706d2904d 1592 /// Bit 0x0002 enables AIN1.
whismanoid 0:f7d706d2904d 1593 /// Bit 0x0004 enables AIN2.
whismanoid 0:f7d706d2904d 1594 /// Bit 0x0008 enables AIN3.
whismanoid 0:f7d706d2904d 1595 /// Bit 0x0010 enables AIN4.
whismanoid 0:f7d706d2904d 1596 /// Bit 0x0020 enables AIN5.
whismanoid 0:f7d706d2904d 1597 /// Bit 0x0040 enables AIN6.
whismanoid 0:f7d706d2904d 1598 /// Bit 0x0080 enables AIN7.
whismanoid 0:f7d706d2904d 1599 /// Bit 0x0100 enables AIN8.
whismanoid 0:f7d706d2904d 1600 /// Bit 0x0200 enables AIN9.
whismanoid 0:f7d706d2904d 1601 /// Bit 0x0400 enables AIN10.
whismanoid 0:f7d706d2904d 1602 /// Bit 0x0800 enables AIN11.
whismanoid 0:f7d706d2904d 1603 /// Bit 0x1000 enables AIN12.
whismanoid 0:f7d706d2904d 1604 /// Bit 0x2000 enables AIN13.
whismanoid 0:f7d706d2904d 1605 /// Bit 0x4000 enables AIN14.
whismanoid 0:f7d706d2904d 1606 /// Bit 0x8000 enables AIN15.
whismanoid 0:f7d706d2904d 1607 /// Internal clock mode.
whismanoid 0:f7d706d2904d 1608 /// @param[in] g_MAX11131_device.enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 0:f7d706d2904d 1609 /// @param[in] g_MAX11131_device.average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid 0:f7d706d2904d 1610 /// average_0_4_8_16_32=0 to disable averaging.
whismanoid 0:f7d706d2904d 1611 /// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1612 /// @param[in] g_MAX11131_device.swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid 0:f7d706d2904d 1613 /// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid 0:f7d706d2904d 1614 /// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid 0:f7d706d2904d 1615 /// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid 0:f7d706d2904d 1616 /// CS must be held low for minimum of 17 SCLK cycles.
whismanoid 0:f7d706d2904d 1617 /// CNVST pin is not used. (AIN14 is available)
whismanoid 0:f7d706d2904d 1618 /// @return number of ScanRead() words needed to retrieve the data.
whismanoid 0:f7d706d2904d 1619 /// For internal clock modes, the data format always includes the channel address.
whismanoid 0:f7d706d2904d 1620 /// misoData16 = CH[3:0] DATA[11:0]
whismanoid 0:f7d706d2904d 1621 ///
whismanoid 0:f7d706d2904d 1622 int ScanCustomInternalClock(void);
whismanoid 0:f7d706d2904d 1623
whismanoid 0:f7d706d2904d 1624 //----------------------------------------
whismanoid 0:f7d706d2904d 1625 /// SCAN_1000_CustomExternalClock
whismanoid 0:f7d706d2904d 1626 ///
whismanoid 0:f7d706d2904d 1627 /// Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid 0:f7d706d2904d 1628 /// using only the channels enabled by enabledChannelsMask.
whismanoid 0:f7d706d2904d 1629 /// Bit 0x0001 enables AIN0.
whismanoid 0:f7d706d2904d 1630 /// Bit 0x0002 enables AIN1.
whismanoid 0:f7d706d2904d 1631 /// Bit 0x0004 enables AIN2.
whismanoid 0:f7d706d2904d 1632 /// Bit 0x0008 enables AIN3.
whismanoid 0:f7d706d2904d 1633 /// Bit 0x0010 enables AIN4.
whismanoid 0:f7d706d2904d 1634 /// Bit 0x0020 enables AIN5.
whismanoid 0:f7d706d2904d 1635 /// Bit 0x0040 enables AIN6.
whismanoid 0:f7d706d2904d 1636 /// Bit 0x0080 enables AIN7.
whismanoid 0:f7d706d2904d 1637 /// Bit 0x0100 enables AIN8.
whismanoid 0:f7d706d2904d 1638 /// Bit 0x0200 enables AIN9.
whismanoid 0:f7d706d2904d 1639 /// Bit 0x0400 enables AIN10.
whismanoid 0:f7d706d2904d 1640 /// Bit 0x0800 enables AIN11.
whismanoid 0:f7d706d2904d 1641 /// Bit 0x1000 enables AIN12.
whismanoid 0:f7d706d2904d 1642 /// Bit 0x2000 enables AIN13.
whismanoid 0:f7d706d2904d 1643 /// Bit 0x4000 enables AIN14.
whismanoid 0:f7d706d2904d 1644 /// Bit 0x8000 enables AIN15.
whismanoid 0:f7d706d2904d 1645 /// External clock mode.
whismanoid 0:f7d706d2904d 1646 /// @param[in] g_MAX11131_device.enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid 0:f7d706d2904d 1647 /// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1648 /// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 0:f7d706d2904d 1649 /// @return number of ScanRead() words needed to retrieve the data.
whismanoid 0:f7d706d2904d 1650 /// For external clock modes, the data format depends on CHAN_ID.
whismanoid 0:f7d706d2904d 1651 /// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 0:f7d706d2904d 1652 /// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 0:f7d706d2904d 1653 ///
whismanoid 0:f7d706d2904d 1654 int ScanCustomExternalClock(void);
whismanoid 0:f7d706d2904d 1655
whismanoid 0:f7d706d2904d 1656 //----------------------------------------
whismanoid 0:f7d706d2904d 1657 /// SCAN_1001_SampleSetExternalClock
whismanoid 0:f7d706d2904d 1658 ///
whismanoid 0:f7d706d2904d 1659 /// Measure ADC channels in an arbitrary pattern.
whismanoid 0:f7d706d2904d 1660 /// Channels can be visited in any order, with repetition allowed.
whismanoid 0:f7d706d2904d 1661 /// External clock mode.
whismanoid 0:f7d706d2904d 1662 /// @pre g_MAX11131_device.enabledChannelsPatternLength_1_256: number of channel selections
whismanoid 0:f7d706d2904d 1663 /// @pre g_MAX11131_device.enabledChannelsPattern: array containing channel selection pattern
whismanoid 0:f7d706d2904d 1664 /// In the array, one channel select per byte.
whismanoid 0:f7d706d2904d 1665 /// In the SPI interface, immediately after SAMPLESET register is written,
whismanoid 0:f7d706d2904d 1666 /// each byte encodes two channelNumber selections.
whismanoid 0:f7d706d2904d 1667 /// The high 4 bits encode the first channelNumber.
whismanoid 0:f7d706d2904d 1668 /// (((enabledChannelsPattern[0]) & 0x0F) << 4) | ((enabledChannelsPattern[1]) & 0x0F)
whismanoid 0:f7d706d2904d 1669 /// If it is an odd number of channels, additional nybbles will be ignored.
whismanoid 0:f7d706d2904d 1670 /// CS will be asserted low during the entire SAMPLESET pattern selection.
whismanoid 0:f7d706d2904d 1671 /// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid 0:f7d706d2904d 1672 /// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid 0:f7d706d2904d 1673 /// @return number of ScanRead() words needed to retrieve the data.
whismanoid 0:f7d706d2904d 1674 /// For external clock modes, the data format depends on CHAN_ID.
whismanoid 0:f7d706d2904d 1675 /// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid 0:f7d706d2904d 1676 /// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid 0:f7d706d2904d 1677 ///
whismanoid 0:f7d706d2904d 1678 int ScanSampleSetExternalClock(void);
whismanoid 0:f7d706d2904d 1679
whismanoid 0:f7d706d2904d 1680 //----------------------------------------
whismanoid 0:f7d706d2904d 1681 /// Example configure and perform some measurements in ScanManual mode.
whismanoid 0:f7d706d2904d 1682 /// @param[out] pd_mean = address for double mean (avearge)
whismanoid 0:f7d706d2904d 1683 /// @param[out] pd_variance = address for double variance (variance)
whismanoid 0:f7d706d2904d 1684 /// @param[out] pd_stddev = address for double stddev (standard deviation)
whismanoid 0:f7d706d2904d 1685 /// @param[out] pd_Sx = address for double Sx (sum of all X)
whismanoid 0:f7d706d2904d 1686 /// @param[out] pd_Sxx = address for double Sxx (sum of squares of each X)
whismanoid 0:f7d706d2904d 1687 void Example_ScanManual(int channelNumber_0_15, int nWords,
whismanoid 0:f7d706d2904d 1688 double* pd_mean, double* pd_variance, double* pd_stddev,
whismanoid 0:f7d706d2904d 1689 double* pd_Sx, double* pd_Sxx);
whismanoid 0:f7d706d2904d 1690
whismanoid 0:f7d706d2904d 1691 }; // end of class MAX11131
whismanoid 0:f7d706d2904d 1692
whismanoid 0:f7d706d2904d 1693 #endif // __MAX11131_H__
whismanoid 0:f7d706d2904d 1694
whismanoid 0:f7d706d2904d 1695 // End of file