MAX11131 - Maxim Integrated MAX11131 SPI 12-bit 16-channel A…

Maxim Integrated » Code » MAX11131

Maxim Integrated MAX11131 SPI 12-bit 16-channel ADC with SampleSet

Dependents: MAX11131BOB_Tester MAX11131BOB_12bit_16ch_SampleSet_SPI_ADC MAX11131BOB_Serial_Tester

MAX11131.h@1:77f1ee332e4a, 2019-06-17 (annotated)

Committer:: whismanoid
Date:: Mon Jun 17 05:37:06 2019 +0000
Revision:: 1:77f1ee332e4a
Parent:: 0:f7d706d2904d
Child:: 4:8a0ae95546fa

remove serial port dependency from mbed hello; minor documentation updates

Who changed what in which revision?

User	Revision	Line number	New contents of line
whismanoid	1:77f1ee332e4a	1	// /*******************************************************************************
whismanoid	0:f7d706d2904d	2	// * Copyright (C) 2019 Maxim Integrated Products, Inc., All Rights Reserved.
whismanoid	0:f7d706d2904d	3	// *
whismanoid	0:f7d706d2904d	4	// * Permission is hereby granted, free of charge, to any person obtaining a
whismanoid	0:f7d706d2904d	5	// * copy of this software and associated documentation files (the "Software"),
whismanoid	0:f7d706d2904d	6	// * to deal in the Software without restriction, including without limitation
whismanoid	0:f7d706d2904d	7	// * the rights to use, copy, modify, merge, publish, distribute, sublicense,
whismanoid	0:f7d706d2904d	8	// * and/or sell copies of the Software, and to permit persons to whom the
whismanoid	0:f7d706d2904d	9	// * Software is furnished to do so, subject to the following conditions:
whismanoid	0:f7d706d2904d	10	// *
whismanoid	0:f7d706d2904d	11	// * The above copyright notice and this permission notice shall be included
whismanoid	0:f7d706d2904d	12	// * in all copies or substantial portions of the Software.
whismanoid	0:f7d706d2904d	13	// *
whismanoid	0:f7d706d2904d	14	// * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
whismanoid	0:f7d706d2904d	15	// * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
whismanoid	0:f7d706d2904d	16	// * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
whismanoid	0:f7d706d2904d	17	// * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
whismanoid	0:f7d706d2904d	18	// * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
whismanoid	0:f7d706d2904d	19	// * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
whismanoid	0:f7d706d2904d	20	// * OTHER DEALINGS IN THE SOFTWARE.
whismanoid	0:f7d706d2904d	21	// *
whismanoid	0:f7d706d2904d	22	// * Except as contained in this notice, the name of Maxim Integrated
whismanoid	0:f7d706d2904d	23	// * Products, Inc. shall not be used except as stated in the Maxim Integrated
whismanoid	0:f7d706d2904d	24	// * Products, Inc. Branding Policy.
whismanoid	0:f7d706d2904d	25	// *
whismanoid	0:f7d706d2904d	26	// * The mere transfer of this software does not imply any licenses
whismanoid	0:f7d706d2904d	27	// * of trade secrets, proprietary technology, copyrights, patents,
whismanoid	0:f7d706d2904d	28	// * trademarks, maskwork rights, or any other form of intellectual
whismanoid	0:f7d706d2904d	29	// * property whatsoever. Maxim Integrated Products, Inc. retains all
whismanoid	0:f7d706d2904d	30	// * ownership rights.
whismanoid	0:f7d706d2904d	31	// *******************************************************************************
whismanoid	0:f7d706d2904d	32	// */
whismanoid	0:f7d706d2904d	33	// *********************************************************************
whismanoid	0:f7d706d2904d	34	// @file MAX11131.h
whismanoid	0:f7d706d2904d	35	// *********************************************************************
whismanoid	0:f7d706d2904d	36	// Header file
whismanoid	0:f7d706d2904d	37	// DO NOT EDIT; except areas designated "CUSTOMIZE". Automatically generated file.
whismanoid	0:f7d706d2904d	38	// generated by XMLSystemOfDevicesToMBED.py
whismanoid	0:f7d706d2904d	39	// System Name = ExampleSystem
whismanoid	0:f7d706d2904d	40	// System Description = Device driver example
whismanoid	0:f7d706d2904d	41	// Device Name = MAX11131
whismanoid	0:f7d706d2904d	42	// Device Description = 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid	0:f7d706d2904d	43	// Device Manufacturer = Maxim Integrated
whismanoid	0:f7d706d2904d	44	// Device PartNumber = MAX11131ATI+
whismanoid	0:f7d706d2904d	45	// Device RegValue_Width = DataWidth16bit_HL
whismanoid	0:f7d706d2904d	46	//
whismanoid	0:f7d706d2904d	47	// ADC MaxOutputDataRate = 3Msps
whismanoid	0:f7d706d2904d	48	// ADC NumChannels = 16
whismanoid	0:f7d706d2904d	49	// ADC ResolutionBits = 12
whismanoid	0:f7d706d2904d	50	//
whismanoid	0:f7d706d2904d	51	// SPI CS = ActiveLow
whismanoid	0:f7d706d2904d	52	// SPI FrameStart = CS
whismanoid	0:f7d706d2904d	53	// SPI CPOL = 1
whismanoid	0:f7d706d2904d	54	// SPI CPHA = 1
whismanoid	0:f7d706d2904d	55	// SPI MOSI and MISO Data are both stable on Rising edge of SCLK
whismanoid	0:f7d706d2904d	56	// SPI SCLK Idle High
whismanoid	0:f7d706d2904d	57	// SPI SCLKMaxMHz = 48
whismanoid	0:f7d706d2904d	58	// SPI SCLKMinMHz = 0.48
whismanoid	0:f7d706d2904d	59	//
whismanoid	0:f7d706d2904d	60
whismanoid	0:f7d706d2904d	61
whismanoid	0:f7d706d2904d	62	// Prevent multiple declaration
whismanoid	0:f7d706d2904d	63	#ifndef __MAX11131_H__
whismanoid	0:f7d706d2904d	64	#define __MAX11131_H__
whismanoid	0:f7d706d2904d	65
whismanoid	0:f7d706d2904d	66	#include "mbed.h"
whismanoid	0:f7d706d2904d	67
whismanoid	0:f7d706d2904d	68	// CODE GENERATOR: conditional defines
whismanoid	0:f7d706d2904d	69	//----------------------------------------
whismanoid	0:f7d706d2904d	70	// Global setting for all channels: ADC_CONFIGURATION.REFSEL
whismanoid	0:f7d706d2904d	71	//
whismanoid	0:f7d706d2904d	72	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	73	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	74	//--------------------
whismanoid	0:f7d706d2904d	75	// external single-ended reference
whismanoid	0:f7d706d2904d	76	//~ #define REFSEL_0 1
whismanoid	0:f7d706d2904d	77	//
whismanoid	0:f7d706d2904d	78	//--------------------
whismanoid	0:f7d706d2904d	79	// external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)
whismanoid	0:f7d706d2904d	80	//~ #define REFSEL_1 1
whismanoid	0:f7d706d2904d	81	//
whismanoid	0:f7d706d2904d	82	//--------------------
whismanoid	0:f7d706d2904d	83	//
whismanoid	0:f7d706d2904d	84	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	85	#ifndef REFSEL_0
whismanoid	0:f7d706d2904d	86	# ifndef REFSEL_1
whismanoid	0:f7d706d2904d	87	# define REFSEL_0 1
whismanoid	0:f7d706d2904d	88	# define REFSEL_1 0
whismanoid	0:f7d706d2904d	89	# endif // REFSEL_1
whismanoid	0:f7d706d2904d	90	#endif // REFSEL_0
whismanoid	0:f7d706d2904d	91	//
whismanoid	0:f7d706d2904d	92	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	93	#if REFSEL_0
whismanoid	0:f7d706d2904d	94	//~ # pragma message("REFSEL_0: external single-ended reference")
whismanoid	0:f7d706d2904d	95	#endif // REFSEL_0
whismanoid	0:f7d706d2904d	96	#if REFSEL_1
whismanoid	0:f7d706d2904d	97	//~ # pragma message("REFSEL_1: external differential reference (For the 16-channel chips: channel AIN15 is unavailable, the pin is assigned to REF-.)")
whismanoid	0:f7d706d2904d	98	#endif // REFSEL_1
whismanoid	0:f7d706d2904d	99	//
whismanoid	0:f7d706d2904d	100	// Validate the REFSEL_0 setting
whismanoid	0:f7d706d2904d	101	#if REFSEL_0
whismanoid	0:f7d706d2904d	102	# if REFSEL_1
whismanoid	0:f7d706d2904d	103	# error("cannot have both REFSEL_0 and REFSEL_1; choose one")
whismanoid	0:f7d706d2904d	104	# endif // REFSEL_1
whismanoid	0:f7d706d2904d	105	#endif // REFSEL_0
whismanoid	0:f7d706d2904d	106
whismanoid	0:f7d706d2904d	107	//----------------------------------------
whismanoid	0:f7d706d2904d	108	// Global setting for all channels: UNIPOLAR.PDIFF_COMM
whismanoid	0:f7d706d2904d	109	//
whismanoid	0:f7d706d2904d	110	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	111	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	112	//--------------------
whismanoid	0:f7d706d2904d	113	// all single-ended channels are pseudo-differential with REF- as common
whismanoid	0:f7d706d2904d	114	//~ #define PDIFF_COMM_1 1
whismanoid	0:f7d706d2904d	115	//
whismanoid	0:f7d706d2904d	116	//--------------------
whismanoid	0:f7d706d2904d	117	// all single-ended channels use GND as common
whismanoid	0:f7d706d2904d	118	//~ #define PDIFF_COMM_0 1
whismanoid	0:f7d706d2904d	119	//
whismanoid	0:f7d706d2904d	120	//--------------------
whismanoid	0:f7d706d2904d	121	//
whismanoid	0:f7d706d2904d	122	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	123	#ifndef PDIFF_COMM_1
whismanoid	0:f7d706d2904d	124	# ifndef PDIFF_COMM_0
whismanoid	0:f7d706d2904d	125	# define PDIFF_COMM_1 0
whismanoid	0:f7d706d2904d	126	# define PDIFF_COMM_0 1
whismanoid	0:f7d706d2904d	127	# endif // PDIFF_COMM_0
whismanoid	0:f7d706d2904d	128	#endif // PDIFF_COMM_1
whismanoid	0:f7d706d2904d	129	//
whismanoid	0:f7d706d2904d	130	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	131	#if PDIFF_COMM_1
whismanoid	0:f7d706d2904d	132	//~ # pragma message("PDIFF_COMM_1: all single-ended channels are pseudo-differential with REF- as common")
whismanoid	0:f7d706d2904d	133	#endif // PDIFF_COMM_1
whismanoid	0:f7d706d2904d	134	#if PDIFF_COMM_0
whismanoid	0:f7d706d2904d	135	//~ # pragma message("PDIFF_COMM_0: all single-ended channels use GND as common")
whismanoid	0:f7d706d2904d	136	#endif // PDIFF_COMM_0
whismanoid	0:f7d706d2904d	137	//
whismanoid	0:f7d706d2904d	138	// Validate the PDIFF_COMM_1 setting
whismanoid	0:f7d706d2904d	139	#if PDIFF_COMM_1
whismanoid	0:f7d706d2904d	140	# if PDIFF_COMM_0
whismanoid	0:f7d706d2904d	141	# error("cannot have both PDIFF_COMM_1 and PDIFF_COMM_0; choose one")
whismanoid	0:f7d706d2904d	142	# endif // PDIFF_COMM_0
whismanoid	0:f7d706d2904d	143	#endif // PDIFF_COMM_1
whismanoid	0:f7d706d2904d	144
whismanoid	0:f7d706d2904d	145	//----------------------------------------
whismanoid	0:f7d706d2904d	146	// ADC Channels AIN0, AIN1
whismanoid	0:f7d706d2904d	147	//
whismanoid	0:f7d706d2904d	148	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	149	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	150	//--------------------
whismanoid	0:f7d706d2904d	151	// ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)
whismanoid	0:f7d706d2904d	152	// Full Scale = VREF
whismanoid	0:f7d706d2904d	153	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	154	// AIN0, AIN1 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	155	// AIN0 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	156	// AIN1 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	157	//
whismanoid	0:f7d706d2904d	158	//~ #define AIN_0_1_DifferentialUnipolar 1
whismanoid	0:f7d706d2904d	159	//
whismanoid	0:f7d706d2904d	160	//--------------------
whismanoid	0:f7d706d2904d	161	// ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid	0:f7d706d2904d	162	// Full Scale = VREF
whismanoid	0:f7d706d2904d	163	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	164	// AIN0, AIN1 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	165	// AIN0 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	166	// AIN1 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	167	//
whismanoid	0:f7d706d2904d	168	//~ #define AIN_0_1_DifferentialBipolarFSVref 1
whismanoid	0:f7d706d2904d	169	//
whismanoid	0:f7d706d2904d	170	//--------------------
whismanoid	0:f7d706d2904d	171	// ADC Channels AIN0, AIN1 = Differential Bipolar
whismanoid	0:f7d706d2904d	172	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	173	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	174	// AIN0, AIN1 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	175	// AIN0 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	176	// AIN1 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	177	//
whismanoid	0:f7d706d2904d	178	//~ #define AIN_0_1_DifferentialBipolarFS2Vref 1
whismanoid	0:f7d706d2904d	179	//
whismanoid	0:f7d706d2904d	180	//--------------------
whismanoid	0:f7d706d2904d	181	// ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	182	// Full Scale = VREF
whismanoid	0:f7d706d2904d	183	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	184	// AIN0 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	185	// AIN1 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	186	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	187	// AIN0 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	188	// AIN1 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	189	//
whismanoid	0:f7d706d2904d	190	//~ #define AIN_0_1_SingleEnded 1
whismanoid	0:f7d706d2904d	191	//
whismanoid	0:f7d706d2904d	192	//--------------------
whismanoid	0:f7d706d2904d	193	//
whismanoid	0:f7d706d2904d	194	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	195	#ifndef AIN_0_1_DifferentialUnipolar
whismanoid	0:f7d706d2904d	196	# ifndef AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	197	# ifndef AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	198	# ifndef AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	199	# define AIN_0_1_DifferentialUnipolar 0
whismanoid	0:f7d706d2904d	200	# define AIN_0_1_DifferentialBipolarFSVref 0
whismanoid	0:f7d706d2904d	201	# define AIN_0_1_DifferentialBipolarFS2Vref 0
whismanoid	0:f7d706d2904d	202	# define AIN_0_1_SingleEnded 1
whismanoid	0:f7d706d2904d	203	# endif // AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	204	# endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	205	# endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	206	#endif // AIN_0_1_DifferentialUnipolar
whismanoid	0:f7d706d2904d	207	//
whismanoid	0:f7d706d2904d	208	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	209	#if AIN_0_1_DifferentialUnipolar
whismanoid	0:f7d706d2904d	210	//~ # pragma message("AIN_0_1_DifferentialUnipolar: ADC Channels AIN0, AIN1 = Differential Unipolar (AIN0 > AIN1)")
whismanoid	0:f7d706d2904d	211	#endif // AIN_0_1_DifferentialUnipolar
whismanoid	0:f7d706d2904d	212	#if AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	213	//~ # pragma message("AIN_0_1_DifferentialBipolarFSVref: ADC Channels AIN0, AIN1 = Differential Bipolar")
whismanoid	0:f7d706d2904d	214	#endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	215	#if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	216	//~ # pragma message("AIN_0_1_DifferentialBipolarFS2Vref: ADC Channels AIN0, AIN1 = Differential Bipolar")
whismanoid	0:f7d706d2904d	217	#endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	218	#if AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	219	//~ # pragma message("AIN_0_1_SingleEnded: ADC Channels AIN0, AIN1 = Both Single-Ended, Unipolar")
whismanoid	0:f7d706d2904d	220	#endif // AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	221	//
whismanoid	0:f7d706d2904d	222	// Validate the AIN_0_1_DifferentialUnipolar setting
whismanoid	0:f7d706d2904d	223	#if AIN_0_1_DifferentialUnipolar
whismanoid	0:f7d706d2904d	224	# if AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	225	# error("cannot have both AIN_0_1_DifferentialUnipolar and AIN_0_1_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	226	# endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	227	# if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	228	# error("cannot have both AIN_0_1_DifferentialUnipolar and AIN_0_1_DifferentialBipolarFS2Vref; choose one")
whismanoid	0:f7d706d2904d	229	# endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	230	# if AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	231	# error("cannot have both AIN_0_1_DifferentialUnipolar and AIN_0_1_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	232	# endif // AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	233	#endif // AIN_0_1_DifferentialUnipolar
whismanoid	0:f7d706d2904d	234	//
whismanoid	0:f7d706d2904d	235	// Validate the AIN_0_1_DifferentialBipolarFSVref setting
whismanoid	0:f7d706d2904d	236	#if AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	237	# if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	238	# error("cannot have both AIN_0_1_DifferentialBipolarFSVref and AIN_0_1_DifferentialBipolarFS2Vref; choose one")
whismanoid	0:f7d706d2904d	239	# endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	240	# if AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	241	# error("cannot have both AIN_0_1_DifferentialBipolarFSVref and AIN_0_1_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	242	# endif // AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	243	#endif // AIN_0_1_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	244	//
whismanoid	0:f7d706d2904d	245	// Validate the AIN_0_1_DifferentialBipolarFS2Vref setting
whismanoid	0:f7d706d2904d	246	#if AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	247	# if AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	248	# error("cannot have both AIN_0_1_DifferentialBipolarFS2Vref and AIN_0_1_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	249	# endif // AIN_0_1_SingleEnded
whismanoid	0:f7d706d2904d	250	#endif // AIN_0_1_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	251
whismanoid	0:f7d706d2904d	252	//----------------------------------------
whismanoid	0:f7d706d2904d	253	// ADC Channels AIN2, AIN3
whismanoid	0:f7d706d2904d	254	//
whismanoid	0:f7d706d2904d	255	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	256	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	257	//--------------------
whismanoid	0:f7d706d2904d	258	// ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid	0:f7d706d2904d	259	// Full Scale = VREF
whismanoid	0:f7d706d2904d	260	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	261	// AIN2, AIN3 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	262	// AIN2 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	263	// AIN3 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	264	//
whismanoid	0:f7d706d2904d	265	//~ #define AIN_2_3_DifferentialBipolarFSVref 1
whismanoid	0:f7d706d2904d	266	//
whismanoid	0:f7d706d2904d	267	//--------------------
whismanoid	0:f7d706d2904d	268	// ADC Channels AIN2, AIN3 = Differential Bipolar
whismanoid	0:f7d706d2904d	269	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	270	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	271	// AIN2, AIN3 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	272	// AIN2 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	273	// AIN3 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	274	//
whismanoid	0:f7d706d2904d	275	//~ #define AIN_2_3_DifferentialBipolarFS2Vref 1
whismanoid	0:f7d706d2904d	276	//
whismanoid	0:f7d706d2904d	277	//--------------------
whismanoid	0:f7d706d2904d	278	// ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	279	// Full Scale = VREF
whismanoid	0:f7d706d2904d	280	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	281	// AIN2 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	282	// AIN3 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	283	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	284	// AIN2 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	285	// AIN3 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	286	//
whismanoid	0:f7d706d2904d	287	//~ #define AIN_2_3_SingleEnded 1
whismanoid	0:f7d706d2904d	288	//
whismanoid	0:f7d706d2904d	289	//--------------------
whismanoid	0:f7d706d2904d	290	// ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)
whismanoid	0:f7d706d2904d	291	// Full Scale = VREF
whismanoid	0:f7d706d2904d	292	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	293	// AIN2, AIN3 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	294	// AIN2 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	295	// AIN3 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	296	//
whismanoid	0:f7d706d2904d	297	//~ #define AIN_2_3_DifferentialUnipolar 1
whismanoid	0:f7d706d2904d	298	//
whismanoid	0:f7d706d2904d	299	//--------------------
whismanoid	0:f7d706d2904d	300	//
whismanoid	0:f7d706d2904d	301	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	302	#ifndef AIN_2_3_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	303	# ifndef AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	304	# ifndef AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	305	# ifndef AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	306	# define AIN_2_3_DifferentialBipolarFSVref 0
whismanoid	0:f7d706d2904d	307	# define AIN_2_3_DifferentialBipolarFS2Vref 0
whismanoid	0:f7d706d2904d	308	# define AIN_2_3_SingleEnded 1
whismanoid	0:f7d706d2904d	309	# define AIN_2_3_DifferentialUnipolar 0
whismanoid	0:f7d706d2904d	310	# endif // AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	311	# endif // AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	312	# endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	313	#endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	314	//
whismanoid	0:f7d706d2904d	315	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	316	#if AIN_2_3_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	317	//~ # pragma message("AIN_2_3_DifferentialBipolarFSVref: ADC Channels AIN2, AIN3 = Differential Bipolar")
whismanoid	0:f7d706d2904d	318	#endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	319	#if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	320	//~ # pragma message("AIN_2_3_DifferentialBipolarFS2Vref: ADC Channels AIN2, AIN3 = Differential Bipolar")
whismanoid	0:f7d706d2904d	321	#endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	322	#if AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	323	//~ # pragma message("AIN_2_3_SingleEnded: ADC Channels AIN2, AIN3 = Both Single-Ended, Unipolar")
whismanoid	0:f7d706d2904d	324	#endif // AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	325	#if AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	326	//~ # pragma message("AIN_2_3_DifferentialUnipolar: ADC Channels AIN2, AIN3 = Differential Unipolar (AIN2 > AIN3)")
whismanoid	0:f7d706d2904d	327	#endif // AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	328	//
whismanoid	0:f7d706d2904d	329	// Validate the AIN_2_3_DifferentialBipolarFSVref setting
whismanoid	0:f7d706d2904d	330	#if AIN_2_3_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	331	# if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	332	# error("cannot have both AIN_2_3_DifferentialBipolarFSVref and AIN_2_3_DifferentialBipolarFS2Vref; choose one")
whismanoid	0:f7d706d2904d	333	# endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	334	# if AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	335	# error("cannot have both AIN_2_3_DifferentialBipolarFSVref and AIN_2_3_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	336	# endif // AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	337	# if AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	338	# error("cannot have both AIN_2_3_DifferentialBipolarFSVref and AIN_2_3_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	339	# endif // AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	340	#endif // AIN_2_3_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	341	//
whismanoid	0:f7d706d2904d	342	// Validate the AIN_2_3_DifferentialBipolarFS2Vref setting
whismanoid	0:f7d706d2904d	343	#if AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	344	# if AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	345	# error("cannot have both AIN_2_3_DifferentialBipolarFS2Vref and AIN_2_3_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	346	# endif // AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	347	# if AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	348	# error("cannot have both AIN_2_3_DifferentialBipolarFS2Vref and AIN_2_3_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	349	# endif // AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	350	#endif // AIN_2_3_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	351	//
whismanoid	0:f7d706d2904d	352	// Validate the AIN_2_3_SingleEnded setting
whismanoid	0:f7d706d2904d	353	#if AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	354	# if AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	355	# error("cannot have both AIN_2_3_SingleEnded and AIN_2_3_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	356	# endif // AIN_2_3_DifferentialUnipolar
whismanoid	0:f7d706d2904d	357	#endif // AIN_2_3_SingleEnded
whismanoid	0:f7d706d2904d	358
whismanoid	0:f7d706d2904d	359	//----------------------------------------
whismanoid	0:f7d706d2904d	360	// ADC Channels AIN4, AIN5
whismanoid	0:f7d706d2904d	361	//
whismanoid	0:f7d706d2904d	362	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	363	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	364	//--------------------
whismanoid	0:f7d706d2904d	365	// ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)
whismanoid	0:f7d706d2904d	366	// Full Scale = VREF
whismanoid	0:f7d706d2904d	367	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	368	// AIN4, AIN5 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	369	// AIN4 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	370	// AIN5 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	371	//
whismanoid	0:f7d706d2904d	372	//~ #define AIN_4_5_DifferentialUnipolar 1
whismanoid	0:f7d706d2904d	373	//
whismanoid	0:f7d706d2904d	374	//--------------------
whismanoid	0:f7d706d2904d	375	// ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid	0:f7d706d2904d	376	// Full Scale = VREF
whismanoid	0:f7d706d2904d	377	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	378	// AIN4, AIN5 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	379	// AIN4 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	380	// AIN5 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	381	//
whismanoid	0:f7d706d2904d	382	//~ #define AIN_4_5_DifferentialBipolarFSVref 1
whismanoid	0:f7d706d2904d	383	//
whismanoid	0:f7d706d2904d	384	//--------------------
whismanoid	0:f7d706d2904d	385	// ADC Channels AIN4, AIN5 = Differential Bipolar
whismanoid	0:f7d706d2904d	386	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	387	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	388	// AIN4, AIN5 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	389	// AIN4 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	390	// AIN5 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	391	//
whismanoid	0:f7d706d2904d	392	//~ #define AIN_4_5_DifferentialBipolarFS2Vref 1
whismanoid	0:f7d706d2904d	393	//
whismanoid	0:f7d706d2904d	394	//--------------------
whismanoid	0:f7d706d2904d	395	// ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	396	// Full Scale = VREF
whismanoid	0:f7d706d2904d	397	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	398	// AIN4 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	399	// AIN5 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	400	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	401	// AIN4 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	402	// AIN5 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	403	//
whismanoid	0:f7d706d2904d	404	//~ #define AIN_4_5_SingleEnded 1
whismanoid	0:f7d706d2904d	405	//
whismanoid	0:f7d706d2904d	406	//--------------------
whismanoid	0:f7d706d2904d	407	//
whismanoid	0:f7d706d2904d	408	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	409	#ifndef AIN_4_5_DifferentialUnipolar
whismanoid	0:f7d706d2904d	410	# ifndef AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	411	# ifndef AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	412	# ifndef AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	413	# define AIN_4_5_DifferentialUnipolar 0
whismanoid	0:f7d706d2904d	414	# define AIN_4_5_DifferentialBipolarFSVref 0
whismanoid	0:f7d706d2904d	415	# define AIN_4_5_DifferentialBipolarFS2Vref 0
whismanoid	0:f7d706d2904d	416	# define AIN_4_5_SingleEnded 1
whismanoid	0:f7d706d2904d	417	# endif // AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	418	# endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	419	# endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	420	#endif // AIN_4_5_DifferentialUnipolar
whismanoid	0:f7d706d2904d	421	//
whismanoid	0:f7d706d2904d	422	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	423	#if AIN_4_5_DifferentialUnipolar
whismanoid	0:f7d706d2904d	424	//~ # pragma message("AIN_4_5_DifferentialUnipolar: ADC Channels AIN4, AIN5 = Differential Unipolar (AIN4 > AIN5)")
whismanoid	0:f7d706d2904d	425	#endif // AIN_4_5_DifferentialUnipolar
whismanoid	0:f7d706d2904d	426	#if AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	427	//~ # pragma message("AIN_4_5_DifferentialBipolarFSVref: ADC Channels AIN4, AIN5 = Differential Bipolar")
whismanoid	0:f7d706d2904d	428	#endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	429	#if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	430	//~ # pragma message("AIN_4_5_DifferentialBipolarFS2Vref: ADC Channels AIN4, AIN5 = Differential Bipolar")
whismanoid	0:f7d706d2904d	431	#endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	432	#if AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	433	//~ # pragma message("AIN_4_5_SingleEnded: ADC Channels AIN4, AIN5 = Both Single-Ended, Unipolar")
whismanoid	0:f7d706d2904d	434	#endif // AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	435	//
whismanoid	0:f7d706d2904d	436	// Validate the AIN_4_5_DifferentialUnipolar setting
whismanoid	0:f7d706d2904d	437	#if AIN_4_5_DifferentialUnipolar
whismanoid	0:f7d706d2904d	438	# if AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	439	# error("cannot have both AIN_4_5_DifferentialUnipolar and AIN_4_5_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	440	# endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	441	# if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	442	# error("cannot have both AIN_4_5_DifferentialUnipolar and AIN_4_5_DifferentialBipolarFS2Vref; choose one")
whismanoid	0:f7d706d2904d	443	# endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	444	# if AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	445	# error("cannot have both AIN_4_5_DifferentialUnipolar and AIN_4_5_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	446	# endif // AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	447	#endif // AIN_4_5_DifferentialUnipolar
whismanoid	0:f7d706d2904d	448	//
whismanoid	0:f7d706d2904d	449	// Validate the AIN_4_5_DifferentialBipolarFSVref setting
whismanoid	0:f7d706d2904d	450	#if AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	451	# if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	452	# error("cannot have both AIN_4_5_DifferentialBipolarFSVref and AIN_4_5_DifferentialBipolarFS2Vref; choose one")
whismanoid	0:f7d706d2904d	453	# endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	454	# if AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	455	# error("cannot have both AIN_4_5_DifferentialBipolarFSVref and AIN_4_5_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	456	# endif // AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	457	#endif // AIN_4_5_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	458	//
whismanoid	0:f7d706d2904d	459	// Validate the AIN_4_5_DifferentialBipolarFS2Vref setting
whismanoid	0:f7d706d2904d	460	#if AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	461	# if AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	462	# error("cannot have both AIN_4_5_DifferentialBipolarFS2Vref and AIN_4_5_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	463	# endif // AIN_4_5_SingleEnded
whismanoid	0:f7d706d2904d	464	#endif // AIN_4_5_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	465
whismanoid	0:f7d706d2904d	466	//----------------------------------------
whismanoid	0:f7d706d2904d	467	// ADC Channels AIN6, AIN7
whismanoid	0:f7d706d2904d	468	//
whismanoid	0:f7d706d2904d	469	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	470	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	471	//--------------------
whismanoid	0:f7d706d2904d	472	// ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid	0:f7d706d2904d	473	// Full Scale = VREF
whismanoid	0:f7d706d2904d	474	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	475	// AIN6, AIN7 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	476	// AIN6 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	477	// AIN7 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	478	//
whismanoid	0:f7d706d2904d	479	//~ #define AIN_6_7_DifferentialBipolarFSVref 1
whismanoid	0:f7d706d2904d	480	//
whismanoid	0:f7d706d2904d	481	//--------------------
whismanoid	0:f7d706d2904d	482	// ADC Channels AIN6, AIN7 = Differential Bipolar
whismanoid	0:f7d706d2904d	483	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	484	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	485	// AIN6, AIN7 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	486	// AIN6 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	487	// AIN7 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	488	//
whismanoid	0:f7d706d2904d	489	//~ #define AIN_6_7_DifferentialBipolarFS2Vref 1
whismanoid	0:f7d706d2904d	490	//
whismanoid	0:f7d706d2904d	491	//--------------------
whismanoid	0:f7d706d2904d	492	// ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	493	// Full Scale = VREF
whismanoid	0:f7d706d2904d	494	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	495	// AIN6 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	496	// AIN7 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	497	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	498	// AIN6 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	499	// AIN7 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	500	//
whismanoid	0:f7d706d2904d	501	//~ #define AIN_6_7_SingleEnded 1
whismanoid	0:f7d706d2904d	502	//
whismanoid	0:f7d706d2904d	503	//--------------------
whismanoid	0:f7d706d2904d	504	// ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)
whismanoid	0:f7d706d2904d	505	// Full Scale = VREF
whismanoid	0:f7d706d2904d	506	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	507	// AIN6, AIN7 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	508	// AIN6 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	509	// AIN7 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	510	//
whismanoid	0:f7d706d2904d	511	//~ #define AIN_6_7_DifferentialUnipolar 1
whismanoid	0:f7d706d2904d	512	//
whismanoid	0:f7d706d2904d	513	//--------------------
whismanoid	0:f7d706d2904d	514	//
whismanoid	0:f7d706d2904d	515	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	516	#ifndef AIN_6_7_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	517	# ifndef AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	518	# ifndef AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	519	# ifndef AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	520	# define AIN_6_7_DifferentialBipolarFSVref 0
whismanoid	0:f7d706d2904d	521	# define AIN_6_7_DifferentialBipolarFS2Vref 0
whismanoid	0:f7d706d2904d	522	# define AIN_6_7_SingleEnded 1
whismanoid	0:f7d706d2904d	523	# define AIN_6_7_DifferentialUnipolar 0
whismanoid	0:f7d706d2904d	524	# endif // AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	525	# endif // AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	526	# endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	527	#endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	528	//
whismanoid	0:f7d706d2904d	529	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	530	#if AIN_6_7_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	531	//~ # pragma message("AIN_6_7_DifferentialBipolarFSVref: ADC Channels AIN6, AIN7 = Differential Bipolar")
whismanoid	0:f7d706d2904d	532	#endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	533	#if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	534	//~ # pragma message("AIN_6_7_DifferentialBipolarFS2Vref: ADC Channels AIN6, AIN7 = Differential Bipolar")
whismanoid	0:f7d706d2904d	535	#endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	536	#if AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	537	//~ # pragma message("AIN_6_7_SingleEnded: ADC Channels AIN6, AIN7 = Both Single-Ended, Unipolar")
whismanoid	0:f7d706d2904d	538	#endif // AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	539	#if AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	540	//~ # pragma message("AIN_6_7_DifferentialUnipolar: ADC Channels AIN6, AIN7 = Differential Unipolar (AIN6 > AIN7)")
whismanoid	0:f7d706d2904d	541	#endif // AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	542	//
whismanoid	0:f7d706d2904d	543	// Validate the AIN_6_7_DifferentialBipolarFSVref setting
whismanoid	0:f7d706d2904d	544	#if AIN_6_7_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	545	# if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	546	# error("cannot have both AIN_6_7_DifferentialBipolarFSVref and AIN_6_7_DifferentialBipolarFS2Vref; choose one")
whismanoid	0:f7d706d2904d	547	# endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	548	# if AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	549	# error("cannot have both AIN_6_7_DifferentialBipolarFSVref and AIN_6_7_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	550	# endif // AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	551	# if AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	552	# error("cannot have both AIN_6_7_DifferentialBipolarFSVref and AIN_6_7_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	553	# endif // AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	554	#endif // AIN_6_7_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	555	//
whismanoid	0:f7d706d2904d	556	// Validate the AIN_6_7_DifferentialBipolarFS2Vref setting
whismanoid	0:f7d706d2904d	557	#if AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	558	# if AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	559	# error("cannot have both AIN_6_7_DifferentialBipolarFS2Vref and AIN_6_7_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	560	# endif // AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	561	# if AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	562	# error("cannot have both AIN_6_7_DifferentialBipolarFS2Vref and AIN_6_7_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	563	# endif // AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	564	#endif // AIN_6_7_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	565	//
whismanoid	0:f7d706d2904d	566	// Validate the AIN_6_7_SingleEnded setting
whismanoid	0:f7d706d2904d	567	#if AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	568	# if AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	569	# error("cannot have both AIN_6_7_SingleEnded and AIN_6_7_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	570	# endif // AIN_6_7_DifferentialUnipolar
whismanoid	0:f7d706d2904d	571	#endif // AIN_6_7_SingleEnded
whismanoid	0:f7d706d2904d	572
whismanoid	0:f7d706d2904d	573	//----------------------------------------
whismanoid	0:f7d706d2904d	574	// ADC Channels AIN8, AIN9
whismanoid	0:f7d706d2904d	575	//
whismanoid	0:f7d706d2904d	576	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	577	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	578	//--------------------
whismanoid	0:f7d706d2904d	579	// ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)
whismanoid	0:f7d706d2904d	580	// Full Scale = VREF
whismanoid	0:f7d706d2904d	581	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	582	// AIN8, AIN9 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	583	// AIN8 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	584	// AIN9 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	585	//
whismanoid	0:f7d706d2904d	586	//~ #define AIN_8_9_DifferentialUnipolar 1
whismanoid	0:f7d706d2904d	587	//
whismanoid	0:f7d706d2904d	588	//--------------------
whismanoid	0:f7d706d2904d	589	// ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid	0:f7d706d2904d	590	// Full Scale = VREF
whismanoid	0:f7d706d2904d	591	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	592	// AIN8, AIN9 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	593	// AIN8 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	594	// AIN9 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	595	//
whismanoid	0:f7d706d2904d	596	//~ #define AIN_8_9_DifferentialBipolarFSVref 1
whismanoid	0:f7d706d2904d	597	//
whismanoid	0:f7d706d2904d	598	//--------------------
whismanoid	0:f7d706d2904d	599	// ADC Channels AIN8, AIN9 = Differential Bipolar
whismanoid	0:f7d706d2904d	600	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	601	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	602	// AIN8, AIN9 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	603	// AIN8 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	604	// AIN9 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	605	//
whismanoid	0:f7d706d2904d	606	//~ #define AIN_8_9_DifferentialBipolarFS2Vref 1
whismanoid	0:f7d706d2904d	607	//
whismanoid	0:f7d706d2904d	608	//--------------------
whismanoid	0:f7d706d2904d	609	// ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	610	// Full Scale = VREF
whismanoid	0:f7d706d2904d	611	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	612	// AIN8 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	613	// AIN9 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	614	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	615	// AIN8 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	616	// AIN9 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	617	//
whismanoid	0:f7d706d2904d	618	//~ #define AIN_8_9_SingleEnded 1
whismanoid	0:f7d706d2904d	619	//
whismanoid	0:f7d706d2904d	620	//--------------------
whismanoid	0:f7d706d2904d	621	//
whismanoid	0:f7d706d2904d	622	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	623	#ifndef AIN_8_9_DifferentialUnipolar
whismanoid	0:f7d706d2904d	624	# ifndef AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	625	# ifndef AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	626	# ifndef AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	627	# define AIN_8_9_DifferentialUnipolar 0
whismanoid	0:f7d706d2904d	628	# define AIN_8_9_DifferentialBipolarFSVref 0
whismanoid	0:f7d706d2904d	629	# define AIN_8_9_DifferentialBipolarFS2Vref 0
whismanoid	0:f7d706d2904d	630	# define AIN_8_9_SingleEnded 1
whismanoid	0:f7d706d2904d	631	# endif // AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	632	# endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	633	# endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	634	#endif // AIN_8_9_DifferentialUnipolar
whismanoid	0:f7d706d2904d	635	//
whismanoid	0:f7d706d2904d	636	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	637	#if AIN_8_9_DifferentialUnipolar
whismanoid	0:f7d706d2904d	638	//~ # pragma message("AIN_8_9_DifferentialUnipolar: ADC Channels AIN8, AIN9 = Differential Unipolar (AIN8 > AIN9)")
whismanoid	0:f7d706d2904d	639	#endif // AIN_8_9_DifferentialUnipolar
whismanoid	0:f7d706d2904d	640	#if AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	641	//~ # pragma message("AIN_8_9_DifferentialBipolarFSVref: ADC Channels AIN8, AIN9 = Differential Bipolar")
whismanoid	0:f7d706d2904d	642	#endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	643	#if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	644	//~ # pragma message("AIN_8_9_DifferentialBipolarFS2Vref: ADC Channels AIN8, AIN9 = Differential Bipolar")
whismanoid	0:f7d706d2904d	645	#endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	646	#if AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	647	//~ # pragma message("AIN_8_9_SingleEnded: ADC Channels AIN8, AIN9 = Both Single-Ended, Unipolar")
whismanoid	0:f7d706d2904d	648	#endif // AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	649	//
whismanoid	0:f7d706d2904d	650	// Validate the AIN_8_9_DifferentialUnipolar setting
whismanoid	0:f7d706d2904d	651	#if AIN_8_9_DifferentialUnipolar
whismanoid	0:f7d706d2904d	652	# if AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	653	# error("cannot have both AIN_8_9_DifferentialUnipolar and AIN_8_9_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	654	# endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	655	# if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	656	# error("cannot have both AIN_8_9_DifferentialUnipolar and AIN_8_9_DifferentialBipolarFS2Vref; choose one")
whismanoid	0:f7d706d2904d	657	# endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	658	# if AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	659	# error("cannot have both AIN_8_9_DifferentialUnipolar and AIN_8_9_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	660	# endif // AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	661	#endif // AIN_8_9_DifferentialUnipolar
whismanoid	0:f7d706d2904d	662	//
whismanoid	0:f7d706d2904d	663	// Validate the AIN_8_9_DifferentialBipolarFSVref setting
whismanoid	0:f7d706d2904d	664	#if AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	665	# if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	666	# error("cannot have both AIN_8_9_DifferentialBipolarFSVref and AIN_8_9_DifferentialBipolarFS2Vref; choose one")
whismanoid	0:f7d706d2904d	667	# endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	668	# if AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	669	# error("cannot have both AIN_8_9_DifferentialBipolarFSVref and AIN_8_9_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	670	# endif // AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	671	#endif // AIN_8_9_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	672	//
whismanoid	0:f7d706d2904d	673	// Validate the AIN_8_9_DifferentialBipolarFS2Vref setting
whismanoid	0:f7d706d2904d	674	#if AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	675	# if AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	676	# error("cannot have both AIN_8_9_DifferentialBipolarFS2Vref and AIN_8_9_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	677	# endif // AIN_8_9_SingleEnded
whismanoid	0:f7d706d2904d	678	#endif // AIN_8_9_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	679
whismanoid	0:f7d706d2904d	680	//----------------------------------------
whismanoid	0:f7d706d2904d	681	// ADC Channels AIN10, AIN11
whismanoid	0:f7d706d2904d	682	//
whismanoid	0:f7d706d2904d	683	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	684	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	685	//--------------------
whismanoid	0:f7d706d2904d	686	// ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid	0:f7d706d2904d	687	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	688	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	689	// AIN10, AIN11 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	690	// AIN10 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	691	// AIN11 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	692	//
whismanoid	0:f7d706d2904d	693	//~ #define AIN_10_11_DifferentialBipolarFS2Vref 1
whismanoid	0:f7d706d2904d	694	//
whismanoid	0:f7d706d2904d	695	//--------------------
whismanoid	0:f7d706d2904d	696	// ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	697	// Full Scale = VREF
whismanoid	0:f7d706d2904d	698	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	699	// AIN10 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	700	// AIN11 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	701	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	702	// AIN10 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	703	// AIN11 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	704	//
whismanoid	0:f7d706d2904d	705	//~ #define AIN_10_11_SingleEnded 1
whismanoid	0:f7d706d2904d	706	//
whismanoid	0:f7d706d2904d	707	//--------------------
whismanoid	0:f7d706d2904d	708	// ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)
whismanoid	0:f7d706d2904d	709	// Full Scale = VREF
whismanoid	0:f7d706d2904d	710	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	711	// AIN10, AIN11 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	712	// AIN10 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	713	// AIN11 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	714	//
whismanoid	0:f7d706d2904d	715	//~ #define AIN_10_11_DifferentialUnipolar 1
whismanoid	0:f7d706d2904d	716	//
whismanoid	0:f7d706d2904d	717	//--------------------
whismanoid	0:f7d706d2904d	718	// ADC Channels AIN10, AIN11 = Differential Bipolar
whismanoid	0:f7d706d2904d	719	// Full Scale = VREF
whismanoid	0:f7d706d2904d	720	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	721	// AIN10, AIN11 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	722	// AIN10 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	723	// AIN11 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	724	//
whismanoid	0:f7d706d2904d	725	//~ #define AIN_10_11_DifferentialBipolarFSVref 1
whismanoid	0:f7d706d2904d	726	//
whismanoid	0:f7d706d2904d	727	//--------------------
whismanoid	0:f7d706d2904d	728	//
whismanoid	0:f7d706d2904d	729	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	730	#ifndef AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	731	# ifndef AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	732	# ifndef AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	733	# ifndef AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	734	# define AIN_10_11_DifferentialBipolarFS2Vref 0
whismanoid	0:f7d706d2904d	735	# define AIN_10_11_SingleEnded 1
whismanoid	0:f7d706d2904d	736	# define AIN_10_11_DifferentialUnipolar 0
whismanoid	0:f7d706d2904d	737	# define AIN_10_11_DifferentialBipolarFSVref 0
whismanoid	0:f7d706d2904d	738	# endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	739	# endif // AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	740	# endif // AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	741	#endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	742	//
whismanoid	0:f7d706d2904d	743	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	744	#if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	745	//~ # pragma message("AIN_10_11_DifferentialBipolarFS2Vref: ADC Channels AIN10, AIN11 = Differential Bipolar")
whismanoid	0:f7d706d2904d	746	#endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	747	#if AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	748	//~ # pragma message("AIN_10_11_SingleEnded: ADC Channels AIN10, AIN11 = Both Single-Ended, Unipolar")
whismanoid	0:f7d706d2904d	749	#endif // AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	750	#if AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	751	//~ # pragma message("AIN_10_11_DifferentialUnipolar: ADC Channels AIN10, AIN11 = Differential Unipolar (AIN10 > AIN11)")
whismanoid	0:f7d706d2904d	752	#endif // AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	753	#if AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	754	//~ # pragma message("AIN_10_11_DifferentialBipolarFSVref: ADC Channels AIN10, AIN11 = Differential Bipolar")
whismanoid	0:f7d706d2904d	755	#endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	756	//
whismanoid	0:f7d706d2904d	757	// Validate the AIN_10_11_DifferentialBipolarFS2Vref setting
whismanoid	0:f7d706d2904d	758	#if AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	759	# if AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	760	# error("cannot have both AIN_10_11_DifferentialBipolarFS2Vref and AIN_10_11_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	761	# endif // AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	762	# if AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	763	# error("cannot have both AIN_10_11_DifferentialBipolarFS2Vref and AIN_10_11_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	764	# endif // AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	765	# if AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	766	# error("cannot have both AIN_10_11_DifferentialBipolarFS2Vref and AIN_10_11_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	767	# endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	768	#endif // AIN_10_11_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	769	//
whismanoid	0:f7d706d2904d	770	// Validate the AIN_10_11_SingleEnded setting
whismanoid	0:f7d706d2904d	771	#if AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	772	# if AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	773	# error("cannot have both AIN_10_11_SingleEnded and AIN_10_11_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	774	# endif // AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	775	# if AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	776	# error("cannot have both AIN_10_11_SingleEnded and AIN_10_11_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	777	# endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	778	#endif // AIN_10_11_SingleEnded
whismanoid	0:f7d706d2904d	779	//
whismanoid	0:f7d706d2904d	780	// Validate the AIN_10_11_DifferentialUnipolar setting
whismanoid	0:f7d706d2904d	781	#if AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	782	# if AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	783	# error("cannot have both AIN_10_11_DifferentialUnipolar and AIN_10_11_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	784	# endif // AIN_10_11_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	785	#endif // AIN_10_11_DifferentialUnipolar
whismanoid	0:f7d706d2904d	786
whismanoid	0:f7d706d2904d	787	//----------------------------------------
whismanoid	0:f7d706d2904d	788	// ADC Channels AIN12, AIN13
whismanoid	0:f7d706d2904d	789	//
whismanoid	0:f7d706d2904d	790	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	791	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	792	//--------------------
whismanoid	0:f7d706d2904d	793	// ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid	0:f7d706d2904d	794	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	795	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	796	// AIN12, AIN13 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	797	// AIN12 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	798	// AIN13 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	799	//
whismanoid	0:f7d706d2904d	800	//~ #define AIN_12_13_DifferentialBipolarFS2Vref 1
whismanoid	0:f7d706d2904d	801	//
whismanoid	0:f7d706d2904d	802	//--------------------
whismanoid	0:f7d706d2904d	803	// ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	804	// Full Scale = VREF
whismanoid	0:f7d706d2904d	805	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	806	// AIN12 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	807	// AIN13 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	808	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	809	// AIN12 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	810	// AIN13 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	811	//
whismanoid	0:f7d706d2904d	812	//~ #define AIN_12_13_SingleEnded 1
whismanoid	0:f7d706d2904d	813	//
whismanoid	0:f7d706d2904d	814	//--------------------
whismanoid	0:f7d706d2904d	815	// ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)
whismanoid	0:f7d706d2904d	816	// Full Scale = VREF
whismanoid	0:f7d706d2904d	817	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	818	// AIN12, AIN13 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	819	// AIN12 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	820	// AIN13 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	821	//
whismanoid	0:f7d706d2904d	822	//~ #define AIN_12_13_DifferentialUnipolar 1
whismanoid	0:f7d706d2904d	823	//
whismanoid	0:f7d706d2904d	824	//--------------------
whismanoid	0:f7d706d2904d	825	// ADC Channels AIN12, AIN13 = Differential Bipolar
whismanoid	0:f7d706d2904d	826	// Full Scale = VREF
whismanoid	0:f7d706d2904d	827	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	828	// AIN12, AIN13 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	829	// AIN12 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	830	// AIN13 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	831	//
whismanoid	0:f7d706d2904d	832	//~ #define AIN_12_13_DifferentialBipolarFSVref 1
whismanoid	0:f7d706d2904d	833	//
whismanoid	0:f7d706d2904d	834	//--------------------
whismanoid	0:f7d706d2904d	835	//
whismanoid	0:f7d706d2904d	836	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	837	#ifndef AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	838	# ifndef AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	839	# ifndef AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	840	# ifndef AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	841	# define AIN_12_13_DifferentialBipolarFS2Vref 0
whismanoid	0:f7d706d2904d	842	# define AIN_12_13_SingleEnded 1
whismanoid	0:f7d706d2904d	843	# define AIN_12_13_DifferentialUnipolar 0
whismanoid	0:f7d706d2904d	844	# define AIN_12_13_DifferentialBipolarFSVref 0
whismanoid	0:f7d706d2904d	845	# endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	846	# endif // AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	847	# endif // AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	848	#endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	849	//
whismanoid	0:f7d706d2904d	850	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	851	#if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	852	//~ # pragma message("AIN_12_13_DifferentialBipolarFS2Vref: ADC Channels AIN12, AIN13 = Differential Bipolar")
whismanoid	0:f7d706d2904d	853	#endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	854	#if AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	855	//~ # pragma message("AIN_12_13_SingleEnded: ADC Channels AIN12, AIN13 = Both Single-Ended, Unipolar")
whismanoid	0:f7d706d2904d	856	#endif // AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	857	#if AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	858	//~ # pragma message("AIN_12_13_DifferentialUnipolar: ADC Channels AIN12, AIN13 = Differential Unipolar (AIN12 > AIN13)")
whismanoid	0:f7d706d2904d	859	#endif // AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	860	#if AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	861	//~ # pragma message("AIN_12_13_DifferentialBipolarFSVref: ADC Channels AIN12, AIN13 = Differential Bipolar")
whismanoid	0:f7d706d2904d	862	#endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	863	//
whismanoid	0:f7d706d2904d	864	// Validate the AIN_12_13_DifferentialBipolarFS2Vref setting
whismanoid	0:f7d706d2904d	865	#if AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	866	# if AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	867	# error("cannot have both AIN_12_13_DifferentialBipolarFS2Vref and AIN_12_13_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	868	# endif // AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	869	# if AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	870	# error("cannot have both AIN_12_13_DifferentialBipolarFS2Vref and AIN_12_13_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	871	# endif // AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	872	# if AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	873	# error("cannot have both AIN_12_13_DifferentialBipolarFS2Vref and AIN_12_13_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	874	# endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	875	#endif // AIN_12_13_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	876	//
whismanoid	0:f7d706d2904d	877	// Validate the AIN_12_13_SingleEnded setting
whismanoid	0:f7d706d2904d	878	#if AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	879	# if AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	880	# error("cannot have both AIN_12_13_SingleEnded and AIN_12_13_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	881	# endif // AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	882	# if AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	883	# error("cannot have both AIN_12_13_SingleEnded and AIN_12_13_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	884	# endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	885	#endif // AIN_12_13_SingleEnded
whismanoid	0:f7d706d2904d	886	//
whismanoid	0:f7d706d2904d	887	// Validate the AIN_12_13_DifferentialUnipolar setting
whismanoid	0:f7d706d2904d	888	#if AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	889	# if AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	890	# error("cannot have both AIN_12_13_DifferentialUnipolar and AIN_12_13_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	891	# endif // AIN_12_13_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	892	#endif // AIN_12_13_DifferentialUnipolar
whismanoid	0:f7d706d2904d	893
whismanoid	0:f7d706d2904d	894	//----------------------------------------
whismanoid	0:f7d706d2904d	895	// ADC Channels AIN14, AIN15
whismanoid	0:f7d706d2904d	896	//
whismanoid	0:f7d706d2904d	897	// CUSTOMIZE: select one of the following options
whismanoid	0:f7d706d2904d	898	// either by uncommenting in this file or define at the project level
whismanoid	0:f7d706d2904d	899	//--------------------
whismanoid	0:f7d706d2904d	900	// ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid	0:f7d706d2904d	901	// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	902	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	903	// AIN14, AIN15 are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	904	// AIN14 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	905	// AIN15 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	906	//
whismanoid	0:f7d706d2904d	907	//~ #define AIN_14_15_DifferentialBipolarFS2Vref 1
whismanoid	0:f7d706d2904d	908	//
whismanoid	0:f7d706d2904d	909	//--------------------
whismanoid	0:f7d706d2904d	910	// ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	911	// Full Scale = VREF
whismanoid	0:f7d706d2904d	912	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	913	// AIN14 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	914	// AIN15 is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	915	// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	916	// AIN14 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	917	// AIN15 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	918	//
whismanoid	0:f7d706d2904d	919	//~ #define AIN_14_15_SingleEnded 1
whismanoid	0:f7d706d2904d	920	//
whismanoid	0:f7d706d2904d	921	//--------------------
whismanoid	0:f7d706d2904d	922	// ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)
whismanoid	0:f7d706d2904d	923	// Full Scale = VREF
whismanoid	0:f7d706d2904d	924	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	925	// AIN14, AIN15 are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	926	// AIN14 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	927	// AIN15 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	928	//
whismanoid	0:f7d706d2904d	929	//~ #define AIN_14_15_DifferentialUnipolar 1
whismanoid	0:f7d706d2904d	930	//
whismanoid	0:f7d706d2904d	931	//--------------------
whismanoid	0:f7d706d2904d	932	// ADC Channels AIN14, AIN15 = Differential Bipolar
whismanoid	0:f7d706d2904d	933	// Full Scale = VREF
whismanoid	0:f7d706d2904d	934	// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	935	// AIN14, AIN15 are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	936	// AIN14 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	937	// AIN15 voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	938	//
whismanoid	0:f7d706d2904d	939	//~ #define AIN_14_15_DifferentialBipolarFSVref 1
whismanoid	0:f7d706d2904d	940	//
whismanoid	0:f7d706d2904d	941	//--------------------
whismanoid	0:f7d706d2904d	942	//
whismanoid	0:f7d706d2904d	943	// Default settings if not defined at project level
whismanoid	0:f7d706d2904d	944	#ifndef AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	945	# ifndef AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	946	# ifndef AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	947	# ifndef AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	948	# define AIN_14_15_DifferentialBipolarFS2Vref 0
whismanoid	0:f7d706d2904d	949	# define AIN_14_15_SingleEnded 1
whismanoid	0:f7d706d2904d	950	# define AIN_14_15_DifferentialUnipolar 0
whismanoid	0:f7d706d2904d	951	# define AIN_14_15_DifferentialBipolarFSVref 0
whismanoid	0:f7d706d2904d	952	# endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	953	# endif // AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	954	# endif // AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	955	#endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	956	//
whismanoid	0:f7d706d2904d	957	// (optional diagnostic) pragma message the active setting
whismanoid	0:f7d706d2904d	958	#if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	959	//~ # pragma message("AIN_14_15_DifferentialBipolarFS2Vref: ADC Channels AIN14, AIN15 = Differential Bipolar")
whismanoid	0:f7d706d2904d	960	#endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	961	#if AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	962	//~ # pragma message("AIN_14_15_SingleEnded: ADC Channels AIN14, AIN15 = Both Single-Ended, Unipolar")
whismanoid	0:f7d706d2904d	963	#endif // AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	964	#if AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	965	//~ # pragma message("AIN_14_15_DifferentialUnipolar: ADC Channels AIN14, AIN15 = Differential Unipolar (AIN14 > AIN15)")
whismanoid	0:f7d706d2904d	966	#endif // AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	967	#if AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	968	//~ # pragma message("AIN_14_15_DifferentialBipolarFSVref: ADC Channels AIN14, AIN15 = Differential Bipolar")
whismanoid	0:f7d706d2904d	969	#endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	970	//
whismanoid	0:f7d706d2904d	971	// Validate the AIN_14_15_DifferentialBipolarFS2Vref setting
whismanoid	0:f7d706d2904d	972	#if AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	973	# if AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	974	# error("cannot have both AIN_14_15_DifferentialBipolarFS2Vref and AIN_14_15_SingleEnded; choose one")
whismanoid	0:f7d706d2904d	975	# endif // AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	976	# if AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	977	# error("cannot have both AIN_14_15_DifferentialBipolarFS2Vref and AIN_14_15_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	978	# endif // AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	979	# if AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	980	# error("cannot have both AIN_14_15_DifferentialBipolarFS2Vref and AIN_14_15_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	981	# endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	982	#endif // AIN_14_15_DifferentialBipolarFS2Vref
whismanoid	0:f7d706d2904d	983	//
whismanoid	0:f7d706d2904d	984	// Validate the AIN_14_15_SingleEnded setting
whismanoid	0:f7d706d2904d	985	#if AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	986	# if AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	987	# error("cannot have both AIN_14_15_SingleEnded and AIN_14_15_DifferentialUnipolar; choose one")
whismanoid	0:f7d706d2904d	988	# endif // AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	989	# if AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	990	# error("cannot have both AIN_14_15_SingleEnded and AIN_14_15_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	991	# endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	992	#endif // AIN_14_15_SingleEnded
whismanoid	0:f7d706d2904d	993	//
whismanoid	0:f7d706d2904d	994	// Validate the AIN_14_15_DifferentialUnipolar setting
whismanoid	0:f7d706d2904d	995	#if AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	996	# if AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	997	# error("cannot have both AIN_14_15_DifferentialUnipolar and AIN_14_15_DifferentialBipolarFSVref; choose one")
whismanoid	0:f7d706d2904d	998	# endif // AIN_14_15_DifferentialBipolarFSVref
whismanoid	0:f7d706d2904d	999	#endif // AIN_14_15_DifferentialUnipolar
whismanoid	0:f7d706d2904d	1000
whismanoid	0:f7d706d2904d	1001	// CODE GENERATOR: class declaration and docstrings
whismanoid	0:f7d706d2904d	1002	/**
whismanoid	0:f7d706d2904d	1003	* @brief MAX11131 3Msps, Low-Power, Serial SPI 12-Bit, 16-Channel, Differential/Single-Ended Input, SAR ADC
whismanoid	0:f7d706d2904d	1004	*
whismanoid	0:f7d706d2904d	1005	*
whismanoid	0:f7d706d2904d	1006	*
whismanoid	0:f7d706d2904d	1007	* Datasheet: https://www.maximintegrated.com/MAX11131
whismanoid	0:f7d706d2904d	1008	*
whismanoid	0:f7d706d2904d	1009	*
whismanoid	0:f7d706d2904d	1010	*
whismanoid	1:77f1ee332e4a	1011	* //---------- CODE GENERATOR: helloCppCodeList
whismanoid	0:f7d706d2904d	1012	* @code
whismanoid	0:f7d706d2904d	1013	* // CODE GENERATOR: example code includes
whismanoid	0:f7d706d2904d	1014	* // example code includes
whismanoid	0:f7d706d2904d	1015	* #include "mbed.h"
whismanoid	0:f7d706d2904d	1016	* //#include "max32625.h"
whismanoid	0:f7d706d2904d	1017	* #include "MAX11131.h"
whismanoid	0:f7d706d2904d	1018	*
whismanoid	0:f7d706d2904d	1019	* // example code board support
whismanoid	0:f7d706d2904d	1020	* //MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
whismanoid	0:f7d706d2904d	1021	* //DigitalOut rLED(LED1);
whismanoid	0:f7d706d2904d	1022	* //DigitalOut gLED(LED2);
whismanoid	0:f7d706d2904d	1023	* //DigitalOut bLED(LED3);
whismanoid	0:f7d706d2904d	1024	* //
whismanoid	0:f7d706d2904d	1025	* // Arduino "shield" connector port definitions (MAX32625MBED shown)
whismanoid	0:f7d706d2904d	1026	* #if defined(TARGET_MAX32625MBED)
whismanoid	0:f7d706d2904d	1027	* #define A0 AIN_0
whismanoid	0:f7d706d2904d	1028	* #define A1 AIN_1
whismanoid	0:f7d706d2904d	1029	* #define A2 AIN_2
whismanoid	0:f7d706d2904d	1030	* #define A3 AIN_3
whismanoid	0:f7d706d2904d	1031	* #define D0 P0_0
whismanoid	0:f7d706d2904d	1032	* #define D1 P0_1
whismanoid	0:f7d706d2904d	1033	* #define D2 P0_2
whismanoid	0:f7d706d2904d	1034	* #define D3 P0_3
whismanoid	0:f7d706d2904d	1035	* #define D4 P0_4
whismanoid	0:f7d706d2904d	1036	* #define D5 P0_5
whismanoid	0:f7d706d2904d	1037	* #define D6 P0_6
whismanoid	0:f7d706d2904d	1038	* #define D7 P0_7
whismanoid	0:f7d706d2904d	1039	* #define D8 P1_4
whismanoid	0:f7d706d2904d	1040	* #define D9 P1_5
whismanoid	0:f7d706d2904d	1041	* #define D10 P1_3
whismanoid	0:f7d706d2904d	1042	* #define D11 P1_1
whismanoid	0:f7d706d2904d	1043	* #define D12 P1_2
whismanoid	0:f7d706d2904d	1044	* #define D13 P1_0
whismanoid	0:f7d706d2904d	1045	* #endif
whismanoid	0:f7d706d2904d	1046	*
whismanoid	0:f7d706d2904d	1047	* // example code declare SPI interface
whismanoid	0:f7d706d2904d	1048	* #if defined(TARGET_MAX32625MBED)
whismanoid	0:f7d706d2904d	1049	* SPI spi(SPI1_MOSI, SPI1_MISO, SPI1_SCK); // mosi, miso, sclk spi1 TARGET_MAX32625MBED: P1_1 P1_2 P1_0 Arduino 10-pin header D11 D12 D13
whismanoid	0:f7d706d2904d	1050	* DigitalOut spi_cs(SPI1_SS); // TARGET_MAX32625MBED: P1_3 Arduino 10-pin header D10
whismanoid	0:f7d706d2904d	1051	* #elif defined(TARGET_MAX32600MBED)
whismanoid	0:f7d706d2904d	1052	* SPI spi(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13
whismanoid	0:f7d706d2904d	1053	* DigitalOut spi_cs(SPI2_SS); // Generic: Arduino 10-pin header D10
whismanoid	0:f7d706d2904d	1054	* #else
whismanoid	0:f7d706d2904d	1055	* SPI spi(D11, D12, D13); // mosi, miso, sclk spi1 TARGET_MAX32600MBED: Arduino 10-pin header D11 D12 D13
whismanoid	0:f7d706d2904d	1056	* DigitalOut spi_cs(D10); // Generic: Arduino 10-pin header D10
whismanoid	0:f7d706d2904d	1057	* #endif
whismanoid	0:f7d706d2904d	1058	*
whismanoid	0:f7d706d2904d	1059	* // example code declare GPIO interface pins
whismanoid	0:f7d706d2904d	1060	* DigitalOut CNVST_pin(D9); // Digital Trigger Input to MAX11131 device
whismanoid	0:f7d706d2904d	1061	* // AnalogOut REF__pin(Px_x_PortName_To_Be_Determined); // Reference Input to MAX11131 device
whismanoid	0:f7d706d2904d	1062	* // AnalogOut REF__AIN15_pin(Px_x_PortName_To_Be_Determined); // Reference Input to MAX11131 device
whismanoid	0:f7d706d2904d	1063	* DigitalIn EOC_pin(D2); // Digital Event Output from MAX11131 device
whismanoid	0:f7d706d2904d	1064	* // example code declare device instance
whismanoid	0:f7d706d2904d	1065	* MAX11131 g_MAX11131_device(spi, spi_cs, CNVST_pin, EOC_pin, MAX11131::MAX11131_IC);
whismanoid	0:f7d706d2904d	1066	*
whismanoid	0:f7d706d2904d	1067	* // example code main function
whismanoid	0:f7d706d2904d	1068	* int main()
whismanoid	0:f7d706d2904d	1069	* {
whismanoid	0:f7d706d2904d	1070	* while (1)
whismanoid	0:f7d706d2904d	1071	* {
whismanoid	0:f7d706d2904d	1072	* // CODE GENERATOR: example code: member function Init
whismanoid	0:f7d706d2904d	1073	* g_MAX11131_device.Init();
whismanoid	0:f7d706d2904d	1074	*
whismanoid	0:f7d706d2904d	1075	* // CODE GENERATOR: example code: has no member function REF
whismanoid	0:f7d706d2904d	1076	* // CODE GENERATOR: example code: has no member function CODE_LOAD
whismanoid	0:f7d706d2904d	1077	* // CODE GENERATOR: example code: has no member function CODEallLOADall
whismanoid	0:f7d706d2904d	1078	* // CODE GENERATOR: example code: has no member function CODEnLOADn
whismanoid	0:f7d706d2904d	1079	* // CODE GENERATOR: example code: member function ScanManual
whismanoid	0:f7d706d2904d	1080	* // @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1081	* // @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1082	* // @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1083	* int channelId_0_15 = 3;
whismanoid	0:f7d706d2904d	1084	* g_MAX11131_device.channelNumber_0_15 = channelId_0_15;
whismanoid	0:f7d706d2904d	1085	* g_MAX11131_device.PowerManagement_0_2 = 0;
whismanoid	0:f7d706d2904d	1086	* g_MAX11131_device.chan_id_0_1 = 1;
whismanoid	0:f7d706d2904d	1087	* g_MAX11131_device.NumWords = g_MAX11131_device.ScanManual();
whismanoid	0:f7d706d2904d	1088	*
whismanoid	0:f7d706d2904d	1089	* // CODE GENERATOR: example code: member function ReadAINcode
whismanoid	0:f7d706d2904d	1090	* // TODO1: CODE GENERATOR: example code: member function ReadAINcode
whismanoid	0:f7d706d2904d	1091	* // Read raw ADC codes from device into AINcode[] and RAW_misoData16[]
whismanoid	0:f7d706d2904d	1092	* // @pre one of the MAX11311_Scan functions was called, setting g_MAX11131_device.NumWords
whismanoid	0:f7d706d2904d	1093	* g_MAX11131_device.ReadAINcode();
whismanoid	0:f7d706d2904d	1094	* // @post RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid	0:f7d706d2904d	1095	* // @post AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid	0:f7d706d2904d	1096	*
whismanoid	0:f7d706d2904d	1097	* wait(3.0);
whismanoid	0:f7d706d2904d	1098	* }
whismanoid	0:f7d706d2904d	1099	* }
whismanoid	0:f7d706d2904d	1100	* @endcode
whismanoid	1:77f1ee332e4a	1101	* //---------- CODE GENERATOR: end helloCppCodeList
whismanoid	0:f7d706d2904d	1102	*/
whismanoid	0:f7d706d2904d	1103	class MAX11131 {
whismanoid	0:f7d706d2904d	1104	public:
whismanoid	0:f7d706d2904d	1105	// CODE GENERATOR: TypedefEnum EnumItem declarations
whismanoid	0:f7d706d2904d	1106	// CODE GENERATOR: TypedefEnum MAX11131_SCAN_enum_t
whismanoid	0:f7d706d2904d	1107	//----------------------------------------
whismanoid	0:f7d706d2904d	1108	/// ADC_MODE_CONTROL.SCAN[3:0] ADC Scan Control (command)
whismanoid	0:f7d706d2904d	1109	typedef enum MAX11131_SCAN_enum_t {
whismanoid	0:f7d706d2904d	1110	SCAN_0000_NOP = 0x00, //!< 8'b00000000
whismanoid	0:f7d706d2904d	1111	SCAN_0001_Manual = 0x01, //!< 8'b00000001
whismanoid	0:f7d706d2904d	1112	SCAN_0010_Repeat = 0x02, //!< 8'b00000010
whismanoid	0:f7d706d2904d	1113	SCAN_0011_StandardInternalClock = 0x03, //!< 8'b00000011
whismanoid	0:f7d706d2904d	1114	SCAN_0100_StandardExternalClock = 0x04, //!< 8'b00000100
whismanoid	0:f7d706d2904d	1115	SCAN_0101_UpperInternalClock = 0x05, //!< 8'b00000101
whismanoid	0:f7d706d2904d	1116	SCAN_0110_UpperExternalClock = 0x06, //!< 8'b00000110
whismanoid	0:f7d706d2904d	1117	SCAN_0111_CustomInternalClock = 0x07, //!< 8'b00000111
whismanoid	0:f7d706d2904d	1118	SCAN_1000_CustomExternalClock = 0x08, //!< 8'b00001000
whismanoid	0:f7d706d2904d	1119	SCAN_1001_SampleSetExternalClock = 0x09, //!< 8'b00001001
whismanoid	0:f7d706d2904d	1120	} MAX11131_SCAN_enum_t;
whismanoid	0:f7d706d2904d	1121
whismanoid	0:f7d706d2904d	1122	// CODE GENERATOR: TypedefEnum MAX11131_RESET_enum_t
whismanoid	0:f7d706d2904d	1123	//----------------------------------------
whismanoid	0:f7d706d2904d	1124	/// ADC_MODE_CONTROL.RESET[1:0] Reset 0=Normal 1=ResetFIFO 2=ResetAllRegisters 3=reserved
whismanoid	0:f7d706d2904d	1125	typedef enum MAX11131_RESET_enum_t {
whismanoid	0:f7d706d2904d	1126	RESET_00_Normal = 0x00, //!< 8'b00000000
whismanoid	0:f7d706d2904d	1127	RESET_01_ResetFIFO = 0x01, //!< 8'b00000001
whismanoid	0:f7d706d2904d	1128	RESET_10_ResetAllRegisters = 0x02, //!< 8'b00000010
whismanoid	0:f7d706d2904d	1129	} MAX11131_RESET_enum_t;
whismanoid	0:f7d706d2904d	1130
whismanoid	0:f7d706d2904d	1131	// CODE GENERATOR: TypedefEnum MAX11131_PM_enum_t
whismanoid	0:f7d706d2904d	1132	//----------------------------------------
whismanoid	0:f7d706d2904d	1133	/// ADC_MODE_CONTROL.PM[1:0] Power Management 0=Normal, 1=AutoShutdown, 2=AutoStandby 3=reserved
whismanoid	0:f7d706d2904d	1134	typedef enum MAX11131_PM_enum_t {
whismanoid	0:f7d706d2904d	1135	PM_00_Normal = 0x00, //!< 8'b00000000
whismanoid	0:f7d706d2904d	1136	PM_01_AutoShutdown = 0x01, //!< 8'b00000001
whismanoid	0:f7d706d2904d	1137	PM_10_AutoStandby = 0x02, //!< 8'b00000010
whismanoid	0:f7d706d2904d	1138	} MAX11131_PM_enum_t;
whismanoid	0:f7d706d2904d	1139
whismanoid	0:f7d706d2904d	1140	// TODO1: CODE GENERATOR: ic_variant -- IC's supported with this driver
whismanoid	0:f7d706d2904d	1141	/**
whismanoid	0:f7d706d2904d	1142	* @brief IC's supported with this driver
whismanoid	0:f7d706d2904d	1143	* @details MAX11131
whismanoid	0:f7d706d2904d	1144	*/
whismanoid	0:f7d706d2904d	1145	typedef enum
whismanoid	0:f7d706d2904d	1146	{
whismanoid	0:f7d706d2904d	1147	MAX11131_IC = 0,
whismanoid	0:f7d706d2904d	1148	//MAX11131_IC = 1
whismanoid	0:f7d706d2904d	1149	} MAX11131_ic_t;
whismanoid	0:f7d706d2904d	1150
whismanoid	0:f7d706d2904d	1151	// TODO1: CODE GENERATOR: class constructor declaration
whismanoid	0:f7d706d2904d	1152	/********************************************************//
whismanoid	0:f7d706d2904d	1153	* @brief Constructor for MAX11131 Class.
whismanoid	0:f7d706d2904d	1154	*
whismanoid	0:f7d706d2904d	1155	* @details Requires an existing SPI object as well as a DigitalOut object.
whismanoid	0:f7d706d2904d	1156	* The DigitalOut object is used for a chip enable signal
whismanoid	0:f7d706d2904d	1157	*
whismanoid	0:f7d706d2904d	1158	* On Entry:
whismanoid	0:f7d706d2904d	1159	* @param[in] spi - pointer to existing SPI object
whismanoid	0:f7d706d2904d	1160	* @param[in] cs_pin - pointer to a DigitalOut pin object
whismanoid	0:f7d706d2904d	1161	* CODE GENERATOR: class constructor docstrings gpio InputPin pins
whismanoid	0:f7d706d2904d	1162	* @param[in] CNVST_pin - pointer to a DigitalOut pin object
whismanoid	0:f7d706d2904d	1163	* CODE GENERATOR: class constructor docstrings gpio OutputPin pins
whismanoid	0:f7d706d2904d	1164	* @param[in] EOC_pin - pointer to a DigitalIn pin object
whismanoid	0:f7d706d2904d	1165	* @param[in] ic_variant - which type of MAX11131 is used
whismanoid	0:f7d706d2904d	1166	*
whismanoid	0:f7d706d2904d	1167	* On Exit:
whismanoid	0:f7d706d2904d	1168	*
whismanoid	0:f7d706d2904d	1169	* @return None
whismanoid	0:f7d706d2904d	1170	**************************************************************/
whismanoid	0:f7d706d2904d	1171	MAX11131(SPI &spi, DigitalOut &cs_pin, // SPI interface
whismanoid	0:f7d706d2904d	1172	// CODE GENERATOR: class constructor declaration gpio InputPin pins
whismanoid	0:f7d706d2904d	1173	DigitalOut &CNVST_pin, // Digital Trigger Input to MAX11131 device
whismanoid	0:f7d706d2904d	1174	// AnalogOut &REF__pin, // Reference Input to MAX11131 device
whismanoid	0:f7d706d2904d	1175	// AnalogOut &REF__AIN15_pin, // Reference Input to MAX11131 device
whismanoid	0:f7d706d2904d	1176	// CODE GENERATOR: class constructor declaration gpio OutputPin pins
whismanoid	0:f7d706d2904d	1177	DigitalIn &EOC_pin, // Digital Event Output from MAX11131 device
whismanoid	0:f7d706d2904d	1178	MAX11131_ic_t ic_variant);
whismanoid	0:f7d706d2904d	1179
whismanoid	0:f7d706d2904d	1180	// CODE GENERATOR: class destructor declaration
whismanoid	0:f7d706d2904d	1181	/************************************************************
whismanoid	0:f7d706d2904d	1182	* @brief Default destructor for MAX11131 Class.
whismanoid	0:f7d706d2904d	1183	*
whismanoid	0:f7d706d2904d	1184	* @details Destroys SPI object if owner
whismanoid	0:f7d706d2904d	1185	*
whismanoid	0:f7d706d2904d	1186	* On Entry:
whismanoid	0:f7d706d2904d	1187	*
whismanoid	0:f7d706d2904d	1188	* On Exit:
whismanoid	0:f7d706d2904d	1189	*
whismanoid	0:f7d706d2904d	1190	* @return None
whismanoid	0:f7d706d2904d	1191	**************************************************************/
whismanoid	0:f7d706d2904d	1192	~MAX11131();
whismanoid	0:f7d706d2904d	1193
whismanoid	0:f7d706d2904d	1194	// CODE GENERATOR: spi_frequency setter declaration
whismanoid	0:f7d706d2904d	1195	// set SPI SCLK frequency
whismanoid	0:f7d706d2904d	1196	void spi_frequency(int spi_sclk_Hz);
whismanoid	0:f7d706d2904d	1197
whismanoid	0:f7d706d2904d	1198	//----------------------------------------
whismanoid	0:f7d706d2904d	1199	// CODE GENERATOR: omit typedef enum MAX11131_device_t, class members instead of global device object
whismanoid	0:f7d706d2904d	1200	public:
whismanoid	0:f7d706d2904d	1201
whismanoid	0:f7d706d2904d	1202	/// shadow of write-only register ADC_MODE_CONTROL
whismanoid	0:f7d706d2904d	1203	/// mosiData16 0x0000..0x7FFF format: 0 SCAN[3:0] CHSEL[3:0] RESET[1:0] PM[1:0] CHAN_ID SWCNV 0
whismanoid	0:f7d706d2904d	1204	int16_t ADC_MODE_CONTROL;
whismanoid	0:f7d706d2904d	1205
whismanoid	0:f7d706d2904d	1206	/// shadow of write-only register ADC_CONFIGURATION
whismanoid	0:f7d706d2904d	1207	/// mosiData16 0x8000..0x87FF format: 1 0 0 0 0 REFSEL AVGON NAVG[1:0] NSCAN[1:0] SPM[1:0] ECHO 0 0
whismanoid	0:f7d706d2904d	1208	int16_t ADC_CONFIGURATION;
whismanoid	0:f7d706d2904d	1209
whismanoid	0:f7d706d2904d	1210	/// shadow of write-only register UNIPOLAR
whismanoid	0:f7d706d2904d	1211	/// mosiData16 0x8800..0x8FFF format: 1 0 0 0 1 UCH0/1 UCH2/3 UCH4/5 UCH6/7 UCH8/9 UCH10/11 UCH12/13 UCH14/15 PDIFF_COM x x
whismanoid	0:f7d706d2904d	1212	int16_t UNIPOLAR;
whismanoid	0:f7d706d2904d	1213
whismanoid	0:f7d706d2904d	1214	/// shadow of write-only register BIPOLAR
whismanoid	0:f7d706d2904d	1215	/// mosiData16 0x9000..0x97FF format: 1 0 0 1 0 BCH0/1 BCH2/3 BCH4/5 BCH6/7 BCH8/9 BCH10/11 BCH12/13 BCH14/15 x x x
whismanoid	0:f7d706d2904d	1216	int16_t BIPOLAR;
whismanoid	0:f7d706d2904d	1217
whismanoid	0:f7d706d2904d	1218	/// shadow of write-only register RANGE
whismanoid	0:f7d706d2904d	1219	/// mosiData16 0x9800..0x9FFF format: 1 0 0 1 1 RANGE0/1 RANGE2/3 RANGE4/5 RANGE6/7 RANGE8/9 RANGE10/11 RANGE12/13 RANGE14/15 x x x
whismanoid	0:f7d706d2904d	1220	int16_t RANGE;
whismanoid	0:f7d706d2904d	1221
whismanoid	0:f7d706d2904d	1222	/// shadow of write-only register CSCAN0
whismanoid	0:f7d706d2904d	1223	/// mosiData16 0xA000..0xA7FF format: 1 0 1 0 0 CHSCAN15 CHSCAN14 CHSCAN13 CHSCAN12 CHSCAN11 CHSCAN10 CHSCAN9 CHSCAN8 x x x
whismanoid	0:f7d706d2904d	1224	int16_t CSCAN0;
whismanoid	0:f7d706d2904d	1225
whismanoid	0:f7d706d2904d	1226	/// shadow of write-only register CSCAN1
whismanoid	0:f7d706d2904d	1227	/// mosiData16 0xA800..0xAFFF format: 1 0 1 0 1 CHSCAN7 CHSCAN6 CHSCAN5 CHSCAN4 CHSCAN3 CHSCAN2 CHSCAN1 CHSCAN0 x x x
whismanoid	0:f7d706d2904d	1228	int16_t CSCAN1;
whismanoid	0:f7d706d2904d	1229
whismanoid	0:f7d706d2904d	1230	/// shadow of write-only register SAMPLESET
whismanoid	0:f7d706d2904d	1231	/// mosiData16 0xB000..0xB7FF format: 1 0 1 1 0 SEQ_LENGTH[7:0] x x x followed by enabledChannelsPattern.
whismanoid	0:f7d706d2904d	1232	/// NOTE: Send the sampleset pattern, with 4 entries packed into each 16-bit SPI word. Pad unused entries with 0.
whismanoid	0:f7d706d2904d	1233	/// NOTE: Keep CS low during the entire enabledChannelsPattern entry.
whismanoid	0:f7d706d2904d	1234	int16_t SAMPLESET;
whismanoid	0:f7d706d2904d	1235
whismanoid	0:f7d706d2904d	1236	/// unpacked SAMPLESET.SEQ_LENGTH[7:0] determines length of pattern
whismanoid	0:f7d706d2904d	1237	/// NOTE: SAMPLESET.SEQ_LENGTH[7:0] is the number of channel entries in the pattern.
whismanoid	0:f7d706d2904d	1238	/// NOTE: Each channel entry is 4 bits. The first 4 bits are the first channel in the sequence.
whismanoid	0:f7d706d2904d	1239	/// NOTE: Channels can be repeated in any arbitrary order.
whismanoid	0:f7d706d2904d	1240	/// NOTE: The channel entry pattern is sent immediately after writing SAMPLESET.
whismanoid	0:f7d706d2904d	1241	uint8_t enabledChannelsPatternLength_1_256;
whismanoid	0:f7d706d2904d	1242
whismanoid	0:f7d706d2904d	1243	/// unpacked shadow of write-only register SAMPLESET enabledChannelsPattern.
whismanoid	0:f7d706d2904d	1244	/// Each entry is a channel number between 0 and 15.
whismanoid	0:f7d706d2904d	1245	uint8_t enabledChannelsPattern[256];
whismanoid	0:f7d706d2904d	1246
whismanoid	0:f7d706d2904d	1247	/// Diagnostic: what is the meaning of SPI Master Out data.
whismanoid	0:f7d706d2904d	1248	/// 0:Nothing 1:regWrite 2:sampleSetPattern
whismanoid	0:f7d706d2904d	1249	uint8_t SPI_MOSI_Semantic;
whismanoid	0:f7d706d2904d	1250
whismanoid	0:f7d706d2904d	1251	/// number of ScanRead() words needed to retrieve all measurements.
whismanoid	0:f7d706d2904d	1252	uint16_t NumWords;
whismanoid	0:f7d706d2904d	1253
whismanoid	0:f7d706d2904d	1254	/// Is the currently configured mode external or internal clock. 1:External Clock 0:Internal Clock
whismanoid	0:f7d706d2904d	1255	uint8_t isExternalClock;
whismanoid	0:f7d706d2904d	1256
whismanoid	0:f7d706d2904d	1257	/// unpacked ADC_MODE_CONTROL.SCAN[3:0] Scan Mode MAX11131_SCAN_enum_t
whismanoid	0:f7d706d2904d	1258	uint8_t ScanMode;
whismanoid	0:f7d706d2904d	1259
whismanoid	0:f7d706d2904d	1260	/// unpacked ADC_MODE_CONTROL.CHSEL[3:0] Analog Input Channel Select
whismanoid	0:f7d706d2904d	1261	uint8_t channelNumber_0_15;
whismanoid	0:f7d706d2904d	1262
whismanoid	0:f7d706d2904d	1263	/// unpacked ADC_MODE_CONTROL.PM[1:0] Power Management MAX11131_PM_enum_t
whismanoid	0:f7d706d2904d	1264	uint8_t PowerManagement_0_2;
whismanoid	0:f7d706d2904d	1265
whismanoid	0:f7d706d2904d	1266	/// unpacked ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1267	uint8_t chan_id_0_1;
whismanoid	0:f7d706d2904d	1268
whismanoid	0:f7d706d2904d	1269	/// unpacked ADC_CONFIGURATION.AVG and ADC_CONFIGURATION.NAVG[1:0] may be 0, 4, 8, 16, or 32
whismanoid	0:f7d706d2904d	1270	uint8_t average_0_4_8_16_32;
whismanoid	0:f7d706d2904d	1271
whismanoid	0:f7d706d2904d	1272	/// unpacked ADC_CONFIGURATION.NSCAN[1:0] may be 4, 8, 12, or 16
whismanoid	0:f7d706d2904d	1273	uint8_t nscan_4_8_12_16;
whismanoid	0:f7d706d2904d	1274
whismanoid	0:f7d706d2904d	1275	/// unpacked ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1276	uint8_t swcnv_0_1;
whismanoid	0:f7d706d2904d	1277
whismanoid	0:f7d706d2904d	1278	/// unpacked CSCAN0 and CSCAN1
whismanoid	0:f7d706d2904d	1279	int16_t enabledChannelsMask;
whismanoid	0:f7d706d2904d	1280
whismanoid	0:f7d706d2904d	1281	/// Each channel's most recent value in LSBs.
whismanoid	0:f7d706d2904d	1282	/// Updated by ReadAINcode function.
whismanoid	0:f7d706d2904d	1283	/// Use VoltageOfCode function to convert LSBs to physical voltage.
whismanoid	0:f7d706d2904d	1284	uint16_t AINcode[16];
whismanoid	0:f7d706d2904d	1285
whismanoid	0:f7d706d2904d	1286	/// SPI master-in slave-out data.
whismanoid	0:f7d706d2904d	1287	/// Updated by ReadAINcode function.
whismanoid	0:f7d706d2904d	1288	/// SampleSet mode allows up to 256 channel entry selections.
whismanoid	0:f7d706d2904d	1289	int16_t RAW_misoData16[256];
whismanoid	0:f7d706d2904d	1290
whismanoid	0:f7d706d2904d	1291	/// reference voltage, in Volts
whismanoid	0:f7d706d2904d	1292	double VRef;
whismanoid	0:f7d706d2904d	1293
whismanoid	0:f7d706d2904d	1294	// CODE GENERATOR: omit global g_MAX11131_device
whismanoid	0:f7d706d2904d	1295
whismanoid	0:f7d706d2904d	1296	// CODE GENERATOR: extern function declarations
whismanoid	0:f7d706d2904d	1297	// CODE GENERATOR: extern function declaration SPIoutputCS
whismanoid	0:f7d706d2904d	1298	//----------------------------------------
whismanoid	0:f7d706d2904d	1299	// Assert SPI Chip Select
whismanoid	0:f7d706d2904d	1300	// SPI chip-select for MAX11131
whismanoid	0:f7d706d2904d	1301	//
whismanoid	0:f7d706d2904d	1302	void SPIoutputCS(int isLogicHigh);
whismanoid	0:f7d706d2904d	1303
whismanoid	0:f7d706d2904d	1304	// CODE GENERATOR: extern function declaration SPIwrite16bits
whismanoid	0:f7d706d2904d	1305	//----------------------------------------
whismanoid	0:f7d706d2904d	1306	// SPI write 16 bits
whismanoid	0:f7d706d2904d	1307	// SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid	0:f7d706d2904d	1308	// ignoring MAX11131 DOUT
whismanoid	0:f7d706d2904d	1309	//
whismanoid	0:f7d706d2904d	1310	void SPIwrite16bits(int16_t mosiData16);
whismanoid	0:f7d706d2904d	1311
whismanoid	0:f7d706d2904d	1312	// CODE GENERATOR: extern function declaration SPIwrite24bits
whismanoid	0:f7d706d2904d	1313	//----------------------------------------
whismanoid	0:f7d706d2904d	1314	// SPI write 17-24 bits
whismanoid	0:f7d706d2904d	1315	// SPI interface to MAX11131 shift 16 bits mosiData16 into MAX11131 DIN
whismanoid	0:f7d706d2904d	1316	// followed by one additional SCLK byte.
whismanoid	0:f7d706d2904d	1317	// ignoring MAX11131 DOUT
whismanoid	0:f7d706d2904d	1318	//
whismanoid	0:f7d706d2904d	1319	void SPIwrite24bits(int16_t mosiData16_FFFF00, int8_t mosiData8_0000FF);
whismanoid	0:f7d706d2904d	1320
whismanoid	0:f7d706d2904d	1321	// CODE GENERATOR: extern function declaration SPIread16bits
whismanoid	0:f7d706d2904d	1322	//----------------------------------------
whismanoid	0:f7d706d2904d	1323	// SPI read 16 bits while MOSI (MAX11131 DIN) is 0
whismanoid	0:f7d706d2904d	1324	// SPI interface to capture 16 bits miso data from MAX11131 DOUT
whismanoid	0:f7d706d2904d	1325	//
whismanoid	0:f7d706d2904d	1326	int16_t SPIread16bits();
whismanoid	0:f7d706d2904d	1327
whismanoid	0:f7d706d2904d	1328	// CODE GENERATOR: extern function declaration CNVSToutputPulseLow
whismanoid	0:f7d706d2904d	1329	//----------------------------------------
whismanoid	0:f7d706d2904d	1330	// Assert MAX11131 CNVST convert start.
whismanoid	0:f7d706d2904d	1331	// Required when using any of the InternalClock modes with SWCNV 0.
whismanoid	0:f7d706d2904d	1332	// Trigger measurement by driving CNVST/AIN14 pin low for a minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1333	//
whismanoid	0:f7d706d2904d	1334	void CNVSToutputPulseLow();
whismanoid	0:f7d706d2904d	1335
whismanoid	0:f7d706d2904d	1336	// CODE GENERATOR: extern function declaration EOCinputWaitUntilLow
whismanoid	0:f7d706d2904d	1337	//----------------------------------------
whismanoid	0:f7d706d2904d	1338	// Wait for MAX11131 EOC pin low, indicating end of conversion.
whismanoid	0:f7d706d2904d	1339	// Required when using any of the InternalClock modes.
whismanoid	0:f7d706d2904d	1340	//
whismanoid	0:f7d706d2904d	1341	void EOCinputWaitUntilLow();
whismanoid	0:f7d706d2904d	1342
whismanoid	0:f7d706d2904d	1343	// CODE GENERATOR: extern function declaration EOCinputValue
whismanoid	0:f7d706d2904d	1344	//----------------------------------------
whismanoid	0:f7d706d2904d	1345	// Return the status of the MAX11131 EOC pin.
whismanoid	0:f7d706d2904d	1346	//
whismanoid	0:f7d706d2904d	1347	int EOCinputValue();
whismanoid	0:f7d706d2904d	1348
whismanoid	0:f7d706d2904d	1349	// CODE GENERATOR: class member data
whismanoid	0:f7d706d2904d	1350	private:
whismanoid	0:f7d706d2904d	1351	// CODE GENERATOR: class member data for SPI interface
whismanoid	0:f7d706d2904d	1352	// SPI object
whismanoid	0:f7d706d2904d	1353	SPI &m_spi;
whismanoid	0:f7d706d2904d	1354	int m_SPI_SCLK_Hz;
whismanoid	0:f7d706d2904d	1355	int m_SPI_dataMode;
whismanoid	0:f7d706d2904d	1356	int m_SPI_cs_state;
whismanoid	0:f7d706d2904d	1357
whismanoid	0:f7d706d2904d	1358	// Selector pin object
whismanoid	0:f7d706d2904d	1359	DigitalOut &m_cs_pin;
whismanoid	0:f7d706d2904d	1360
whismanoid	0:f7d706d2904d	1361	// CODE GENERATOR: class member data for gpio InputPin pins
whismanoid	0:f7d706d2904d	1362	// InputPin Name = CNVST
whismanoid	0:f7d706d2904d	1363	// InputPin Description = Active-Low Conversion Start Input/Analog Input 14
whismanoid	0:f7d706d2904d	1364	// InputPin Function = Trigger
whismanoid	0:f7d706d2904d	1365	DigitalOut &m_CNVST_pin;
whismanoid	0:f7d706d2904d	1366	//
whismanoid	0:f7d706d2904d	1367	// InputPin Name = REF+
whismanoid	0:f7d706d2904d	1368	// InputPin Description = External Positive Reference Input. Apply a reference voltage at REF+. Bypass to GND with a 0.47uF capacitor.
whismanoid	0:f7d706d2904d	1369	// InputPin Function = Reference
whismanoid	0:f7d706d2904d	1370	// AnalogOut &m_REF__pin;
whismanoid	0:f7d706d2904d	1371	//
whismanoid	0:f7d706d2904d	1372	// InputPin Name = REF-/AIN15
whismanoid	0:f7d706d2904d	1373	// InputPin Description = External Differential Reference Negative Input/Analog Input 15
whismanoid	0:f7d706d2904d	1374	// InputPin Function = Reference
whismanoid	0:f7d706d2904d	1375	// AnalogOut &m_REF__AIN15_pin;
whismanoid	0:f7d706d2904d	1376	//
whismanoid	0:f7d706d2904d	1377	// CODE GENERATOR: class member data for gpio OutputPin pins
whismanoid	0:f7d706d2904d	1378	// OutputPin Name = EOC
whismanoid	0:f7d706d2904d	1379	// OutputPin Description = End of Conversion Output. Data is valid after EOC pulls low (Internal clock mode only).
whismanoid	0:f7d706d2904d	1380	// OutputPin Function = Event
whismanoid	0:f7d706d2904d	1381	DigitalIn &m_EOC_pin;
whismanoid	0:f7d706d2904d	1382	//
whismanoid	0:f7d706d2904d	1383
whismanoid	0:f7d706d2904d	1384	// Identifies which IC variant is being used
whismanoid	0:f7d706d2904d	1385	MAX11131_ic_t m_ic_variant;
whismanoid	0:f7d706d2904d	1386
whismanoid	0:f7d706d2904d	1387	public:
whismanoid	0:f7d706d2904d	1388
whismanoid	0:f7d706d2904d	1389	// CODE GENERATOR: class member function declarations
whismanoid	0:f7d706d2904d	1390	//----------------------------------------
whismanoid	0:f7d706d2904d	1391	/// Initialize device
whismanoid	0:f7d706d2904d	1392	void Init(void);
whismanoid	0:f7d706d2904d	1393
whismanoid	0:f7d706d2904d	1394	//----------------------------------------
whismanoid	0:f7d706d2904d	1395	/// ADC Channels AIN(channelId), AIN(channelId+1) = Both Single-Ended, Unipolar
whismanoid	0:f7d706d2904d	1396	/// Full Scale = VREF
whismanoid	0:f7d706d2904d	1397	/// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1398	/// AIN(channelId) is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1399	/// AIN(channelId+1) is a Single-Ended input using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1400	/// If PDIFF_COM_1, both are Pseudo-Differential with REF- as common.
whismanoid	0:f7d706d2904d	1401	/// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1402	/// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1403	///
whismanoid	0:f7d706d2904d	1404	void Reconfigure_SingleEnded(int channelNumber_0_15);
whismanoid	0:f7d706d2904d	1405
whismanoid	0:f7d706d2904d	1406	//----------------------------------------
whismanoid	0:f7d706d2904d	1407	/// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Unipolar (AIN(channelId) > AIN(channelId+1))
whismanoid	0:f7d706d2904d	1408	/// Full Scale = VREF
whismanoid	0:f7d706d2904d	1409	/// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1410	/// AIN(channelId), AIN(channelId+1) are a Differential pair using Unipolar transfer function.
whismanoid	0:f7d706d2904d	1411	/// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1412	/// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1413	///
whismanoid	0:f7d706d2904d	1414	void Reconfigure_DifferentialUnipolar(int channelNumber_0_15);
whismanoid	0:f7d706d2904d	1415
whismanoid	0:f7d706d2904d	1416	//----------------------------------------
whismanoid	0:f7d706d2904d	1417	/// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid	0:f7d706d2904d	1418	/// Full Scale = VREF
whismanoid	0:f7d706d2904d	1419	/// Voltage per LSB count = VREF/4096
whismanoid	0:f7d706d2904d	1420	/// AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range ±½Vref
whismanoid	0:f7d706d2904d	1421	/// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1422	/// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1423	///
whismanoid	0:f7d706d2904d	1424	void Reconfigure_DifferentialBipolarFSVref(int channelNumber_0_15);
whismanoid	0:f7d706d2904d	1425
whismanoid	0:f7d706d2904d	1426	//----------------------------------------
whismanoid	0:f7d706d2904d	1427	/// ADC Channels AIN(channelId), AIN(channelId+1) = Differential Bipolar
whismanoid	0:f7d706d2904d	1428	/// Full Scale = 2 * VREF
whismanoid	0:f7d706d2904d	1429	/// Voltage per LSB count = VREF/2048
whismanoid	0:f7d706d2904d	1430	/// AIN(channelId), AIN(channelId+1) are a Differential pair using Bipolar transfer function with range ±Vref
whismanoid	0:f7d706d2904d	1431	/// AIN(channelId) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1432	/// AIN(channelId+1) voltage must always be between 0 and VREF.
whismanoid	0:f7d706d2904d	1433	///
whismanoid	0:f7d706d2904d	1434	void Reconfigure_DifferentialBipolarFS2Vref(int channelNumber_0_15);
whismanoid	0:f7d706d2904d	1435
whismanoid	0:f7d706d2904d	1436	//----------------------------------------
whismanoid	0:f7d706d2904d	1437	/// SCAN_0000_NOP
whismanoid	0:f7d706d2904d	1438	///
whismanoid	0:f7d706d2904d	1439	/// Shift 16 bits out of ADC, without changing configuration.
whismanoid	0:f7d706d2904d	1440	/// Note: @return data format depends on CHAN_ID bit:
whismanoid	0:f7d706d2904d	1441	/// "CH[3:0] DATA[11:0]" when CHAN_ID = 1, or
whismanoid	0:f7d706d2904d	1442	/// "0 DATA[11:0] x x x" when CHAN_ID = 0.
whismanoid	0:f7d706d2904d	1443	int16_t ScanRead(void);
whismanoid	0:f7d706d2904d	1444
whismanoid	0:f7d706d2904d	1445	//----------------------------------------
whismanoid	0:f7d706d2904d	1446	/// SCAN_0000_NOP
whismanoid	0:f7d706d2904d	1447	///
whismanoid	0:f7d706d2904d	1448	/// Read raw ADC codes from device into AINcode[] and RAW_misoData16[].
whismanoid	0:f7d706d2904d	1449	/// If internal clock mode with SWCNV=0, measurements will be triggered using CNVST pin.
whismanoid	0:f7d706d2904d	1450	///
whismanoid	0:f7d706d2904d	1451	/// @pre one of the Scan functions was called, setting g_MAX11131_device.NumWords
whismanoid	0:f7d706d2904d	1452	/// @post g_MAX11131_device.RAW_misoData16[index] contains the raw SPI Master-In,Slave-Out data
whismanoid	0:f7d706d2904d	1453	/// @post g_MAX11131_device.AINcode[NUM_CHANNELS] contains the latest readings in LSBs
whismanoid	0:f7d706d2904d	1454	///
whismanoid	0:f7d706d2904d	1455	void ReadAINcode(void);
whismanoid	0:f7d706d2904d	1456
whismanoid	0:f7d706d2904d	1457	//----------------------------------------
whismanoid	0:f7d706d2904d	1458	/// Sign-Extend a right-aligned MAX11131 code into a signed 2's complement value.
whismanoid	0:f7d706d2904d	1459	/// Supports the bipolar transfer functions.
whismanoid	0:f7d706d2904d	1460	/// @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid	0:f7d706d2904d	1461	/// @return sign-extended 2's complement value.
whismanoid	0:f7d706d2904d	1462	///
whismanoid	0:f7d706d2904d	1463	int32_t TwosComplementValue(uint32_t regValue);
whismanoid	0:f7d706d2904d	1464
whismanoid	0:f7d706d2904d	1465	//----------------------------------------
whismanoid	0:f7d706d2904d	1466	/// Return the physical voltage corresponding to MAX11131 code.
whismanoid	0:f7d706d2904d	1467	/// Does not perform any offset or gain correction.
whismanoid	0:f7d706d2904d	1468	/// @pre g_MAX11131_device.VRef = Voltage of REF input, in Volts
whismanoid	0:f7d706d2904d	1469	/// @param[in] value_u12: raw 12-bit MAX11131 code (right justified).
whismanoid	0:f7d706d2904d	1470	/// @param[in] channelId: AIN channel number.
whismanoid	0:f7d706d2904d	1471	/// @return physical voltage corresponding to MAX11131 code.
whismanoid	0:f7d706d2904d	1472	///
whismanoid	0:f7d706d2904d	1473	double VoltageOfCode(int16_t value_u12, int channelId);
whismanoid	0:f7d706d2904d	1474
whismanoid	0:f7d706d2904d	1475	//----------------------------------------
whismanoid	0:f7d706d2904d	1476	/// SCAN_0001_Manual
whismanoid	0:f7d706d2904d	1477	///
whismanoid	0:f7d706d2904d	1478	/// Measure ADC channel channelNumber_0_15 once.
whismanoid	0:f7d706d2904d	1479	/// External clock mode.
whismanoid	0:f7d706d2904d	1480	/// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1481	/// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1482	/// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1483	/// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1484	/// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	1485	/// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1486	/// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1487	///
whismanoid	0:f7d706d2904d	1488	int ScanManual(void);
whismanoid	0:f7d706d2904d	1489
whismanoid	0:f7d706d2904d	1490	//----------------------------------------
whismanoid	0:f7d706d2904d	1491	/// SCAN_0010_Repeat
whismanoid	0:f7d706d2904d	1492	///
whismanoid	0:f7d706d2904d	1493	/// Measure ADC channel channelNumber_0_15 repeatedly with averaging.
whismanoid	0:f7d706d2904d	1494	/// Internal clock mode.
whismanoid	0:f7d706d2904d	1495	/// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1496	/// @param[in] g_MAX11131_device.average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	0:f7d706d2904d	1497	/// average_0_4_8_16_32=0 to disable averaging.
whismanoid	0:f7d706d2904d	1498	/// @param[in] g_MAX11131_device.nscan_4_8_12_16: Number of ScanRead() words to report.
whismanoid	0:f7d706d2904d	1499	/// @param[in] g_MAX11131_device.swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1500	/// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	0:f7d706d2904d	1501	/// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1502	/// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	0:f7d706d2904d	1503	/// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1504	/// CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	1505	/// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1506	/// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1507	/// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1508	/// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1509	///
whismanoid	0:f7d706d2904d	1510	int ScanRepeat(void);
whismanoid	0:f7d706d2904d	1511
whismanoid	0:f7d706d2904d	1512	//----------------------------------------
whismanoid	0:f7d706d2904d	1513	/// SCAN_0011_StandardInternalClock
whismanoid	0:f7d706d2904d	1514	///
whismanoid	0:f7d706d2904d	1515	/// Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid	0:f7d706d2904d	1516	/// Internal clock mode.
whismanoid	0:f7d706d2904d	1517	/// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1518	/// @param[in] g_MAX11131_device.average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	0:f7d706d2904d	1519	/// average_0_4_8_16_32=0 to disable averaging.
whismanoid	0:f7d706d2904d	1520	/// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1521	/// @param[in] g_MAX11131_device.swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1522	/// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	0:f7d706d2904d	1523	/// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1524	/// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	0:f7d706d2904d	1525	/// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1526	/// CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	1527	/// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1528	/// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1529	/// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1530	///
whismanoid	0:f7d706d2904d	1531	int ScanStandardInternalClock(void);
whismanoid	0:f7d706d2904d	1532
whismanoid	0:f7d706d2904d	1533	//----------------------------------------
whismanoid	0:f7d706d2904d	1534	/// SCAN_0100_StandardExternalClock
whismanoid	0:f7d706d2904d	1535	///
whismanoid	0:f7d706d2904d	1536	/// Measure ADC channels in sequence from AIN0 to channelNumber_0_15.
whismanoid	0:f7d706d2904d	1537	/// External clock mode.
whismanoid	0:f7d706d2904d	1538	/// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1539	/// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1540	/// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1541	/// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1542	/// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	1543	/// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1544	/// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1545	///
whismanoid	0:f7d706d2904d	1546	int ScanStandardExternalClock(void);
whismanoid	0:f7d706d2904d	1547
whismanoid	0:f7d706d2904d	1548	//----------------------------------------
whismanoid	0:f7d706d2904d	1549	/// SCAN_0101_UpperInternalClock
whismanoid	0:f7d706d2904d	1550	///
whismanoid	0:f7d706d2904d	1551	/// Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid	0:f7d706d2904d	1552	/// Internal clock mode.
whismanoid	0:f7d706d2904d	1553	/// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1554	/// @param[in] g_MAX11131_device.average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	0:f7d706d2904d	1555	/// average_0_4_8_16_32=0 to disable averaging.
whismanoid	0:f7d706d2904d	1556	/// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1557	/// @param[in] g_MAX11131_device.swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1558	/// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	0:f7d706d2904d	1559	/// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1560	/// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	0:f7d706d2904d	1561	/// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1562	/// CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	1563	/// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1564	/// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1565	/// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1566	///
whismanoid	0:f7d706d2904d	1567	int ScanUpperInternalClock(void);
whismanoid	0:f7d706d2904d	1568
whismanoid	0:f7d706d2904d	1569	//----------------------------------------
whismanoid	0:f7d706d2904d	1570	/// SCAN_0110_UpperExternalClock
whismanoid	0:f7d706d2904d	1571	///
whismanoid	0:f7d706d2904d	1572	/// Measure ADC channels in sequence from channelNumber_0_15 to AIN15.
whismanoid	0:f7d706d2904d	1573	/// External clock mode.
whismanoid	0:f7d706d2904d	1574	/// @param[in] g_MAX11131_device.channelNumber_0_15: AIN Channel Number
whismanoid	0:f7d706d2904d	1575	/// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1576	/// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1577	/// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1578	/// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	1579	/// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1580	/// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1581	///
whismanoid	0:f7d706d2904d	1582	int ScanUpperExternalClock(void);
whismanoid	0:f7d706d2904d	1583
whismanoid	0:f7d706d2904d	1584	//----------------------------------------
whismanoid	0:f7d706d2904d	1585	/// SCAN_0111_CustomInternalClock
whismanoid	0:f7d706d2904d	1586	///
whismanoid	0:f7d706d2904d	1587	/// Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid	0:f7d706d2904d	1588	/// using only the channels enabled by enabledChannelsMask.
whismanoid	0:f7d706d2904d	1589	/// Bit 0x0001 enables AIN0.
whismanoid	0:f7d706d2904d	1590	/// Bit 0x0002 enables AIN1.
whismanoid	0:f7d706d2904d	1591	/// Bit 0x0004 enables AIN2.
whismanoid	0:f7d706d2904d	1592	/// Bit 0x0008 enables AIN3.
whismanoid	0:f7d706d2904d	1593	/// Bit 0x0010 enables AIN4.
whismanoid	0:f7d706d2904d	1594	/// Bit 0x0020 enables AIN5.
whismanoid	0:f7d706d2904d	1595	/// Bit 0x0040 enables AIN6.
whismanoid	0:f7d706d2904d	1596	/// Bit 0x0080 enables AIN7.
whismanoid	0:f7d706d2904d	1597	/// Bit 0x0100 enables AIN8.
whismanoid	0:f7d706d2904d	1598	/// Bit 0x0200 enables AIN9.
whismanoid	0:f7d706d2904d	1599	/// Bit 0x0400 enables AIN10.
whismanoid	0:f7d706d2904d	1600	/// Bit 0x0800 enables AIN11.
whismanoid	0:f7d706d2904d	1601	/// Bit 0x1000 enables AIN12.
whismanoid	0:f7d706d2904d	1602	/// Bit 0x2000 enables AIN13.
whismanoid	0:f7d706d2904d	1603	/// Bit 0x4000 enables AIN14.
whismanoid	0:f7d706d2904d	1604	/// Bit 0x8000 enables AIN15.
whismanoid	0:f7d706d2904d	1605	/// Internal clock mode.
whismanoid	0:f7d706d2904d	1606	/// @param[in] g_MAX11131_device.enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid	0:f7d706d2904d	1607	/// @param[in] g_MAX11131_device.average_0_4_8_16_32: Number of samples averaged per ScanRead() word.
whismanoid	0:f7d706d2904d	1608	/// average_0_4_8_16_32=0 to disable averaging.
whismanoid	0:f7d706d2904d	1609	/// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1610	/// @param[in] g_MAX11131_device.swcnv_0_1: ADC_MODE_CONTROL.SWCNV
whismanoid	0:f7d706d2904d	1611	/// SWCNV=0: trigger measurement by driving CNVST pin low.
whismanoid	0:f7d706d2904d	1612	/// Minimum active-low pulse duration of 5ns. (AIN14 is not available)
whismanoid	0:f7d706d2904d	1613	/// SWCNV=1: trigger measurement on SPI CS rising edge.
whismanoid	0:f7d706d2904d	1614	/// CS must be held low for minimum of 17 SCLK cycles.
whismanoid	0:f7d706d2904d	1615	/// CNVST pin is not used. (AIN14 is available)
whismanoid	0:f7d706d2904d	1616	/// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1617	/// For internal clock modes, the data format always includes the channel address.
whismanoid	0:f7d706d2904d	1618	/// misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1619	///
whismanoid	0:f7d706d2904d	1620	int ScanCustomInternalClock(void);
whismanoid	0:f7d706d2904d	1621
whismanoid	0:f7d706d2904d	1622	//----------------------------------------
whismanoid	0:f7d706d2904d	1623	/// SCAN_1000_CustomExternalClock
whismanoid	0:f7d706d2904d	1624	///
whismanoid	0:f7d706d2904d	1625	/// Measure selected ADC channels in sequence from AIN0 to AIN15,
whismanoid	0:f7d706d2904d	1626	/// using only the channels enabled by enabledChannelsMask.
whismanoid	0:f7d706d2904d	1627	/// Bit 0x0001 enables AIN0.
whismanoid	0:f7d706d2904d	1628	/// Bit 0x0002 enables AIN1.
whismanoid	0:f7d706d2904d	1629	/// Bit 0x0004 enables AIN2.
whismanoid	0:f7d706d2904d	1630	/// Bit 0x0008 enables AIN3.
whismanoid	0:f7d706d2904d	1631	/// Bit 0x0010 enables AIN4.
whismanoid	0:f7d706d2904d	1632	/// Bit 0x0020 enables AIN5.
whismanoid	0:f7d706d2904d	1633	/// Bit 0x0040 enables AIN6.
whismanoid	0:f7d706d2904d	1634	/// Bit 0x0080 enables AIN7.
whismanoid	0:f7d706d2904d	1635	/// Bit 0x0100 enables AIN8.
whismanoid	0:f7d706d2904d	1636	/// Bit 0x0200 enables AIN9.
whismanoid	0:f7d706d2904d	1637	/// Bit 0x0400 enables AIN10.
whismanoid	0:f7d706d2904d	1638	/// Bit 0x0800 enables AIN11.
whismanoid	0:f7d706d2904d	1639	/// Bit 0x1000 enables AIN12.
whismanoid	0:f7d706d2904d	1640	/// Bit 0x2000 enables AIN13.
whismanoid	0:f7d706d2904d	1641	/// Bit 0x4000 enables AIN14.
whismanoid	0:f7d706d2904d	1642	/// Bit 0x8000 enables AIN15.
whismanoid	0:f7d706d2904d	1643	/// External clock mode.
whismanoid	0:f7d706d2904d	1644	/// @param[in] g_MAX11131_device.enabledChannelsMask: Bitmap of AIN Channels to scan.
whismanoid	0:f7d706d2904d	1645	/// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1646	/// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1647	/// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1648	/// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	1649	/// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1650	/// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1651	///
whismanoid	0:f7d706d2904d	1652	int ScanCustomExternalClock(void);
whismanoid	0:f7d706d2904d	1653
whismanoid	0:f7d706d2904d	1654	//----------------------------------------
whismanoid	0:f7d706d2904d	1655	/// SCAN_1001_SampleSetExternalClock
whismanoid	0:f7d706d2904d	1656	///
whismanoid	0:f7d706d2904d	1657	/// Measure ADC channels in an arbitrary pattern.
whismanoid	0:f7d706d2904d	1658	/// Channels can be visited in any order, with repetition allowed.
whismanoid	0:f7d706d2904d	1659	/// External clock mode.
whismanoid	0:f7d706d2904d	1660	/// @pre g_MAX11131_device.enabledChannelsPatternLength_1_256: number of channel selections
whismanoid	0:f7d706d2904d	1661	/// @pre g_MAX11131_device.enabledChannelsPattern: array containing channel selection pattern
whismanoid	0:f7d706d2904d	1662	/// In the array, one channel select per byte.
whismanoid	0:f7d706d2904d	1663	/// In the SPI interface, immediately after SAMPLESET register is written,
whismanoid	0:f7d706d2904d	1664	/// each byte encodes two channelNumber selections.
whismanoid	0:f7d706d2904d	1665	/// The high 4 bits encode the first channelNumber.
whismanoid	0:f7d706d2904d	1666	/// (((enabledChannelsPattern[0]) & 0x0F) << 4) \| ((enabledChannelsPattern[1]) & 0x0F)
whismanoid	0:f7d706d2904d	1667	/// If it is an odd number of channels, additional nybbles will be ignored.
whismanoid	0:f7d706d2904d	1668	/// CS will be asserted low during the entire SAMPLESET pattern selection.
whismanoid	0:f7d706d2904d	1669	/// @param[in] g_MAX11131_device.PowerManagement_0_2: 0=Normal, 1=AutoShutdown, 2=AutoStandby
whismanoid	0:f7d706d2904d	1670	/// @param[in] g_MAX11131_device.chan_id_0_1: ADC_MODE_CONTROL.CHAN_ID
whismanoid	0:f7d706d2904d	1671	/// @return number of ScanRead() words needed to retrieve the data.
whismanoid	0:f7d706d2904d	1672	/// For external clock modes, the data format depends on CHAN_ID.
whismanoid	0:f7d706d2904d	1673	/// when CHAN_ID = 0: misoData16 = 0 DATA[11:0] x x x
whismanoid	0:f7d706d2904d	1674	/// when CHAN_ID = 1: misoData16 = CH[3:0] DATA[11:0]
whismanoid	0:f7d706d2904d	1675	///
whismanoid	0:f7d706d2904d	1676	int ScanSampleSetExternalClock(void);
whismanoid	0:f7d706d2904d	1677
whismanoid	0:f7d706d2904d	1678	//----------------------------------------
whismanoid	0:f7d706d2904d	1679	/// Example configure and perform some measurements in ScanManual mode.
whismanoid	0:f7d706d2904d	1680	/// @param[out] pd_mean = address for double mean (avearge)
whismanoid	0:f7d706d2904d	1681	/// @param[out] pd_variance = address for double variance (variance)
whismanoid	0:f7d706d2904d	1682	/// @param[out] pd_stddev = address for double stddev (standard deviation)
whismanoid	0:f7d706d2904d	1683	/// @param[out] pd_Sx = address for double Sx (sum of all X)
whismanoid	0:f7d706d2904d	1684	/// @param[out] pd_Sxx = address for double Sxx (sum of squares of each X)
whismanoid	0:f7d706d2904d	1685	void Example_ScanManual(int channelNumber_0_15, int nWords,
whismanoid	0:f7d706d2904d	1686	double* pd_mean, double* pd_variance, double* pd_stddev,
whismanoid	0:f7d706d2904d	1687	double* pd_Sx, double* pd_Sxx);
whismanoid	0:f7d706d2904d	1688
whismanoid	0:f7d706d2904d	1689	}; // end of class MAX11131
whismanoid	0:f7d706d2904d	1690
whismanoid	0:f7d706d2904d	1691	#endif // __MAX11131_H__
whismanoid	0:f7d706d2904d	1692
whismanoid	0:f7d706d2904d	1693	// End of file

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Type:	Library
Created:	05 Jun 2019
Imports:	7
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Commits:	12
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MAX11131BOB

MAX11131.h@1:77f1ee332e4a, 2019-06-17 (annotated)

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