main.cpp

00001 /*******************************************************************************
00002  * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
00003  *
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00005  * copy of this software and associated documentation files (the "Software"),
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00010  *
00011  * The above copyright notice and this permission notice shall be included
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00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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00022  * Except as contained in this notice, the name of Maxim Integrated
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00024  * Products, Inc. Branding Policy.
00025  *
00026  * The mere transfer of this software does not imply any licenses
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00033  
00034 
00035 
00036 #include "mbed.h"
00037 #include "max32630fthr.h"
00038 #include "MAX30003.h"
00039 
00040 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
00041 
00042 void ecg_config(MAX30003 &ecgAFE);
00043 
00044 /* ECG FIFO nearly full callback */
00045 volatile bool ecgFIFOIntFlag = 0; 
00046 void ecgFIFO_callback()  {
00047     
00048     ecgFIFOIntFlag = 1;
00049 
00050 }  
00051 
00052 int main()
00053 {   
00054 
00055     // Constants
00056     const int EINT_STATUS_MASK =  1 << 23;
00057     const int FIFO_OVF_MASK =  0x7;
00058     const int FIFO_VALID_SAMPLE_MASK =  0x0;
00059     const int FIFO_FAST_SAMPLE_MASK =  0x1;
00060     const int ETAG_BITS_MASK = 0x7;
00061     
00062     // Ports and serial connections
00063     Serial pc(USBTX, USBRX);            // Use USB debug probe for serial link
00064     pc.baud(115200);                    // Baud rate = 115200
00065     
00066     DigitalOut rLed(LED1, LED_OFF);      // Debug LEDs
00067     
00068     InterruptIn ecgFIFO_int(P5_4);          // Config P5_4 as int. in for the
00069     ecgFIFO_int.fall(&ecgFIFO_callback);    // ecg FIFO almost full interrupt
00070     
00071     SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK);     // SPI bus, P5_1 = MOSI, 
00072                                                     // P5_2 = MISO, P5_0 = SCK
00073     
00074     MAX30003 ecgAFE(spiBus, P5_3);          // New MAX30003 on spiBus, CS = P5_3 
00075     ecg_config(ecgAFE);                    // Config ECG 
00076      
00077     
00078     ecgAFE.writeRegister( MAX30003::SYNCH , 0);
00079     
00080     uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status;
00081     int16_t ecgSample[32];
00082     
00083     while(1) {
00084         
00085         // Read back ECG samples from the FIFO 
00086         if( ecgFIFOIntFlag ) {
00087             
00088             ecgFIFOIntFlag = 0; 
00089             status = ecgAFE.readRegister( MAX30003::STATUS );      // Read the STATUS register
00090              
00091             // Check if EINT interrupt asserted
00092             if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {     
00093             
00094                 readECGSamples = 0;                        // Reset sample counter
00095                 
00096                 do {
00097                     ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO );       // Read FIFO
00098                     ecgSample[readECGSamples] = ecgFIFO >> 8;                  // Isolate voltage data
00099                     ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK;  // Isolate ETAG
00100                     readECGSamples++;                                          // Increment sample counter
00101                 
00102                 // Check that sample is not last sample in FIFO                                              
00103                 } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK || 
00104                           ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK ); 
00105                 
00106                 // Check if FIFO has overflowed
00107                 if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){                  
00108                     ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
00109                     rLed = 1;//notifies the user that an over flow occured
00110                 }
00111                 
00112                 // Print results 
00113                 for( idx = 0; idx < readECGSamples; idx++ ) {
00114                     pc.printf("%6d\r\n", ecgSample[idx]);           
00115                 } 
00116                                
00117             }
00118         }
00119     }
00120 }
00121 
00122 
00123 
00124 
00125 void ecg_config(MAX30003& ecgAFE) { 
00126 
00127     // Reset ECG to clear registers
00128     ecgAFE.writeRegister( MAX30003::SW_RST , 0);
00129     
00130     // General config register setting
00131     MAX30003::GeneralConfiguration_u CNFG_GEN_r;
00132     CNFG_GEN_r.bits.en_ecg = 1;     // Enable ECG channel
00133     CNFG_GEN_r.bits.rbiasn = 1;     // Enable resistive bias on negative input
00134     CNFG_GEN_r.bits.rbiasp = 1;     // Enable resistive bias on positive input
00135     CNFG_GEN_r.bits.en_rbias = 1;   // Enable resistive bias
00136     CNFG_GEN_r.bits.imag = 2;       // Current magnitude = 10nA
00137     CNFG_GEN_r.bits.en_dcloff = 1;  // Enable DC lead-off detection   
00138     ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
00139         
00140     
00141     // ECG Config register setting
00142     MAX30003::ECGConfiguration_u CNFG_ECG_r;
00143     CNFG_ECG_r.bits.dlpf = 1;       // Digital LPF cutoff = 40Hz
00144     CNFG_ECG_r.bits.dhpf = 1;       // Digital HPF cutoff = 0.5Hz
00145     CNFG_ECG_r.bits.gain = 3;       // ECG gain = 160V/V
00146     CNFG_ECG_r.bits.rate = 2;       // Sample rate = 128 sps
00147     ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
00148       
00149     
00150     //R-to-R configuration
00151     MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
00152     CNFG_RTOR_r.bits.en_rtor = 1;           // Enable R-to-R detection
00153     ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
00154        
00155         
00156     //Manage interrupts register setting
00157     MAX30003::ManageInterrupts_u MNG_INT_r;
00158     MNG_INT_r.bits.efit = 0b00011;          // Assert EINT w/ 4 unread samples
00159     MNG_INT_r.bits.clr_rrint = 0b01;        // Clear R-to-R on RTOR reg. read back
00160     ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
00161     
00162     
00163     //Enable interrupts register setting
00164     MAX30003::EnableInterrupts_u EN_INT_r;
00165     EN_INT_r.all = 0;
00166     EN_INT_r.bits.en_eint = 1;              // Enable EINT interrupt
00167     EN_INT_r.bits.en_rrint = 0;             // Disable R-to-R interrupt
00168     EN_INT_r.bits.intb_type = 3;            // Open-drain NMOS with internal pullup
00169     ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
00170        
00171        
00172     //Dyanmic modes config
00173     MAX30003::ManageDynamicModes_u MNG_DYN_r;
00174     MNG_DYN_r.bits.fast = 0;                // Fast recovery mode disabled
00175     ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
00176     
00177     // MUX Config
00178     MAX30003::MuxConfiguration_u CNFG_MUX_r;
00179     CNFG_MUX_r.bits.openn = 0;          // Connect ECGN to AFE channel
00180     CNFG_MUX_r.bits.openp = 0;          // Connect ECGP to AFE channel
00181     ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
00182        
00183     return;
00184 }  
00185