Maintool / mbed-src-v4

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Fork of mbed-src by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_irq_api.c@427:8eeb5157dee4, 2014-12-04 (annotated)

Committer:
mbed_official
Date:
Thu Dec 04 07:30:08 2014 +0000
Revision:
427:8eeb5157dee4
Parent:
409:a95c696104d3
Child:
430:d406b7919023
Synchronized with git revision e815194b578628edb5746650abfdde926be5e3fe



Full URL: https://github.com/mbedmicro/mbed/commit/e815194b578628edb5746650abfdde926be5e3fe/



Targets: RZ_A1H - Fix bugs that I2C freq become fixed 100kHz and a static value will be indefiniteness.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 409:a95c696104d3 1 /* mbed Microcontroller Library
mbed_official 409:a95c696104d3 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 409:a95c696104d3 3 *
mbed_official 409:a95c696104d3 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 409:a95c696104d3 5 * you may not use this file except in compliance with the License.
mbed_official 409:a95c696104d3 6 * You may obtain a copy of the License at
mbed_official 409:a95c696104d3 7 *
mbed_official 409:a95c696104d3 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 409:a95c696104d3 9 *
mbed_official 409:a95c696104d3 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 409:a95c696104d3 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 409:a95c696104d3 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 409:a95c696104d3 13 * See the License for the specific language governing permissions and
mbed_official 409:a95c696104d3 14 * limitations under the License.
mbed_official 409:a95c696104d3 15 */
mbed_official 409:a95c696104d3 16 #include <stddef.h>
mbed_official 409:a95c696104d3 17
mbed_official 409:a95c696104d3 18 #include "gpio_irq_api.h"
mbed_official 409:a95c696104d3 19 #include "intc_iodefine.h"
mbed_official 409:a95c696104d3 20 #include "pinmap.h"
mbed_official 409:a95c696104d3 21 #include "cmsis.h"
mbed_official 409:a95c696104d3 22
mbed_official 409:a95c696104d3 23 #define CHANNEL_NUM 8
mbed_official 409:a95c696104d3 24
mbed_official 409:a95c696104d3 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
mbed_official 409:a95c696104d3 26 static gpio_irq_handler irq_handler;
mbed_official 409:a95c696104d3 27 static const int nIRQn_h = 32;
mbed_official 409:a95c696104d3 28 extern PinName gpio_multi_guard;
mbed_official 409:a95c696104d3 29
mbed_official 409:a95c696104d3 30 enum {
mbed_official 409:a95c696104d3 31 IRQ0,IRQ1,
mbed_official 409:a95c696104d3 32 IRQ2,IRQ3,
mbed_official 409:a95c696104d3 33 IRQ4,IRQ5,
mbed_official 409:a95c696104d3 34 IRQ6,IRQ7,
mbed_official 409:a95c696104d3 35
mbed_official 409:a95c696104d3 36 } IRQNo;
mbed_official 409:a95c696104d3 37
mbed_official 409:a95c696104d3 38 static const PinMap PinMap_IRQ[] = {
mbed_official 409:a95c696104d3 39 {P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4},
mbed_official 409:a95c696104d3 40 {P1_3, IRQ3, 4}, {P1_5, IRQ5, 4}, {P1_7, IRQ7, 4},
mbed_official 409:a95c696104d3 41 {P1_8, IRQ2, 3}, {P1_9, IRQ3, 3}, {P1_10, IRQ4, 3},
mbed_official 409:a95c696104d3 42 {P1_11, IRQ5, 3}, // 9
mbed_official 409:a95c696104d3 43 {P2_0, IRQ5, 6}, {P2_13, IRQ7, 8}, {P2_14, IRQ0, 8},
mbed_official 409:a95c696104d3 44 {P2_15, IRQ1, 8}, // 13
mbed_official 409:a95c696104d3 45 {P3_0, IRQ2, 3}, {P3_3, IRQ4, 3}, // 15
mbed_official 409:a95c696104d3 46 {P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8},
mbed_official 409:a95c696104d3 47 {P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
mbed_official 409:a95c696104d3 48 {P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 23
mbed_official 409:a95c696104d3 49 {P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 26
mbed_official 409:a95c696104d3 50 {P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4},
mbed_official 409:a95c696104d3 51 {P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8},
mbed_official 409:a95c696104d3 52 {P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
mbed_official 409:a95c696104d3 53 {P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
mbed_official 409:a95c696104d3 54 {P6_15, IRQ7, 8}, // 39
mbed_official 409:a95c696104d3 55 {P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8},
mbed_official 409:a95c696104d3 56 {P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
mbed_official 409:a95c696104d3 57 {P7_14, IRQ6, 8}, // 46
mbed_official 409:a95c696104d3 58 {P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4},
mbed_official 409:a95c696104d3 59 {P9_1, IRQ0, 4}, // 50
mbed_official 409:a95c696104d3 60 {P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 52
mbed_official 409:a95c696104d3 61
mbed_official 409:a95c696104d3 62 {NC, NC, 0}
mbed_official 409:a95c696104d3 63 };
mbed_official 409:a95c696104d3 64
mbed_official 409:a95c696104d3 65 static gpio_irq_event irq_event;
mbed_official 409:a95c696104d3 66
mbed_official 409:a95c696104d3 67 static void handle_interrupt_in(void) {
mbed_official 409:a95c696104d3 68 int i;
mbed_official 409:a95c696104d3 69 uint16_t irqs;
mbed_official 409:a95c696104d3 70
mbed_official 409:a95c696104d3 71 irqs = INTCIRQRR;
mbed_official 409:a95c696104d3 72 for(i = 0; i< 8; i++) {
mbed_official 409:a95c696104d3 73 if (channel_ids[i] && (irqs & (1 << i))) {
mbed_official 409:a95c696104d3 74 irq_handler(channel_ids[i], irq_event);
mbed_official 409:a95c696104d3 75 INTCIRQRR &= ~(1 << i);
mbed_official 427:8eeb5157dee4 76 GIC_EndInterrupt((IRQn_Type)(nIRQn_h + i));
mbed_official 409:a95c696104d3 77 }
mbed_official 409:a95c696104d3 78 }
mbed_official 409:a95c696104d3 79 }
mbed_official 409:a95c696104d3 80
mbed_official 409:a95c696104d3 81 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
mbed_official 409:a95c696104d3 82 int shift;
mbed_official 409:a95c696104d3 83 if (pin == NC) return -1;
mbed_official 409:a95c696104d3 84
mbed_official 409:a95c696104d3 85 obj->ch = pinmap_peripheral(pin, PinMap_IRQ);
mbed_official 409:a95c696104d3 86 obj->pin = (int)pin ;
mbed_official 409:a95c696104d3 87 obj->port = (int)id ;
mbed_official 409:a95c696104d3 88
mbed_official 409:a95c696104d3 89 shift = obj->ch*2;
mbed_official 409:a95c696104d3 90 channel_ids[obj->ch] = id;
mbed_official 409:a95c696104d3 91 irq_handler = handler;
mbed_official 409:a95c696104d3 92
mbed_official 409:a95c696104d3 93 pinmap_pinout(pin, PinMap_IRQ);
mbed_official 409:a95c696104d3 94 gpio_multi_guard = pin; /* Set multi guard */
mbed_official 409:a95c696104d3 95
mbed_official 409:a95c696104d3 96 // INTC settings
mbed_official 409:a95c696104d3 97 InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))handle_interrupt_in);
mbed_official 409:a95c696104d3 98 INTCICR1 &= ~(0x3 << shift);
mbed_official 409:a95c696104d3 99 INTCICR1 |= (0x3 << shift);
mbed_official 409:a95c696104d3 100 irq_event = IRQ_RISE;
mbed_official 409:a95c696104d3 101 GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
mbed_official 409:a95c696104d3 102 GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
mbed_official 409:a95c696104d3 103 __enable_irq();
mbed_official 409:a95c696104d3 104
mbed_official 409:a95c696104d3 105 return 0;
mbed_official 409:a95c696104d3 106 }
mbed_official 409:a95c696104d3 107
mbed_official 409:a95c696104d3 108 void gpio_irq_free(gpio_irq_t *obj) {
mbed_official 409:a95c696104d3 109 channel_ids[obj->ch] = 0;
mbed_official 409:a95c696104d3 110 }
mbed_official 409:a95c696104d3 111
mbed_official 409:a95c696104d3 112 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
mbed_official 409:a95c696104d3 113 int shift = obj->ch*2;
mbed_official 409:a95c696104d3 114 uint16_t val = event == IRQ_RISE ? 2 :
mbed_official 409:a95c696104d3 115 event == IRQ_FALL ? 1 : 0;
mbed_official 409:a95c696104d3 116 uint16_t work_icr_val;
mbed_official 409:a95c696104d3 117 uint16_t work_irqrr_val;
mbed_official 409:a95c696104d3 118
mbed_official 409:a95c696104d3 119 /* check edge interrupt setting */
mbed_official 409:a95c696104d3 120 work_icr_val = INTCICR1;
mbed_official 409:a95c696104d3 121 if (enable == 1) {
mbed_official 409:a95c696104d3 122 /* Set interrupt serect */
mbed_official 409:a95c696104d3 123 work_icr_val |= (val << shift);
mbed_official 409:a95c696104d3 124 } else {
mbed_official 409:a95c696104d3 125 /* Clear interrupt serect */
mbed_official 409:a95c696104d3 126 work_icr_val &= ~(val << shift);
mbed_official 409:a95c696104d3 127 }
mbed_official 409:a95c696104d3 128
mbed_official 409:a95c696104d3 129 if ((work_icr_val & (3 << shift)) == 0) {
mbed_official 409:a95c696104d3 130 /* No edge interrupt setting */
mbed_official 409:a95c696104d3 131 GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
mbed_official 409:a95c696104d3 132 /* Clear Interrupt flags */
mbed_official 409:a95c696104d3 133 work_irqrr_val = INTCIRQRR;
mbed_official 409:a95c696104d3 134 INTCIRQRR = (work_irqrr_val & ~(1 << obj->ch));
mbed_official 409:a95c696104d3 135 } else {
mbed_official 409:a95c696104d3 136 /* Edge interrupt setting */
mbed_official 409:a95c696104d3 137 if ((work_icr_val & (3 << shift)) == 2) {
mbed_official 409:a95c696104d3 138 /* Setting of rising edge */
mbed_official 409:a95c696104d3 139 irq_event = IRQ_RISE;
mbed_official 409:a95c696104d3 140 } else {
mbed_official 409:a95c696104d3 141 /* Setting of falling edge of both edge */
mbed_official 409:a95c696104d3 142 irq_event = IRQ_FALL;
mbed_official 409:a95c696104d3 143 }
mbed_official 409:a95c696104d3 144 GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
mbed_official 409:a95c696104d3 145 }
mbed_official 409:a95c696104d3 146 INTCICR1 = work_icr_val;
mbed_official 409:a95c696104d3 147 }
mbed_official 409:a95c696104d3 148
mbed_official 409:a95c696104d3 149 void gpio_irq_enable(gpio_irq_t *obj) {
mbed_official 409:a95c696104d3 150 GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
mbed_official 409:a95c696104d3 151 }
mbed_official 409:a95c696104d3 152
mbed_official 409:a95c696104d3 153 void gpio_irq_disable(gpio_irq_t *obj) {
mbed_official 409:a95c696104d3 154 GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
mbed_official 409:a95c696104d3 155 }
mbed_official 409:a95c696104d3 156