MSS / MAX44008

MAX44008 RGB Color, Infrared, and Temperature Sensor

Dependents:   test_MAX44008 testSensor

MAX44008.cpp@0:7d913e68a6d7, 2015-12-22 (annotated)

Committer:
Rhyme
Date:
Tue Dec 22 05:44:07 2015 +0000
Revision:
0:7d913e68a6d7
Child:
1:45b23a5fff8e
First commit after creating files;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:7d913e68a6d7 1 /**
Rhyme 0:7d913e68a6d7 2 * MAX44008 RGB Color, Infrared,
Rhyme 0:7d913e68a6d7 3 * and Temperature Sensor
Rhyme 0:7d913e68a6d7 4 * I2C 7bit address: 0x40 (A0 = 1) 0x41 (A0 = 0)
Rhyme 0:7d913e68a6d7 5 */
Rhyme 0:7d913e68a6d7 6 #include "mbed.h"
Rhyme 0:7d913e68a6d7 7 #include "MAX44008.h"
Rhyme 0:7d913e68a6d7 8
Rhyme 0:7d913e68a6d7 9 /* STATUS */
Rhyme 0:7d913e68a6d7 10 #define REG_INT_STATUS 0x00
Rhyme 0:7d913e68a6d7 11
Rhyme 0:7d913e68a6d7 12 /* CONFIGURATION */
Rhyme 0:7d913e68a6d7 13 #define REG_MAIN_CONFIG 0x01
Rhyme 0:7d913e68a6d7 14 #define REG_AMB_CONFIG 0x02
Rhyme 0:7d913e68a6d7 15
Rhyme 0:7d913e68a6d7 16 /* AMBIENT READING */
Rhyme 0:7d913e68a6d7 17 #define REG_AMB_CLR_MSB 0x04
Rhyme 0:7d913e68a6d7 18 #define REG_AMB_CLR_LSB 0x05
Rhyme 0:7d913e68a6d7 19 #define REG_AMB_RED_MSB 0x06
Rhyme 0:7d913e68a6d7 20 #define REG_AMB_RED_LSB 0x07
Rhyme 0:7d913e68a6d7 21 #define REG_AMB_GRN_MSB 0x08
Rhyme 0:7d913e68a6d7 22 #define REG_AMB_GRN_LSB 0x09
Rhyme 0:7d913e68a6d7 23 #define REG_AMB_BLU_MSB 0x0A
Rhyme 0:7d913e68a6d7 24 #define REG_AMB_BLU_LSB 0x0B
Rhyme 0:7d913e68a6d7 25 #define REG_AMB_IR_MSB 0x0C
Rhyme 0:7d913e68a6d7 26 #define REG_AMB_IR_LSB 0x0D
Rhyme 0:7d913e68a6d7 27 #define REG_AMB_IRCMP_MSB 0x0E
Rhyme 0:7d913e68a6d7 28 #define REG_AMB_IRCMP_LSB 0x0F
Rhyme 0:7d913e68a6d7 29 #define REG_TMP_MSB 0x12
Rhyme 0:7d913e68a6d7 30 #define REG_TMP_LSB 0x13
Rhyme 0:7d913e68a6d7 31
Rhyme 0:7d913e68a6d7 32 /* Interrupt Thresholds */
Rhyme 0:7d913e68a6d7 33 #define REG_AMB_UPTHR_MSB 0x14
Rhyme 0:7d913e68a6d7 34 #define REG_AMB_UPTHR_LSB 0x15
Rhyme 0:7d913e68a6d7 35 #define REG_AMB_LOTHR_MSB 0x16
Rhyme 0:7d913e68a6d7 36 #define REG_AMB_LOTHR_LSB 0x17
Rhyme 0:7d913e68a6d7 37 #define REG_AMB_PST 0x18
Rhyme 0:7d913e68a6d7 38
Rhyme 0:7d913e68a6d7 39 /* Ambient ADC Gains */
Rhyme 0:7d913e68a6d7 40 #define REG_TRIM_GAIN_CLR 0x1D
Rhyme 0:7d913e68a6d7 41 #define REG_TRIM_GAIN_RED 0x1E
Rhyme 0:7d913e68a6d7 42 #define REG_TRIM_GAIN_GRN 0x1F
Rhyme 0:7d913e68a6d7 43 #define REG_TRIM_GAIN_BLU 0x20
Rhyme 0:7d913e68a6d7 44 #define REG_TRIM_GAIN_IR 0x21
Rhyme 0:7d913e68a6d7 45
Rhyme 0:7d913e68a6d7 46 /* Operation Mode */
Rhyme 0:7d913e68a6d7 47 #define MODE_CLEAR 0x00
Rhyme 0:7d913e68a6d7 48 #define MODE_CLEAR_IR 0x01
Rhyme 0:7d913e68a6d7 49 #define MODE_CLEAR_RGB_IR 0x02
Rhyme 0:7d913e68a6d7 50
Rhyme 0:7d913e68a6d7 51 /* Ambient Interrupt Select */
Rhyme 0:7d913e68a6d7 52 #define AMB_INT_CLEAR 0x00
Rhyme 0:7d913e68a6d7 53 #define AMB_INT_GREEN 0x01
Rhyme 0:7d913e68a6d7 54 #define AMB_INT_IR 0x02
Rhyme 0:7d913e68a6d7 55 #define AMB_INT_TEMP 0x03
Rhyme 0:7d913e68a6d7 56
Rhyme 0:7d913e68a6d7 57 MAX44008::MAX44008(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr<<1) {
Rhyme 0:7d913e68a6d7 58 // activate the peripheral
Rhyme 0:7d913e68a6d7 59 }
Rhyme 0:7d913e68a6d7 60
Rhyme 0:7d913e68a6d7 61 MAX44008::~MAX44008() { }
Rhyme 0:7d913e68a6d7 62
Rhyme 0:7d913e68a6d7 63 void MAX44008::readRegs(int addr, uint8_t *data, int len)
Rhyme 0:7d913e68a6d7 64 {
Rhyme 0:7d913e68a6d7 65 char t[1] = {addr} ;
Rhyme 0:7d913e68a6d7 66 m_i2c.write(m_addr, t, 1, true) ;
Rhyme 0:7d913e68a6d7 67 m_i2c.read(m_addr, (char*)data, len) ;
Rhyme 0:7d913e68a6d7 68 }
Rhyme 0:7d913e68a6d7 69
Rhyme 0:7d913e68a6d7 70 void MAX44008::writeRegs(uint8_t *data, int len)
Rhyme 0:7d913e68a6d7 71 {
Rhyme 0:7d913e68a6d7 72 m_i2c.write(m_addr, (char *)data, len) ;
Rhyme 0:7d913e68a6d7 73 }
Rhyme 0:7d913e68a6d7 74
Rhyme 0:7d913e68a6d7 75 /**
Rhyme 0:7d913e68a6d7 76 * REGISTER: Interrupt Status
Rhyme 0:7d913e68a6d7 77 * Bit7: -
Rhyme 0:7d913e68a6d7 78 * Bit6: -
Rhyme 0:7d913e68a6d7 79 * Bit5: -
Rhyme 0:7d913e68a6d7 80 * Bit4: RESET : Reset Control
Rhyme 0:7d913e68a6d7 81 * 0 : The part is in normal operation.
Rhyme 0:7d913e68a6d7 82 * 1 : The part undergoes a forced POR sequence.
Rhyme 0:7d913e68a6d7 83 * All configuration, threshold, and data registers are
Rhyme 0:7d913e68a6d7 84 * reset to a power-on state by writing a 1 to this bit,
Rhyme 0:7d913e68a6d7 85 * and an internal hardware reset pulse is generated.
Rhyme 0:7d913e68a6d7 86 * This bit then automatically becomes 0 after the RESET sequence is completed.
Rhyme 0:7d913e68a6d7 87 * After resettign, the PWRON interrupt is triggered.
Rhyme 0:7d913e68a6d7 88 * Bit3: SHDN : Shutdown Control
Rhyme 0:7d913e68a6d7 89 * 0 : The part is in normal operatin.
Rhyme 0:7d913e68a6d7 90 * When the part returns from shutdown, note that the value in data registers
Rhyme 0:7d913e68a6d7 91 * is not current until the first conversion cycle is completed.
Rhyme 0:7d913e68a6d7 92 * 1 : The part can be put into a power-save mode by writing a 1 to this bit.
Rhyme 0:7d913e68a6d7 93 * Supply current is reduced to approximately 0.5uA with no I2C clock activity.
Rhyme 0:7d913e68a6d7 94 * While all registers remain accessible and retain data, ADC conversion data
Rhyme 0:7d913e68a6d7 95 * contained in them may not be current. Writeable registers also remain
Rhyme 0:7d913e68a6d7 96 * accessible in shutdown. All interrupts are cleared.
Rhyme 0:7d913e68a6d7 97 * Bit2: PWRON : Power-On INTERRUPT STATUS Flag
Rhyme 0:7d913e68a6d7 98 * 0 : Normal operating mode.
Rhyme 0:7d913e68a6d7 99 * 1 : The part went through a power-up event, either because the part was turned on,
Rhyme 0:7d913e68a6d7 100 * or because there was a power-supply voltage glitch.
Rhyme 0:7d913e68a6d7 101 * All interrupt threshold settings in the registers have been reset to power-on
Rhyme 0:7d913e68a6d7 102 * default states, and should be examined if nccessary. The /INT pin is also pulled low.
Rhyme 0:7d913e68a6d7 103 * Once this bit is set, the only way to clear this bit is to read this register.
Rhyme 0:7d913e68a6d7 104 * Bit1: -
Rhyme 0:7d913e68a6d7 105 * Bit0: AMBINTS : Ambient INTERRUPT STATUS Flag
Rhyme 0:7d913e68a6d7 106 * 0 : No interrupt trigger ever has occurred.
Rhyme 0:7d913e68a6d7 107 * 1 : The ambient light has exceeded the designated window limits defined
Rhyme 0:7d913e68a6d7 108 * by the threshold registers for longer than persist timer count AMBPST[1:0].
Rhyme 0:7d913e68a6d7 109 * It also causes the /INT pin to be pulled low. Once set,
Rhyme 0:7d913e68a6d7 110 * the only way to clear this bit is to read this register.
Rhyme 0:7d913e68a6d7 111 * This bit is always set to 0 if AMBINTE bit is set to 0.
Rhyme 0:7d913e68a6d7 112 */
Rhyme 0:7d913e68a6d7 113 uint8_t MAX44008::getIntStatus(void)
Rhyme 0:7d913e68a6d7 114 {
Rhyme 0:7d913e68a6d7 115 uint8_t value = 0 ;
Rhyme 0:7d913e68a6d7 116 readRegs(REG_INT_STATUS, &value, 1) ;
Rhyme 0:7d913e68a6d7 117 return( value ) ;
Rhyme 0:7d913e68a6d7 118 }
Rhyme 0:7d913e68a6d7 119
Rhyme 0:7d913e68a6d7 120 void MAX44008::setIntStatus(uint8_t newValue)
Rhyme 0:7d913e68a6d7 121 {
Rhyme 0:7d913e68a6d7 122 uint8_t val[2] ;
Rhyme 0:7d913e68a6d7 123 val[0] = REG_INT_STATUS ;
Rhyme 0:7d913e68a6d7 124 val[1] = newValue ;
Rhyme 0:7d913e68a6d7 125 writeRegs(val, 2) ;
Rhyme 0:7d913e68a6d7 126 }
Rhyme 0:7d913e68a6d7 127
Rhyme 0:7d913e68a6d7 128 /**
Rhyme 0:7d913e68a6d7 129 * REGISTER: Main Configuration
Rhyme 0:7d913e68a6d7 130 * Bit7: -
Rhyme 0:7d913e68a6d7 131 * Bit6: -
Rhyme 0:7d913e68a6d7 132 * Bit5: MODE[1]
Rhyme 0:7d913e68a6d7 133 * Bit4: MODE[0]
Rhyme 0:7d913e68a6d7 134 * 00 : Clear : CLEAR + TEMP(*) channels active
Rhyme 0:7d913e68a6d7 135 * 01 : Clear + IR : CLEAR + TEMP(*) + IR channels active
Rhyme 0:7d913e68a6d7 136 * 10 : Clear + RGB + IR : CLEAR + TEMP(*) + RGB + IR channels active
Rhyme 0:7d913e68a6d7 137 * (*) When TEMPEN set to 1.
Rhyme 0:7d913e68a6d7 138 * Bit3: AMBSEL[1] : Ambient Interrupt Select
Rhyme 0:7d913e68a6d7 139 * Bit2: AMBSEL[0] : Ambient Interrupt Select
Rhyme 0:7d913e68a6d7 140 * 00 : CLEAR channel data is used to compare with ambient interrupt thresholds and ambient timer settings.
Rhyme 0:7d913e68a6d7 141 01 : GREEN channel data is used to compare with ambinet interrupt thresholds and ambient timer settings.
Rhyme 0:7d913e68a6d7 142 10 : IR channel data is used to compare with ambient interrupt thresholds and ambient timer settings.
Rhyme 0:7d913e68a6d7 143 11 : TEMP channel data is used to compare with ambinet interrupt thresholds and ambinet timer settings.
Rhyme 0:7d913e68a6d7 144 * Bit1: -
Rhyme 0:7d913e68a6d7 145 * Bit0: AMBINTE : Ambient Interrupt Enable
Rhyme 0:7d913e68a6d7 146 * 0 : The AMBINTS bit and /INT pin remain unasserted even if an ambient interrupt event has occurred.
Rhyme 0:7d913e68a6d7 147 * The AMBINTS bit is set to 0 if previously set to 1.
Rhyme 0:7d913e68a6d7 148 * 1 : Detection of ambient interrupt is enabled (see the AMBINTS bit for more details).
Rhyme 0:7d913e68a6d7 149 * An ambient interrupt can trigger a hardware interrupt (/INT pin pullued low)
Rhyme 0:7d913e68a6d7 150 * and set AMBINTS bit (register 0x00, BIT0)
Rhyme 0:7d913e68a6d7 151 */
Rhyme 0:7d913e68a6d7 152 uint8_t MAX44008::getMainConfig(void)
Rhyme 0:7d913e68a6d7 153 {
Rhyme 0:7d913e68a6d7 154 uint8_t value = 0 ;
Rhyme 0:7d913e68a6d7 155 readRegs(REG_MAIN_CONFIG, &value, 1) ;
Rhyme 0:7d913e68a6d7 156 return( value ) ;
Rhyme 0:7d913e68a6d7 157 }
Rhyme 0:7d913e68a6d7 158
Rhyme 0:7d913e68a6d7 159 void MAX44008::setMainConfig(uint8_t newConfig)
Rhyme 0:7d913e68a6d7 160 {
Rhyme 0:7d913e68a6d7 161 uint8_t val[2] ;
Rhyme 0:7d913e68a6d7 162 val[0] = REG_MAIN_CONFIG ;
Rhyme 0:7d913e68a6d7 163 val[1] = newConfig ;
Rhyme 0:7d913e68a6d7 164 writeRegs(val, 2) ;
Rhyme 0:7d913e68a6d7 165 }
Rhyme 0:7d913e68a6d7 166
Rhyme 0:7d913e68a6d7 167 /**
Rhyme 0:7d913e68a6d7 168 * REGISTER: Ambient Configuration
Rhyme 0:7d913e68a6d7 169 * Bit7: TRIM
Rhyme 0:7d913e68a6d7 170 * 0 : Use factory-programmed gains for all the channels.
Rhyme 0:7d913e68a6d7 171 * Ignore any bytes written to TRIM_GAIN_GREEN[6:0],
Rhyme 0:7d913e68a6d7 172 * TRIM_GAIN_RED[6:0], TRIM_GAIN_BLUE[6:0], TRIM_GAIN_CLEAR[6:0],
Rhyme 0:7d913e68a6d7 173 * and TRIM_GAIN_IR[6:0] registers.
Rhyme 0:7d913e68a6d7 174 * 1 : Use bytes written to TRIM_GAIN_GREEN[6:0], TRIM_GAIN_RED[6:0],
Rhyme 0:7d913e68a6d7 175 * TRIM_GAIN_BLUE[6:0], TRIM_GAIN_CLEAR[6:0],
Rhyme 0:7d913e68a6d7 176 * and TRIM_GAIN_IR[6:0] registers to set the gain for each channel.
Rhyme 0:7d913e68a6d7 177 * Bit6: COMPEN
Rhyme 0:7d913e68a6d7 178 * 0 : Disables IR compensation.
Rhyme 0:7d913e68a6d7 179 * 1 : Enables IR compensation.
Rhyme 0:7d913e68a6d7 180 * Only for MODE[1:0] = 00 Mode.
Rhyme 0:7d913e68a6d7 181 * The integration time of compensation channel is controlled by the AMB mode settings.
Rhyme 0:7d913e68a6d7 182 * The compensation is enabled only when the clear channel is on.
Rhyme 0:7d913e68a6d7 183 * When COMPEN = 1, the CLEAR data is automatically compensated
Rhyme 0:7d913e68a6d7 184 * for stray IR leakeds and temperature variations.
Rhyme 0:7d913e68a6d7 185 * When COMPEN = 0, the IR compensation is disabled,
Rhyme 0:7d913e68a6d7 186 * but the output of the IR compensation data exits.
Rhyme 0:7d913e68a6d7 187 * Bit5: TEMPEN
Rhyme 0:7d913e68a6d7 188 * 0 : Disables temperature sensor.
Rhyme 0:7d913e68a6d7 189 * 1 : Enables temperature sensor.
Rhyme 0:7d913e68a6d7 190 * The integration time of temperature sensor is controlled by the ambient mode settings.
Rhyme 0:7d913e68a6d7 191 * The temperature sensor is enabled only if the clear channel is on.
Rhyme 0:7d913e68a6d7 192 * Bit4: AMBTIM[2]
Rhyme 0:7d913e68a6d7 193 * Bit3: AMBTIM[1]
Rhyme 0:7d913e68a6d7 194 * Bit2: AMBTIM[0]
Rhyme 0:7d913e68a6d7 195 * | Integration Time | Full-scale ADC | Bit Resolution | Relative LSB Size |
Rhyme 0:7d913e68a6d7 196 * | (ms) | (counts) | | for fixed AMPGA[1:0] |
Rhyme 0:7d913e68a6d7 197 * 000 : 100 | 16,384 | 14 | 1x |
Rhyme 0:7d913e68a6d7 198 * 001 : 25 | 4,096 | 12 | 4x |
Rhyme 0:7d913e68a6d7 199 * 010 : 6.25 | 1,024 | 10 | 16x |
Rhyme 0:7d913e68a6d7 200 * 011 : 1.5625 | 256 | 8 | 64x |
Rhyme 0:7d913e68a6d7 201 * 100 : 400 | 16,384 | 14 | 1/4x |
Rhyme 0:7d913e68a6d7 202 * 101 : Reserved | Not applicable | Not applicable | Not applicable |
Rhyme 0:7d913e68a6d7 203 * 110 : Reserved | Not applicable | Not applicable | Not applicable |
Rhyme 0:7d913e68a6d7 204 * 111 : Reserved | Not applicable | Not applicable | Not applicable |
Rhyme 0:7d913e68a6d7 205 * Bit1: AMBPGA[1]
Rhyme 0:7d913e68a6d7 206 * Bit0: AMBPGA[0]
Rhyme 0:7d913e68a6d7 207 * In AMBTIM[2:0] = 000 Mode (100ms integraation time)
Rhyme 0:7d913e68a6d7 208 * | CLEAR/RED/GREEN/IR | BLUE |
Rhyme 0:7d913e68a6d7 209 * | nW/cm^2 per LSB | Full-scale (nW/cm^2) | nW/cm^2 per LSB | Full-scale (nW/cm^2) |
Rhyme 0:7d913e68a6d7 210 * 00 : 2 | 32.768 | 4 | 65.536 |
Rhyme 0:7d913e68a6d7 211 * 01 : 8 | 131.072 | 16 | 262.144 |
Rhyme 0:7d913e68a6d7 212 * 10 : 32 | 524.288 | 64 | 1048.573 |
Rhyme 0:7d913e68a6d7 213 * 11 : 512 | 8388.61 | 1024 | 16777.2 |
Rhyme 0:7d913e68a6d7 214 * In AMBTIM[2:0] = 100 Mode (400ms integration time)
Rhyme 0:7d913e68a6d7 215 * | CLEAR/RED/GREEN/IR | BLUE |
Rhyme 0:7d913e68a6d7 216 * | nW/cm^2 per LSB | Full-scale (nW/cm^2) | nW/cm^2 per LSB | Full-scale (nW/cm^2) |
Rhyme 0:7d913e68a6d7 217 * 00 : 0.5 | 8.192 | 1 | 16.384 |
Rhyme 0:7d913e68a6d7 218 * 01 : 2 | 32.768 | 4 | 65.536 |
Rhyme 0:7d913e68a6d7 219 * 10 : 8 | 131.072 | 16 | 262.1433 |
Rhyme 0:7d913e68a6d7 220 * 11 : 128 | 2097.153 | 256 | 4194.3 |
Rhyme 0:7d913e68a6d7 221 */
Rhyme 0:7d913e68a6d7 222 uint8_t MAX44008::getAMB_Config(void)
Rhyme 0:7d913e68a6d7 223 {
Rhyme 0:7d913e68a6d7 224 uint8_t value = 0 ;
Rhyme 0:7d913e68a6d7 225 readRegs(REG_AMB_CONFIG, &value, 1) ;
Rhyme 0:7d913e68a6d7 226 return( value ) ;
Rhyme 0:7d913e68a6d7 227 }
Rhyme 0:7d913e68a6d7 228
Rhyme 0:7d913e68a6d7 229 void MAX44008::setAMB_Config(uint8_t newConfig)
Rhyme 0:7d913e68a6d7 230 {
Rhyme 0:7d913e68a6d7 231 uint8_t val[2] ;
Rhyme 0:7d913e68a6d7 232 val[0] = REG_AMB_CONFIG ;
Rhyme 0:7d913e68a6d7 233 val[1] = newConfig ;
Rhyme 0:7d913e68a6d7 234 writeRegs(val, 2) ;
Rhyme 0:7d913e68a6d7 235 }
Rhyme 0:7d913e68a6d7 236
Rhyme 0:7d913e68a6d7 237 int16_t MAX44008::getAMB_CLEAR(void) {
Rhyme 0:7d913e68a6d7 238 int16_t value;
Rhyme 0:7d913e68a6d7 239 uint8_t res[2];
Rhyme 0:7d913e68a6d7 240 readRegs(REG_AMB_CLR_MSB, res, 2) ;
Rhyme 0:7d913e68a6d7 241 value = (res[0] << 8)+res[1] ;
Rhyme 0:7d913e68a6d7 242 return( value ) ;
Rhyme 0:7d913e68a6d7 243 }
Rhyme 0:7d913e68a6d7 244
Rhyme 0:7d913e68a6d7 245 int16_t MAX44008::getAMB_RED(void) {
Rhyme 0:7d913e68a6d7 246 int16_t value;
Rhyme 0:7d913e68a6d7 247 uint8_t res[2];
Rhyme 0:7d913e68a6d7 248 readRegs(REG_AMB_RED_MSB, res, 2) ;
Rhyme 0:7d913e68a6d7 249 value = (res[0] << 8)+res[1] ;
Rhyme 0:7d913e68a6d7 250 return( value ) ;
Rhyme 0:7d913e68a6d7 251 }
Rhyme 0:7d913e68a6d7 252
Rhyme 0:7d913e68a6d7 253 int16_t MAX44008::getAMB_GREEN(void) {
Rhyme 0:7d913e68a6d7 254 int16_t value;
Rhyme 0:7d913e68a6d7 255 uint8_t res[2];
Rhyme 0:7d913e68a6d7 256 readRegs(REG_AMB_GRN_MSB, res, 2) ;
Rhyme 0:7d913e68a6d7 257 value = (res[0] << 8)+res[1] ;
Rhyme 0:7d913e68a6d7 258 return( value ) ;
Rhyme 0:7d913e68a6d7 259 }
Rhyme 0:7d913e68a6d7 260
Rhyme 0:7d913e68a6d7 261 int16_t MAX44008::getAMB_BLUE(void) {
Rhyme 0:7d913e68a6d7 262 int16_t value;
Rhyme 0:7d913e68a6d7 263 uint8_t res[2];
Rhyme 0:7d913e68a6d7 264 readRegs(REG_AMB_BLU_MSB, res, 2) ;
Rhyme 0:7d913e68a6d7 265 value = (res[0] << 8)+res[1] ;
Rhyme 0:7d913e68a6d7 266 return( value ) ;
Rhyme 0:7d913e68a6d7 267 }
Rhyme 0:7d913e68a6d7 268
Rhyme 0:7d913e68a6d7 269 int16_t MAX44008::getIR(void) {
Rhyme 0:7d913e68a6d7 270 int16_t value;
Rhyme 0:7d913e68a6d7 271 uint8_t res[2];
Rhyme 0:7d913e68a6d7 272 readRegs(REG_AMB_IR_MSB, res, 2) ;
Rhyme 0:7d913e68a6d7 273 value = (res[0] << 8)+res[1] ;
Rhyme 0:7d913e68a6d7 274 return( value ) ;
Rhyme 0:7d913e68a6d7 275 }
Rhyme 0:7d913e68a6d7 276
Rhyme 0:7d913e68a6d7 277 int16_t MAX44008::getIRCOMP(void) {
Rhyme 0:7d913e68a6d7 278 int16_t value;
Rhyme 0:7d913e68a6d7 279 uint8_t res[2];
Rhyme 0:7d913e68a6d7 280 readRegs(REG_AMB_IRCMP_MSB, res, 2) ;
Rhyme 0:7d913e68a6d7 281 value = (res[0] << 8)+res[1] ;
Rhyme 0:7d913e68a6d7 282 return( value ) ;
Rhyme 0:7d913e68a6d7 283 }
Rhyme 0:7d913e68a6d7 284
Rhyme 0:7d913e68a6d7 285 int16_t MAX44008::getTEMP(void)
Rhyme 0:7d913e68a6d7 286 {
Rhyme 0:7d913e68a6d7 287 int16_t value;
Rhyme 0:7d913e68a6d7 288 uint8_t res[2];
Rhyme 0:7d913e68a6d7 289 readRegs(REG_TMP_MSB, res, 2) ;
Rhyme 0:7d913e68a6d7 290 value = (res[0] << 8)+res[1] ;
Rhyme 0:7d913e68a6d7 291 return( value ) ;
Rhyme 0:7d913e68a6d7 292 }
Rhyme 0:7d913e68a6d7 293
Rhyme 0:7d913e68a6d7 294 int16_t MAX44008::getAMB_UPTHR(void)
Rhyme 0:7d913e68a6d7 295 {
Rhyme 0:7d913e68a6d7 296 uint16_t value ;
Rhyme 0:7d913e68a6d7 297 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 298 readRegs(REG_AMB_UPTHR_MSB, res, 2) ;
Rhyme 0:7d913e68a6d7 299 value = (res[0] << 8) | res[1] ;
Rhyme 0:7d913e68a6d7 300 return( value ) ;
Rhyme 0:7d913e68a6d7 301 }
Rhyme 0:7d913e68a6d7 302
Rhyme 0:7d913e68a6d7 303 void MAX44008::setAMB_UPTHR(int16_t newTHR)
Rhyme 0:7d913e68a6d7 304 {
Rhyme 0:7d913e68a6d7 305 uint8_t res[3] ;
Rhyme 0:7d913e68a6d7 306 res[0] = REG_AMB_UPTHR_MSB ;
Rhyme 0:7d913e68a6d7 307 res[1] = (newTHR >> 8) & 0x3F ;
Rhyme 0:7d913e68a6d7 308 res[2] = newTHR & 0xFF ;
Rhyme 0:7d913e68a6d7 309 writeRegs(res, 3) ;
Rhyme 0:7d913e68a6d7 310 }
Rhyme 0:7d913e68a6d7 311
Rhyme 0:7d913e68a6d7 312 int16_t MAX44008::getAMB_LOTHR(void)
Rhyme 0:7d913e68a6d7 313 {
Rhyme 0:7d913e68a6d7 314 uint16_t value ;
Rhyme 0:7d913e68a6d7 315 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 316 readRegs(REG_AMB_LOTHR_MSB, res, 2) ;
Rhyme 0:7d913e68a6d7 317 value = (res[0] << 8) | res[1] ;
Rhyme 0:7d913e68a6d7 318 return( value ) ;
Rhyme 0:7d913e68a6d7 319 }
Rhyme 0:7d913e68a6d7 320
Rhyme 0:7d913e68a6d7 321 void MAX44008::setAMB_LOTHR(int16_t newTHR)
Rhyme 0:7d913e68a6d7 322 {
Rhyme 0:7d913e68a6d7 323 uint8_t res[3] ;
Rhyme 0:7d913e68a6d7 324 res[0] = REG_AMB_LOTHR_MSB ;
Rhyme 0:7d913e68a6d7 325 res[1] = (newTHR >> 8) & 0x3F ;
Rhyme 0:7d913e68a6d7 326 res[2] = newTHR & 0xFF ;
Rhyme 0:7d913e68a6d7 327 writeRegs(res, 3) ;
Rhyme 0:7d913e68a6d7 328 }
Rhyme 0:7d913e68a6d7 329
Rhyme 0:7d913e68a6d7 330 uint8_t MAX44008::getAMB_PST(void)
Rhyme 0:7d913e68a6d7 331 {
Rhyme 0:7d913e68a6d7 332 uint8_t value ;
Rhyme 0:7d913e68a6d7 333 readRegs(REG_AMB_PST, &value, 1) ;
Rhyme 0:7d913e68a6d7 334 return( value ) ;
Rhyme 0:7d913e68a6d7 335 }
Rhyme 0:7d913e68a6d7 336
Rhyme 0:7d913e68a6d7 337 void MAX44008::setAMB_PST(uint8_t newValue)
Rhyme 0:7d913e68a6d7 338 {
Rhyme 0:7d913e68a6d7 339 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 340 res[0] = REG_AMB_PST ;
Rhyme 0:7d913e68a6d7 341 res[1] = newValue ;
Rhyme 0:7d913e68a6d7 342 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 343 }
Rhyme 0:7d913e68a6d7 344
Rhyme 0:7d913e68a6d7 345 /* Ambient ADC Gains */
Rhyme 0:7d913e68a6d7 346 uint8_t MAX44008::getTRIM_GAIN_CLEAR(void)
Rhyme 0:7d913e68a6d7 347 {
Rhyme 0:7d913e68a6d7 348 uint8_t value ;
Rhyme 0:7d913e68a6d7 349 readRegs(REG_TRIM_GAIN_CLR, &value, 1) ;
Rhyme 0:7d913e68a6d7 350 return(value) ;
Rhyme 0:7d913e68a6d7 351 }
Rhyme 0:7d913e68a6d7 352
Rhyme 0:7d913e68a6d7 353 void MAX44008::setTRIM_GAIN_CLEAR(uint8_t newValue)
Rhyme 0:7d913e68a6d7 354 {
Rhyme 0:7d913e68a6d7 355 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 356 res[0] = REG_TRIM_GAIN_CLR ;
Rhyme 0:7d913e68a6d7 357 res[1] = newValue ;
Rhyme 0:7d913e68a6d7 358 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 359 }
Rhyme 0:7d913e68a6d7 360
Rhyme 0:7d913e68a6d7 361 uint8_t MAX44008::getTRIM_GAIN_RED(void)
Rhyme 0:7d913e68a6d7 362 {
Rhyme 0:7d913e68a6d7 363 uint8_t value ;
Rhyme 0:7d913e68a6d7 364 readRegs(REG_TRIM_GAIN_RED, &value, 1) ;
Rhyme 0:7d913e68a6d7 365 return(value) ;
Rhyme 0:7d913e68a6d7 366 }
Rhyme 0:7d913e68a6d7 367
Rhyme 0:7d913e68a6d7 368 void MAX44008::setTRIM_GAIN_RED(uint8_t newValue)
Rhyme 0:7d913e68a6d7 369 {
Rhyme 0:7d913e68a6d7 370 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 371 res[0] = REG_TRIM_GAIN_RED ;
Rhyme 0:7d913e68a6d7 372 res[1] = newValue ;
Rhyme 0:7d913e68a6d7 373 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 374 }
Rhyme 0:7d913e68a6d7 375
Rhyme 0:7d913e68a6d7 376 uint8_t MAX44008::getTRIM_GAIN_GREEN(void)
Rhyme 0:7d913e68a6d7 377 {
Rhyme 0:7d913e68a6d7 378 uint8_t value ;
Rhyme 0:7d913e68a6d7 379 readRegs(REG_TRIM_GAIN_GRN, &value, 1) ;
Rhyme 0:7d913e68a6d7 380 return(value) ;
Rhyme 0:7d913e68a6d7 381 }
Rhyme 0:7d913e68a6d7 382
Rhyme 0:7d913e68a6d7 383 void MAX44008::setTRIM_GAIN_GREEN(uint8_t newValue)
Rhyme 0:7d913e68a6d7 384 {
Rhyme 0:7d913e68a6d7 385 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 386 res[0] = REG_TRIM_GAIN_GRN ;
Rhyme 0:7d913e68a6d7 387 res[1] = newValue ;
Rhyme 0:7d913e68a6d7 388 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 389 }
Rhyme 0:7d913e68a6d7 390
Rhyme 0:7d913e68a6d7 391 uint8_t MAX44008::getTRIM_GAIN_BLUE(void)
Rhyme 0:7d913e68a6d7 392 {
Rhyme 0:7d913e68a6d7 393 uint8_t value ;
Rhyme 0:7d913e68a6d7 394 readRegs(REG_TRIM_GAIN_BLU, &value, 1) ;
Rhyme 0:7d913e68a6d7 395 return(value) ;
Rhyme 0:7d913e68a6d7 396 }
Rhyme 0:7d913e68a6d7 397
Rhyme 0:7d913e68a6d7 398 void MAX44008::setTRIM_GAIN_BLUE(uint8_t newValue)
Rhyme 0:7d913e68a6d7 399 {
Rhyme 0:7d913e68a6d7 400 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 401 res[0] = REG_TRIM_GAIN_BLU ;
Rhyme 0:7d913e68a6d7 402 res[1] = newValue ;
Rhyme 0:7d913e68a6d7 403 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 404 }
Rhyme 0:7d913e68a6d7 405
Rhyme 0:7d913e68a6d7 406 uint8_t MAX44008::getTRIM_GAIN_IR(void)
Rhyme 0:7d913e68a6d7 407 {
Rhyme 0:7d913e68a6d7 408 uint8_t value ;
Rhyme 0:7d913e68a6d7 409 readRegs(REG_TRIM_GAIN_IR, &value, 1) ;
Rhyme 0:7d913e68a6d7 410 return(value) ;
Rhyme 0:7d913e68a6d7 411 }
Rhyme 0:7d913e68a6d7 412
Rhyme 0:7d913e68a6d7 413 void MAX44008::setTRIM_GAIN_IR(uint8_t newValue)
Rhyme 0:7d913e68a6d7 414 {
Rhyme 0:7d913e68a6d7 415 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 416 res[0] = REG_TRIM_GAIN_IR ;
Rhyme 0:7d913e68a6d7 417 res[1] = newValue ;
Rhyme 0:7d913e68a6d7 418 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 419 }
Rhyme 0:7d913e68a6d7 420
Rhyme 0:7d913e68a6d7 421 void MAX44008::enableTRIM(void)
Rhyme 0:7d913e68a6d7 422 {
Rhyme 0:7d913e68a6d7 423 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 424 res[0] = REG_AMB_CONFIG ;
Rhyme 0:7d913e68a6d7 425 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 426 res[1] |= 0x80 ; /* BIT7 = TRIM */
Rhyme 0:7d913e68a6d7 427 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 428 }
Rhyme 0:7d913e68a6d7 429
Rhyme 0:7d913e68a6d7 430 void MAX44008::disableTRIM(void)
Rhyme 0:7d913e68a6d7 431 {
Rhyme 0:7d913e68a6d7 432 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 433 res[0] = REG_AMB_CONFIG ;
Rhyme 0:7d913e68a6d7 434 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 435 res[1] &= (uint8_t)(0x7F) ; /* BIT7 = TRIM */
Rhyme 0:7d913e68a6d7 436 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 437 }
Rhyme 0:7d913e68a6d7 438
Rhyme 0:7d913e68a6d7 439 void MAX44008::enableCOMP(void)
Rhyme 0:7d913e68a6d7 440 {
Rhyme 0:7d913e68a6d7 441 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 442 res[0] = REG_AMB_CONFIG ;
Rhyme 0:7d913e68a6d7 443 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 444 res[1] |= 0x40 ; /* BIT6 = COMPEN */
Rhyme 0:7d913e68a6d7 445 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 446 }
Rhyme 0:7d913e68a6d7 447
Rhyme 0:7d913e68a6d7 448 void MAX44008::disableCOMP(void)
Rhyme 0:7d913e68a6d7 449 {
Rhyme 0:7d913e68a6d7 450 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 451 res[0] = REG_AMB_CONFIG ;
Rhyme 0:7d913e68a6d7 452 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 453 res[1] &= (uint8_t)(0xBF) ; /* BIT6 = COMPEN */
Rhyme 0:7d913e68a6d7 454 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 455 }
Rhyme 0:7d913e68a6d7 456
Rhyme 0:7d913e68a6d7 457 void MAX44008::enableTEMP(void)
Rhyme 0:7d913e68a6d7 458 {
Rhyme 0:7d913e68a6d7 459 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 460 res[0] = REG_AMB_CONFIG ;
Rhyme 0:7d913e68a6d7 461 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 462 res[1] |= 0x20 ; /* BIT5 = TEMPEN */
Rhyme 0:7d913e68a6d7 463 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 464 }
Rhyme 0:7d913e68a6d7 465
Rhyme 0:7d913e68a6d7 466 void MAX44008::disableTEMP(void)
Rhyme 0:7d913e68a6d7 467 {
Rhyme 0:7d913e68a6d7 468 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 469 res[0] = REG_AMB_CONFIG ;
Rhyme 0:7d913e68a6d7 470 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 471 res[1] &= (uint8_t)(0xDF) ; /* BIT5 = TEMPEN */
Rhyme 0:7d913e68a6d7 472 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 473 }
Rhyme 0:7d913e68a6d7 474
Rhyme 0:7d913e68a6d7 475 void MAX44008::enableAMBINT(void)
Rhyme 0:7d913e68a6d7 476 {
Rhyme 0:7d913e68a6d7 477 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 478 res[0] = REG_MAIN_CONFIG ;
Rhyme 0:7d913e68a6d7 479 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 480 res[1] |= 0x01 ; /* BIT0 = AMBINTE */
Rhyme 0:7d913e68a6d7 481 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 482 }
Rhyme 0:7d913e68a6d7 483
Rhyme 0:7d913e68a6d7 484 void MAX44008::disableAMBINT(void)
Rhyme 0:7d913e68a6d7 485 {
Rhyme 0:7d913e68a6d7 486 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 487 res[0] = REG_MAIN_CONFIG ;
Rhyme 0:7d913e68a6d7 488 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 489 res[1] &= (uint8_t)(0xFE) ; /* BIT0 = AMBINTE */
Rhyme 0:7d913e68a6d7 490 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 491 }
Rhyme 0:7d913e68a6d7 492
Rhyme 0:7d913e68a6d7 493 void MAX44008::selectAMBINT(uint8_t newChannel)
Rhyme 0:7d913e68a6d7 494 {
Rhyme 0:7d913e68a6d7 495 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 496 res[0] = REG_MAIN_CONFIG ;
Rhyme 0:7d913e68a6d7 497 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 498 res[1] &= 0xF3 ; /* clear AMBSEL[1:0] */
Rhyme 0:7d913e68a6d7 499 res[1] |= ((newChannel & 0x03) << 2) ;
Rhyme 0:7d913e68a6d7 500 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 501 }
Rhyme 0:7d913e68a6d7 502 void MAX44008::setMode(uint8_t newMode)
Rhyme 0:7d913e68a6d7 503 {
Rhyme 0:7d913e68a6d7 504 uint8_t res[2] ;
Rhyme 0:7d913e68a6d7 505 res[0] = REG_MAIN_CONFIG ;
Rhyme 0:7d913e68a6d7 506 readRegs(res[0], &res[1], 1) ;
Rhyme 0:7d913e68a6d7 507 res[1] &= 0xCF ; /* clear MODE[1:0] */
Rhyme 0:7d913e68a6d7 508 res[1] |= ((newMode & 0x03) << 4) ;
Rhyme 0:7d913e68a6d7 509 writeRegs(res, 2) ;
Rhyme 0:7d913e68a6d7 510 }