Central Applications - Mbed Code repo / MAX2871_Shield_MAXREFDES161

First version of the MAX2871 shield library. Includes demo program with terminal for setting frequency on channel A.

MAX2871.h@1:40b397b31d13, 2017-07-31 (annotated)

Committer:
MI
Date:
Mon Jul 31 23:57:09 2017 +0000
Revision:
1:40b397b31d13
Parent:
0:9f09f1b58389 
Committed the wrong version the first time.

Who changed what in which revision?

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MI 0:9f09f1b58389 1 /*******************************************************************************
MI 0:9f09f1b58389 2 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
MI 0:9f09f1b58389 3 *
MI 0:9f09f1b58389 4 * Permission is hereby granted, free of charge, to any person obtaining a
MI 0:9f09f1b58389 5 * copy of this software and associated documentation files (the "Software"),
MI 0:9f09f1b58389 6 * to deal in the Software without restriction, including without limitation
MI 0:9f09f1b58389 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
MI 0:9f09f1b58389 8 * and/or sell copies of the Software, and to permit persons to whom the
MI 0:9f09f1b58389 9 * Software is furnished to do so, subject to the following conditions:
MI 0:9f09f1b58389 10 *
MI 0:9f09f1b58389 11 * The above copyright notice and this permission notice shall be included
MI 0:9f09f1b58389 12 * in all copies or substantial portions of the Software.
MI 0:9f09f1b58389 13 *
MI 0:9f09f1b58389 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
MI 0:9f09f1b58389 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MI 0:9f09f1b58389 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
MI 0:9f09f1b58389 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
MI 0:9f09f1b58389 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
MI 0:9f09f1b58389 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
MI 0:9f09f1b58389 20 * OTHER DEALINGS IN THE SOFTWARE.
MI 0:9f09f1b58389 21 *
MI 0:9f09f1b58389 22 * Except as contained in this notice, the name of Maxim Integrated
MI 0:9f09f1b58389 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
MI 0:9f09f1b58389 24 * Products, Inc. Branding Policy.
MI 0:9f09f1b58389 25 *
MI 0:9f09f1b58389 26 * The mere transfer of this software does not imply any licenses
MI 0:9f09f1b58389 27 * of trade secrets, proprietary technology, copyrights, patents,
MI 0:9f09f1b58389 28 * trademarks, maskwork rights, or any other form of intellectual
MI 0:9f09f1b58389 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
MI 0:9f09f1b58389 30 * ownership rights.
MI 0:9f09f1b58389 31 *******************************************************************************
MI 0:9f09f1b58389 32 */
MI 0:9f09f1b58389 33
MI 0:9f09f1b58389 34
MI 0:9f09f1b58389 35 #ifndef _MAX2871_H_
MI 0:9f09f1b58389 36 #define _MAX2871_H_
MI 0:9f09f1b58389 37
MI 0:9f09f1b58389 38
MI 0:9f09f1b58389 39 #include "mbed.h"
MI 0:9f09f1b58389 40
MI 0:9f09f1b58389 41
MI 0:9f09f1b58389 42 /**
MI 0:9f09f1b58389 43 * @brief The MAX2871 is an ultra-wideband phase-locked loop (PLL) with integrated
MI 0:9f09f1b58389 44 * voltage control oscillators (VCOs)capable of operating in both integer-N and
MI 0:9f09f1b58389 45 * fractional-N modes. When combined with an external reference oscillator and
MI 0:9f09f1b58389 46 * loop filter, the MAX2871 is a high-performance frequency synthesizer capable
MI 0:9f09f1b58389 47 * of synthesizing frequencies from 23.5MHz to 6.0GHz while maintaining superior
MI 0:9f09f1b58389 48 * phase noise and spurious performance.
MI 0:9f09f1b58389 49 *
MI 0:9f09f1b58389 50 * @code
MI 0:9f09f1b58389 51 #include "mbed.h"
MI 0:9f09f1b58389 52 #include <stdio.h>
MI 0:9f09f1b58389 53
MI 0:9f09f1b58389 54 #include "MAX2871.h"
MI 0:9f09f1b58389 55
MI 0:9f09f1b58389 56 SPI spi(D11,D12,D13); //mosi, miso, sclk
MI 0:9f09f1b58389 57 Serial pc(USBTX,USBRX,9600); //tx, rx, baud
MI 0:9f09f1b58389 58
MI 0:9f09f1b58389 59 DigitalOut le(D10,1); //latch enable
MI 0:9f09f1b58389 60 DigitalOut ce(D9,1); //chip enable
MI 0:9f09f1b58389 61 DigitalOut rfout_en(D8,1); //RF output enable
MI 0:9f09f1b58389 62
MI 0:9f09f1b58389 63 int main() {
MI 0:9f09f1b58389 64 float freq_entry; //frequency input to terminal
MI 0:9f09f1b58389 65 float freq_actual; //frequency based on MAX2871 settings
MI 0:9f09f1b58389 66 float freq_pfd; //frequency of phase frequency detector
MI 0:9f09f1b58389 67 float pll_coefficient; //fractional-N coefficient (N + F/M)
MI 0:9f09f1b58389 68 float vco_divisor; //divisor from f_vco to f_rfouta
MI 0:9f09f1b58389 69 char buffer[256]; //string input from terminal
MI 0:9f09f1b58389 70
MI 0:9f09f1b58389 71 spi.format(8,0); //CPOL = CPHA = 0, 8 bits per frame
MI 0:9f09f1b58389 72 spi.frequency(1000000); //1 MHz SPI clock
MI 0:9f09f1b58389 73
MI 0:9f09f1b58389 74 MAX2871 max2871(spi,D10); //create object of class MAX2871
MI 0:9f09f1b58389 75
MI 0:9f09f1b58389 76 //The routine in the while(1) loop will ask the user to input a desired
MI 0:9f09f1b58389 77 //output frequency, calculate the corresponding register settings, update
MI 0:9f09f1b58389 78 //the MAX2871 registers, and then independently use the programmed values
MI 0:9f09f1b58389 79 //from the registers to re-calculate the output frequency chosen
MI 0:9f09f1b58389 80 while(1){
MI 0:9f09f1b58389 81 pc.printf("\n\rEnter a frequency in MHz:");
MI 0:9f09f1b58389 82 fgets(buffer,256,stdin); //store entry as string until newline entered
MI 0:9f09f1b58389 83 freq_entry = atof (buffer); //convert string to a float
MI 0:9f09f1b58389 84 max2871.frequency(freq_entry); //update MAX2871 registers for new frequency
MI 1:40b397b31d13 85 max2871.readRegister6(); //read register 6 and update max2871.reg6
MI 0:9f09f1b58389 86
MI 0:9f09f1b58389 87 //Examples for how to calculate important operation parameters like
MI 0:9f09f1b58389 88 //PFD frequency and divisor ratios using members of the MAX2871 class
MI 0:9f09f1b58389 89 freq_pfd = max2871.f_reference*(1+max2871.reg2.bits.dbr)/(max2871.reg2.bits.r*(1+max2871.reg2.bits.rdiv2));
MI 1:40b397b31d13 90 pll_coefficient = (max2871.reg0.bits.n+1.0*max2871.reg0.bits.frac/max2871.reg1.bits.m);
MI 0:9f09f1b58389 91 vco_divisor = powf(2,max2871.reg4.bits.diva);
MI 0:9f09f1b58389 92
MI 0:9f09f1b58389 93 //calculate expected f_RFOUTA based on the register settings
MI 0:9f09f1b58389 94 freq_actual = freq_pfd*pll_coefficient/vco_divisor;
MI 1:40b397b31d13 95 pc.printf("\n\rTarget: %.3f MHz\tActual: %.3f MHz",freq_entry,freq_actual);
MI 1:40b397b31d13 96 pc.printf("\n\rDie: %d, VCO: %d, F_PFD: %f",max2871.reg6.bits.die,max2871.reg6.bits.v,freq_pfd);
MI 1:40b397b31d13 97 pc.printf("\n\rN: %d, F: %d, M: %d, N+F/M: %f",max2871.reg0.bits.n,max2871.reg0.bits.frac,max2871.reg1.bits.m,pll_coefficient);
MI 0:9f09f1b58389 98 }
MI 0:9f09f1b58389 99
MI 0:9f09f1b58389 100 }
MI 0:9f09f1b58389 101
MI 0:9f09f1b58389 102 * @endcode
MI 0:9f09f1b58389 103 */
MI 0:9f09f1b58389 104 class MAX2871
MI 0:9f09f1b58389 105 {
MI 0:9f09f1b58389 106 public:
MI 0:9f09f1b58389 107 ///Register 0 bits
MI 0:9f09f1b58389 108 union REG0_u
MI 0:9f09f1b58389 109 {
MI 0:9f09f1b58389 110 ///Access all bits
MI 0:9f09f1b58389 111 uint32_t all;
MI 0:9f09f1b58389 112
MI 0:9f09f1b58389 113 ///Access individual bits
MI 0:9f09f1b58389 114 struct BitField_s
MI 0:9f09f1b58389 115 {
MI 0:9f09f1b58389 116 uint32_t addr : 3;
MI 0:9f09f1b58389 117 uint32_t frac : 12;
MI 0:9f09f1b58389 118 uint32_t n : 16;
MI 0:9f09f1b58389 119 uint32_t intfrac : 1;
MI 0:9f09f1b58389 120 }bits;
MI 0:9f09f1b58389 121 };
MI 0:9f09f1b58389 122
MI 0:9f09f1b58389 123 ///Register 1 bits
MI 0:9f09f1b58389 124 union REG1_u
MI 0:9f09f1b58389 125 {
MI 0:9f09f1b58389 126 ///Access all bits
MI 0:9f09f1b58389 127 uint32_t all;
MI 0:9f09f1b58389 128
MI 0:9f09f1b58389 129 ///Access individual bits
MI 0:9f09f1b58389 130 struct BitField_s
MI 0:9f09f1b58389 131 {
MI 0:9f09f1b58389 132 uint32_t addr : 3;
MI 0:9f09f1b58389 133 uint32_t m : 12;
MI 0:9f09f1b58389 134 uint32_t p : 12;
MI 0:9f09f1b58389 135 uint32_t cpt : 2;
MI 0:9f09f1b58389 136 uint32_t cpl : 2;
MI 0:9f09f1b58389 137 uint32_t reserved1 : 1;
MI 0:9f09f1b58389 138 }bits;
MI 0:9f09f1b58389 139 };
MI 0:9f09f1b58389 140
MI 0:9f09f1b58389 141 ///Register 2 bits
MI 0:9f09f1b58389 142 union REG2_u
MI 0:9f09f1b58389 143 {
MI 0:9f09f1b58389 144 ///Access all bits
MI 0:9f09f1b58389 145 uint32_t all;
MI 0:9f09f1b58389 146
MI 0:9f09f1b58389 147 ///Access individual bits
MI 0:9f09f1b58389 148 struct BitField_s
MI 0:9f09f1b58389 149 {
MI 0:9f09f1b58389 150 uint32_t addr : 3;
MI 0:9f09f1b58389 151 uint32_t rst : 1;
MI 0:9f09f1b58389 152 uint32_t tri : 1;
MI 0:9f09f1b58389 153 uint32_t shdn : 1;
MI 0:9f09f1b58389 154 uint32_t pdp : 1;
MI 0:9f09f1b58389 155 uint32_t ldp : 1;
MI 0:9f09f1b58389 156 uint32_t ldf : 1;
MI 0:9f09f1b58389 157 uint32_t cp : 4;
MI 0:9f09f1b58389 158 uint32_t reg4db : 1;
MI 0:9f09f1b58389 159 uint32_t r : 10;
MI 0:9f09f1b58389 160 uint32_t rdiv2 : 1;
MI 0:9f09f1b58389 161 uint32_t dbr : 1;
MI 0:9f09f1b58389 162 uint32_t mux : 3;
MI 0:9f09f1b58389 163 uint32_t sdn : 2;
MI 0:9f09f1b58389 164 uint32_t lds : 1;
MI 0:9f09f1b58389 165 }bits;
MI 0:9f09f1b58389 166 };
MI 0:9f09f1b58389 167
MI 0:9f09f1b58389 168 ///Register 3 bits
MI 0:9f09f1b58389 169 union REG3_u
MI 0:9f09f1b58389 170 {
MI 0:9f09f1b58389 171 ///Access all bits
MI 0:9f09f1b58389 172 uint32_t all;
MI 0:9f09f1b58389 173
MI 0:9f09f1b58389 174 ///Access individual bits
MI 0:9f09f1b58389 175 struct BitField_s
MI 0:9f09f1b58389 176 {
MI 0:9f09f1b58389 177 uint32_t addr : 3;
MI 0:9f09f1b58389 178 uint32_t cdiv : 12;
MI 0:9f09f1b58389 179 uint32_t cdm : 2;
MI 0:9f09f1b58389 180 uint32_t mutedel : 1;
MI 0:9f09f1b58389 181 uint32_t csm : 1;
MI 0:9f09f1b58389 182 uint32_t reserved1 : 5;
MI 0:9f09f1b58389 183 uint32_t vas_temp : 1;
MI 0:9f09f1b58389 184 uint32_t vas_shdn : 1;
MI 0:9f09f1b58389 185 uint32_t vco : 6;
MI 0:9f09f1b58389 186 }bits;
MI 0:9f09f1b58389 187 };
MI 0:9f09f1b58389 188
MI 0:9f09f1b58389 189 ///Register 4 bits
MI 0:9f09f1b58389 190 union REG4_u
MI 0:9f09f1b58389 191 {
MI 0:9f09f1b58389 192 ///Access all bits
MI 0:9f09f1b58389 193 uint32_t all;
MI 0:9f09f1b58389 194
MI 0:9f09f1b58389 195 ///Access individual bits
MI 0:9f09f1b58389 196 struct BitField_s
MI 0:9f09f1b58389 197 {
MI 0:9f09f1b58389 198 uint32_t addr : 3;
MI 0:9f09f1b58389 199 uint32_t apwr : 2;
MI 0:9f09f1b58389 200 uint32_t rfa_en : 1;
MI 0:9f09f1b58389 201 uint32_t bpwr : 2;
MI 0:9f09f1b58389 202 uint32_t rfb_en : 1;
MI 0:9f09f1b58389 203 uint32_t bdiv : 1;
MI 0:9f09f1b58389 204 uint32_t mtld : 1;
MI 0:9f09f1b58389 205 uint32_t sdvco : 1;
MI 0:9f09f1b58389 206 uint32_t bs : 8;
MI 0:9f09f1b58389 207 uint32_t diva : 3;
MI 0:9f09f1b58389 208 uint32_t fb : 1;
MI 0:9f09f1b58389 209 uint32_t bs2 : 2;
MI 0:9f09f1b58389 210 uint32_t sdref : 1;
MI 0:9f09f1b58389 211 uint32_t sddiv : 1;
MI 0:9f09f1b58389 212 uint32_t sdldo : 1;
MI 0:9f09f1b58389 213 uint32_t reservered1: 3;
MI 0:9f09f1b58389 214 }bits;
MI 0:9f09f1b58389 215 };
MI 0:9f09f1b58389 216
MI 0:9f09f1b58389 217 ///Register 5 bits
MI 0:9f09f1b58389 218 union REG5_u
MI 0:9f09f1b58389 219 {
MI 0:9f09f1b58389 220 ///Access all bits
MI 0:9f09f1b58389 221 uint32_t all;
MI 0:9f09f1b58389 222
MI 0:9f09f1b58389 223 ///Access individual bits
MI 0:9f09f1b58389 224 struct BitField_s
MI 0:9f09f1b58389 225 {
MI 0:9f09f1b58389 226 uint32_t addr : 3;
MI 0:9f09f1b58389 227 uint32_t adcm : 3;
MI 0:9f09f1b58389 228 uint32_t adcs : 1;
MI 0:9f09f1b58389 229 uint32_t reserved1 : 11;
MI 0:9f09f1b58389 230 uint32_t mux : 1;
MI 0:9f09f1b58389 231 uint32_t reserved2 : 3;
MI 0:9f09f1b58389 232 uint32_t ld : 2;
MI 0:9f09f1b58389 233 uint32_t f01 : 1;
MI 0:9f09f1b58389 234 uint32_t sdpll : 1;
MI 0:9f09f1b58389 235 uint32_t reserved3 : 3;
MI 0:9f09f1b58389 236 uint32_t vas_dly : 2;
MI 0:9f09f1b58389 237 uint32_t reserved4 : 1;
MI 0:9f09f1b58389 238
MI 0:9f09f1b58389 239 }bits;
MI 0:9f09f1b58389 240 };
MI 0:9f09f1b58389 241
MI 0:9f09f1b58389 242 ///Register 6 bits
MI 0:9f09f1b58389 243 union REG6_u
MI 0:9f09f1b58389 244 {
MI 0:9f09f1b58389 245 ///Access all bits
MI 0:9f09f1b58389 246 uint32_t all;
MI 0:9f09f1b58389 247
MI 0:9f09f1b58389 248 ///Access individual bits
MI 0:9f09f1b58389 249 struct BitField_s
MI 0:9f09f1b58389 250 {
MI 0:9f09f1b58389 251 uint32_t addr : 3;
MI 0:9f09f1b58389 252 uint32_t v : 6;
MI 0:9f09f1b58389 253 uint32_t vasa : 1;
MI 0:9f09f1b58389 254 uint32_t reserved1 : 5;
MI 0:9f09f1b58389 255 uint32_t adcv : 1;
MI 0:9f09f1b58389 256 uint32_t adc : 7;
MI 0:9f09f1b58389 257 uint32_t por : 1;
MI 0:9f09f1b58389 258 uint32_t reserved2 : 4;
MI 0:9f09f1b58389 259 uint32_t die : 4;
MI 0:9f09f1b58389 260 }bits;
MI 0:9f09f1b58389 261 };
MI 0:9f09f1b58389 262
MI 0:9f09f1b58389 263 REG0_u reg0;
MI 0:9f09f1b58389 264 REG1_u reg1;
MI 0:9f09f1b58389 265 REG2_u reg2;
MI 0:9f09f1b58389 266 REG3_u reg3;
MI 0:9f09f1b58389 267 REG4_u reg4;
MI 0:9f09f1b58389 268 REG5_u reg5;
MI 0:9f09f1b58389 269 REG6_u reg6;
MI 1:40b397b31d13 270
MI 0:9f09f1b58389 271 float f_reference;
MI 0:9f09f1b58389 272
MI 0:9f09f1b58389 273 ///@brief MAX2871 Constructor
MI 0:9f09f1b58389 274 ///@param spiBus - Reference to spi interface
MI 0:9f09f1b58389 275 ///@param le - Pin used for latch enable
MI 0:9f09f1b58389 276 MAX2871(SPI &spiBus, PinName le);
MI 0:9f09f1b58389 277
MI 0:9f09f1b58389 278 ///@brief MAX2871 Destructor
MI 0:9f09f1b58389 279 ~MAX2871();
MI 0:9f09f1b58389 280
MI 0:9f09f1b58389 281 ///@brief Write given register.\n
MI 0:9f09f1b58389 282 ///
MI 0:9f09f1b58389 283 ///On Entry:
MI 0:9f09f1b58389 284 ///@param[in] reg - Register to write
MI 0:9f09f1b58389 285 ///@param[in] data - Data to write
MI 0:9f09f1b58389 286 ///
MI 0:9f09f1b58389 287 ///@returns None
MI 0:9f09f1b58389 288 void writeRegister(const uint32_t data);
MI 0:9f09f1b58389 289
MI 0:9f09f1b58389 290 ///@brief Read Register 6 and update reg6 member.\n
MI 0:9f09f1b58389 291 ///
MI 0:9f09f1b58389 292 ///@returns None
MI 0:9f09f1b58389 293 void readRegister6();
MI 0:9f09f1b58389 294
MI 0:9f09f1b58389 295 ///@brief Update all registers.\n
MI 0:9f09f1b58389 296 ///
MI 0:9f09f1b58389 297 ///@returns None
MI 0:9f09f1b58389 298 void update();
MI 0:9f09f1b58389 299
MI 0:9f09f1b58389 300 ///@brief Updates MAX2871 settings to achieve frequency output.\n
MI 0:9f09f1b58389 301 ///
MI 0:9f09f1b58389 302 ///On Entry:
MI 0:9f09f1b58389 303 ///@param[in] freq - Frequency in MHz
MI 0:9f09f1b58389 304 ///
MI 0:9f09f1b58389 305 ///@returns None
MI 0:9f09f1b58389 306 void frequency(const float freq);
MI 0:9f09f1b58389 307
MI 0:9f09f1b58389 308 private:
MI 0:9f09f1b58389 309
MI 0:9f09f1b58389 310 SPI &m_spiBus;
MI 0:9f09f1b58389 311 DigitalOut m_le;
MI 0:9f09f1b58389 312 };
MI 0:9f09f1b58389 313
MI 0:9f09f1b58389 314 #endif /* _MAX2871_H_ */
MI 0:9f09f1b58389 315