mbed-lite-test - test

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test

TARGET_NRF51_MICROBIT/core_cm7.h@1:a7c51b5e0534, 2016-04-07 (annotated)

Committer:: jamesadevine
Date:: Thu Apr 07 17:50:29 2016 +0000
Revision:: 1:a7c51b5e0534
Parent:: 0:e1a608bb55e8

Added correct nrf51.h ; Added scatter file.

Who changed what in which revision?

User	Revision	Line number	New contents of line
jamesadevine	0:e1a608bb55e8	1	/************************************************************************//
jamesadevine	0:e1a608bb55e8	2	* @file core_cm7.h
jamesadevine	0:e1a608bb55e8	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
jamesadevine	0:e1a608bb55e8	4	* @version V4.10
jamesadevine	0:e1a608bb55e8	5	* @date 18. March 2015
jamesadevine	0:e1a608bb55e8	6	*
jamesadevine	0:e1a608bb55e8	7	* @note
jamesadevine	0:e1a608bb55e8	8	*
jamesadevine	0:e1a608bb55e8	9	******************************************************************************/
jamesadevine	0:e1a608bb55e8	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
jamesadevine	0:e1a608bb55e8	11
jamesadevine	0:e1a608bb55e8	12	All rights reserved.
jamesadevine	0:e1a608bb55e8	13	Redistribution and use in source and binary forms, with or without
jamesadevine	0:e1a608bb55e8	14	modification, are permitted provided that the following conditions are met:
jamesadevine	0:e1a608bb55e8	15	- Redistributions of source code must retain the above copyright
jamesadevine	0:e1a608bb55e8	16	notice, this list of conditions and the following disclaimer.
jamesadevine	0:e1a608bb55e8	17	- Redistributions in binary form must reproduce the above copyright
jamesadevine	0:e1a608bb55e8	18	notice, this list of conditions and the following disclaimer in the
jamesadevine	0:e1a608bb55e8	19	documentation and/or other materials provided with the distribution.
jamesadevine	0:e1a608bb55e8	20	- Neither the name of ARM nor the names of its contributors may be used
jamesadevine	0:e1a608bb55e8	21	to endorse or promote products derived from this software without
jamesadevine	0:e1a608bb55e8	22	specific prior written permission.
jamesadevine	0:e1a608bb55e8	23	*
jamesadevine	0:e1a608bb55e8	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jamesadevine	0:e1a608bb55e8	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jamesadevine	0:e1a608bb55e8	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jamesadevine	0:e1a608bb55e8	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jamesadevine	0:e1a608bb55e8	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jamesadevine	0:e1a608bb55e8	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jamesadevine	0:e1a608bb55e8	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jamesadevine	0:e1a608bb55e8	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jamesadevine	0:e1a608bb55e8	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jamesadevine	0:e1a608bb55e8	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jamesadevine	0:e1a608bb55e8	34	POSSIBILITY OF SUCH DAMAGE.
jamesadevine	0:e1a608bb55e8	35	---------------------------------------------------------------------------*/
jamesadevine	0:e1a608bb55e8	36
jamesadevine	0:e1a608bb55e8	37
jamesadevine	0:e1a608bb55e8	38	#if defined ( __ICCARM__ )
jamesadevine	0:e1a608bb55e8	39	#pragma system_include /* treat file as system include file for MISRA check */
jamesadevine	0:e1a608bb55e8	40	#endif
jamesadevine	0:e1a608bb55e8	41
jamesadevine	0:e1a608bb55e8	42	#ifndef __CORE_CM7_H_GENERIC
jamesadevine	0:e1a608bb55e8	43	#define __CORE_CM7_H_GENERIC
jamesadevine	0:e1a608bb55e8	44
jamesadevine	0:e1a608bb55e8	45	#ifdef __cplusplus
jamesadevine	0:e1a608bb55e8	46	extern "C" {
jamesadevine	0:e1a608bb55e8	47	#endif
jamesadevine	0:e1a608bb55e8	48
jamesadevine	0:e1a608bb55e8	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jamesadevine	0:e1a608bb55e8	50	CMSIS violates the following MISRA-C:2004 rules:
jamesadevine	0:e1a608bb55e8	51
jamesadevine	0:e1a608bb55e8	52	\li Required Rule 8.5, object/function definition in header file.<br>
jamesadevine	0:e1a608bb55e8	53	Function definitions in header files are used to allow 'inlining'.
jamesadevine	0:e1a608bb55e8	54
jamesadevine	0:e1a608bb55e8	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jamesadevine	0:e1a608bb55e8	56	Unions are used for effective representation of core registers.
jamesadevine	0:e1a608bb55e8	57
jamesadevine	0:e1a608bb55e8	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
jamesadevine	0:e1a608bb55e8	59	Function-like macros are used to allow more efficient code.
jamesadevine	0:e1a608bb55e8	60	*/
jamesadevine	0:e1a608bb55e8	61
jamesadevine	0:e1a608bb55e8	62
jamesadevine	0:e1a608bb55e8	63	/*******************************************************************************
jamesadevine	0:e1a608bb55e8	64	* CMSIS definitions
jamesadevine	0:e1a608bb55e8	65	******************************************************************************/
jamesadevine	0:e1a608bb55e8	66	/** \ingroup Cortex_M7
jamesadevine	0:e1a608bb55e8	67	@{
jamesadevine	0:e1a608bb55e8	68	*/
jamesadevine	0:e1a608bb55e8	69
jamesadevine	0:e1a608bb55e8	70	/* CMSIS CM7 definitions */
jamesadevine	0:e1a608bb55e8	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
jamesadevine	0:e1a608bb55e8	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
jamesadevine	0:e1a608bb55e8	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
jamesadevine	0:e1a608bb55e8	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
jamesadevine	0:e1a608bb55e8	75
jamesadevine	0:e1a608bb55e8	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
jamesadevine	0:e1a608bb55e8	77
jamesadevine	0:e1a608bb55e8	78
jamesadevine	0:e1a608bb55e8	79	#if defined ( __CC_ARM )
jamesadevine	0:e1a608bb55e8	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
jamesadevine	0:e1a608bb55e8	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
jamesadevine	0:e1a608bb55e8	82	#define __STATIC_INLINE static __inline
jamesadevine	0:e1a608bb55e8	83
jamesadevine	0:e1a608bb55e8	84	#elif defined ( __GNUC__ )
jamesadevine	0:e1a608bb55e8	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
jamesadevine	0:e1a608bb55e8	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
jamesadevine	0:e1a608bb55e8	87	#define __STATIC_INLINE static inline
jamesadevine	0:e1a608bb55e8	88
jamesadevine	0:e1a608bb55e8	89	#elif defined ( __ICCARM__ )
jamesadevine	0:e1a608bb55e8	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
jamesadevine	0:e1a608bb55e8	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
jamesadevine	0:e1a608bb55e8	92	#define __STATIC_INLINE static inline
jamesadevine	0:e1a608bb55e8	93
jamesadevine	0:e1a608bb55e8	94	#elif defined ( __TMS470__ )
jamesadevine	0:e1a608bb55e8	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
jamesadevine	0:e1a608bb55e8	96	#define __STATIC_INLINE static inline
jamesadevine	0:e1a608bb55e8	97
jamesadevine	0:e1a608bb55e8	98	#elif defined ( __TASKING__ )
jamesadevine	0:e1a608bb55e8	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
jamesadevine	0:e1a608bb55e8	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
jamesadevine	0:e1a608bb55e8	101	#define __STATIC_INLINE static inline
jamesadevine	0:e1a608bb55e8	102
jamesadevine	0:e1a608bb55e8	103	#elif defined ( __CSMC__ )
jamesadevine	0:e1a608bb55e8	104	#define __packed
jamesadevine	0:e1a608bb55e8	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
jamesadevine	0:e1a608bb55e8	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
jamesadevine	0:e1a608bb55e8	107	#define __STATIC_INLINE static inline
jamesadevine	0:e1a608bb55e8	108
jamesadevine	0:e1a608bb55e8	109	#endif
jamesadevine	0:e1a608bb55e8	110
jamesadevine	0:e1a608bb55e8	111	/** __FPU_USED indicates whether an FPU is used or not.
jamesadevine	0:e1a608bb55e8	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
jamesadevine	0:e1a608bb55e8	113	*/
jamesadevine	0:e1a608bb55e8	114	#if defined ( __CC_ARM )
jamesadevine	0:e1a608bb55e8	115	#if defined __TARGET_FPU_VFP
jamesadevine	0:e1a608bb55e8	116	#if (__FPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	117	#define __FPU_USED 1
jamesadevine	0:e1a608bb55e8	118	#else
jamesadevine	0:e1a608bb55e8	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine	0:e1a608bb55e8	120	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	121	#endif
jamesadevine	0:e1a608bb55e8	122	#else
jamesadevine	0:e1a608bb55e8	123	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	124	#endif
jamesadevine	0:e1a608bb55e8	125
jamesadevine	0:e1a608bb55e8	126	#elif defined ( __GNUC__ )
jamesadevine	0:e1a608bb55e8	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
jamesadevine	0:e1a608bb55e8	128	#if (__FPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	129	#define __FPU_USED 1
jamesadevine	0:e1a608bb55e8	130	#else
jamesadevine	0:e1a608bb55e8	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine	0:e1a608bb55e8	132	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	133	#endif
jamesadevine	0:e1a608bb55e8	134	#else
jamesadevine	0:e1a608bb55e8	135	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	136	#endif
jamesadevine	0:e1a608bb55e8	137
jamesadevine	0:e1a608bb55e8	138	#elif defined ( __ICCARM__ )
jamesadevine	0:e1a608bb55e8	139	#if defined __ARMVFP__
jamesadevine	0:e1a608bb55e8	140	#if (__FPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	141	#define __FPU_USED 1
jamesadevine	0:e1a608bb55e8	142	#else
jamesadevine	0:e1a608bb55e8	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine	0:e1a608bb55e8	144	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	145	#endif
jamesadevine	0:e1a608bb55e8	146	#else
jamesadevine	0:e1a608bb55e8	147	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	148	#endif
jamesadevine	0:e1a608bb55e8	149
jamesadevine	0:e1a608bb55e8	150	#elif defined ( __TMS470__ )
jamesadevine	0:e1a608bb55e8	151	#if defined __TI_VFP_SUPPORT__
jamesadevine	0:e1a608bb55e8	152	#if (__FPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	153	#define __FPU_USED 1
jamesadevine	0:e1a608bb55e8	154	#else
jamesadevine	0:e1a608bb55e8	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine	0:e1a608bb55e8	156	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	157	#endif
jamesadevine	0:e1a608bb55e8	158	#else
jamesadevine	0:e1a608bb55e8	159	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	160	#endif
jamesadevine	0:e1a608bb55e8	161
jamesadevine	0:e1a608bb55e8	162	#elif defined ( __TASKING__ )
jamesadevine	0:e1a608bb55e8	163	#if defined __FPU_VFP__
jamesadevine	0:e1a608bb55e8	164	#if (__FPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	165	#define __FPU_USED 1
jamesadevine	0:e1a608bb55e8	166	#else
jamesadevine	0:e1a608bb55e8	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine	0:e1a608bb55e8	168	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	169	#endif
jamesadevine	0:e1a608bb55e8	170	#else
jamesadevine	0:e1a608bb55e8	171	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	172	#endif
jamesadevine	0:e1a608bb55e8	173
jamesadevine	0:e1a608bb55e8	174	#elif defined ( __CSMC__ ) /* Cosmic */
jamesadevine	0:e1a608bb55e8	175	#if ( __CSMC__ & 0x400) // FPU present for parser
jamesadevine	0:e1a608bb55e8	176	#if (__FPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	177	#define __FPU_USED 1
jamesadevine	0:e1a608bb55e8	178	#else
jamesadevine	0:e1a608bb55e8	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jamesadevine	0:e1a608bb55e8	180	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	181	#endif
jamesadevine	0:e1a608bb55e8	182	#else
jamesadevine	0:e1a608bb55e8	183	#define __FPU_USED 0
jamesadevine	0:e1a608bb55e8	184	#endif
jamesadevine	0:e1a608bb55e8	185	#endif
jamesadevine	0:e1a608bb55e8	186
jamesadevine	0:e1a608bb55e8	187	#include <stdint.h> /* standard types definitions */
jamesadevine	0:e1a608bb55e8	188	#include <core_cmInstr.h> /* Core Instruction Access */
jamesadevine	0:e1a608bb55e8	189	#include <core_cmFunc.h> /* Core Function Access */
jamesadevine	0:e1a608bb55e8	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
jamesadevine	0:e1a608bb55e8	191
jamesadevine	0:e1a608bb55e8	192	#ifdef __cplusplus
jamesadevine	0:e1a608bb55e8	193	}
jamesadevine	0:e1a608bb55e8	194	#endif
jamesadevine	0:e1a608bb55e8	195
jamesadevine	0:e1a608bb55e8	196	#endif /* __CORE_CM7_H_GENERIC */
jamesadevine	0:e1a608bb55e8	197
jamesadevine	0:e1a608bb55e8	198	#ifndef __CMSIS_GENERIC
jamesadevine	0:e1a608bb55e8	199
jamesadevine	0:e1a608bb55e8	200	#ifndef __CORE_CM7_H_DEPENDANT
jamesadevine	0:e1a608bb55e8	201	#define __CORE_CM7_H_DEPENDANT
jamesadevine	0:e1a608bb55e8	202
jamesadevine	0:e1a608bb55e8	203	#ifdef __cplusplus
jamesadevine	0:e1a608bb55e8	204	extern "C" {
jamesadevine	0:e1a608bb55e8	205	#endif
jamesadevine	0:e1a608bb55e8	206
jamesadevine	0:e1a608bb55e8	207	/* check device defines and use defaults */
jamesadevine	0:e1a608bb55e8	208	#if defined __CHECK_DEVICE_DEFINES
jamesadevine	0:e1a608bb55e8	209	#ifndef __CM7_REV
jamesadevine	0:e1a608bb55e8	210	#define __CM7_REV 0x0000
jamesadevine	0:e1a608bb55e8	211	#warning "__CM7_REV not defined in device header file; using default!"
jamesadevine	0:e1a608bb55e8	212	#endif
jamesadevine	0:e1a608bb55e8	213
jamesadevine	0:e1a608bb55e8	214	#ifndef __FPU_PRESENT
jamesadevine	0:e1a608bb55e8	215	#define __FPU_PRESENT 0
jamesadevine	0:e1a608bb55e8	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
jamesadevine	0:e1a608bb55e8	217	#endif
jamesadevine	0:e1a608bb55e8	218
jamesadevine	0:e1a608bb55e8	219	#ifndef __MPU_PRESENT
jamesadevine	0:e1a608bb55e8	220	#define __MPU_PRESENT 0
jamesadevine	0:e1a608bb55e8	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
jamesadevine	0:e1a608bb55e8	222	#endif
jamesadevine	0:e1a608bb55e8	223
jamesadevine	0:e1a608bb55e8	224	#ifndef __ICACHE_PRESENT
jamesadevine	0:e1a608bb55e8	225	#define __ICACHE_PRESENT 0
jamesadevine	0:e1a608bb55e8	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
jamesadevine	0:e1a608bb55e8	227	#endif
jamesadevine	0:e1a608bb55e8	228
jamesadevine	0:e1a608bb55e8	229	#ifndef __DCACHE_PRESENT
jamesadevine	0:e1a608bb55e8	230	#define __DCACHE_PRESENT 0
jamesadevine	0:e1a608bb55e8	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
jamesadevine	0:e1a608bb55e8	232	#endif
jamesadevine	0:e1a608bb55e8	233
jamesadevine	0:e1a608bb55e8	234	#ifndef __DTCM_PRESENT
jamesadevine	0:e1a608bb55e8	235	#define __DTCM_PRESENT 0
jamesadevine	0:e1a608bb55e8	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
jamesadevine	0:e1a608bb55e8	237	#endif
jamesadevine	0:e1a608bb55e8	238
jamesadevine	0:e1a608bb55e8	239	#ifndef __NVIC_PRIO_BITS
jamesadevine	0:e1a608bb55e8	240	#define __NVIC_PRIO_BITS 3
jamesadevine	0:e1a608bb55e8	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jamesadevine	0:e1a608bb55e8	242	#endif
jamesadevine	0:e1a608bb55e8	243
jamesadevine	0:e1a608bb55e8	244	#ifndef __Vendor_SysTickConfig
jamesadevine	0:e1a608bb55e8	245	#define __Vendor_SysTickConfig 0
jamesadevine	0:e1a608bb55e8	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jamesadevine	0:e1a608bb55e8	247	#endif
jamesadevine	0:e1a608bb55e8	248	#endif
jamesadevine	0:e1a608bb55e8	249
jamesadevine	0:e1a608bb55e8	250	/* IO definitions (access restrictions to peripheral registers) */
jamesadevine	0:e1a608bb55e8	251	/**
jamesadevine	0:e1a608bb55e8	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
jamesadevine	0:e1a608bb55e8	253
jamesadevine	0:e1a608bb55e8	254	<strong>IO Type Qualifiers</strong> are used
jamesadevine	0:e1a608bb55e8	255	\li to specify the access to peripheral variables.
jamesadevine	0:e1a608bb55e8	256	\li for automatic generation of peripheral register debug information.
jamesadevine	0:e1a608bb55e8	257	*/
jamesadevine	0:e1a608bb55e8	258	#ifdef __cplusplus
jamesadevine	0:e1a608bb55e8	259	#define __I volatile /!< Defines 'read only' permissions /
jamesadevine	0:e1a608bb55e8	260	#else
jamesadevine	0:e1a608bb55e8	261	#define __I volatile const /!< Defines 'read only' permissions /
jamesadevine	0:e1a608bb55e8	262	#endif
jamesadevine	0:e1a608bb55e8	263	#define __O volatile /!< Defines 'write only' permissions /
jamesadevine	0:e1a608bb55e8	264	#define __IO volatile /!< Defines 'read / write' permissions /
jamesadevine	0:e1a608bb55e8	265
jamesadevine	0:e1a608bb55e8	266	/@} end of group Cortex_M7 /
jamesadevine	0:e1a608bb55e8	267
jamesadevine	0:e1a608bb55e8	268
jamesadevine	0:e1a608bb55e8	269
jamesadevine	0:e1a608bb55e8	270	/*******************************************************************************
jamesadevine	0:e1a608bb55e8	271	* Register Abstraction
jamesadevine	0:e1a608bb55e8	272	Core Register contain:
jamesadevine	0:e1a608bb55e8	273	- Core Register
jamesadevine	0:e1a608bb55e8	274	- Core NVIC Register
jamesadevine	0:e1a608bb55e8	275	- Core SCB Register
jamesadevine	0:e1a608bb55e8	276	- Core SysTick Register
jamesadevine	0:e1a608bb55e8	277	- Core Debug Register
jamesadevine	0:e1a608bb55e8	278	- Core MPU Register
jamesadevine	0:e1a608bb55e8	279	- Core FPU Register
jamesadevine	0:e1a608bb55e8	280	******************************************************************************/
jamesadevine	0:e1a608bb55e8	281	/** \defgroup CMSIS_core_register Defines and Type Definitions
jamesadevine	0:e1a608bb55e8	282	\brief Type definitions and defines for Cortex-M processor based devices.
jamesadevine	0:e1a608bb55e8	283	*/
jamesadevine	0:e1a608bb55e8	284
jamesadevine	0:e1a608bb55e8	285	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	286	\defgroup CMSIS_CORE Status and Control Registers
jamesadevine	0:e1a608bb55e8	287	\brief Core Register type definitions.
jamesadevine	0:e1a608bb55e8	288	@{
jamesadevine	0:e1a608bb55e8	289	*/
jamesadevine	0:e1a608bb55e8	290
jamesadevine	0:e1a608bb55e8	291	/** \brief Union type to access the Application Program Status Register (APSR).
jamesadevine	0:e1a608bb55e8	292	*/
jamesadevine	0:e1a608bb55e8	293	typedef union
jamesadevine	0:e1a608bb55e8	294	{
jamesadevine	0:e1a608bb55e8	295	struct
jamesadevine	0:e1a608bb55e8	296	{
jamesadevine	0:e1a608bb55e8	297	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
jamesadevine	0:e1a608bb55e8	298	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
jamesadevine	0:e1a608bb55e8	299	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
jamesadevine	0:e1a608bb55e8	300	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
jamesadevine	0:e1a608bb55e8	301	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
jamesadevine	0:e1a608bb55e8	302	uint32_t C:1; /!< bit: 29 Carry condition code flag /
jamesadevine	0:e1a608bb55e8	303	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
jamesadevine	0:e1a608bb55e8	304	uint32_t N:1; /!< bit: 31 Negative condition code flag /
jamesadevine	0:e1a608bb55e8	305	} b; /!< Structure used for bit access /
jamesadevine	0:e1a608bb55e8	306	uint32_t w; /!< Type used for word access /
jamesadevine	0:e1a608bb55e8	307	} APSR_Type;
jamesadevine	0:e1a608bb55e8	308
jamesadevine	0:e1a608bb55e8	309	/* APSR Register Definitions */
jamesadevine	0:e1a608bb55e8	310	#define APSR_N_Pos 31 /!< APSR: N Position /
jamesadevine	0:e1a608bb55e8	311	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
jamesadevine	0:e1a608bb55e8	312
jamesadevine	0:e1a608bb55e8	313	#define APSR_Z_Pos 30 /!< APSR: Z Position /
jamesadevine	0:e1a608bb55e8	314	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
jamesadevine	0:e1a608bb55e8	315
jamesadevine	0:e1a608bb55e8	316	#define APSR_C_Pos 29 /!< APSR: C Position /
jamesadevine	0:e1a608bb55e8	317	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
jamesadevine	0:e1a608bb55e8	318
jamesadevine	0:e1a608bb55e8	319	#define APSR_V_Pos 28 /!< APSR: V Position /
jamesadevine	0:e1a608bb55e8	320	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
jamesadevine	0:e1a608bb55e8	321
jamesadevine	0:e1a608bb55e8	322	#define APSR_Q_Pos 27 /!< APSR: Q Position /
jamesadevine	0:e1a608bb55e8	323	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
jamesadevine	0:e1a608bb55e8	324
jamesadevine	0:e1a608bb55e8	325	#define APSR_GE_Pos 16 /!< APSR: GE Position /
jamesadevine	0:e1a608bb55e8	326	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
jamesadevine	0:e1a608bb55e8	327
jamesadevine	0:e1a608bb55e8	328
jamesadevine	0:e1a608bb55e8	329	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
jamesadevine	0:e1a608bb55e8	330	*/
jamesadevine	0:e1a608bb55e8	331	typedef union
jamesadevine	0:e1a608bb55e8	332	{
jamesadevine	0:e1a608bb55e8	333	struct
jamesadevine	0:e1a608bb55e8	334	{
jamesadevine	0:e1a608bb55e8	335	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
jamesadevine	0:e1a608bb55e8	336	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
jamesadevine	0:e1a608bb55e8	337	} b; /!< Structure used for bit access /
jamesadevine	0:e1a608bb55e8	338	uint32_t w; /!< Type used for word access /
jamesadevine	0:e1a608bb55e8	339	} IPSR_Type;
jamesadevine	0:e1a608bb55e8	340
jamesadevine	0:e1a608bb55e8	341	/* IPSR Register Definitions */
jamesadevine	0:e1a608bb55e8	342	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
jamesadevine	0:e1a608bb55e8	343	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
jamesadevine	0:e1a608bb55e8	344
jamesadevine	0:e1a608bb55e8	345
jamesadevine	0:e1a608bb55e8	346	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jamesadevine	0:e1a608bb55e8	347	*/
jamesadevine	0:e1a608bb55e8	348	typedef union
jamesadevine	0:e1a608bb55e8	349	{
jamesadevine	0:e1a608bb55e8	350	struct
jamesadevine	0:e1a608bb55e8	351	{
jamesadevine	0:e1a608bb55e8	352	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
jamesadevine	0:e1a608bb55e8	353	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
jamesadevine	0:e1a608bb55e8	354	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
jamesadevine	0:e1a608bb55e8	355	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
jamesadevine	0:e1a608bb55e8	356	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
jamesadevine	0:e1a608bb55e8	357	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
jamesadevine	0:e1a608bb55e8	358	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
jamesadevine	0:e1a608bb55e8	359	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
jamesadevine	0:e1a608bb55e8	360	uint32_t C:1; /!< bit: 29 Carry condition code flag /
jamesadevine	0:e1a608bb55e8	361	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
jamesadevine	0:e1a608bb55e8	362	uint32_t N:1; /!< bit: 31 Negative condition code flag /
jamesadevine	0:e1a608bb55e8	363	} b; /!< Structure used for bit access /
jamesadevine	0:e1a608bb55e8	364	uint32_t w; /!< Type used for word access /
jamesadevine	0:e1a608bb55e8	365	} xPSR_Type;
jamesadevine	0:e1a608bb55e8	366
jamesadevine	0:e1a608bb55e8	367	/* xPSR Register Definitions */
jamesadevine	0:e1a608bb55e8	368	#define xPSR_N_Pos 31 /!< xPSR: N Position /
jamesadevine	0:e1a608bb55e8	369	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
jamesadevine	0:e1a608bb55e8	370
jamesadevine	0:e1a608bb55e8	371	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
jamesadevine	0:e1a608bb55e8	372	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
jamesadevine	0:e1a608bb55e8	373
jamesadevine	0:e1a608bb55e8	374	#define xPSR_C_Pos 29 /!< xPSR: C Position /
jamesadevine	0:e1a608bb55e8	375	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
jamesadevine	0:e1a608bb55e8	376
jamesadevine	0:e1a608bb55e8	377	#define xPSR_V_Pos 28 /!< xPSR: V Position /
jamesadevine	0:e1a608bb55e8	378	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
jamesadevine	0:e1a608bb55e8	379
jamesadevine	0:e1a608bb55e8	380	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
jamesadevine	0:e1a608bb55e8	381	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
jamesadevine	0:e1a608bb55e8	382
jamesadevine	0:e1a608bb55e8	383	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
jamesadevine	0:e1a608bb55e8	384	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
jamesadevine	0:e1a608bb55e8	385
jamesadevine	0:e1a608bb55e8	386	#define xPSR_T_Pos 24 /!< xPSR: T Position /
jamesadevine	0:e1a608bb55e8	387	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
jamesadevine	0:e1a608bb55e8	388
jamesadevine	0:e1a608bb55e8	389	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
jamesadevine	0:e1a608bb55e8	390	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
jamesadevine	0:e1a608bb55e8	391
jamesadevine	0:e1a608bb55e8	392	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
jamesadevine	0:e1a608bb55e8	393	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
jamesadevine	0:e1a608bb55e8	394
jamesadevine	0:e1a608bb55e8	395
jamesadevine	0:e1a608bb55e8	396	/** \brief Union type to access the Control Registers (CONTROL).
jamesadevine	0:e1a608bb55e8	397	*/
jamesadevine	0:e1a608bb55e8	398	typedef union
jamesadevine	0:e1a608bb55e8	399	{
jamesadevine	0:e1a608bb55e8	400	struct
jamesadevine	0:e1a608bb55e8	401	{
jamesadevine	0:e1a608bb55e8	402	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
jamesadevine	0:e1a608bb55e8	403	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
jamesadevine	0:e1a608bb55e8	404	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
jamesadevine	0:e1a608bb55e8	405	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
jamesadevine	0:e1a608bb55e8	406	} b; /!< Structure used for bit access /
jamesadevine	0:e1a608bb55e8	407	uint32_t w; /!< Type used for word access /
jamesadevine	0:e1a608bb55e8	408	} CONTROL_Type;
jamesadevine	0:e1a608bb55e8	409
jamesadevine	0:e1a608bb55e8	410	/* CONTROL Register Definitions */
jamesadevine	0:e1a608bb55e8	411	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
jamesadevine	0:e1a608bb55e8	412	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
jamesadevine	0:e1a608bb55e8	413
jamesadevine	0:e1a608bb55e8	414	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
jamesadevine	0:e1a608bb55e8	415	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
jamesadevine	0:e1a608bb55e8	416
jamesadevine	0:e1a608bb55e8	417	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
jamesadevine	0:e1a608bb55e8	418	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
jamesadevine	0:e1a608bb55e8	419
jamesadevine	0:e1a608bb55e8	420	/@} end of group CMSIS_CORE /
jamesadevine	0:e1a608bb55e8	421
jamesadevine	0:e1a608bb55e8	422
jamesadevine	0:e1a608bb55e8	423	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	424	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jamesadevine	0:e1a608bb55e8	425	\brief Type definitions for the NVIC Registers
jamesadevine	0:e1a608bb55e8	426	@{
jamesadevine	0:e1a608bb55e8	427	*/
jamesadevine	0:e1a608bb55e8	428
jamesadevine	0:e1a608bb55e8	429	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jamesadevine	0:e1a608bb55e8	430	*/
jamesadevine	0:e1a608bb55e8	431	typedef struct
jamesadevine	0:e1a608bb55e8	432	{
jamesadevine	0:e1a608bb55e8	433	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
jamesadevine	0:e1a608bb55e8	434	uint32_t RESERVED0[24];
jamesadevine	0:e1a608bb55e8	435	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
jamesadevine	0:e1a608bb55e8	436	uint32_t RSERVED1[24];
jamesadevine	0:e1a608bb55e8	437	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
jamesadevine	0:e1a608bb55e8	438	uint32_t RESERVED2[24];
jamesadevine	0:e1a608bb55e8	439	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
jamesadevine	0:e1a608bb55e8	440	uint32_t RESERVED3[24];
jamesadevine	0:e1a608bb55e8	441	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
jamesadevine	0:e1a608bb55e8	442	uint32_t RESERVED4[56];
jamesadevine	0:e1a608bb55e8	443	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
jamesadevine	0:e1a608bb55e8	444	uint32_t RESERVED5[644];
jamesadevine	0:e1a608bb55e8	445	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
jamesadevine	0:e1a608bb55e8	446	} NVIC_Type;
jamesadevine	0:e1a608bb55e8	447
jamesadevine	0:e1a608bb55e8	448	/* Software Triggered Interrupt Register Definitions */
jamesadevine	0:e1a608bb55e8	449	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
jamesadevine	0:e1a608bb55e8	450	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
jamesadevine	0:e1a608bb55e8	451
jamesadevine	0:e1a608bb55e8	452	/@} end of group CMSIS_NVIC /
jamesadevine	0:e1a608bb55e8	453
jamesadevine	0:e1a608bb55e8	454
jamesadevine	0:e1a608bb55e8	455	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	456	\defgroup CMSIS_SCB System Control Block (SCB)
jamesadevine	0:e1a608bb55e8	457	\brief Type definitions for the System Control Block Registers
jamesadevine	0:e1a608bb55e8	458	@{
jamesadevine	0:e1a608bb55e8	459	*/
jamesadevine	0:e1a608bb55e8	460
jamesadevine	0:e1a608bb55e8	461	/** \brief Structure type to access the System Control Block (SCB).
jamesadevine	0:e1a608bb55e8	462	*/
jamesadevine	0:e1a608bb55e8	463	typedef struct
jamesadevine	0:e1a608bb55e8	464	{
jamesadevine	0:e1a608bb55e8	465	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
jamesadevine	0:e1a608bb55e8	466	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
jamesadevine	0:e1a608bb55e8	467	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
jamesadevine	0:e1a608bb55e8	468	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
jamesadevine	0:e1a608bb55e8	469	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
jamesadevine	0:e1a608bb55e8	470	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
jamesadevine	0:e1a608bb55e8	471	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
jamesadevine	0:e1a608bb55e8	472	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
jamesadevine	0:e1a608bb55e8	473	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
jamesadevine	0:e1a608bb55e8	474	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
jamesadevine	0:e1a608bb55e8	475	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
jamesadevine	0:e1a608bb55e8	476	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
jamesadevine	0:e1a608bb55e8	477	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
jamesadevine	0:e1a608bb55e8	478	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
jamesadevine	0:e1a608bb55e8	479	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
jamesadevine	0:e1a608bb55e8	480	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
jamesadevine	0:e1a608bb55e8	481	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
jamesadevine	0:e1a608bb55e8	482	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
jamesadevine	0:e1a608bb55e8	483	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
jamesadevine	0:e1a608bb55e8	484	uint32_t RESERVED0[1];
jamesadevine	0:e1a608bb55e8	485	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
jamesadevine	0:e1a608bb55e8	486	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
jamesadevine	0:e1a608bb55e8	487	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
jamesadevine	0:e1a608bb55e8	488	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
jamesadevine	0:e1a608bb55e8	489	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
jamesadevine	0:e1a608bb55e8	490	uint32_t RESERVED3[93];
jamesadevine	0:e1a608bb55e8	491	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
jamesadevine	0:e1a608bb55e8	492	uint32_t RESERVED4[15];
jamesadevine	0:e1a608bb55e8	493	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
jamesadevine	0:e1a608bb55e8	494	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
jamesadevine	0:e1a608bb55e8	495	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
jamesadevine	0:e1a608bb55e8	496	uint32_t RESERVED5[1];
jamesadevine	0:e1a608bb55e8	497	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
jamesadevine	0:e1a608bb55e8	498	uint32_t RESERVED6[1];
jamesadevine	0:e1a608bb55e8	499	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
jamesadevine	0:e1a608bb55e8	500	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
jamesadevine	0:e1a608bb55e8	501	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
jamesadevine	0:e1a608bb55e8	502	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
jamesadevine	0:e1a608bb55e8	503	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
jamesadevine	0:e1a608bb55e8	504	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
jamesadevine	0:e1a608bb55e8	505	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
jamesadevine	0:e1a608bb55e8	506	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
jamesadevine	0:e1a608bb55e8	507	uint32_t RESERVED7[6];
jamesadevine	0:e1a608bb55e8	508	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
jamesadevine	0:e1a608bb55e8	509	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
jamesadevine	0:e1a608bb55e8	510	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
jamesadevine	0:e1a608bb55e8	511	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
jamesadevine	0:e1a608bb55e8	512	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
jamesadevine	0:e1a608bb55e8	513	uint32_t RESERVED8[1];
jamesadevine	0:e1a608bb55e8	514	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
jamesadevine	0:e1a608bb55e8	515	} SCB_Type;
jamesadevine	0:e1a608bb55e8	516
jamesadevine	0:e1a608bb55e8	517	/* SCB CPUID Register Definitions */
jamesadevine	0:e1a608bb55e8	518	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
jamesadevine	0:e1a608bb55e8	519	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
jamesadevine	0:e1a608bb55e8	520
jamesadevine	0:e1a608bb55e8	521	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
jamesadevine	0:e1a608bb55e8	522	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
jamesadevine	0:e1a608bb55e8	523
jamesadevine	0:e1a608bb55e8	524	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
jamesadevine	0:e1a608bb55e8	525	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
jamesadevine	0:e1a608bb55e8	526
jamesadevine	0:e1a608bb55e8	527	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
jamesadevine	0:e1a608bb55e8	528	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
jamesadevine	0:e1a608bb55e8	529
jamesadevine	0:e1a608bb55e8	530	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
jamesadevine	0:e1a608bb55e8	531	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
jamesadevine	0:e1a608bb55e8	532
jamesadevine	0:e1a608bb55e8	533	/* SCB Interrupt Control State Register Definitions */
jamesadevine	0:e1a608bb55e8	534	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
jamesadevine	0:e1a608bb55e8	535	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
jamesadevine	0:e1a608bb55e8	536
jamesadevine	0:e1a608bb55e8	537	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
jamesadevine	0:e1a608bb55e8	538	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
jamesadevine	0:e1a608bb55e8	539
jamesadevine	0:e1a608bb55e8	540	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
jamesadevine	0:e1a608bb55e8	541	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
jamesadevine	0:e1a608bb55e8	542
jamesadevine	0:e1a608bb55e8	543	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
jamesadevine	0:e1a608bb55e8	544	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
jamesadevine	0:e1a608bb55e8	545
jamesadevine	0:e1a608bb55e8	546	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
jamesadevine	0:e1a608bb55e8	547	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
jamesadevine	0:e1a608bb55e8	548
jamesadevine	0:e1a608bb55e8	549	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
jamesadevine	0:e1a608bb55e8	550	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
jamesadevine	0:e1a608bb55e8	551
jamesadevine	0:e1a608bb55e8	552	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
jamesadevine	0:e1a608bb55e8	553	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
jamesadevine	0:e1a608bb55e8	554
jamesadevine	0:e1a608bb55e8	555	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
jamesadevine	0:e1a608bb55e8	556	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
jamesadevine	0:e1a608bb55e8	557
jamesadevine	0:e1a608bb55e8	558	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
jamesadevine	0:e1a608bb55e8	559	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
jamesadevine	0:e1a608bb55e8	560
jamesadevine	0:e1a608bb55e8	561	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
jamesadevine	0:e1a608bb55e8	562	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
jamesadevine	0:e1a608bb55e8	563
jamesadevine	0:e1a608bb55e8	564	/* SCB Vector Table Offset Register Definitions */
jamesadevine	0:e1a608bb55e8	565	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
jamesadevine	0:e1a608bb55e8	566	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
jamesadevine	0:e1a608bb55e8	567
jamesadevine	0:e1a608bb55e8	568	/* SCB Application Interrupt and Reset Control Register Definitions */
jamesadevine	0:e1a608bb55e8	569	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
jamesadevine	0:e1a608bb55e8	570	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
jamesadevine	0:e1a608bb55e8	571
jamesadevine	0:e1a608bb55e8	572	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
jamesadevine	0:e1a608bb55e8	573	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
jamesadevine	0:e1a608bb55e8	574
jamesadevine	0:e1a608bb55e8	575	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
jamesadevine	0:e1a608bb55e8	576	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
jamesadevine	0:e1a608bb55e8	577
jamesadevine	0:e1a608bb55e8	578	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
jamesadevine	0:e1a608bb55e8	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
jamesadevine	0:e1a608bb55e8	580
jamesadevine	0:e1a608bb55e8	581	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
jamesadevine	0:e1a608bb55e8	582	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
jamesadevine	0:e1a608bb55e8	583
jamesadevine	0:e1a608bb55e8	584	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
jamesadevine	0:e1a608bb55e8	585	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
jamesadevine	0:e1a608bb55e8	586
jamesadevine	0:e1a608bb55e8	587	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
jamesadevine	0:e1a608bb55e8	588	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
jamesadevine	0:e1a608bb55e8	589
jamesadevine	0:e1a608bb55e8	590	/* SCB System Control Register Definitions */
jamesadevine	0:e1a608bb55e8	591	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
jamesadevine	0:e1a608bb55e8	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
jamesadevine	0:e1a608bb55e8	593
jamesadevine	0:e1a608bb55e8	594	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
jamesadevine	0:e1a608bb55e8	595	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
jamesadevine	0:e1a608bb55e8	596
jamesadevine	0:e1a608bb55e8	597	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
jamesadevine	0:e1a608bb55e8	598	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
jamesadevine	0:e1a608bb55e8	599
jamesadevine	0:e1a608bb55e8	600	/* SCB Configuration Control Register Definitions */
jamesadevine	0:e1a608bb55e8	601	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
jamesadevine	0:e1a608bb55e8	602	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
jamesadevine	0:e1a608bb55e8	603
jamesadevine	0:e1a608bb55e8	604	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
jamesadevine	0:e1a608bb55e8	605	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
jamesadevine	0:e1a608bb55e8	606
jamesadevine	0:e1a608bb55e8	607	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
jamesadevine	0:e1a608bb55e8	608	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
jamesadevine	0:e1a608bb55e8	609
jamesadevine	0:e1a608bb55e8	610	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
jamesadevine	0:e1a608bb55e8	611	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
jamesadevine	0:e1a608bb55e8	612
jamesadevine	0:e1a608bb55e8	613	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
jamesadevine	0:e1a608bb55e8	614	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
jamesadevine	0:e1a608bb55e8	615
jamesadevine	0:e1a608bb55e8	616	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
jamesadevine	0:e1a608bb55e8	617	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
jamesadevine	0:e1a608bb55e8	618
jamesadevine	0:e1a608bb55e8	619	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
jamesadevine	0:e1a608bb55e8	620	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
jamesadevine	0:e1a608bb55e8	621
jamesadevine	0:e1a608bb55e8	622	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
jamesadevine	0:e1a608bb55e8	623	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
jamesadevine	0:e1a608bb55e8	624
jamesadevine	0:e1a608bb55e8	625	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
jamesadevine	0:e1a608bb55e8	626	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
jamesadevine	0:e1a608bb55e8	627
jamesadevine	0:e1a608bb55e8	628	/* SCB System Handler Control and State Register Definitions */
jamesadevine	0:e1a608bb55e8	629	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
jamesadevine	0:e1a608bb55e8	630	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
jamesadevine	0:e1a608bb55e8	631
jamesadevine	0:e1a608bb55e8	632	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
jamesadevine	0:e1a608bb55e8	633	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
jamesadevine	0:e1a608bb55e8	634
jamesadevine	0:e1a608bb55e8	635	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
jamesadevine	0:e1a608bb55e8	636	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
jamesadevine	0:e1a608bb55e8	637
jamesadevine	0:e1a608bb55e8	638	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
jamesadevine	0:e1a608bb55e8	639	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
jamesadevine	0:e1a608bb55e8	640
jamesadevine	0:e1a608bb55e8	641	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
jamesadevine	0:e1a608bb55e8	642	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
jamesadevine	0:e1a608bb55e8	643
jamesadevine	0:e1a608bb55e8	644	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
jamesadevine	0:e1a608bb55e8	645	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
jamesadevine	0:e1a608bb55e8	646
jamesadevine	0:e1a608bb55e8	647	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
jamesadevine	0:e1a608bb55e8	648	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
jamesadevine	0:e1a608bb55e8	649
jamesadevine	0:e1a608bb55e8	650	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
jamesadevine	0:e1a608bb55e8	651	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
jamesadevine	0:e1a608bb55e8	652
jamesadevine	0:e1a608bb55e8	653	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
jamesadevine	0:e1a608bb55e8	654	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
jamesadevine	0:e1a608bb55e8	655
jamesadevine	0:e1a608bb55e8	656	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
jamesadevine	0:e1a608bb55e8	657	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
jamesadevine	0:e1a608bb55e8	658
jamesadevine	0:e1a608bb55e8	659	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
jamesadevine	0:e1a608bb55e8	660	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
jamesadevine	0:e1a608bb55e8	661
jamesadevine	0:e1a608bb55e8	662	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
jamesadevine	0:e1a608bb55e8	663	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
jamesadevine	0:e1a608bb55e8	664
jamesadevine	0:e1a608bb55e8	665	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
jamesadevine	0:e1a608bb55e8	666	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
jamesadevine	0:e1a608bb55e8	667
jamesadevine	0:e1a608bb55e8	668	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
jamesadevine	0:e1a608bb55e8	669	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
jamesadevine	0:e1a608bb55e8	670
jamesadevine	0:e1a608bb55e8	671	/* SCB Configurable Fault Status Registers Definitions */
jamesadevine	0:e1a608bb55e8	672	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
jamesadevine	0:e1a608bb55e8	673	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
jamesadevine	0:e1a608bb55e8	674
jamesadevine	0:e1a608bb55e8	675	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
jamesadevine	0:e1a608bb55e8	676	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
jamesadevine	0:e1a608bb55e8	677
jamesadevine	0:e1a608bb55e8	678	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
jamesadevine	0:e1a608bb55e8	679	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
jamesadevine	0:e1a608bb55e8	680
jamesadevine	0:e1a608bb55e8	681	/* SCB Hard Fault Status Registers Definitions */
jamesadevine	0:e1a608bb55e8	682	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
jamesadevine	0:e1a608bb55e8	683	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
jamesadevine	0:e1a608bb55e8	684
jamesadevine	0:e1a608bb55e8	685	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
jamesadevine	0:e1a608bb55e8	686	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
jamesadevine	0:e1a608bb55e8	687
jamesadevine	0:e1a608bb55e8	688	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
jamesadevine	0:e1a608bb55e8	689	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
jamesadevine	0:e1a608bb55e8	690
jamesadevine	0:e1a608bb55e8	691	/* SCB Debug Fault Status Register Definitions */
jamesadevine	0:e1a608bb55e8	692	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
jamesadevine	0:e1a608bb55e8	693	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
jamesadevine	0:e1a608bb55e8	694
jamesadevine	0:e1a608bb55e8	695	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
jamesadevine	0:e1a608bb55e8	696	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
jamesadevine	0:e1a608bb55e8	697
jamesadevine	0:e1a608bb55e8	698	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
jamesadevine	0:e1a608bb55e8	699	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
jamesadevine	0:e1a608bb55e8	700
jamesadevine	0:e1a608bb55e8	701	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
jamesadevine	0:e1a608bb55e8	702	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
jamesadevine	0:e1a608bb55e8	703
jamesadevine	0:e1a608bb55e8	704	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
jamesadevine	0:e1a608bb55e8	705	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
jamesadevine	0:e1a608bb55e8	706
jamesadevine	0:e1a608bb55e8	707	/* Cache Level ID register */
jamesadevine	0:e1a608bb55e8	708	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
jamesadevine	0:e1a608bb55e8	709	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
jamesadevine	0:e1a608bb55e8	710
jamesadevine	0:e1a608bb55e8	711	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
jamesadevine	0:e1a608bb55e8	712	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
jamesadevine	0:e1a608bb55e8	713
jamesadevine	0:e1a608bb55e8	714	/* Cache Type register */
jamesadevine	0:e1a608bb55e8	715	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
jamesadevine	0:e1a608bb55e8	716	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
jamesadevine	0:e1a608bb55e8	717
jamesadevine	0:e1a608bb55e8	718	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
jamesadevine	0:e1a608bb55e8	719	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
jamesadevine	0:e1a608bb55e8	720
jamesadevine	0:e1a608bb55e8	721	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
jamesadevine	0:e1a608bb55e8	722	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
jamesadevine	0:e1a608bb55e8	723
jamesadevine	0:e1a608bb55e8	724	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
jamesadevine	0:e1a608bb55e8	725	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
jamesadevine	0:e1a608bb55e8	726
jamesadevine	0:e1a608bb55e8	727	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
jamesadevine	0:e1a608bb55e8	728	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
jamesadevine	0:e1a608bb55e8	729
jamesadevine	0:e1a608bb55e8	730	/* Cache Size ID Register */
jamesadevine	0:e1a608bb55e8	731	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
jamesadevine	0:e1a608bb55e8	732	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
jamesadevine	0:e1a608bb55e8	733
jamesadevine	0:e1a608bb55e8	734	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
jamesadevine	0:e1a608bb55e8	735	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
jamesadevine	0:e1a608bb55e8	736
jamesadevine	0:e1a608bb55e8	737	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
jamesadevine	0:e1a608bb55e8	738	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
jamesadevine	0:e1a608bb55e8	739
jamesadevine	0:e1a608bb55e8	740	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
jamesadevine	0:e1a608bb55e8	741	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
jamesadevine	0:e1a608bb55e8	742
jamesadevine	0:e1a608bb55e8	743	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
jamesadevine	0:e1a608bb55e8	744	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
jamesadevine	0:e1a608bb55e8	745
jamesadevine	0:e1a608bb55e8	746	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
jamesadevine	0:e1a608bb55e8	747	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
jamesadevine	0:e1a608bb55e8	748
jamesadevine	0:e1a608bb55e8	749	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
jamesadevine	0:e1a608bb55e8	750	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
jamesadevine	0:e1a608bb55e8	751
jamesadevine	0:e1a608bb55e8	752	/* Cache Size Selection Register */
jamesadevine	0:e1a608bb55e8	753	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
jamesadevine	0:e1a608bb55e8	754	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
jamesadevine	0:e1a608bb55e8	755
jamesadevine	0:e1a608bb55e8	756	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
jamesadevine	0:e1a608bb55e8	757	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
jamesadevine	0:e1a608bb55e8	758
jamesadevine	0:e1a608bb55e8	759	/* SCB Software Triggered Interrupt Register */
jamesadevine	0:e1a608bb55e8	760	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
jamesadevine	0:e1a608bb55e8	761	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
jamesadevine	0:e1a608bb55e8	762
jamesadevine	0:e1a608bb55e8	763	/* Instruction Tightly-Coupled Memory Control Register*/
jamesadevine	0:e1a608bb55e8	764	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
jamesadevine	0:e1a608bb55e8	765	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
jamesadevine	0:e1a608bb55e8	766
jamesadevine	0:e1a608bb55e8	767	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
jamesadevine	0:e1a608bb55e8	768	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
jamesadevine	0:e1a608bb55e8	769
jamesadevine	0:e1a608bb55e8	770	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
jamesadevine	0:e1a608bb55e8	771	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
jamesadevine	0:e1a608bb55e8	772
jamesadevine	0:e1a608bb55e8	773	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
jamesadevine	0:e1a608bb55e8	774	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
jamesadevine	0:e1a608bb55e8	775
jamesadevine	0:e1a608bb55e8	776	/* Data Tightly-Coupled Memory Control Registers */
jamesadevine	0:e1a608bb55e8	777	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
jamesadevine	0:e1a608bb55e8	778	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
jamesadevine	0:e1a608bb55e8	779
jamesadevine	0:e1a608bb55e8	780	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
jamesadevine	0:e1a608bb55e8	781	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
jamesadevine	0:e1a608bb55e8	782
jamesadevine	0:e1a608bb55e8	783	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
jamesadevine	0:e1a608bb55e8	784	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
jamesadevine	0:e1a608bb55e8	785
jamesadevine	0:e1a608bb55e8	786	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
jamesadevine	0:e1a608bb55e8	787	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
jamesadevine	0:e1a608bb55e8	788
jamesadevine	0:e1a608bb55e8	789	/* AHBP Control Register */
jamesadevine	0:e1a608bb55e8	790	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
jamesadevine	0:e1a608bb55e8	791	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
jamesadevine	0:e1a608bb55e8	792
jamesadevine	0:e1a608bb55e8	793	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
jamesadevine	0:e1a608bb55e8	794	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
jamesadevine	0:e1a608bb55e8	795
jamesadevine	0:e1a608bb55e8	796	/* L1 Cache Control Register */
jamesadevine	0:e1a608bb55e8	797	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
jamesadevine	0:e1a608bb55e8	798	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
jamesadevine	0:e1a608bb55e8	799
jamesadevine	0:e1a608bb55e8	800	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
jamesadevine	0:e1a608bb55e8	801	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
jamesadevine	0:e1a608bb55e8	802
jamesadevine	0:e1a608bb55e8	803	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
jamesadevine	0:e1a608bb55e8	804	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
jamesadevine	0:e1a608bb55e8	805
jamesadevine	0:e1a608bb55e8	806	/* AHBS control register */
jamesadevine	0:e1a608bb55e8	807	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
jamesadevine	0:e1a608bb55e8	808	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
jamesadevine	0:e1a608bb55e8	809
jamesadevine	0:e1a608bb55e8	810	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
jamesadevine	0:e1a608bb55e8	811	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
jamesadevine	0:e1a608bb55e8	812
jamesadevine	0:e1a608bb55e8	813	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
jamesadevine	0:e1a608bb55e8	814	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
jamesadevine	0:e1a608bb55e8	815
jamesadevine	0:e1a608bb55e8	816	/* Auxiliary Bus Fault Status Register */
jamesadevine	0:e1a608bb55e8	817	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
jamesadevine	0:e1a608bb55e8	818	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
jamesadevine	0:e1a608bb55e8	819
jamesadevine	0:e1a608bb55e8	820	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
jamesadevine	0:e1a608bb55e8	821	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
jamesadevine	0:e1a608bb55e8	822
jamesadevine	0:e1a608bb55e8	823	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
jamesadevine	0:e1a608bb55e8	824	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
jamesadevine	0:e1a608bb55e8	825
jamesadevine	0:e1a608bb55e8	826	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
jamesadevine	0:e1a608bb55e8	827	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
jamesadevine	0:e1a608bb55e8	828
jamesadevine	0:e1a608bb55e8	829	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
jamesadevine	0:e1a608bb55e8	830	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
jamesadevine	0:e1a608bb55e8	831
jamesadevine	0:e1a608bb55e8	832	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
jamesadevine	0:e1a608bb55e8	833	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
jamesadevine	0:e1a608bb55e8	834
jamesadevine	0:e1a608bb55e8	835	/@} end of group CMSIS_SCB /
jamesadevine	0:e1a608bb55e8	836
jamesadevine	0:e1a608bb55e8	837
jamesadevine	0:e1a608bb55e8	838	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	839	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
jamesadevine	0:e1a608bb55e8	840	\brief Type definitions for the System Control and ID Register not in the SCB
jamesadevine	0:e1a608bb55e8	841	@{
jamesadevine	0:e1a608bb55e8	842	*/
jamesadevine	0:e1a608bb55e8	843
jamesadevine	0:e1a608bb55e8	844	/** \brief Structure type to access the System Control and ID Register not in the SCB.
jamesadevine	0:e1a608bb55e8	845	*/
jamesadevine	0:e1a608bb55e8	846	typedef struct
jamesadevine	0:e1a608bb55e8	847	{
jamesadevine	0:e1a608bb55e8	848	uint32_t RESERVED0[1];
jamesadevine	0:e1a608bb55e8	849	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
jamesadevine	0:e1a608bb55e8	850	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
jamesadevine	0:e1a608bb55e8	851	} SCnSCB_Type;
jamesadevine	0:e1a608bb55e8	852
jamesadevine	0:e1a608bb55e8	853	/* Interrupt Controller Type Register Definitions */
jamesadevine	0:e1a608bb55e8	854	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
jamesadevine	0:e1a608bb55e8	855	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
jamesadevine	0:e1a608bb55e8	856
jamesadevine	0:e1a608bb55e8	857	/* Auxiliary Control Register Definitions */
jamesadevine	0:e1a608bb55e8	858	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
jamesadevine	0:e1a608bb55e8	859	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
jamesadevine	0:e1a608bb55e8	860
jamesadevine	0:e1a608bb55e8	861	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
jamesadevine	0:e1a608bb55e8	862	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
jamesadevine	0:e1a608bb55e8	863
jamesadevine	0:e1a608bb55e8	864	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
jamesadevine	0:e1a608bb55e8	865	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
jamesadevine	0:e1a608bb55e8	866
jamesadevine	0:e1a608bb55e8	867	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
jamesadevine	0:e1a608bb55e8	868	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
jamesadevine	0:e1a608bb55e8	869
jamesadevine	0:e1a608bb55e8	870	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
jamesadevine	0:e1a608bb55e8	871	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
jamesadevine	0:e1a608bb55e8	872
jamesadevine	0:e1a608bb55e8	873	/@} end of group CMSIS_SCnotSCB /
jamesadevine	0:e1a608bb55e8	874
jamesadevine	0:e1a608bb55e8	875
jamesadevine	0:e1a608bb55e8	876	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	877	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
jamesadevine	0:e1a608bb55e8	878	\brief Type definitions for the System Timer Registers.
jamesadevine	0:e1a608bb55e8	879	@{
jamesadevine	0:e1a608bb55e8	880	*/
jamesadevine	0:e1a608bb55e8	881
jamesadevine	0:e1a608bb55e8	882	/** \brief Structure type to access the System Timer (SysTick).
jamesadevine	0:e1a608bb55e8	883	*/
jamesadevine	0:e1a608bb55e8	884	typedef struct
jamesadevine	0:e1a608bb55e8	885	{
jamesadevine	0:e1a608bb55e8	886	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
jamesadevine	0:e1a608bb55e8	887	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
jamesadevine	0:e1a608bb55e8	888	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
jamesadevine	0:e1a608bb55e8	889	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
jamesadevine	0:e1a608bb55e8	890	} SysTick_Type;
jamesadevine	0:e1a608bb55e8	891
jamesadevine	0:e1a608bb55e8	892	/* SysTick Control / Status Register Definitions */
jamesadevine	0:e1a608bb55e8	893	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
jamesadevine	0:e1a608bb55e8	894	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
jamesadevine	0:e1a608bb55e8	895
jamesadevine	0:e1a608bb55e8	896	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
jamesadevine	0:e1a608bb55e8	897	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
jamesadevine	0:e1a608bb55e8	898
jamesadevine	0:e1a608bb55e8	899	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
jamesadevine	0:e1a608bb55e8	900	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
jamesadevine	0:e1a608bb55e8	901
jamesadevine	0:e1a608bb55e8	902	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
jamesadevine	0:e1a608bb55e8	903	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
jamesadevine	0:e1a608bb55e8	904
jamesadevine	0:e1a608bb55e8	905	/* SysTick Reload Register Definitions */
jamesadevine	0:e1a608bb55e8	906	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
jamesadevine	0:e1a608bb55e8	907	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
jamesadevine	0:e1a608bb55e8	908
jamesadevine	0:e1a608bb55e8	909	/* SysTick Current Register Definitions */
jamesadevine	0:e1a608bb55e8	910	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
jamesadevine	0:e1a608bb55e8	911	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
jamesadevine	0:e1a608bb55e8	912
jamesadevine	0:e1a608bb55e8	913	/* SysTick Calibration Register Definitions */
jamesadevine	0:e1a608bb55e8	914	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
jamesadevine	0:e1a608bb55e8	915	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
jamesadevine	0:e1a608bb55e8	916
jamesadevine	0:e1a608bb55e8	917	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
jamesadevine	0:e1a608bb55e8	918	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
jamesadevine	0:e1a608bb55e8	919
jamesadevine	0:e1a608bb55e8	920	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
jamesadevine	0:e1a608bb55e8	921	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
jamesadevine	0:e1a608bb55e8	922
jamesadevine	0:e1a608bb55e8	923	/@} end of group CMSIS_SysTick /
jamesadevine	0:e1a608bb55e8	924
jamesadevine	0:e1a608bb55e8	925
jamesadevine	0:e1a608bb55e8	926	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	927	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
jamesadevine	0:e1a608bb55e8	928	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
jamesadevine	0:e1a608bb55e8	929	@{
jamesadevine	0:e1a608bb55e8	930	*/
jamesadevine	0:e1a608bb55e8	931
jamesadevine	0:e1a608bb55e8	932	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
jamesadevine	0:e1a608bb55e8	933	*/
jamesadevine	0:e1a608bb55e8	934	typedef struct
jamesadevine	0:e1a608bb55e8	935	{
jamesadevine	0:e1a608bb55e8	936	__O union
jamesadevine	0:e1a608bb55e8	937	{
jamesadevine	0:e1a608bb55e8	938	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
jamesadevine	0:e1a608bb55e8	939	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
jamesadevine	0:e1a608bb55e8	940	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
jamesadevine	0:e1a608bb55e8	941	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
jamesadevine	0:e1a608bb55e8	942	uint32_t RESERVED0[864];
jamesadevine	0:e1a608bb55e8	943	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
jamesadevine	0:e1a608bb55e8	944	uint32_t RESERVED1[15];
jamesadevine	0:e1a608bb55e8	945	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
jamesadevine	0:e1a608bb55e8	946	uint32_t RESERVED2[15];
jamesadevine	0:e1a608bb55e8	947	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
jamesadevine	0:e1a608bb55e8	948	uint32_t RESERVED3[29];
jamesadevine	0:e1a608bb55e8	949	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
jamesadevine	0:e1a608bb55e8	950	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
jamesadevine	0:e1a608bb55e8	951	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
jamesadevine	0:e1a608bb55e8	952	uint32_t RESERVED4[43];
jamesadevine	0:e1a608bb55e8	953	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
jamesadevine	0:e1a608bb55e8	954	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
jamesadevine	0:e1a608bb55e8	955	uint32_t RESERVED5[6];
jamesadevine	0:e1a608bb55e8	956	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
jamesadevine	0:e1a608bb55e8	957	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
jamesadevine	0:e1a608bb55e8	958	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
jamesadevine	0:e1a608bb55e8	959	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
jamesadevine	0:e1a608bb55e8	960	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
jamesadevine	0:e1a608bb55e8	961	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
jamesadevine	0:e1a608bb55e8	962	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
jamesadevine	0:e1a608bb55e8	963	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
jamesadevine	0:e1a608bb55e8	964	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
jamesadevine	0:e1a608bb55e8	965	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
jamesadevine	0:e1a608bb55e8	966	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
jamesadevine	0:e1a608bb55e8	967	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
jamesadevine	0:e1a608bb55e8	968	} ITM_Type;
jamesadevine	0:e1a608bb55e8	969
jamesadevine	0:e1a608bb55e8	970	/* ITM Trace Privilege Register Definitions */
jamesadevine	0:e1a608bb55e8	971	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
jamesadevine	0:e1a608bb55e8	972	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
jamesadevine	0:e1a608bb55e8	973
jamesadevine	0:e1a608bb55e8	974	/* ITM Trace Control Register Definitions */
jamesadevine	0:e1a608bb55e8	975	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
jamesadevine	0:e1a608bb55e8	976	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
jamesadevine	0:e1a608bb55e8	977
jamesadevine	0:e1a608bb55e8	978	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
jamesadevine	0:e1a608bb55e8	979	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
jamesadevine	0:e1a608bb55e8	980
jamesadevine	0:e1a608bb55e8	981	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
jamesadevine	0:e1a608bb55e8	982	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
jamesadevine	0:e1a608bb55e8	983
jamesadevine	0:e1a608bb55e8	984	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
jamesadevine	0:e1a608bb55e8	985	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
jamesadevine	0:e1a608bb55e8	986
jamesadevine	0:e1a608bb55e8	987	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
jamesadevine	0:e1a608bb55e8	988	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
jamesadevine	0:e1a608bb55e8	989
jamesadevine	0:e1a608bb55e8	990	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
jamesadevine	0:e1a608bb55e8	991	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
jamesadevine	0:e1a608bb55e8	992
jamesadevine	0:e1a608bb55e8	993	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
jamesadevine	0:e1a608bb55e8	994	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
jamesadevine	0:e1a608bb55e8	995
jamesadevine	0:e1a608bb55e8	996	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
jamesadevine	0:e1a608bb55e8	997	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
jamesadevine	0:e1a608bb55e8	998
jamesadevine	0:e1a608bb55e8	999	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
jamesadevine	0:e1a608bb55e8	1000	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
jamesadevine	0:e1a608bb55e8	1001
jamesadevine	0:e1a608bb55e8	1002	/* ITM Integration Write Register Definitions */
jamesadevine	0:e1a608bb55e8	1003	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
jamesadevine	0:e1a608bb55e8	1004	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
jamesadevine	0:e1a608bb55e8	1005
jamesadevine	0:e1a608bb55e8	1006	/* ITM Integration Read Register Definitions */
jamesadevine	0:e1a608bb55e8	1007	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
jamesadevine	0:e1a608bb55e8	1008	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
jamesadevine	0:e1a608bb55e8	1009
jamesadevine	0:e1a608bb55e8	1010	/* ITM Integration Mode Control Register Definitions */
jamesadevine	0:e1a608bb55e8	1011	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
jamesadevine	0:e1a608bb55e8	1012	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
jamesadevine	0:e1a608bb55e8	1013
jamesadevine	0:e1a608bb55e8	1014	/* ITM Lock Status Register Definitions */
jamesadevine	0:e1a608bb55e8	1015	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
jamesadevine	0:e1a608bb55e8	1016	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
jamesadevine	0:e1a608bb55e8	1017
jamesadevine	0:e1a608bb55e8	1018	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
jamesadevine	0:e1a608bb55e8	1019	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
jamesadevine	0:e1a608bb55e8	1020
jamesadevine	0:e1a608bb55e8	1021	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
jamesadevine	0:e1a608bb55e8	1022	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
jamesadevine	0:e1a608bb55e8	1023
jamesadevine	0:e1a608bb55e8	1024	/@}/ /* end of group CMSIS_ITM */
jamesadevine	0:e1a608bb55e8	1025
jamesadevine	0:e1a608bb55e8	1026
jamesadevine	0:e1a608bb55e8	1027	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	1028	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
jamesadevine	0:e1a608bb55e8	1029	\brief Type definitions for the Data Watchpoint and Trace (DWT)
jamesadevine	0:e1a608bb55e8	1030	@{
jamesadevine	0:e1a608bb55e8	1031	*/
jamesadevine	0:e1a608bb55e8	1032
jamesadevine	0:e1a608bb55e8	1033	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
jamesadevine	0:e1a608bb55e8	1034	*/
jamesadevine	0:e1a608bb55e8	1035	typedef struct
jamesadevine	0:e1a608bb55e8	1036	{
jamesadevine	0:e1a608bb55e8	1037	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
jamesadevine	0:e1a608bb55e8	1038	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
jamesadevine	0:e1a608bb55e8	1039	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
jamesadevine	0:e1a608bb55e8	1040	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
jamesadevine	0:e1a608bb55e8	1041	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
jamesadevine	0:e1a608bb55e8	1042	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
jamesadevine	0:e1a608bb55e8	1043	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
jamesadevine	0:e1a608bb55e8	1044	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
jamesadevine	0:e1a608bb55e8	1045	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
jamesadevine	0:e1a608bb55e8	1046	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
jamesadevine	0:e1a608bb55e8	1047	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
jamesadevine	0:e1a608bb55e8	1048	uint32_t RESERVED0[1];
jamesadevine	0:e1a608bb55e8	1049	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
jamesadevine	0:e1a608bb55e8	1050	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
jamesadevine	0:e1a608bb55e8	1051	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
jamesadevine	0:e1a608bb55e8	1052	uint32_t RESERVED1[1];
jamesadevine	0:e1a608bb55e8	1053	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
jamesadevine	0:e1a608bb55e8	1054	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
jamesadevine	0:e1a608bb55e8	1055	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
jamesadevine	0:e1a608bb55e8	1056	uint32_t RESERVED2[1];
jamesadevine	0:e1a608bb55e8	1057	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
jamesadevine	0:e1a608bb55e8	1058	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
jamesadevine	0:e1a608bb55e8	1059	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
jamesadevine	0:e1a608bb55e8	1060	uint32_t RESERVED3[981];
jamesadevine	0:e1a608bb55e8	1061	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
jamesadevine	0:e1a608bb55e8	1062	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
jamesadevine	0:e1a608bb55e8	1063	} DWT_Type;
jamesadevine	0:e1a608bb55e8	1064
jamesadevine	0:e1a608bb55e8	1065	/* DWT Control Register Definitions */
jamesadevine	0:e1a608bb55e8	1066	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
jamesadevine	0:e1a608bb55e8	1067	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
jamesadevine	0:e1a608bb55e8	1068
jamesadevine	0:e1a608bb55e8	1069	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
jamesadevine	0:e1a608bb55e8	1070	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
jamesadevine	0:e1a608bb55e8	1071
jamesadevine	0:e1a608bb55e8	1072	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
jamesadevine	0:e1a608bb55e8	1073	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
jamesadevine	0:e1a608bb55e8	1074
jamesadevine	0:e1a608bb55e8	1075	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
jamesadevine	0:e1a608bb55e8	1076	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
jamesadevine	0:e1a608bb55e8	1077
jamesadevine	0:e1a608bb55e8	1078	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
jamesadevine	0:e1a608bb55e8	1079	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
jamesadevine	0:e1a608bb55e8	1080
jamesadevine	0:e1a608bb55e8	1081	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
jamesadevine	0:e1a608bb55e8	1082	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
jamesadevine	0:e1a608bb55e8	1083
jamesadevine	0:e1a608bb55e8	1084	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
jamesadevine	0:e1a608bb55e8	1085	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
jamesadevine	0:e1a608bb55e8	1086
jamesadevine	0:e1a608bb55e8	1087	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
jamesadevine	0:e1a608bb55e8	1088	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
jamesadevine	0:e1a608bb55e8	1089
jamesadevine	0:e1a608bb55e8	1090	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
jamesadevine	0:e1a608bb55e8	1091	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
jamesadevine	0:e1a608bb55e8	1092
jamesadevine	0:e1a608bb55e8	1093	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
jamesadevine	0:e1a608bb55e8	1094	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
jamesadevine	0:e1a608bb55e8	1095
jamesadevine	0:e1a608bb55e8	1096	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
jamesadevine	0:e1a608bb55e8	1097	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
jamesadevine	0:e1a608bb55e8	1098
jamesadevine	0:e1a608bb55e8	1099	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
jamesadevine	0:e1a608bb55e8	1100	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
jamesadevine	0:e1a608bb55e8	1101
jamesadevine	0:e1a608bb55e8	1102	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
jamesadevine	0:e1a608bb55e8	1103	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
jamesadevine	0:e1a608bb55e8	1104
jamesadevine	0:e1a608bb55e8	1105	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
jamesadevine	0:e1a608bb55e8	1106	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
jamesadevine	0:e1a608bb55e8	1107
jamesadevine	0:e1a608bb55e8	1108	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
jamesadevine	0:e1a608bb55e8	1109	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
jamesadevine	0:e1a608bb55e8	1110
jamesadevine	0:e1a608bb55e8	1111	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
jamesadevine	0:e1a608bb55e8	1112	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
jamesadevine	0:e1a608bb55e8	1113
jamesadevine	0:e1a608bb55e8	1114	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
jamesadevine	0:e1a608bb55e8	1115	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
jamesadevine	0:e1a608bb55e8	1116
jamesadevine	0:e1a608bb55e8	1117	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
jamesadevine	0:e1a608bb55e8	1118	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
jamesadevine	0:e1a608bb55e8	1119
jamesadevine	0:e1a608bb55e8	1120	/* DWT CPI Count Register Definitions */
jamesadevine	0:e1a608bb55e8	1121	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
jamesadevine	0:e1a608bb55e8	1122	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
jamesadevine	0:e1a608bb55e8	1123
jamesadevine	0:e1a608bb55e8	1124	/* DWT Exception Overhead Count Register Definitions */
jamesadevine	0:e1a608bb55e8	1125	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
jamesadevine	0:e1a608bb55e8	1126	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
jamesadevine	0:e1a608bb55e8	1127
jamesadevine	0:e1a608bb55e8	1128	/* DWT Sleep Count Register Definitions */
jamesadevine	0:e1a608bb55e8	1129	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
jamesadevine	0:e1a608bb55e8	1130	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
jamesadevine	0:e1a608bb55e8	1131
jamesadevine	0:e1a608bb55e8	1132	/* DWT LSU Count Register Definitions */
jamesadevine	0:e1a608bb55e8	1133	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
jamesadevine	0:e1a608bb55e8	1134	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
jamesadevine	0:e1a608bb55e8	1135
jamesadevine	0:e1a608bb55e8	1136	/* DWT Folded-instruction Count Register Definitions */
jamesadevine	0:e1a608bb55e8	1137	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
jamesadevine	0:e1a608bb55e8	1138	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
jamesadevine	0:e1a608bb55e8	1139
jamesadevine	0:e1a608bb55e8	1140	/* DWT Comparator Mask Register Definitions */
jamesadevine	0:e1a608bb55e8	1141	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
jamesadevine	0:e1a608bb55e8	1142	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
jamesadevine	0:e1a608bb55e8	1143
jamesadevine	0:e1a608bb55e8	1144	/* DWT Comparator Function Register Definitions */
jamesadevine	0:e1a608bb55e8	1145	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
jamesadevine	0:e1a608bb55e8	1146	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
jamesadevine	0:e1a608bb55e8	1147
jamesadevine	0:e1a608bb55e8	1148	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
jamesadevine	0:e1a608bb55e8	1149	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
jamesadevine	0:e1a608bb55e8	1150
jamesadevine	0:e1a608bb55e8	1151	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
jamesadevine	0:e1a608bb55e8	1152	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
jamesadevine	0:e1a608bb55e8	1153
jamesadevine	0:e1a608bb55e8	1154	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
jamesadevine	0:e1a608bb55e8	1155	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
jamesadevine	0:e1a608bb55e8	1156
jamesadevine	0:e1a608bb55e8	1157	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
jamesadevine	0:e1a608bb55e8	1158	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
jamesadevine	0:e1a608bb55e8	1159
jamesadevine	0:e1a608bb55e8	1160	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
jamesadevine	0:e1a608bb55e8	1161	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
jamesadevine	0:e1a608bb55e8	1162
jamesadevine	0:e1a608bb55e8	1163	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
jamesadevine	0:e1a608bb55e8	1164	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
jamesadevine	0:e1a608bb55e8	1165
jamesadevine	0:e1a608bb55e8	1166	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
jamesadevine	0:e1a608bb55e8	1167	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
jamesadevine	0:e1a608bb55e8	1168
jamesadevine	0:e1a608bb55e8	1169	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
jamesadevine	0:e1a608bb55e8	1170	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
jamesadevine	0:e1a608bb55e8	1171
jamesadevine	0:e1a608bb55e8	1172	/@}/ /* end of group CMSIS_DWT */
jamesadevine	0:e1a608bb55e8	1173
jamesadevine	0:e1a608bb55e8	1174
jamesadevine	0:e1a608bb55e8	1175	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	1176	\defgroup CMSIS_TPI Trace Port Interface (TPI)
jamesadevine	0:e1a608bb55e8	1177	\brief Type definitions for the Trace Port Interface (TPI)
jamesadevine	0:e1a608bb55e8	1178	@{
jamesadevine	0:e1a608bb55e8	1179	*/
jamesadevine	0:e1a608bb55e8	1180
jamesadevine	0:e1a608bb55e8	1181	/** \brief Structure type to access the Trace Port Interface Register (TPI).
jamesadevine	0:e1a608bb55e8	1182	*/
jamesadevine	0:e1a608bb55e8	1183	typedef struct
jamesadevine	0:e1a608bb55e8	1184	{
jamesadevine	0:e1a608bb55e8	1185	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
jamesadevine	0:e1a608bb55e8	1186	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
jamesadevine	0:e1a608bb55e8	1187	uint32_t RESERVED0[2];
jamesadevine	0:e1a608bb55e8	1188	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
jamesadevine	0:e1a608bb55e8	1189	uint32_t RESERVED1[55];
jamesadevine	0:e1a608bb55e8	1190	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
jamesadevine	0:e1a608bb55e8	1191	uint32_t RESERVED2[131];
jamesadevine	0:e1a608bb55e8	1192	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
jamesadevine	0:e1a608bb55e8	1193	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
jamesadevine	0:e1a608bb55e8	1194	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
jamesadevine	0:e1a608bb55e8	1195	uint32_t RESERVED3[759];
jamesadevine	0:e1a608bb55e8	1196	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
jamesadevine	0:e1a608bb55e8	1197	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
jamesadevine	0:e1a608bb55e8	1198	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
jamesadevine	0:e1a608bb55e8	1199	uint32_t RESERVED4[1];
jamesadevine	0:e1a608bb55e8	1200	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
jamesadevine	0:e1a608bb55e8	1201	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
jamesadevine	0:e1a608bb55e8	1202	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
jamesadevine	0:e1a608bb55e8	1203	uint32_t RESERVED5[39];
jamesadevine	0:e1a608bb55e8	1204	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
jamesadevine	0:e1a608bb55e8	1205	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
jamesadevine	0:e1a608bb55e8	1206	uint32_t RESERVED7[8];
jamesadevine	0:e1a608bb55e8	1207	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
jamesadevine	0:e1a608bb55e8	1208	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
jamesadevine	0:e1a608bb55e8	1209	} TPI_Type;
jamesadevine	0:e1a608bb55e8	1210
jamesadevine	0:e1a608bb55e8	1211	/* TPI Asynchronous Clock Prescaler Register Definitions */
jamesadevine	0:e1a608bb55e8	1212	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
jamesadevine	0:e1a608bb55e8	1213	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
jamesadevine	0:e1a608bb55e8	1214
jamesadevine	0:e1a608bb55e8	1215	/* TPI Selected Pin Protocol Register Definitions */
jamesadevine	0:e1a608bb55e8	1216	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
jamesadevine	0:e1a608bb55e8	1217	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
jamesadevine	0:e1a608bb55e8	1218
jamesadevine	0:e1a608bb55e8	1219	/* TPI Formatter and Flush Status Register Definitions */
jamesadevine	0:e1a608bb55e8	1220	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
jamesadevine	0:e1a608bb55e8	1221	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
jamesadevine	0:e1a608bb55e8	1222
jamesadevine	0:e1a608bb55e8	1223	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
jamesadevine	0:e1a608bb55e8	1224	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
jamesadevine	0:e1a608bb55e8	1225
jamesadevine	0:e1a608bb55e8	1226	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
jamesadevine	0:e1a608bb55e8	1227	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
jamesadevine	0:e1a608bb55e8	1228
jamesadevine	0:e1a608bb55e8	1229	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
jamesadevine	0:e1a608bb55e8	1230	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
jamesadevine	0:e1a608bb55e8	1231
jamesadevine	0:e1a608bb55e8	1232	/* TPI Formatter and Flush Control Register Definitions */
jamesadevine	0:e1a608bb55e8	1233	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
jamesadevine	0:e1a608bb55e8	1234	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
jamesadevine	0:e1a608bb55e8	1235
jamesadevine	0:e1a608bb55e8	1236	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
jamesadevine	0:e1a608bb55e8	1237	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
jamesadevine	0:e1a608bb55e8	1238
jamesadevine	0:e1a608bb55e8	1239	/* TPI TRIGGER Register Definitions */
jamesadevine	0:e1a608bb55e8	1240	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
jamesadevine	0:e1a608bb55e8	1241	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
jamesadevine	0:e1a608bb55e8	1242
jamesadevine	0:e1a608bb55e8	1243	/* TPI Integration ETM Data Register Definitions (FIFO0) */
jamesadevine	0:e1a608bb55e8	1244	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
jamesadevine	0:e1a608bb55e8	1245	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
jamesadevine	0:e1a608bb55e8	1246
jamesadevine	0:e1a608bb55e8	1247	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
jamesadevine	0:e1a608bb55e8	1248	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
jamesadevine	0:e1a608bb55e8	1249
jamesadevine	0:e1a608bb55e8	1250	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
jamesadevine	0:e1a608bb55e8	1251	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
jamesadevine	0:e1a608bb55e8	1252
jamesadevine	0:e1a608bb55e8	1253	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
jamesadevine	0:e1a608bb55e8	1254	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
jamesadevine	0:e1a608bb55e8	1255
jamesadevine	0:e1a608bb55e8	1256	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
jamesadevine	0:e1a608bb55e8	1257	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
jamesadevine	0:e1a608bb55e8	1258
jamesadevine	0:e1a608bb55e8	1259	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
jamesadevine	0:e1a608bb55e8	1260	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
jamesadevine	0:e1a608bb55e8	1261
jamesadevine	0:e1a608bb55e8	1262	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
jamesadevine	0:e1a608bb55e8	1263	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
jamesadevine	0:e1a608bb55e8	1264
jamesadevine	0:e1a608bb55e8	1265	/* TPI ITATBCTR2 Register Definitions */
jamesadevine	0:e1a608bb55e8	1266	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
jamesadevine	0:e1a608bb55e8	1267	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
jamesadevine	0:e1a608bb55e8	1268
jamesadevine	0:e1a608bb55e8	1269	/* TPI Integration ITM Data Register Definitions (FIFO1) */
jamesadevine	0:e1a608bb55e8	1270	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
jamesadevine	0:e1a608bb55e8	1271	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
jamesadevine	0:e1a608bb55e8	1272
jamesadevine	0:e1a608bb55e8	1273	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
jamesadevine	0:e1a608bb55e8	1274	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
jamesadevine	0:e1a608bb55e8	1275
jamesadevine	0:e1a608bb55e8	1276	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
jamesadevine	0:e1a608bb55e8	1277	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
jamesadevine	0:e1a608bb55e8	1278
jamesadevine	0:e1a608bb55e8	1279	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
jamesadevine	0:e1a608bb55e8	1280	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
jamesadevine	0:e1a608bb55e8	1281
jamesadevine	0:e1a608bb55e8	1282	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
jamesadevine	0:e1a608bb55e8	1283	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
jamesadevine	0:e1a608bb55e8	1284
jamesadevine	0:e1a608bb55e8	1285	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
jamesadevine	0:e1a608bb55e8	1286	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
jamesadevine	0:e1a608bb55e8	1287
jamesadevine	0:e1a608bb55e8	1288	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
jamesadevine	0:e1a608bb55e8	1289	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
jamesadevine	0:e1a608bb55e8	1290
jamesadevine	0:e1a608bb55e8	1291	/* TPI ITATBCTR0 Register Definitions */
jamesadevine	0:e1a608bb55e8	1292	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
jamesadevine	0:e1a608bb55e8	1293	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
jamesadevine	0:e1a608bb55e8	1294
jamesadevine	0:e1a608bb55e8	1295	/* TPI Integration Mode Control Register Definitions */
jamesadevine	0:e1a608bb55e8	1296	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
jamesadevine	0:e1a608bb55e8	1297	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
jamesadevine	0:e1a608bb55e8	1298
jamesadevine	0:e1a608bb55e8	1299	/* TPI DEVID Register Definitions */
jamesadevine	0:e1a608bb55e8	1300	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
jamesadevine	0:e1a608bb55e8	1301	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
jamesadevine	0:e1a608bb55e8	1302
jamesadevine	0:e1a608bb55e8	1303	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
jamesadevine	0:e1a608bb55e8	1304	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
jamesadevine	0:e1a608bb55e8	1305
jamesadevine	0:e1a608bb55e8	1306	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
jamesadevine	0:e1a608bb55e8	1307	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
jamesadevine	0:e1a608bb55e8	1308
jamesadevine	0:e1a608bb55e8	1309	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
jamesadevine	0:e1a608bb55e8	1310	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
jamesadevine	0:e1a608bb55e8	1311
jamesadevine	0:e1a608bb55e8	1312	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
jamesadevine	0:e1a608bb55e8	1313	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
jamesadevine	0:e1a608bb55e8	1314
jamesadevine	0:e1a608bb55e8	1315	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
jamesadevine	0:e1a608bb55e8	1316	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
jamesadevine	0:e1a608bb55e8	1317
jamesadevine	0:e1a608bb55e8	1318	/* TPI DEVTYPE Register Definitions */
jamesadevine	0:e1a608bb55e8	1319	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
jamesadevine	0:e1a608bb55e8	1320	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
jamesadevine	0:e1a608bb55e8	1321
jamesadevine	0:e1a608bb55e8	1322	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
jamesadevine	0:e1a608bb55e8	1323	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
jamesadevine	0:e1a608bb55e8	1324
jamesadevine	0:e1a608bb55e8	1325	/@}/ /* end of group CMSIS_TPI */
jamesadevine	0:e1a608bb55e8	1326
jamesadevine	0:e1a608bb55e8	1327
jamesadevine	0:e1a608bb55e8	1328	#if (__MPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	1329	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	1330	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
jamesadevine	0:e1a608bb55e8	1331	\brief Type definitions for the Memory Protection Unit (MPU)
jamesadevine	0:e1a608bb55e8	1332	@{
jamesadevine	0:e1a608bb55e8	1333	*/
jamesadevine	0:e1a608bb55e8	1334
jamesadevine	0:e1a608bb55e8	1335	/** \brief Structure type to access the Memory Protection Unit (MPU).
jamesadevine	0:e1a608bb55e8	1336	*/
jamesadevine	0:e1a608bb55e8	1337	typedef struct
jamesadevine	0:e1a608bb55e8	1338	{
jamesadevine	0:e1a608bb55e8	1339	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
jamesadevine	0:e1a608bb55e8	1340	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
jamesadevine	0:e1a608bb55e8	1341	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
jamesadevine	0:e1a608bb55e8	1342	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
jamesadevine	0:e1a608bb55e8	1343	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
jamesadevine	0:e1a608bb55e8	1344	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
jamesadevine	0:e1a608bb55e8	1345	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
jamesadevine	0:e1a608bb55e8	1346	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
jamesadevine	0:e1a608bb55e8	1347	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
jamesadevine	0:e1a608bb55e8	1348	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
jamesadevine	0:e1a608bb55e8	1349	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
jamesadevine	0:e1a608bb55e8	1350	} MPU_Type;
jamesadevine	0:e1a608bb55e8	1351
jamesadevine	0:e1a608bb55e8	1352	/* MPU Type Register */
jamesadevine	0:e1a608bb55e8	1353	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
jamesadevine	0:e1a608bb55e8	1354	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
jamesadevine	0:e1a608bb55e8	1355
jamesadevine	0:e1a608bb55e8	1356	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
jamesadevine	0:e1a608bb55e8	1357	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
jamesadevine	0:e1a608bb55e8	1358
jamesadevine	0:e1a608bb55e8	1359	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
jamesadevine	0:e1a608bb55e8	1360	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
jamesadevine	0:e1a608bb55e8	1361
jamesadevine	0:e1a608bb55e8	1362	/* MPU Control Register */
jamesadevine	0:e1a608bb55e8	1363	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
jamesadevine	0:e1a608bb55e8	1364	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
jamesadevine	0:e1a608bb55e8	1365
jamesadevine	0:e1a608bb55e8	1366	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
jamesadevine	0:e1a608bb55e8	1367	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
jamesadevine	0:e1a608bb55e8	1368
jamesadevine	0:e1a608bb55e8	1369	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
jamesadevine	0:e1a608bb55e8	1370	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
jamesadevine	0:e1a608bb55e8	1371
jamesadevine	0:e1a608bb55e8	1372	/* MPU Region Number Register */
jamesadevine	0:e1a608bb55e8	1373	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
jamesadevine	0:e1a608bb55e8	1374	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
jamesadevine	0:e1a608bb55e8	1375
jamesadevine	0:e1a608bb55e8	1376	/* MPU Region Base Address Register */
jamesadevine	0:e1a608bb55e8	1377	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
jamesadevine	0:e1a608bb55e8	1378	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
jamesadevine	0:e1a608bb55e8	1379
jamesadevine	0:e1a608bb55e8	1380	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
jamesadevine	0:e1a608bb55e8	1381	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
jamesadevine	0:e1a608bb55e8	1382
jamesadevine	0:e1a608bb55e8	1383	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
jamesadevine	0:e1a608bb55e8	1384	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
jamesadevine	0:e1a608bb55e8	1385
jamesadevine	0:e1a608bb55e8	1386	/* MPU Region Attribute and Size Register */
jamesadevine	0:e1a608bb55e8	1387	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
jamesadevine	0:e1a608bb55e8	1388	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
jamesadevine	0:e1a608bb55e8	1389
jamesadevine	0:e1a608bb55e8	1390	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
jamesadevine	0:e1a608bb55e8	1391	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
jamesadevine	0:e1a608bb55e8	1392
jamesadevine	0:e1a608bb55e8	1393	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
jamesadevine	0:e1a608bb55e8	1394	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
jamesadevine	0:e1a608bb55e8	1395
jamesadevine	0:e1a608bb55e8	1396	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
jamesadevine	0:e1a608bb55e8	1397	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
jamesadevine	0:e1a608bb55e8	1398
jamesadevine	0:e1a608bb55e8	1399	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
jamesadevine	0:e1a608bb55e8	1400	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
jamesadevine	0:e1a608bb55e8	1401
jamesadevine	0:e1a608bb55e8	1402	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
jamesadevine	0:e1a608bb55e8	1403	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
jamesadevine	0:e1a608bb55e8	1404
jamesadevine	0:e1a608bb55e8	1405	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
jamesadevine	0:e1a608bb55e8	1406	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
jamesadevine	0:e1a608bb55e8	1407
jamesadevine	0:e1a608bb55e8	1408	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
jamesadevine	0:e1a608bb55e8	1409	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
jamesadevine	0:e1a608bb55e8	1410
jamesadevine	0:e1a608bb55e8	1411	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
jamesadevine	0:e1a608bb55e8	1412	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
jamesadevine	0:e1a608bb55e8	1413
jamesadevine	0:e1a608bb55e8	1414	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
jamesadevine	0:e1a608bb55e8	1415	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
jamesadevine	0:e1a608bb55e8	1416
jamesadevine	0:e1a608bb55e8	1417	/@} end of group CMSIS_MPU /
jamesadevine	0:e1a608bb55e8	1418	#endif
jamesadevine	0:e1a608bb55e8	1419
jamesadevine	0:e1a608bb55e8	1420
jamesadevine	0:e1a608bb55e8	1421	#if (__FPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	1422	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	1423	\defgroup CMSIS_FPU Floating Point Unit (FPU)
jamesadevine	0:e1a608bb55e8	1424	\brief Type definitions for the Floating Point Unit (FPU)
jamesadevine	0:e1a608bb55e8	1425	@{
jamesadevine	0:e1a608bb55e8	1426	*/
jamesadevine	0:e1a608bb55e8	1427
jamesadevine	0:e1a608bb55e8	1428	/** \brief Structure type to access the Floating Point Unit (FPU).
jamesadevine	0:e1a608bb55e8	1429	*/
jamesadevine	0:e1a608bb55e8	1430	typedef struct
jamesadevine	0:e1a608bb55e8	1431	{
jamesadevine	0:e1a608bb55e8	1432	uint32_t RESERVED0[1];
jamesadevine	0:e1a608bb55e8	1433	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
jamesadevine	0:e1a608bb55e8	1434	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
jamesadevine	0:e1a608bb55e8	1435	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
jamesadevine	0:e1a608bb55e8	1436	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
jamesadevine	0:e1a608bb55e8	1437	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
jamesadevine	0:e1a608bb55e8	1438	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
jamesadevine	0:e1a608bb55e8	1439	} FPU_Type;
jamesadevine	0:e1a608bb55e8	1440
jamesadevine	0:e1a608bb55e8	1441	/* Floating-Point Context Control Register */
jamesadevine	0:e1a608bb55e8	1442	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
jamesadevine	0:e1a608bb55e8	1443	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
jamesadevine	0:e1a608bb55e8	1444
jamesadevine	0:e1a608bb55e8	1445	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
jamesadevine	0:e1a608bb55e8	1446	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
jamesadevine	0:e1a608bb55e8	1447
jamesadevine	0:e1a608bb55e8	1448	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
jamesadevine	0:e1a608bb55e8	1449	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
jamesadevine	0:e1a608bb55e8	1450
jamesadevine	0:e1a608bb55e8	1451	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
jamesadevine	0:e1a608bb55e8	1452	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
jamesadevine	0:e1a608bb55e8	1453
jamesadevine	0:e1a608bb55e8	1454	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
jamesadevine	0:e1a608bb55e8	1455	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
jamesadevine	0:e1a608bb55e8	1456
jamesadevine	0:e1a608bb55e8	1457	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
jamesadevine	0:e1a608bb55e8	1458	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
jamesadevine	0:e1a608bb55e8	1459
jamesadevine	0:e1a608bb55e8	1460	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
jamesadevine	0:e1a608bb55e8	1461	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
jamesadevine	0:e1a608bb55e8	1462
jamesadevine	0:e1a608bb55e8	1463	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
jamesadevine	0:e1a608bb55e8	1464	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
jamesadevine	0:e1a608bb55e8	1465
jamesadevine	0:e1a608bb55e8	1466	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
jamesadevine	0:e1a608bb55e8	1467	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
jamesadevine	0:e1a608bb55e8	1468
jamesadevine	0:e1a608bb55e8	1469	/* Floating-Point Context Address Register */
jamesadevine	0:e1a608bb55e8	1470	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
jamesadevine	0:e1a608bb55e8	1471	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
jamesadevine	0:e1a608bb55e8	1472
jamesadevine	0:e1a608bb55e8	1473	/* Floating-Point Default Status Control Register */
jamesadevine	0:e1a608bb55e8	1474	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
jamesadevine	0:e1a608bb55e8	1475	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
jamesadevine	0:e1a608bb55e8	1476
jamesadevine	0:e1a608bb55e8	1477	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
jamesadevine	0:e1a608bb55e8	1478	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
jamesadevine	0:e1a608bb55e8	1479
jamesadevine	0:e1a608bb55e8	1480	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
jamesadevine	0:e1a608bb55e8	1481	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
jamesadevine	0:e1a608bb55e8	1482
jamesadevine	0:e1a608bb55e8	1483	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
jamesadevine	0:e1a608bb55e8	1484	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
jamesadevine	0:e1a608bb55e8	1485
jamesadevine	0:e1a608bb55e8	1486	/* Media and FP Feature Register 0 */
jamesadevine	0:e1a608bb55e8	1487	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
jamesadevine	0:e1a608bb55e8	1488	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
jamesadevine	0:e1a608bb55e8	1489
jamesadevine	0:e1a608bb55e8	1490	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
jamesadevine	0:e1a608bb55e8	1491	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
jamesadevine	0:e1a608bb55e8	1492
jamesadevine	0:e1a608bb55e8	1493	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
jamesadevine	0:e1a608bb55e8	1494	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
jamesadevine	0:e1a608bb55e8	1495
jamesadevine	0:e1a608bb55e8	1496	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
jamesadevine	0:e1a608bb55e8	1497	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
jamesadevine	0:e1a608bb55e8	1498
jamesadevine	0:e1a608bb55e8	1499	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
jamesadevine	0:e1a608bb55e8	1500	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
jamesadevine	0:e1a608bb55e8	1501
jamesadevine	0:e1a608bb55e8	1502	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
jamesadevine	0:e1a608bb55e8	1503	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
jamesadevine	0:e1a608bb55e8	1504
jamesadevine	0:e1a608bb55e8	1505	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
jamesadevine	0:e1a608bb55e8	1506	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
jamesadevine	0:e1a608bb55e8	1507
jamesadevine	0:e1a608bb55e8	1508	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
jamesadevine	0:e1a608bb55e8	1509	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
jamesadevine	0:e1a608bb55e8	1510
jamesadevine	0:e1a608bb55e8	1511	/* Media and FP Feature Register 1 */
jamesadevine	0:e1a608bb55e8	1512	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
jamesadevine	0:e1a608bb55e8	1513	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
jamesadevine	0:e1a608bb55e8	1514
jamesadevine	0:e1a608bb55e8	1515	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
jamesadevine	0:e1a608bb55e8	1516	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
jamesadevine	0:e1a608bb55e8	1517
jamesadevine	0:e1a608bb55e8	1518	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
jamesadevine	0:e1a608bb55e8	1519	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
jamesadevine	0:e1a608bb55e8	1520
jamesadevine	0:e1a608bb55e8	1521	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
jamesadevine	0:e1a608bb55e8	1522	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
jamesadevine	0:e1a608bb55e8	1523
jamesadevine	0:e1a608bb55e8	1524	/* Media and FP Feature Register 2 */
jamesadevine	0:e1a608bb55e8	1525
jamesadevine	0:e1a608bb55e8	1526	/@} end of group CMSIS_FPU /
jamesadevine	0:e1a608bb55e8	1527	#endif
jamesadevine	0:e1a608bb55e8	1528
jamesadevine	0:e1a608bb55e8	1529
jamesadevine	0:e1a608bb55e8	1530	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	1531	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jamesadevine	0:e1a608bb55e8	1532	\brief Type definitions for the Core Debug Registers
jamesadevine	0:e1a608bb55e8	1533	@{
jamesadevine	0:e1a608bb55e8	1534	*/
jamesadevine	0:e1a608bb55e8	1535
jamesadevine	0:e1a608bb55e8	1536	/** \brief Structure type to access the Core Debug Register (CoreDebug).
jamesadevine	0:e1a608bb55e8	1537	*/
jamesadevine	0:e1a608bb55e8	1538	typedef struct
jamesadevine	0:e1a608bb55e8	1539	{
jamesadevine	0:e1a608bb55e8	1540	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
jamesadevine	0:e1a608bb55e8	1541	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
jamesadevine	0:e1a608bb55e8	1542	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
jamesadevine	0:e1a608bb55e8	1543	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
jamesadevine	0:e1a608bb55e8	1544	} CoreDebug_Type;
jamesadevine	0:e1a608bb55e8	1545
jamesadevine	0:e1a608bb55e8	1546	/* Debug Halting Control and Status Register */
jamesadevine	0:e1a608bb55e8	1547	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
jamesadevine	0:e1a608bb55e8	1548	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
jamesadevine	0:e1a608bb55e8	1549
jamesadevine	0:e1a608bb55e8	1550	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
jamesadevine	0:e1a608bb55e8	1551	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
jamesadevine	0:e1a608bb55e8	1552
jamesadevine	0:e1a608bb55e8	1553	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
jamesadevine	0:e1a608bb55e8	1554	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
jamesadevine	0:e1a608bb55e8	1555
jamesadevine	0:e1a608bb55e8	1556	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
jamesadevine	0:e1a608bb55e8	1557	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
jamesadevine	0:e1a608bb55e8	1558
jamesadevine	0:e1a608bb55e8	1559	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
jamesadevine	0:e1a608bb55e8	1560	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
jamesadevine	0:e1a608bb55e8	1561
jamesadevine	0:e1a608bb55e8	1562	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
jamesadevine	0:e1a608bb55e8	1563	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
jamesadevine	0:e1a608bb55e8	1564
jamesadevine	0:e1a608bb55e8	1565	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
jamesadevine	0:e1a608bb55e8	1566	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
jamesadevine	0:e1a608bb55e8	1567
jamesadevine	0:e1a608bb55e8	1568	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
jamesadevine	0:e1a608bb55e8	1569	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
jamesadevine	0:e1a608bb55e8	1570
jamesadevine	0:e1a608bb55e8	1571	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
jamesadevine	0:e1a608bb55e8	1572	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
jamesadevine	0:e1a608bb55e8	1573
jamesadevine	0:e1a608bb55e8	1574	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
jamesadevine	0:e1a608bb55e8	1575	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
jamesadevine	0:e1a608bb55e8	1576
jamesadevine	0:e1a608bb55e8	1577	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
jamesadevine	0:e1a608bb55e8	1578	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
jamesadevine	0:e1a608bb55e8	1579
jamesadevine	0:e1a608bb55e8	1580	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
jamesadevine	0:e1a608bb55e8	1581	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
jamesadevine	0:e1a608bb55e8	1582
jamesadevine	0:e1a608bb55e8	1583	/* Debug Core Register Selector Register */
jamesadevine	0:e1a608bb55e8	1584	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
jamesadevine	0:e1a608bb55e8	1585	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
jamesadevine	0:e1a608bb55e8	1586
jamesadevine	0:e1a608bb55e8	1587	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
jamesadevine	0:e1a608bb55e8	1588	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
jamesadevine	0:e1a608bb55e8	1589
jamesadevine	0:e1a608bb55e8	1590	/* Debug Exception and Monitor Control Register */
jamesadevine	0:e1a608bb55e8	1591	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
jamesadevine	0:e1a608bb55e8	1592	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
jamesadevine	0:e1a608bb55e8	1593
jamesadevine	0:e1a608bb55e8	1594	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
jamesadevine	0:e1a608bb55e8	1595	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
jamesadevine	0:e1a608bb55e8	1596
jamesadevine	0:e1a608bb55e8	1597	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
jamesadevine	0:e1a608bb55e8	1598	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
jamesadevine	0:e1a608bb55e8	1599
jamesadevine	0:e1a608bb55e8	1600	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
jamesadevine	0:e1a608bb55e8	1601	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
jamesadevine	0:e1a608bb55e8	1602
jamesadevine	0:e1a608bb55e8	1603	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
jamesadevine	0:e1a608bb55e8	1604	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
jamesadevine	0:e1a608bb55e8	1605
jamesadevine	0:e1a608bb55e8	1606	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
jamesadevine	0:e1a608bb55e8	1607	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
jamesadevine	0:e1a608bb55e8	1608
jamesadevine	0:e1a608bb55e8	1609	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
jamesadevine	0:e1a608bb55e8	1610	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
jamesadevine	0:e1a608bb55e8	1611
jamesadevine	0:e1a608bb55e8	1612	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
jamesadevine	0:e1a608bb55e8	1613	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
jamesadevine	0:e1a608bb55e8	1614
jamesadevine	0:e1a608bb55e8	1615	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
jamesadevine	0:e1a608bb55e8	1616	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
jamesadevine	0:e1a608bb55e8	1617
jamesadevine	0:e1a608bb55e8	1618	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
jamesadevine	0:e1a608bb55e8	1619	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
jamesadevine	0:e1a608bb55e8	1620
jamesadevine	0:e1a608bb55e8	1621	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
jamesadevine	0:e1a608bb55e8	1622	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
jamesadevine	0:e1a608bb55e8	1623
jamesadevine	0:e1a608bb55e8	1624	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
jamesadevine	0:e1a608bb55e8	1625	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
jamesadevine	0:e1a608bb55e8	1626
jamesadevine	0:e1a608bb55e8	1627	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
jamesadevine	0:e1a608bb55e8	1628	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
jamesadevine	0:e1a608bb55e8	1629
jamesadevine	0:e1a608bb55e8	1630	/@} end of group CMSIS_CoreDebug /
jamesadevine	0:e1a608bb55e8	1631
jamesadevine	0:e1a608bb55e8	1632
jamesadevine	0:e1a608bb55e8	1633	/** \ingroup CMSIS_core_register
jamesadevine	0:e1a608bb55e8	1634	\defgroup CMSIS_core_base Core Definitions
jamesadevine	0:e1a608bb55e8	1635	\brief Definitions for base addresses, unions, and structures.
jamesadevine	0:e1a608bb55e8	1636	@{
jamesadevine	0:e1a608bb55e8	1637	*/
jamesadevine	0:e1a608bb55e8	1638
jamesadevine	0:e1a608bb55e8	1639	/* Memory mapping of Cortex-M4 Hardware */
jamesadevine	0:e1a608bb55e8	1640	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
jamesadevine	0:e1a608bb55e8	1641	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
jamesadevine	0:e1a608bb55e8	1642	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
jamesadevine	0:e1a608bb55e8	1643	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
jamesadevine	0:e1a608bb55e8	1644	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
jamesadevine	0:e1a608bb55e8	1645	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
jamesadevine	0:e1a608bb55e8	1646	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
jamesadevine	0:e1a608bb55e8	1647	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
jamesadevine	0:e1a608bb55e8	1648
jamesadevine	0:e1a608bb55e8	1649	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
jamesadevine	0:e1a608bb55e8	1650	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
jamesadevine	0:e1a608bb55e8	1651	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
jamesadevine	0:e1a608bb55e8	1652	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
jamesadevine	0:e1a608bb55e8	1653	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
jamesadevine	0:e1a608bb55e8	1654	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
jamesadevine	0:e1a608bb55e8	1655	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
jamesadevine	0:e1a608bb55e8	1656	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
jamesadevine	0:e1a608bb55e8	1657
jamesadevine	0:e1a608bb55e8	1658	#if (__MPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	1659	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
jamesadevine	0:e1a608bb55e8	1660	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
jamesadevine	0:e1a608bb55e8	1661	#endif
jamesadevine	0:e1a608bb55e8	1662
jamesadevine	0:e1a608bb55e8	1663	#if (__FPU_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	1664	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
jamesadevine	0:e1a608bb55e8	1665	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
jamesadevine	0:e1a608bb55e8	1666	#endif
jamesadevine	0:e1a608bb55e8	1667
jamesadevine	0:e1a608bb55e8	1668	/@} /
jamesadevine	0:e1a608bb55e8	1669
jamesadevine	0:e1a608bb55e8	1670
jamesadevine	0:e1a608bb55e8	1671
jamesadevine	0:e1a608bb55e8	1672	/*******************************************************************************
jamesadevine	0:e1a608bb55e8	1673	* Hardware Abstraction Layer
jamesadevine	0:e1a608bb55e8	1674	Core Function Interface contains:
jamesadevine	0:e1a608bb55e8	1675	- Core NVIC Functions
jamesadevine	0:e1a608bb55e8	1676	- Core SysTick Functions
jamesadevine	0:e1a608bb55e8	1677	- Core Debug Functions
jamesadevine	0:e1a608bb55e8	1678	- Core Register Access Functions
jamesadevine	0:e1a608bb55e8	1679	******************************************************************************/
jamesadevine	0:e1a608bb55e8	1680	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jamesadevine	0:e1a608bb55e8	1681	*/
jamesadevine	0:e1a608bb55e8	1682
jamesadevine	0:e1a608bb55e8	1683
jamesadevine	0:e1a608bb55e8	1684
jamesadevine	0:e1a608bb55e8	1685	/* ########################## NVIC functions #################################### */
jamesadevine	0:e1a608bb55e8	1686	/** \ingroup CMSIS_Core_FunctionInterface
jamesadevine	0:e1a608bb55e8	1687	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
jamesadevine	0:e1a608bb55e8	1688	\brief Functions that manage interrupts and exceptions via the NVIC.
jamesadevine	0:e1a608bb55e8	1689	@{
jamesadevine	0:e1a608bb55e8	1690	*/
jamesadevine	0:e1a608bb55e8	1691
jamesadevine	0:e1a608bb55e8	1692	/** \brief Set Priority Grouping
jamesadevine	0:e1a608bb55e8	1693
jamesadevine	0:e1a608bb55e8	1694	The function sets the priority grouping field using the required unlock sequence.
jamesadevine	0:e1a608bb55e8	1695	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
jamesadevine	0:e1a608bb55e8	1696	Only values from 0..7 are used.
jamesadevine	0:e1a608bb55e8	1697	In case of a conflict between priority grouping and available
jamesadevine	0:e1a608bb55e8	1698	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
jamesadevine	0:e1a608bb55e8	1699
jamesadevine	0:e1a608bb55e8	1700	\param [in] PriorityGroup Priority grouping field.
jamesadevine	0:e1a608bb55e8	1701	*/
jamesadevine	0:e1a608bb55e8	1702	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
jamesadevine	0:e1a608bb55e8	1703	{
jamesadevine	0:e1a608bb55e8	1704	uint32_t reg_value;
jamesadevine	0:e1a608bb55e8	1705	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
jamesadevine	0:e1a608bb55e8	1706
jamesadevine	0:e1a608bb55e8	1707	reg_value = SCB->AIRCR; /* read old register configuration */
jamesadevine	0:e1a608bb55e8	1708	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
jamesadevine	0:e1a608bb55e8	1709	reg_value = (reg_value \|
jamesadevine	0:e1a608bb55e8	1710	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
jamesadevine	0:e1a608bb55e8	1711	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
jamesadevine	0:e1a608bb55e8	1712	SCB->AIRCR = reg_value;
jamesadevine	0:e1a608bb55e8	1713	}
jamesadevine	0:e1a608bb55e8	1714
jamesadevine	0:e1a608bb55e8	1715
jamesadevine	0:e1a608bb55e8	1716	/** \brief Get Priority Grouping
jamesadevine	0:e1a608bb55e8	1717
jamesadevine	0:e1a608bb55e8	1718	The function reads the priority grouping field from the NVIC Interrupt Controller.
jamesadevine	0:e1a608bb55e8	1719
jamesadevine	0:e1a608bb55e8	1720	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
jamesadevine	0:e1a608bb55e8	1721	*/
jamesadevine	0:e1a608bb55e8	1722	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
jamesadevine	0:e1a608bb55e8	1723	{
jamesadevine	0:e1a608bb55e8	1724	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
jamesadevine	0:e1a608bb55e8	1725	}
jamesadevine	0:e1a608bb55e8	1726
jamesadevine	0:e1a608bb55e8	1727
jamesadevine	0:e1a608bb55e8	1728	/** \brief Enable External Interrupt
jamesadevine	0:e1a608bb55e8	1729
jamesadevine	0:e1a608bb55e8	1730	The function enables a device-specific interrupt in the NVIC interrupt controller.
jamesadevine	0:e1a608bb55e8	1731
jamesadevine	0:e1a608bb55e8	1732	\param [in] IRQn External interrupt number. Value cannot be negative.
jamesadevine	0:e1a608bb55e8	1733	*/
jamesadevine	0:e1a608bb55e8	1734	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jamesadevine	0:e1a608bb55e8	1735	{
jamesadevine	0:e1a608bb55e8	1736	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
jamesadevine	0:e1a608bb55e8	1737	}
jamesadevine	0:e1a608bb55e8	1738
jamesadevine	0:e1a608bb55e8	1739
jamesadevine	0:e1a608bb55e8	1740	/** \brief Disable External Interrupt
jamesadevine	0:e1a608bb55e8	1741
jamesadevine	0:e1a608bb55e8	1742	The function disables a device-specific interrupt in the NVIC interrupt controller.
jamesadevine	0:e1a608bb55e8	1743
jamesadevine	0:e1a608bb55e8	1744	\param [in] IRQn External interrupt number. Value cannot be negative.
jamesadevine	0:e1a608bb55e8	1745	*/
jamesadevine	0:e1a608bb55e8	1746	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jamesadevine	0:e1a608bb55e8	1747	{
jamesadevine	0:e1a608bb55e8	1748	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
jamesadevine	0:e1a608bb55e8	1749	}
jamesadevine	0:e1a608bb55e8	1750
jamesadevine	0:e1a608bb55e8	1751
jamesadevine	0:e1a608bb55e8	1752	/** \brief Get Pending Interrupt
jamesadevine	0:e1a608bb55e8	1753
jamesadevine	0:e1a608bb55e8	1754	The function reads the pending register in the NVIC and returns the pending bit
jamesadevine	0:e1a608bb55e8	1755	for the specified interrupt.
jamesadevine	0:e1a608bb55e8	1756
jamesadevine	0:e1a608bb55e8	1757	\param [in] IRQn Interrupt number.
jamesadevine	0:e1a608bb55e8	1758
jamesadevine	0:e1a608bb55e8	1759	\return 0 Interrupt status is not pending.
jamesadevine	0:e1a608bb55e8	1760	\return 1 Interrupt status is pending.
jamesadevine	0:e1a608bb55e8	1761	*/
jamesadevine	0:e1a608bb55e8	1762	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jamesadevine	0:e1a608bb55e8	1763	{
jamesadevine	0:e1a608bb55e8	1764	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
jamesadevine	0:e1a608bb55e8	1765	}
jamesadevine	0:e1a608bb55e8	1766
jamesadevine	0:e1a608bb55e8	1767
jamesadevine	0:e1a608bb55e8	1768	/** \brief Set Pending Interrupt
jamesadevine	0:e1a608bb55e8	1769
jamesadevine	0:e1a608bb55e8	1770	The function sets the pending bit of an external interrupt.
jamesadevine	0:e1a608bb55e8	1771
jamesadevine	0:e1a608bb55e8	1772	\param [in] IRQn Interrupt number. Value cannot be negative.
jamesadevine	0:e1a608bb55e8	1773	*/
jamesadevine	0:e1a608bb55e8	1774	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jamesadevine	0:e1a608bb55e8	1775	{
jamesadevine	0:e1a608bb55e8	1776	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
jamesadevine	0:e1a608bb55e8	1777	}
jamesadevine	0:e1a608bb55e8	1778
jamesadevine	0:e1a608bb55e8	1779
jamesadevine	0:e1a608bb55e8	1780	/** \brief Clear Pending Interrupt
jamesadevine	0:e1a608bb55e8	1781
jamesadevine	0:e1a608bb55e8	1782	The function clears the pending bit of an external interrupt.
jamesadevine	0:e1a608bb55e8	1783
jamesadevine	0:e1a608bb55e8	1784	\param [in] IRQn External interrupt number. Value cannot be negative.
jamesadevine	0:e1a608bb55e8	1785	*/
jamesadevine	0:e1a608bb55e8	1786	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jamesadevine	0:e1a608bb55e8	1787	{
jamesadevine	0:e1a608bb55e8	1788	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
jamesadevine	0:e1a608bb55e8	1789	}
jamesadevine	0:e1a608bb55e8	1790
jamesadevine	0:e1a608bb55e8	1791
jamesadevine	0:e1a608bb55e8	1792	/** \brief Get Active Interrupt
jamesadevine	0:e1a608bb55e8	1793
jamesadevine	0:e1a608bb55e8	1794	The function reads the active register in NVIC and returns the active bit.
jamesadevine	0:e1a608bb55e8	1795
jamesadevine	0:e1a608bb55e8	1796	\param [in] IRQn Interrupt number.
jamesadevine	0:e1a608bb55e8	1797
jamesadevine	0:e1a608bb55e8	1798	\return 0 Interrupt status is not active.
jamesadevine	0:e1a608bb55e8	1799	\return 1 Interrupt status is active.
jamesadevine	0:e1a608bb55e8	1800	*/
jamesadevine	0:e1a608bb55e8	1801	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
jamesadevine	0:e1a608bb55e8	1802	{
jamesadevine	0:e1a608bb55e8	1803	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
jamesadevine	0:e1a608bb55e8	1804	}
jamesadevine	0:e1a608bb55e8	1805
jamesadevine	0:e1a608bb55e8	1806
jamesadevine	0:e1a608bb55e8	1807	/** \brief Set Interrupt Priority
jamesadevine	0:e1a608bb55e8	1808
jamesadevine	0:e1a608bb55e8	1809	The function sets the priority of an interrupt.
jamesadevine	0:e1a608bb55e8	1810
jamesadevine	0:e1a608bb55e8	1811	\note The priority cannot be set for every core interrupt.
jamesadevine	0:e1a608bb55e8	1812
jamesadevine	0:e1a608bb55e8	1813	\param [in] IRQn Interrupt number.
jamesadevine	0:e1a608bb55e8	1814	\param [in] priority Priority to set.
jamesadevine	0:e1a608bb55e8	1815	*/
jamesadevine	0:e1a608bb55e8	1816	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jamesadevine	0:e1a608bb55e8	1817	{
jamesadevine	0:e1a608bb55e8	1818	if((int32_t)IRQn < 0) {
jamesadevine	0:e1a608bb55e8	1819	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
jamesadevine	0:e1a608bb55e8	1820	}
jamesadevine	0:e1a608bb55e8	1821	else {
jamesadevine	0:e1a608bb55e8	1822	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
jamesadevine	0:e1a608bb55e8	1823	}
jamesadevine	0:e1a608bb55e8	1824	}
jamesadevine	0:e1a608bb55e8	1825
jamesadevine	0:e1a608bb55e8	1826
jamesadevine	0:e1a608bb55e8	1827	/** \brief Get Interrupt Priority
jamesadevine	0:e1a608bb55e8	1828
jamesadevine	0:e1a608bb55e8	1829	The function reads the priority of an interrupt. The interrupt
jamesadevine	0:e1a608bb55e8	1830	number can be positive to specify an external (device specific)
jamesadevine	0:e1a608bb55e8	1831	interrupt, or negative to specify an internal (core) interrupt.
jamesadevine	0:e1a608bb55e8	1832
jamesadevine	0:e1a608bb55e8	1833
jamesadevine	0:e1a608bb55e8	1834	\param [in] IRQn Interrupt number.
jamesadevine	0:e1a608bb55e8	1835	\return Interrupt Priority. Value is aligned automatically to the implemented
jamesadevine	0:e1a608bb55e8	1836	priority bits of the microcontroller.
jamesadevine	0:e1a608bb55e8	1837	*/
jamesadevine	0:e1a608bb55e8	1838	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jamesadevine	0:e1a608bb55e8	1839	{
jamesadevine	0:e1a608bb55e8	1840
jamesadevine	0:e1a608bb55e8	1841	if((int32_t)IRQn < 0) {
jamesadevine	0:e1a608bb55e8	1842	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
jamesadevine	0:e1a608bb55e8	1843	}
jamesadevine	0:e1a608bb55e8	1844	else {
jamesadevine	0:e1a608bb55e8	1845	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
jamesadevine	0:e1a608bb55e8	1846	}
jamesadevine	0:e1a608bb55e8	1847	}
jamesadevine	0:e1a608bb55e8	1848
jamesadevine	0:e1a608bb55e8	1849
jamesadevine	0:e1a608bb55e8	1850	/** \brief Encode Priority
jamesadevine	0:e1a608bb55e8	1851
jamesadevine	0:e1a608bb55e8	1852	The function encodes the priority for an interrupt with the given priority group,
jamesadevine	0:e1a608bb55e8	1853	preemptive priority value, and subpriority value.
jamesadevine	0:e1a608bb55e8	1854	In case of a conflict between priority grouping and available
jamesadevine	0:e1a608bb55e8	1855	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
jamesadevine	0:e1a608bb55e8	1856
jamesadevine	0:e1a608bb55e8	1857	\param [in] PriorityGroup Used priority group.
jamesadevine	0:e1a608bb55e8	1858	\param [in] PreemptPriority Preemptive priority value (starting from 0).
jamesadevine	0:e1a608bb55e8	1859	\param [in] SubPriority Subpriority value (starting from 0).
jamesadevine	0:e1a608bb55e8	1860	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
jamesadevine	0:e1a608bb55e8	1861	*/
jamesadevine	0:e1a608bb55e8	1862	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
jamesadevine	0:e1a608bb55e8	1863	{
jamesadevine	0:e1a608bb55e8	1864	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
jamesadevine	0:e1a608bb55e8	1865	uint32_t PreemptPriorityBits;
jamesadevine	0:e1a608bb55e8	1866	uint32_t SubPriorityBits;
jamesadevine	0:e1a608bb55e8	1867
jamesadevine	0:e1a608bb55e8	1868	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
jamesadevine	0:e1a608bb55e8	1869	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
jamesadevine	0:e1a608bb55e8	1870
jamesadevine	0:e1a608bb55e8	1871	return (
jamesadevine	0:e1a608bb55e8	1872	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
jamesadevine	0:e1a608bb55e8	1873	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
jamesadevine	0:e1a608bb55e8	1874	);
jamesadevine	0:e1a608bb55e8	1875	}
jamesadevine	0:e1a608bb55e8	1876
jamesadevine	0:e1a608bb55e8	1877
jamesadevine	0:e1a608bb55e8	1878	/** \brief Decode Priority
jamesadevine	0:e1a608bb55e8	1879
jamesadevine	0:e1a608bb55e8	1880	The function decodes an interrupt priority value with a given priority group to
jamesadevine	0:e1a608bb55e8	1881	preemptive priority value and subpriority value.
jamesadevine	0:e1a608bb55e8	1882	In case of a conflict between priority grouping and available
jamesadevine	0:e1a608bb55e8	1883	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
jamesadevine	0:e1a608bb55e8	1884
jamesadevine	0:e1a608bb55e8	1885	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
jamesadevine	0:e1a608bb55e8	1886	\param [in] PriorityGroup Used priority group.
jamesadevine	0:e1a608bb55e8	1887	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
jamesadevine	0:e1a608bb55e8	1888	\param [out] pSubPriority Subpriority value (starting from 0).
jamesadevine	0:e1a608bb55e8	1889	*/
jamesadevine	0:e1a608bb55e8	1890	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
jamesadevine	0:e1a608bb55e8	1891	{
jamesadevine	0:e1a608bb55e8	1892	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
jamesadevine	0:e1a608bb55e8	1893	uint32_t PreemptPriorityBits;
jamesadevine	0:e1a608bb55e8	1894	uint32_t SubPriorityBits;
jamesadevine	0:e1a608bb55e8	1895
jamesadevine	0:e1a608bb55e8	1896	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
jamesadevine	0:e1a608bb55e8	1897	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
jamesadevine	0:e1a608bb55e8	1898
jamesadevine	0:e1a608bb55e8	1899	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
jamesadevine	0:e1a608bb55e8	1900	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
jamesadevine	0:e1a608bb55e8	1901	}
jamesadevine	0:e1a608bb55e8	1902
jamesadevine	0:e1a608bb55e8	1903
jamesadevine	0:e1a608bb55e8	1904	/** \brief System Reset
jamesadevine	0:e1a608bb55e8	1905
jamesadevine	0:e1a608bb55e8	1906	The function initiates a system reset request to reset the MCU.
jamesadevine	0:e1a608bb55e8	1907	*/
jamesadevine	0:e1a608bb55e8	1908	__STATIC_INLINE void NVIC_SystemReset(void)
jamesadevine	0:e1a608bb55e8	1909	{
jamesadevine	0:e1a608bb55e8	1910	__DSB(); /* Ensure all outstanding memory accesses included
jamesadevine	0:e1a608bb55e8	1911	buffered write are completed before reset */
jamesadevine	0:e1a608bb55e8	1912	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
jamesadevine	0:e1a608bb55e8	1913	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
jamesadevine	0:e1a608bb55e8	1914	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
jamesadevine	0:e1a608bb55e8	1915	__DSB(); /* Ensure completion of memory access */
jamesadevine	0:e1a608bb55e8	1916	while(1) { __NOP(); } /* wait until reset */
jamesadevine	0:e1a608bb55e8	1917	}
jamesadevine	0:e1a608bb55e8	1918
jamesadevine	0:e1a608bb55e8	1919	/@} end of CMSIS_Core_NVICFunctions /
jamesadevine	0:e1a608bb55e8	1920
jamesadevine	0:e1a608bb55e8	1921
jamesadevine	0:e1a608bb55e8	1922	/* ########################## FPU functions #################################### */
jamesadevine	0:e1a608bb55e8	1923	/** \ingroup CMSIS_Core_FunctionInterface
jamesadevine	0:e1a608bb55e8	1924	\defgroup CMSIS_Core_FpuFunctions FPU Functions
jamesadevine	0:e1a608bb55e8	1925	\brief Function that provides FPU type.
jamesadevine	0:e1a608bb55e8	1926	@{
jamesadevine	0:e1a608bb55e8	1927	*/
jamesadevine	0:e1a608bb55e8	1928
jamesadevine	0:e1a608bb55e8	1929	/**
jamesadevine	0:e1a608bb55e8	1930	\fn uint32_t SCB_GetFPUType(void)
jamesadevine	0:e1a608bb55e8	1931	\brief get FPU type
jamesadevine	0:e1a608bb55e8	1932	\returns
jamesadevine	0:e1a608bb55e8	1933	- \b 0: No FPU
jamesadevine	0:e1a608bb55e8	1934	- \b 1: Single precision FPU
jamesadevine	0:e1a608bb55e8	1935	- \b 2: Double + Single precision FPU
jamesadevine	0:e1a608bb55e8	1936	*/
jamesadevine	0:e1a608bb55e8	1937	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
jamesadevine	0:e1a608bb55e8	1938	{
jamesadevine	0:e1a608bb55e8	1939	uint32_t mvfr0;
jamesadevine	0:e1a608bb55e8	1940
jamesadevine	0:e1a608bb55e8	1941	mvfr0 = SCB->MVFR0;
jamesadevine	0:e1a608bb55e8	1942	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
jamesadevine	0:e1a608bb55e8	1943	return 2UL; // Double + Single precision FPU
jamesadevine	0:e1a608bb55e8	1944	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
jamesadevine	0:e1a608bb55e8	1945	return 1UL; // Single precision FPU
jamesadevine	0:e1a608bb55e8	1946	} else {
jamesadevine	0:e1a608bb55e8	1947	return 0UL; // No FPU
jamesadevine	0:e1a608bb55e8	1948	}
jamesadevine	0:e1a608bb55e8	1949	}
jamesadevine	0:e1a608bb55e8	1950
jamesadevine	0:e1a608bb55e8	1951
jamesadevine	0:e1a608bb55e8	1952	/@} end of CMSIS_Core_FpuFunctions /
jamesadevine	0:e1a608bb55e8	1953
jamesadevine	0:e1a608bb55e8	1954
jamesadevine	0:e1a608bb55e8	1955
jamesadevine	0:e1a608bb55e8	1956	/* ########################## Cache functions #################################### */
jamesadevine	0:e1a608bb55e8	1957	/** \ingroup CMSIS_Core_FunctionInterface
jamesadevine	0:e1a608bb55e8	1958	\defgroup CMSIS_Core_CacheFunctions Cache Functions
jamesadevine	0:e1a608bb55e8	1959	\brief Functions that configure Instruction and Data cache.
jamesadevine	0:e1a608bb55e8	1960	@{
jamesadevine	0:e1a608bb55e8	1961	*/
jamesadevine	0:e1a608bb55e8	1962
jamesadevine	0:e1a608bb55e8	1963	/* Cache Size ID Register Macros */
jamesadevine	0:e1a608bb55e8	1964	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
jamesadevine	0:e1a608bb55e8	1965	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
jamesadevine	0:e1a608bb55e8	1966	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
jamesadevine	0:e1a608bb55e8	1967
jamesadevine	0:e1a608bb55e8	1968
jamesadevine	0:e1a608bb55e8	1969	/** \brief Enable I-Cache
jamesadevine	0:e1a608bb55e8	1970
jamesadevine	0:e1a608bb55e8	1971	The function turns on I-Cache
jamesadevine	0:e1a608bb55e8	1972	*/
jamesadevine	0:e1a608bb55e8	1973	__STATIC_INLINE void SCB_EnableICache (void)
jamesadevine	0:e1a608bb55e8	1974	{
jamesadevine	0:e1a608bb55e8	1975	#if (__ICACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	1976	__DSB();
jamesadevine	0:e1a608bb55e8	1977	__ISB();
jamesadevine	0:e1a608bb55e8	1978	SCB->ICIALLU = 0UL; // invalidate I-Cache
jamesadevine	0:e1a608bb55e8	1979	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
jamesadevine	0:e1a608bb55e8	1980	__DSB();
jamesadevine	0:e1a608bb55e8	1981	__ISB();
jamesadevine	0:e1a608bb55e8	1982	#endif
jamesadevine	0:e1a608bb55e8	1983	}
jamesadevine	0:e1a608bb55e8	1984
jamesadevine	0:e1a608bb55e8	1985
jamesadevine	0:e1a608bb55e8	1986	/** \brief Disable I-Cache
jamesadevine	0:e1a608bb55e8	1987
jamesadevine	0:e1a608bb55e8	1988	The function turns off I-Cache
jamesadevine	0:e1a608bb55e8	1989	*/
jamesadevine	0:e1a608bb55e8	1990	__STATIC_INLINE void SCB_DisableICache (void)
jamesadevine	0:e1a608bb55e8	1991	{
jamesadevine	0:e1a608bb55e8	1992	#if (__ICACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	1993	__DSB();
jamesadevine	0:e1a608bb55e8	1994	__ISB();
jamesadevine	0:e1a608bb55e8	1995	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
jamesadevine	0:e1a608bb55e8	1996	SCB->ICIALLU = 0UL; // invalidate I-Cache
jamesadevine	0:e1a608bb55e8	1997	__DSB();
jamesadevine	0:e1a608bb55e8	1998	__ISB();
jamesadevine	0:e1a608bb55e8	1999	#endif
jamesadevine	0:e1a608bb55e8	2000	}
jamesadevine	0:e1a608bb55e8	2001
jamesadevine	0:e1a608bb55e8	2002
jamesadevine	0:e1a608bb55e8	2003	/** \brief Invalidate I-Cache
jamesadevine	0:e1a608bb55e8	2004
jamesadevine	0:e1a608bb55e8	2005	The function invalidates I-Cache
jamesadevine	0:e1a608bb55e8	2006	*/
jamesadevine	0:e1a608bb55e8	2007	__STATIC_INLINE void SCB_InvalidateICache (void)
jamesadevine	0:e1a608bb55e8	2008	{
jamesadevine	0:e1a608bb55e8	2009	#if (__ICACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	2010	__DSB();
jamesadevine	0:e1a608bb55e8	2011	__ISB();
jamesadevine	0:e1a608bb55e8	2012	SCB->ICIALLU = 0UL;
jamesadevine	0:e1a608bb55e8	2013	__DSB();
jamesadevine	0:e1a608bb55e8	2014	__ISB();
jamesadevine	0:e1a608bb55e8	2015	#endif
jamesadevine	0:e1a608bb55e8	2016	}
jamesadevine	0:e1a608bb55e8	2017
jamesadevine	0:e1a608bb55e8	2018
jamesadevine	0:e1a608bb55e8	2019	/** \brief Enable D-Cache
jamesadevine	0:e1a608bb55e8	2020
jamesadevine	0:e1a608bb55e8	2021	The function turns on D-Cache
jamesadevine	0:e1a608bb55e8	2022	*/
jamesadevine	0:e1a608bb55e8	2023	__STATIC_INLINE void SCB_EnableDCache (void)
jamesadevine	0:e1a608bb55e8	2024	{
jamesadevine	0:e1a608bb55e8	2025	#if (__DCACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	2026	uint32_t ccsidr, sshift, wshift, sw;
jamesadevine	0:e1a608bb55e8	2027	uint32_t sets, ways;
jamesadevine	0:e1a608bb55e8	2028
jamesadevine	0:e1a608bb55e8	2029	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
jamesadevine	0:e1a608bb55e8	2030	ccsidr = SCB->CCSIDR;
jamesadevine	0:e1a608bb55e8	2031	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jamesadevine	0:e1a608bb55e8	2032	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jamesadevine	0:e1a608bb55e8	2033	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jamesadevine	0:e1a608bb55e8	2034	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jamesadevine	0:e1a608bb55e8	2035
jamesadevine	0:e1a608bb55e8	2036	__DSB();
jamesadevine	0:e1a608bb55e8	2037
jamesadevine	0:e1a608bb55e8	2038	do { // invalidate D-Cache
jamesadevine	0:e1a608bb55e8	2039	uint32_t tmpways = ways;
jamesadevine	0:e1a608bb55e8	2040	do {
jamesadevine	0:e1a608bb55e8	2041	sw = ((tmpways << wshift) \| (sets << sshift));
jamesadevine	0:e1a608bb55e8	2042	SCB->DCISW = sw;
jamesadevine	0:e1a608bb55e8	2043	} while(tmpways--);
jamesadevine	0:e1a608bb55e8	2044	} while(sets--);
jamesadevine	0:e1a608bb55e8	2045	__DSB();
jamesadevine	0:e1a608bb55e8	2046
jamesadevine	0:e1a608bb55e8	2047	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
jamesadevine	0:e1a608bb55e8	2048
jamesadevine	0:e1a608bb55e8	2049	__DSB();
jamesadevine	0:e1a608bb55e8	2050	__ISB();
jamesadevine	0:e1a608bb55e8	2051	#endif
jamesadevine	0:e1a608bb55e8	2052	}
jamesadevine	0:e1a608bb55e8	2053
jamesadevine	0:e1a608bb55e8	2054
jamesadevine	0:e1a608bb55e8	2055	/** \brief Disable D-Cache
jamesadevine	0:e1a608bb55e8	2056
jamesadevine	0:e1a608bb55e8	2057	The function turns off D-Cache
jamesadevine	0:e1a608bb55e8	2058	*/
jamesadevine	0:e1a608bb55e8	2059	__STATIC_INLINE void SCB_DisableDCache (void)
jamesadevine	0:e1a608bb55e8	2060	{
jamesadevine	0:e1a608bb55e8	2061	#if (__DCACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	2062	uint32_t ccsidr, sshift, wshift, sw;
jamesadevine	0:e1a608bb55e8	2063	uint32_t sets, ways;
jamesadevine	0:e1a608bb55e8	2064
jamesadevine	0:e1a608bb55e8	2065	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
jamesadevine	0:e1a608bb55e8	2066	ccsidr = SCB->CCSIDR;
jamesadevine	0:e1a608bb55e8	2067	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jamesadevine	0:e1a608bb55e8	2068	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jamesadevine	0:e1a608bb55e8	2069	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jamesadevine	0:e1a608bb55e8	2070	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jamesadevine	0:e1a608bb55e8	2071
jamesadevine	0:e1a608bb55e8	2072	__DSB();
jamesadevine	0:e1a608bb55e8	2073
jamesadevine	0:e1a608bb55e8	2074	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
jamesadevine	0:e1a608bb55e8	2075
jamesadevine	0:e1a608bb55e8	2076	do { // clean & invalidate D-Cache
jamesadevine	0:e1a608bb55e8	2077	uint32_t tmpways = ways;
jamesadevine	0:e1a608bb55e8	2078	do {
jamesadevine	0:e1a608bb55e8	2079	sw = ((tmpways << wshift) \| (sets << sshift));
jamesadevine	0:e1a608bb55e8	2080	SCB->DCCISW = sw;
jamesadevine	0:e1a608bb55e8	2081	} while(tmpways--);
jamesadevine	0:e1a608bb55e8	2082	} while(sets--);
jamesadevine	0:e1a608bb55e8	2083
jamesadevine	0:e1a608bb55e8	2084
jamesadevine	0:e1a608bb55e8	2085	__DSB();
jamesadevine	0:e1a608bb55e8	2086	__ISB();
jamesadevine	0:e1a608bb55e8	2087	#endif
jamesadevine	0:e1a608bb55e8	2088	}
jamesadevine	0:e1a608bb55e8	2089
jamesadevine	0:e1a608bb55e8	2090
jamesadevine	0:e1a608bb55e8	2091	/** \brief Invalidate D-Cache
jamesadevine	0:e1a608bb55e8	2092
jamesadevine	0:e1a608bb55e8	2093	The function invalidates D-Cache
jamesadevine	0:e1a608bb55e8	2094	*/
jamesadevine	0:e1a608bb55e8	2095	__STATIC_INLINE void SCB_InvalidateDCache (void)
jamesadevine	0:e1a608bb55e8	2096	{
jamesadevine	0:e1a608bb55e8	2097	#if (__DCACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	2098	uint32_t ccsidr, sshift, wshift, sw;
jamesadevine	0:e1a608bb55e8	2099	uint32_t sets, ways;
jamesadevine	0:e1a608bb55e8	2100
jamesadevine	0:e1a608bb55e8	2101	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
jamesadevine	0:e1a608bb55e8	2102	ccsidr = SCB->CCSIDR;
jamesadevine	0:e1a608bb55e8	2103	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jamesadevine	0:e1a608bb55e8	2104	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jamesadevine	0:e1a608bb55e8	2105	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jamesadevine	0:e1a608bb55e8	2106	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jamesadevine	0:e1a608bb55e8	2107
jamesadevine	0:e1a608bb55e8	2108	__DSB();
jamesadevine	0:e1a608bb55e8	2109
jamesadevine	0:e1a608bb55e8	2110	do { // invalidate D-Cache
jamesadevine	0:e1a608bb55e8	2111	uint32_t tmpways = ways;
jamesadevine	0:e1a608bb55e8	2112	do {
jamesadevine	0:e1a608bb55e8	2113	sw = ((tmpways << wshift) \| (sets << sshift));
jamesadevine	0:e1a608bb55e8	2114	SCB->DCISW = sw;
jamesadevine	0:e1a608bb55e8	2115	} while(tmpways--);
jamesadevine	0:e1a608bb55e8	2116	} while(sets--);
jamesadevine	0:e1a608bb55e8	2117
jamesadevine	0:e1a608bb55e8	2118	__DSB();
jamesadevine	0:e1a608bb55e8	2119	__ISB();
jamesadevine	0:e1a608bb55e8	2120	#endif
jamesadevine	0:e1a608bb55e8	2121	}
jamesadevine	0:e1a608bb55e8	2122
jamesadevine	0:e1a608bb55e8	2123
jamesadevine	0:e1a608bb55e8	2124	/** \brief Clean D-Cache
jamesadevine	0:e1a608bb55e8	2125
jamesadevine	0:e1a608bb55e8	2126	The function cleans D-Cache
jamesadevine	0:e1a608bb55e8	2127	*/
jamesadevine	0:e1a608bb55e8	2128	__STATIC_INLINE void SCB_CleanDCache (void)
jamesadevine	0:e1a608bb55e8	2129	{
jamesadevine	0:e1a608bb55e8	2130	#if (__DCACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	2131	uint32_t ccsidr, sshift, wshift, sw;
jamesadevine	0:e1a608bb55e8	2132	uint32_t sets, ways;
jamesadevine	0:e1a608bb55e8	2133
jamesadevine	0:e1a608bb55e8	2134	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
jamesadevine	0:e1a608bb55e8	2135	ccsidr = SCB->CCSIDR;
jamesadevine	0:e1a608bb55e8	2136	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jamesadevine	0:e1a608bb55e8	2137	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jamesadevine	0:e1a608bb55e8	2138	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jamesadevine	0:e1a608bb55e8	2139	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jamesadevine	0:e1a608bb55e8	2140
jamesadevine	0:e1a608bb55e8	2141	__DSB();
jamesadevine	0:e1a608bb55e8	2142
jamesadevine	0:e1a608bb55e8	2143	do { // clean D-Cache
jamesadevine	0:e1a608bb55e8	2144	uint32_t tmpways = ways;
jamesadevine	0:e1a608bb55e8	2145	do {
jamesadevine	0:e1a608bb55e8	2146	sw = ((tmpways << wshift) \| (sets << sshift));
jamesadevine	0:e1a608bb55e8	2147	SCB->DCCSW = sw;
jamesadevine	0:e1a608bb55e8	2148	} while(tmpways--);
jamesadevine	0:e1a608bb55e8	2149	} while(sets--);
jamesadevine	0:e1a608bb55e8	2150
jamesadevine	0:e1a608bb55e8	2151	__DSB();
jamesadevine	0:e1a608bb55e8	2152	__ISB();
jamesadevine	0:e1a608bb55e8	2153	#endif
jamesadevine	0:e1a608bb55e8	2154	}
jamesadevine	0:e1a608bb55e8	2155
jamesadevine	0:e1a608bb55e8	2156
jamesadevine	0:e1a608bb55e8	2157	/** \brief Clean & Invalidate D-Cache
jamesadevine	0:e1a608bb55e8	2158
jamesadevine	0:e1a608bb55e8	2159	The function cleans and Invalidates D-Cache
jamesadevine	0:e1a608bb55e8	2160	*/
jamesadevine	0:e1a608bb55e8	2161	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
jamesadevine	0:e1a608bb55e8	2162	{
jamesadevine	0:e1a608bb55e8	2163	#if (__DCACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	2164	uint32_t ccsidr, sshift, wshift, sw;
jamesadevine	0:e1a608bb55e8	2165	uint32_t sets, ways;
jamesadevine	0:e1a608bb55e8	2166
jamesadevine	0:e1a608bb55e8	2167	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
jamesadevine	0:e1a608bb55e8	2168	ccsidr = SCB->CCSIDR;
jamesadevine	0:e1a608bb55e8	2169	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jamesadevine	0:e1a608bb55e8	2170	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jamesadevine	0:e1a608bb55e8	2171	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jamesadevine	0:e1a608bb55e8	2172	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jamesadevine	0:e1a608bb55e8	2173
jamesadevine	0:e1a608bb55e8	2174	__DSB();
jamesadevine	0:e1a608bb55e8	2175
jamesadevine	0:e1a608bb55e8	2176	do { // clean & invalidate D-Cache
jamesadevine	0:e1a608bb55e8	2177	uint32_t tmpways = ways;
jamesadevine	0:e1a608bb55e8	2178	do {
jamesadevine	0:e1a608bb55e8	2179	sw = ((tmpways << wshift) \| (sets << sshift));
jamesadevine	0:e1a608bb55e8	2180	SCB->DCCISW = sw;
jamesadevine	0:e1a608bb55e8	2181	} while(tmpways--);
jamesadevine	0:e1a608bb55e8	2182	} while(sets--);
jamesadevine	0:e1a608bb55e8	2183
jamesadevine	0:e1a608bb55e8	2184	__DSB();
jamesadevine	0:e1a608bb55e8	2185	__ISB();
jamesadevine	0:e1a608bb55e8	2186	#endif
jamesadevine	0:e1a608bb55e8	2187	}
jamesadevine	0:e1a608bb55e8	2188
jamesadevine	0:e1a608bb55e8	2189
jamesadevine	0:e1a608bb55e8	2190	/**
jamesadevine	0:e1a608bb55e8	2191	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
jamesadevine	0:e1a608bb55e8	2192	\brief D-Cache Invalidate by address
jamesadevine	0:e1a608bb55e8	2193	\param[in] addr address (aligned to 32-byte boundary)
jamesadevine	0:e1a608bb55e8	2194	\param[in] dsize size of memory block (in number of bytes)
jamesadevine	0:e1a608bb55e8	2195	*/
jamesadevine	0:e1a608bb55e8	2196	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
jamesadevine	0:e1a608bb55e8	2197	{
jamesadevine	0:e1a608bb55e8	2198	#if (__DCACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	2199	int32_t op_size = dsize;
jamesadevine	0:e1a608bb55e8	2200	uint32_t op_addr = (uint32_t)addr;
jamesadevine	0:e1a608bb55e8	2201	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
jamesadevine	0:e1a608bb55e8	2202
jamesadevine	0:e1a608bb55e8	2203	__DSB();
jamesadevine	0:e1a608bb55e8	2204
jamesadevine	0:e1a608bb55e8	2205	while (op_size > 0) {
jamesadevine	0:e1a608bb55e8	2206	SCB->DCIMVAC = op_addr;
jamesadevine	0:e1a608bb55e8	2207	op_addr += linesize;
jamesadevine	0:e1a608bb55e8	2208	op_size -= (int32_t)linesize;
jamesadevine	0:e1a608bb55e8	2209	}
jamesadevine	0:e1a608bb55e8	2210
jamesadevine	0:e1a608bb55e8	2211	__DSB();
jamesadevine	0:e1a608bb55e8	2212	__ISB();
jamesadevine	0:e1a608bb55e8	2213	#endif
jamesadevine	0:e1a608bb55e8	2214	}
jamesadevine	0:e1a608bb55e8	2215
jamesadevine	0:e1a608bb55e8	2216
jamesadevine	0:e1a608bb55e8	2217	/**
jamesadevine	0:e1a608bb55e8	2218	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
jamesadevine	0:e1a608bb55e8	2219	\brief D-Cache Clean by address
jamesadevine	0:e1a608bb55e8	2220	\param[in] addr address (aligned to 32-byte boundary)
jamesadevine	0:e1a608bb55e8	2221	\param[in] dsize size of memory block (in number of bytes)
jamesadevine	0:e1a608bb55e8	2222	*/
jamesadevine	0:e1a608bb55e8	2223	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
jamesadevine	0:e1a608bb55e8	2224	{
jamesadevine	0:e1a608bb55e8	2225	#if (__DCACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	2226	int32_t op_size = dsize;
jamesadevine	0:e1a608bb55e8	2227	uint32_t op_addr = (uint32_t) addr;
jamesadevine	0:e1a608bb55e8	2228	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
jamesadevine	0:e1a608bb55e8	2229
jamesadevine	0:e1a608bb55e8	2230	__DSB();
jamesadevine	0:e1a608bb55e8	2231
jamesadevine	0:e1a608bb55e8	2232	while (op_size > 0) {
jamesadevine	0:e1a608bb55e8	2233	SCB->DCCMVAC = op_addr;
jamesadevine	0:e1a608bb55e8	2234	op_addr += linesize;
jamesadevine	0:e1a608bb55e8	2235	op_size -= (int32_t)linesize;
jamesadevine	0:e1a608bb55e8	2236	}
jamesadevine	0:e1a608bb55e8	2237
jamesadevine	0:e1a608bb55e8	2238	__DSB();
jamesadevine	0:e1a608bb55e8	2239	__ISB();
jamesadevine	0:e1a608bb55e8	2240	#endif
jamesadevine	0:e1a608bb55e8	2241	}
jamesadevine	0:e1a608bb55e8	2242
jamesadevine	0:e1a608bb55e8	2243
jamesadevine	0:e1a608bb55e8	2244	/**
jamesadevine	0:e1a608bb55e8	2245	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
jamesadevine	0:e1a608bb55e8	2246	\brief D-Cache Clean and Invalidate by address
jamesadevine	0:e1a608bb55e8	2247	\param[in] addr address (aligned to 32-byte boundary)
jamesadevine	0:e1a608bb55e8	2248	\param[in] dsize size of memory block (in number of bytes)
jamesadevine	0:e1a608bb55e8	2249	*/
jamesadevine	0:e1a608bb55e8	2250	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
jamesadevine	0:e1a608bb55e8	2251	{
jamesadevine	0:e1a608bb55e8	2252	#if (__DCACHE_PRESENT == 1)
jamesadevine	0:e1a608bb55e8	2253	int32_t op_size = dsize;
jamesadevine	0:e1a608bb55e8	2254	uint32_t op_addr = (uint32_t) addr;
jamesadevine	0:e1a608bb55e8	2255	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
jamesadevine	0:e1a608bb55e8	2256
jamesadevine	0:e1a608bb55e8	2257	__DSB();
jamesadevine	0:e1a608bb55e8	2258
jamesadevine	0:e1a608bb55e8	2259	while (op_size > 0) {
jamesadevine	0:e1a608bb55e8	2260	SCB->DCCIMVAC = op_addr;
jamesadevine	0:e1a608bb55e8	2261	op_addr += linesize;
jamesadevine	0:e1a608bb55e8	2262	op_size -= (int32_t)linesize;
jamesadevine	0:e1a608bb55e8	2263	}
jamesadevine	0:e1a608bb55e8	2264
jamesadevine	0:e1a608bb55e8	2265	__DSB();
jamesadevine	0:e1a608bb55e8	2266	__ISB();
jamesadevine	0:e1a608bb55e8	2267	#endif
jamesadevine	0:e1a608bb55e8	2268	}
jamesadevine	0:e1a608bb55e8	2269
jamesadevine	0:e1a608bb55e8	2270
jamesadevine	0:e1a608bb55e8	2271	/@} end of CMSIS_Core_CacheFunctions /
jamesadevine	0:e1a608bb55e8	2272
jamesadevine	0:e1a608bb55e8	2273
jamesadevine	0:e1a608bb55e8	2274
jamesadevine	0:e1a608bb55e8	2275	/* ################################## SysTick function ############################################ */
jamesadevine	0:e1a608bb55e8	2276	/** \ingroup CMSIS_Core_FunctionInterface
jamesadevine	0:e1a608bb55e8	2277	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jamesadevine	0:e1a608bb55e8	2278	\brief Functions that configure the System.
jamesadevine	0:e1a608bb55e8	2279	@{
jamesadevine	0:e1a608bb55e8	2280	*/
jamesadevine	0:e1a608bb55e8	2281
jamesadevine	0:e1a608bb55e8	2282	#if (__Vendor_SysTickConfig == 0)
jamesadevine	0:e1a608bb55e8	2283
jamesadevine	0:e1a608bb55e8	2284	/** \brief System Tick Configuration
jamesadevine	0:e1a608bb55e8	2285
jamesadevine	0:e1a608bb55e8	2286	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jamesadevine	0:e1a608bb55e8	2287	Counter is in free running mode to generate periodic interrupts.
jamesadevine	0:e1a608bb55e8	2288
jamesadevine	0:e1a608bb55e8	2289	\param [in] ticks Number of ticks between two interrupts.
jamesadevine	0:e1a608bb55e8	2290
jamesadevine	0:e1a608bb55e8	2291	\return 0 Function succeeded.
jamesadevine	0:e1a608bb55e8	2292	\return 1 Function failed.
jamesadevine	0:e1a608bb55e8	2293
jamesadevine	0:e1a608bb55e8	2294	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jamesadevine	0:e1a608bb55e8	2295	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jamesadevine	0:e1a608bb55e8	2296	must contain a vendor-specific implementation of this function.
jamesadevine	0:e1a608bb55e8	2297
jamesadevine	0:e1a608bb55e8	2298	*/
jamesadevine	0:e1a608bb55e8	2299	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jamesadevine	0:e1a608bb55e8	2300	{
jamesadevine	0:e1a608bb55e8	2301	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
jamesadevine	0:e1a608bb55e8	2302
jamesadevine	0:e1a608bb55e8	2303	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
jamesadevine	0:e1a608bb55e8	2304	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
jamesadevine	0:e1a608bb55e8	2305	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
jamesadevine	0:e1a608bb55e8	2306	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
jamesadevine	0:e1a608bb55e8	2307	SysTick_CTRL_TICKINT_Msk \|
jamesadevine	0:e1a608bb55e8	2308	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jamesadevine	0:e1a608bb55e8	2309	return (0UL); /* Function successful */
jamesadevine	0:e1a608bb55e8	2310	}
jamesadevine	0:e1a608bb55e8	2311
jamesadevine	0:e1a608bb55e8	2312	#endif
jamesadevine	0:e1a608bb55e8	2313
jamesadevine	0:e1a608bb55e8	2314	/@} end of CMSIS_Core_SysTickFunctions /
jamesadevine	0:e1a608bb55e8	2315
jamesadevine	0:e1a608bb55e8	2316
jamesadevine	0:e1a608bb55e8	2317
jamesadevine	0:e1a608bb55e8	2318	/* ##################################### Debug In/Output function ########################################### */
jamesadevine	0:e1a608bb55e8	2319	/** \ingroup CMSIS_Core_FunctionInterface
jamesadevine	0:e1a608bb55e8	2320	\defgroup CMSIS_core_DebugFunctions ITM Functions
jamesadevine	0:e1a608bb55e8	2321	\brief Functions that access the ITM debug interface.
jamesadevine	0:e1a608bb55e8	2322	@{
jamesadevine	0:e1a608bb55e8	2323	*/
jamesadevine	0:e1a608bb55e8	2324
jamesadevine	0:e1a608bb55e8	2325	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
jamesadevine	0:e1a608bb55e8	2326	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
jamesadevine	0:e1a608bb55e8	2327
jamesadevine	0:e1a608bb55e8	2328
jamesadevine	0:e1a608bb55e8	2329	/** \brief ITM Send Character
jamesadevine	0:e1a608bb55e8	2330
jamesadevine	0:e1a608bb55e8	2331	The function transmits a character via the ITM channel 0, and
jamesadevine	0:e1a608bb55e8	2332	\li Just returns when no debugger is connected that has booked the output.
jamesadevine	0:e1a608bb55e8	2333	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
jamesadevine	0:e1a608bb55e8	2334
jamesadevine	0:e1a608bb55e8	2335	\param [in] ch Character to transmit.
jamesadevine	0:e1a608bb55e8	2336
jamesadevine	0:e1a608bb55e8	2337	\returns Character to transmit.
jamesadevine	0:e1a608bb55e8	2338	*/
jamesadevine	0:e1a608bb55e8	2339	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
jamesadevine	0:e1a608bb55e8	2340	{
jamesadevine	0:e1a608bb55e8	2341	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
jamesadevine	0:e1a608bb55e8	2342	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
jamesadevine	0:e1a608bb55e8	2343	{
jamesadevine	0:e1a608bb55e8	2344	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
jamesadevine	0:e1a608bb55e8	2345	ITM->PORT[0].u8 = (uint8_t)ch;
jamesadevine	0:e1a608bb55e8	2346	}
jamesadevine	0:e1a608bb55e8	2347	return (ch);
jamesadevine	0:e1a608bb55e8	2348	}
jamesadevine	0:e1a608bb55e8	2349
jamesadevine	0:e1a608bb55e8	2350
jamesadevine	0:e1a608bb55e8	2351	/** \brief ITM Receive Character
jamesadevine	0:e1a608bb55e8	2352
jamesadevine	0:e1a608bb55e8	2353	The function inputs a character via the external variable \ref ITM_RxBuffer.
jamesadevine	0:e1a608bb55e8	2354
jamesadevine	0:e1a608bb55e8	2355	\return Received character.
jamesadevine	0:e1a608bb55e8	2356	\return -1 No character pending.
jamesadevine	0:e1a608bb55e8	2357	*/
jamesadevine	0:e1a608bb55e8	2358	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
jamesadevine	0:e1a608bb55e8	2359	int32_t ch = -1; /* no character available */
jamesadevine	0:e1a608bb55e8	2360
jamesadevine	0:e1a608bb55e8	2361	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
jamesadevine	0:e1a608bb55e8	2362	ch = ITM_RxBuffer;
jamesadevine	0:e1a608bb55e8	2363	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
jamesadevine	0:e1a608bb55e8	2364	}
jamesadevine	0:e1a608bb55e8	2365
jamesadevine	0:e1a608bb55e8	2366	return (ch);
jamesadevine	0:e1a608bb55e8	2367	}
jamesadevine	0:e1a608bb55e8	2368
jamesadevine	0:e1a608bb55e8	2369
jamesadevine	0:e1a608bb55e8	2370	/** \brief ITM Check Character
jamesadevine	0:e1a608bb55e8	2371
jamesadevine	0:e1a608bb55e8	2372	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
jamesadevine	0:e1a608bb55e8	2373
jamesadevine	0:e1a608bb55e8	2374	\return 0 No character available.
jamesadevine	0:e1a608bb55e8	2375	\return 1 Character available.
jamesadevine	0:e1a608bb55e8	2376	*/
jamesadevine	0:e1a608bb55e8	2377	__STATIC_INLINE int32_t ITM_CheckChar (void) {
jamesadevine	0:e1a608bb55e8	2378
jamesadevine	0:e1a608bb55e8	2379	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
jamesadevine	0:e1a608bb55e8	2380	return (0); /* no character available */
jamesadevine	0:e1a608bb55e8	2381	} else {
jamesadevine	0:e1a608bb55e8	2382	return (1); /* character available */
jamesadevine	0:e1a608bb55e8	2383	}
jamesadevine	0:e1a608bb55e8	2384	}
jamesadevine	0:e1a608bb55e8	2385
jamesadevine	0:e1a608bb55e8	2386	/@} end of CMSIS_core_DebugFunctions /
jamesadevine	0:e1a608bb55e8	2387
jamesadevine	0:e1a608bb55e8	2388
jamesadevine	0:e1a608bb55e8	2389
jamesadevine	0:e1a608bb55e8	2390
jamesadevine	0:e1a608bb55e8	2391	#ifdef __cplusplus
jamesadevine	0:e1a608bb55e8	2392	}
jamesadevine	0:e1a608bb55e8	2393	#endif
jamesadevine	0:e1a608bb55e8	2394
jamesadevine	0:e1a608bb55e8	2395	#endif /* __CORE_CM7_H_DEPENDANT */
jamesadevine	0:e1a608bb55e8	2396
jamesadevine	0:e1a608bb55e8	2397	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	07 Apr 2016
Imports:	18
Forks:	1
Commits:	2
Dependents:	0
Dependencies:	0
Followers:	14

TARGET_NRF51_MICROBIT/core_cm7.h@1:a7c51b5e0534, 2016-04-07 (annotated)

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