LELEC2811 - I&S
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LSM6DSO
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Dependencies: X_NUCLEO_COMMON ST_INTERFACES
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lsm6dso_reg.c
00001 /* 00002 ****************************************************************************** 00003 * @file lsm6dso_reg.c 00004 * @author Sensor Solutions Software Team 00005 * @brief LSM6DSO driver file 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without 00012 * modification, are permitted provided that the following conditions 00013 * are met: 00014 * 1. Redistributions of source code must retain the above copyright notice, 00015 * this list of conditions and the following disclaimer. 00016 * 2. Redistributions in binary form must reproduce the above copyright 00017 * notice, this list of conditions and the following disclaimer in the 00018 * documentation and/or other materials provided with the distribution. 00019 * 3. Neither the name of STMicroelectronics nor the names of its 00020 * contributors may be used to endorse or promote products derived from 00021 * this software without specific prior written permission. 00022 * 00023 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00024 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00025 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00026 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 00027 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00028 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00029 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00030 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00031 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00032 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00033 * POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 */ 00036 00037 #include "lsm6dso_reg.h" 00038 00039 /** 00040 * @defgroup LSM6DSO 00041 * @brief This file provides a set of functions needed to drive the 00042 * lsm6dso enhanced inertial module. 00043 * @{ 00044 * 00045 */ 00046 00047 /** 00048 * @defgroup LSM6DSO_Interfaces_Functions 00049 * @brief This section provide a set of functions used to read and 00050 * write a generic register of the device. 00051 * MANDATORY: return 0 -> no Error. 00052 * @{ 00053 * 00054 */ 00055 00056 /** 00057 * @brief Read generic device register 00058 * 00059 * @param ctx read / write interface definitions(ptr) 00060 * @param reg register to read 00061 * @param data pointer to buffer that store the data read(ptr) 00062 * @param len number of consecutive register to read 00063 * @retval interface status (MANDATORY: return 0 -> no Error) 00064 * 00065 */ 00066 int32_t lsm6dso_read_reg(lsm6dso_ctx_t *ctx, uint8_t reg, uint8_t *data, 00067 uint16_t len) 00068 { 00069 int32_t ret; 00070 ret = ctx->read_reg(ctx->handle, reg, data, len); 00071 return ret; 00072 } 00073 00074 /** 00075 * @brief Write generic device register 00076 * 00077 * @param ctx read / write interface definitions(ptr) 00078 * @param reg register to write 00079 * @param data pointer to data to write in register reg(ptr) 00080 * @param len number of consecutive register to write 00081 * @retval interface status (MANDATORY: return 0 -> no Error) 00082 * 00083 */ 00084 int32_t lsm6dso_write_reg(lsm6dso_ctx_t *ctx, uint8_t reg, uint8_t *data, 00085 uint16_t len) 00086 { 00087 int32_t ret; 00088 ret = ctx->write_reg(ctx->handle, reg, data, len); 00089 return ret; 00090 } 00091 00092 /** 00093 * @} 00094 * 00095 */ 00096 00097 /** 00098 * @defgroup LSM6DSO_Sensitivity 00099 * @brief These functions convert raw-data into engineering units. 00100 * @{ 00101 * 00102 */ 00103 float_t lsm6dso_from_fs2_to_mg(int16_t lsb) 00104 { 00105 return ((float_t)lsb) * 0.061f; 00106 } 00107 00108 float_t lsm6dso_from_fs4_to_mg(int16_t lsb) 00109 { 00110 return ((float_t)lsb) * 0.122f; 00111 } 00112 00113 float_t lsm6dso_from_fs8_to_mg(int16_t lsb) 00114 { 00115 return ((float_t)lsb) * 0.244f; 00116 } 00117 00118 float_t lsm6dso_from_fs16_to_mg(int16_t lsb) 00119 { 00120 return ((float_t)lsb) * 0.488f; 00121 } 00122 00123 float_t lsm6dso_from_fs125_to_mdps(int16_t lsb) 00124 { 00125 return ((float_t)lsb) * 4.375f; 00126 } 00127 00128 float_t lsm6dso_from_fs500_to_mdps(int16_t lsb) 00129 { 00130 return ((float_t)lsb) * 17.50f; 00131 } 00132 00133 float_t lsm6dso_from_fs250_to_mdps(int16_t lsb) 00134 { 00135 return ((float_t)lsb) * 8.750f; 00136 } 00137 00138 float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb) 00139 { 00140 return ((float_t)lsb) * 35.0f; 00141 } 00142 00143 float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb) 00144 { 00145 return ((float_t)lsb) * 70.0f; 00146 } 00147 00148 float_t lsm6dso_from_lsb_to_celsius(int16_t lsb) 00149 { 00150 return (((float_t)lsb / 256.0f) + 25.0f); 00151 } 00152 00153 float_t lsm6dso_from_lsb_to_nsec(int16_t lsb) 00154 { 00155 return ((float_t)lsb * 25000.0f); 00156 } 00157 00158 /** 00159 * @} 00160 * 00161 */ 00162 00163 /** 00164 * @defgroup LSM6DSO_Data_Generation 00165 * @brief This section groups all the functions concerning 00166 * data generation. 00167 * 00168 */ 00169 00170 /** 00171 * @brief Accelerometer full-scale selection.[set] 00172 * 00173 * @param ctx read / write interface definitions 00174 * @param val change the values of fs_xl in reg CTRL1_XL 00175 * 00176 */ 00177 int32_t lsm6dso_xl_full_scale_set(lsm6dso_ctx_t *ctx, 00178 lsm6dso_fs_xl_t val) 00179 { 00180 lsm6dso_ctrl1_xl_t reg; 00181 int32_t ret; 00182 00183 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1); 00184 if (ret == 0) { 00185 reg.fs_xl = (uint8_t) val; 00186 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1); 00187 } 00188 return ret; 00189 } 00190 00191 /** 00192 * @brief Accelerometer full-scale selection.[get] 00193 * 00194 * @param ctx read / write interface definitions 00195 * @param val Get the values of fs_xl in reg CTRL1_XL 00196 * 00197 */ 00198 int32_t lsm6dso_xl_full_scale_get(lsm6dso_ctx_t *ctx, lsm6dso_fs_xl_t *val) 00199 { 00200 lsm6dso_ctrl1_xl_t reg; 00201 int32_t ret; 00202 00203 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1); 00204 switch (reg.fs_xl) { 00205 case LSM6DSO_2g: 00206 *val = LSM6DSO_2g; 00207 break; 00208 case LSM6DSO_16g: 00209 *val = LSM6DSO_16g; 00210 break; 00211 case LSM6DSO_4g: 00212 *val = LSM6DSO_4g; 00213 break; 00214 case LSM6DSO_8g: 00215 *val = LSM6DSO_8g; 00216 break; 00217 default: 00218 *val = LSM6DSO_2g; 00219 break; 00220 } 00221 00222 return ret; 00223 } 00224 00225 /** 00226 * @brief Accelerometer UI data rate selection.[set] 00227 * 00228 * @param ctx read / write interface definitions 00229 * @param val change the values of odr_xl in reg CTRL1_XL 00230 * 00231 */ 00232 int32_t lsm6dso_xl_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t val) 00233 { 00234 lsm6dso_ctrl1_xl_t reg; 00235 int32_t ret; 00236 00237 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1); 00238 if (ret == 0) { 00239 reg.odr_xl = (uint8_t) val; 00240 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1); 00241 } 00242 return ret; 00243 } 00244 00245 /** 00246 * @brief Accelerometer UI data rate selection.[get] 00247 * 00248 * @param ctx read / write interface definitions 00249 * @param val Get the values of odr_xl in reg CTRL1_XL 00250 * 00251 */ 00252 int32_t lsm6dso_xl_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t *val) 00253 { 00254 lsm6dso_ctrl1_xl_t reg; 00255 int32_t ret; 00256 00257 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1); 00258 00259 switch (reg.odr_xl) { 00260 case LSM6DSO_XL_ODR_OFF: 00261 *val = LSM6DSO_XL_ODR_OFF; 00262 break; 00263 case LSM6DSO_XL_ODR_12Hz5: 00264 *val = LSM6DSO_XL_ODR_12Hz5; 00265 break; 00266 case LSM6DSO_XL_ODR_26Hz: 00267 *val = LSM6DSO_XL_ODR_26Hz; 00268 break; 00269 case LSM6DSO_XL_ODR_52Hz: 00270 *val = LSM6DSO_XL_ODR_52Hz; 00271 break; 00272 case LSM6DSO_XL_ODR_104Hz: 00273 *val = LSM6DSO_XL_ODR_104Hz; 00274 break; 00275 case LSM6DSO_XL_ODR_208Hz: 00276 *val = LSM6DSO_XL_ODR_208Hz; 00277 break; 00278 case LSM6DSO_XL_ODR_417Hz: 00279 *val = LSM6DSO_XL_ODR_417Hz; 00280 break; 00281 case LSM6DSO_XL_ODR_833Hz: 00282 *val = LSM6DSO_XL_ODR_833Hz; 00283 break; 00284 case LSM6DSO_XL_ODR_1667Hz: 00285 *val = LSM6DSO_XL_ODR_1667Hz; 00286 break; 00287 case LSM6DSO_XL_ODR_3333Hz: 00288 *val = LSM6DSO_XL_ODR_3333Hz; 00289 break; 00290 case LSM6DSO_XL_ODR_6667Hz: 00291 *val = LSM6DSO_XL_ODR_6667Hz; 00292 break; 00293 case LSM6DSO_XL_ODR_6Hz5: 00294 *val = LSM6DSO_XL_ODR_6Hz5; 00295 break; 00296 default: 00297 *val = LSM6DSO_XL_ODR_OFF; 00298 break; 00299 } 00300 return ret; 00301 } 00302 00303 /** 00304 * @brief Gyroscope UI chain full-scale selection.[set] 00305 * 00306 * @param ctx read / write interface definitions 00307 * @param val change the values of fs_g in reg CTRL2_G 00308 * 00309 */ 00310 int32_t lsm6dso_gy_full_scale_set(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t val) 00311 { 00312 lsm6dso_ctrl2_g_t reg; 00313 int32_t ret; 00314 00315 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1); 00316 if (ret == 0) { 00317 reg.fs_g = (uint8_t) val; 00318 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1); 00319 } 00320 00321 return ret; 00322 } 00323 00324 /** 00325 * @brief Gyroscope UI chain full-scale selection.[get] 00326 * 00327 * @param ctx read / write interface definitions 00328 * @param val Get the values of fs_g in reg CTRL2_G 00329 * 00330 */ 00331 int32_t lsm6dso_gy_full_scale_get(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t *val) 00332 { 00333 lsm6dso_ctrl2_g_t reg; 00334 int32_t ret; 00335 00336 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1); 00337 switch (reg.fs_g) { 00338 case LSM6DSO_250dps: 00339 *val = LSM6DSO_250dps; 00340 break; 00341 case LSM6DSO_125dps: 00342 *val = LSM6DSO_125dps; 00343 break; 00344 case LSM6DSO_500dps: 00345 *val = LSM6DSO_500dps; 00346 break; 00347 case LSM6DSO_1000dps: 00348 *val = LSM6DSO_1000dps; 00349 break; 00350 case LSM6DSO_2000dps: 00351 *val = LSM6DSO_2000dps; 00352 break; 00353 default: 00354 *val = LSM6DSO_250dps; 00355 break; 00356 } 00357 00358 return ret; 00359 } 00360 00361 /** 00362 * @brief Gyroscope UI data rate selection.[set] 00363 * 00364 * @param ctx read / write interface definitions 00365 * @param val change the values of odr_g in reg CTRL2_G 00366 * 00367 */ 00368 int32_t lsm6dso_gy_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t val) 00369 { 00370 lsm6dso_ctrl2_g_t reg; 00371 int32_t ret; 00372 00373 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1); 00374 if (ret == 0) { 00375 reg.odr_g = (uint8_t) val; 00376 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1); 00377 } 00378 00379 return ret; 00380 } 00381 00382 /** 00383 * @brief Gyroscope UI data rate selection.[get] 00384 * 00385 * @param ctx read / write interface definitions 00386 * @param val Get the values of odr_g in reg CTRL2_G 00387 * 00388 */ 00389 int32_t lsm6dso_gy_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t *val) 00390 { 00391 lsm6dso_ctrl2_g_t reg; 00392 int32_t ret; 00393 00394 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1); 00395 switch (reg.odr_g) { 00396 case LSM6DSO_GY_ODR_OFF: 00397 *val = LSM6DSO_GY_ODR_OFF; 00398 break; 00399 case LSM6DSO_GY_ODR_12Hz5: 00400 *val = LSM6DSO_GY_ODR_12Hz5; 00401 break; 00402 case LSM6DSO_GY_ODR_26Hz: 00403 *val = LSM6DSO_GY_ODR_26Hz; 00404 break; 00405 case LSM6DSO_GY_ODR_52Hz: 00406 *val = LSM6DSO_GY_ODR_52Hz; 00407 break; 00408 case LSM6DSO_GY_ODR_104Hz: 00409 *val = LSM6DSO_GY_ODR_104Hz; 00410 break; 00411 case LSM6DSO_GY_ODR_208Hz: 00412 *val = LSM6DSO_GY_ODR_208Hz; 00413 break; 00414 case LSM6DSO_GY_ODR_417Hz: 00415 *val = LSM6DSO_GY_ODR_417Hz; 00416 break; 00417 case LSM6DSO_GY_ODR_833Hz: 00418 *val = LSM6DSO_GY_ODR_833Hz; 00419 break; 00420 case LSM6DSO_GY_ODR_1667Hz: 00421 *val = LSM6DSO_GY_ODR_1667Hz; 00422 break; 00423 case LSM6DSO_GY_ODR_3333Hz: 00424 *val = LSM6DSO_GY_ODR_3333Hz; 00425 break; 00426 case LSM6DSO_GY_ODR_6667Hz: 00427 *val = LSM6DSO_GY_ODR_6667Hz; 00428 break; 00429 default: 00430 *val = LSM6DSO_GY_ODR_OFF; 00431 break; 00432 } 00433 return ret; 00434 } 00435 00436 /** 00437 * @brief Block data update.[set] 00438 * 00439 * @param ctx read / write interface definitions 00440 * @param val change the values of bdu in reg CTRL3_C 00441 * 00442 */ 00443 int32_t lsm6dso_block_data_update_set(lsm6dso_ctx_t *ctx, uint8_t val) 00444 { 00445 lsm6dso_ctrl3_c_t reg; 00446 int32_t ret; 00447 00448 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 00449 if (ret == 0) { 00450 reg.bdu = val; 00451 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 00452 } 00453 return ret; 00454 } 00455 00456 /** 00457 * @brief Block data update.[get] 00458 * 00459 * @param ctx read / write interface definitions 00460 * @param val change the values of bdu in reg CTRL3_C 00461 * 00462 */ 00463 int32_t lsm6dso_block_data_update_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00464 { 00465 lsm6dso_ctrl3_c_t reg; 00466 int32_t ret; 00467 00468 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 00469 *val = reg.bdu; 00470 00471 return ret; 00472 } 00473 00474 /** 00475 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), 00476 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set] 00477 * 00478 * @param ctx read / write interface definitions 00479 * @param val change the values of usr_off_w in reg CTRL6_C 00480 * 00481 */ 00482 int32_t lsm6dso_xl_offset_weight_set(lsm6dso_ctx_t *ctx, 00483 lsm6dso_usr_off_w_t val) 00484 { 00485 lsm6dso_ctrl6_c_t reg; 00486 int32_t ret; 00487 00488 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1); 00489 if (ret == 0) { 00490 reg.usr_off_w = (uint8_t)val; 00491 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1); 00492 } 00493 return ret; 00494 } 00495 00496 /** 00497 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), 00498 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get] 00499 * 00500 * @param ctx read / write interface definitions 00501 * @param val Get the values of usr_off_w in reg CTRL6_C 00502 * 00503 */ 00504 int32_t lsm6dso_xl_offset_weight_get(lsm6dso_ctx_t *ctx, 00505 lsm6dso_usr_off_w_t *val) 00506 { 00507 lsm6dso_ctrl6_c_t reg; 00508 int32_t ret; 00509 00510 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1); 00511 00512 switch (reg.usr_off_w) { 00513 case LSM6DSO_LSb_1mg: 00514 *val = LSM6DSO_LSb_1mg; 00515 break; 00516 case LSM6DSO_LSb_16mg: 00517 *val = LSM6DSO_LSb_16mg; 00518 break; 00519 default: 00520 *val = LSM6DSO_LSb_1mg; 00521 break; 00522 } 00523 return ret; 00524 } 00525 00526 /** 00527 * @brief Accelerometer power mode.[set] 00528 * 00529 * @param ctx read / write interface definitions 00530 * @param val change the values of xl_hm_mode in 00531 * reg CTRL6_C 00532 * 00533 */ 00534 int32_t lsm6dso_xl_power_mode_set(lsm6dso_ctx_t *ctx, 00535 lsm6dso_xl_hm_mode_t val) 00536 { 00537 lsm6dso_ctrl5_c_t ctrl5_c; 00538 lsm6dso_ctrl6_c_t ctrl6_c; 00539 int32_t ret; 00540 00541 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1); 00542 if (ret == 0) { 00543 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1; 00544 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1); 00545 } 00546 if (ret == 0) { 00547 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1); 00548 } 00549 if (ret == 0) { 00550 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U; 00551 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1); 00552 } 00553 return ret; 00554 } 00555 00556 /** 00557 * @brief Accelerometer power mode.[get] 00558 * 00559 * @param ctx read / write interface definitions 00560 * @param val Get the values of xl_hm_mode in reg CTRL6_C 00561 * 00562 */ 00563 int32_t lsm6dso_xl_power_mode_get(lsm6dso_ctx_t *ctx, 00564 lsm6dso_xl_hm_mode_t *val) 00565 { 00566 lsm6dso_ctrl5_c_t ctrl5_c; 00567 lsm6dso_ctrl6_c_t ctrl6_c; 00568 int32_t ret; 00569 00570 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1); 00571 if (ret == 0) { 00572 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1); 00573 switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode) { 00574 case LSM6DSO_HIGH_PERFORMANCE_MD: 00575 *val = LSM6DSO_HIGH_PERFORMANCE_MD; 00576 break; 00577 case LSM6DSO_LOW_NORMAL_POWER_MD: 00578 *val = LSM6DSO_LOW_NORMAL_POWER_MD; 00579 break; 00580 case LSM6DSO_ULTRA_LOW_POWER_MD: 00581 *val = LSM6DSO_ULTRA_LOW_POWER_MD; 00582 break; 00583 default: 00584 *val = LSM6DSO_HIGH_PERFORMANCE_MD; 00585 break; 00586 } 00587 } 00588 return ret; 00589 } 00590 00591 /** 00592 * @brief Operating mode for gyroscope.[set] 00593 * 00594 * @param ctx read / write interface definitions 00595 * @param val change the values of g_hm_mode in reg CTRL7_G 00596 * 00597 */ 00598 int32_t lsm6dso_gy_power_mode_set(lsm6dso_ctx_t *ctx, 00599 lsm6dso_g_hm_mode_t val) 00600 { 00601 lsm6dso_ctrl7_g_t reg; 00602 int32_t ret; 00603 00604 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 00605 if (ret == 0) { 00606 reg.g_hm_mode = (uint8_t)val; 00607 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 00608 } 00609 return ret; 00610 } 00611 00612 /** 00613 * @brief Operating mode for gyroscope.[get] 00614 * 00615 * @param ctx read / write interface definitions 00616 * @param val Get the values of g_hm_mode in reg CTRL7_G 00617 * 00618 */ 00619 int32_t lsm6dso_gy_power_mode_get(lsm6dso_ctx_t *ctx, 00620 lsm6dso_g_hm_mode_t *val) 00621 { 00622 lsm6dso_ctrl7_g_t reg; 00623 int32_t ret; 00624 00625 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 00626 switch (reg.g_hm_mode) { 00627 case LSM6DSO_GY_HIGH_PERFORMANCE: 00628 *val = LSM6DSO_GY_HIGH_PERFORMANCE; 00629 break; 00630 case LSM6DSO_GY_NORMAL: 00631 *val = LSM6DSO_GY_NORMAL; 00632 break; 00633 default: 00634 *val = LSM6DSO_GY_HIGH_PERFORMANCE; 00635 break; 00636 } 00637 return ret; 00638 } 00639 00640 /** 00641 * @brief Read all the interrupt flag of the device.[get] 00642 * 00643 * @param ctx read / write interface definitions 00644 * @param val registers ALL_INT_SRC; WAKE_UP_SRC; 00645 * TAP_SRC; D6D_SRC; STATUS_REG; 00646 * EMB_FUNC_STATUS; FSM_STATUS_A/B 00647 * 00648 */ 00649 int32_t lsm6dso_all_sources_get(lsm6dso_ctx_t *ctx, 00650 lsm6dso_all_sources_t *val) 00651 { 00652 int32_t ret; 00653 00654 ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC, 00655 (uint8_t *)&val->all_int_src, 1); 00656 if (ret == 0) { 00657 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_SRC, 00658 (uint8_t *)&val->wake_up_src, 1); 00659 } 00660 if (ret == 0) { 00661 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_SRC, 00662 (uint8_t *)&val->tap_src, 1); 00663 } 00664 if (ret == 0) { 00665 ret = lsm6dso_read_reg(ctx, LSM6DSO_D6D_SRC, 00666 (uint8_t *)&val->d6d_src, 1); 00667 } 00668 if (ret == 0) { 00669 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, 00670 (uint8_t *)&val->status_reg, 1); 00671 } 00672 if (ret == 0) { 00673 00674 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 00675 } 00676 if (ret == 0) { 00677 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, 00678 (uint8_t *)&val->emb_func_status, 1); 00679 } 00680 if (ret == 0) { 00681 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_STATUS_A, 00682 (uint8_t *)&val->fsm_status_a, 1); 00683 } 00684 if (ret == 0) { 00685 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_STATUS_B, 00686 (uint8_t *)&val->fsm_status_b, 1); 00687 } 00688 if (ret == 0) { 00689 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 00690 } 00691 return ret; 00692 } 00693 00694 /** 00695 * @brief The STATUS_REG register is read by the primary interface.[get] 00696 * 00697 * @param ctx read / write interface definitions 00698 * @param val register STATUS_REG 00699 * 00700 */ 00701 int32_t lsm6dso_status_reg_get(lsm6dso_ctx_t *ctx, lsm6dso_status_reg_t *val) 00702 { 00703 int32_t ret; 00704 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *) val, 1); 00705 return ret; 00706 } 00707 00708 /** 00709 * @brief Accelerometer new data available.[get] 00710 * 00711 * @param ctx read / write interface definitions 00712 * @param val change the values of xlda in reg STATUS_REG 00713 * 00714 */ 00715 int32_t lsm6dso_xl_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00716 { 00717 lsm6dso_status_reg_t reg; 00718 int32_t ret; 00719 00720 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1); 00721 *val = reg.xlda; 00722 00723 return ret; 00724 } 00725 00726 /** 00727 * @brief Gyroscope new data available.[get] 00728 * 00729 * @param ctx read / write interface definitions 00730 * @param val change the values of gda in reg STATUS_REG 00731 * 00732 */ 00733 int32_t lsm6dso_gy_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00734 { 00735 lsm6dso_status_reg_t reg; 00736 int32_t ret; 00737 00738 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1); 00739 *val = reg.gda; 00740 00741 return ret; 00742 } 00743 00744 /** 00745 * @brief Temperature new data available.[get] 00746 * 00747 * @param ctx read / write interface definitions 00748 * @param val change the values of tda in reg STATUS_REG 00749 * 00750 */ 00751 int32_t lsm6dso_temp_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00752 { 00753 lsm6dso_status_reg_t reg; 00754 int32_t ret; 00755 00756 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1); 00757 *val = reg.tda; 00758 00759 return ret; 00760 } 00761 00762 /** 00763 * @brief Accelerometer X-axis user offset correction expressed in 00764 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00765 * The value must be in the range [-127 127].[set] 00766 * 00767 * @param ctx read / write interface definitions 00768 * @param buff buffer that contains data to write 00769 * 00770 */ 00771 int32_t lsm6dso_xl_usr_offset_x_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 00772 { 00773 int32_t ret; 00774 ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1); 00775 return ret; 00776 } 00777 00778 /** 00779 * @brief Accelerometer X-axis user offset correction expressed in two’s 00780 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00781 * The value must be in the range [-127 127].[get] 00782 * 00783 * @param ctx read / write interface definitions 00784 * @param buff buffer that stores data read 00785 * 00786 */ 00787 int32_t lsm6dso_xl_usr_offset_x_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 00788 { 00789 int32_t ret; 00790 ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1); 00791 return ret; 00792 } 00793 00794 /** 00795 * @brief Accelerometer Y-axis user offset correction expressed in two’s 00796 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00797 * The value must be in the range [-127 127].[set] 00798 * 00799 * @param ctx read / write interface definitions 00800 * @param buff buffer that contains data to write 00801 * 00802 */ 00803 int32_t lsm6dso_xl_usr_offset_y_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 00804 { 00805 int32_t ret; 00806 ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1); 00807 return ret; 00808 } 00809 00810 /** 00811 * @brief Accelerometer Y-axis user offset correction expressed in two’s 00812 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00813 * The value must be in the range [-127 127].[get] 00814 * 00815 * @param ctx read / write interface definitions 00816 * @param buff buffer that stores data read 00817 * 00818 */ 00819 int32_t lsm6dso_xl_usr_offset_y_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 00820 { 00821 int32_t ret; 00822 ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1); 00823 return ret; 00824 } 00825 00826 /** 00827 * @brief Accelerometer Z-axis user offset correction expressed in two’s 00828 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00829 * The value must be in the range [-127 127].[set] 00830 * 00831 * @param ctx read / write interface definitions 00832 * @param buff buffer that contains data to write 00833 * 00834 */ 00835 int32_t lsm6dso_xl_usr_offset_z_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 00836 { 00837 int32_t ret; 00838 ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1); 00839 return ret; 00840 } 00841 00842 /** 00843 * @brief Accelerometer Z-axis user offset correction expressed in two’s 00844 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00845 * The value must be in the range [-127 127].[get] 00846 * 00847 * @param ctx read / write interface definitions 00848 * @param buff buffer that stores data read 00849 * 00850 */ 00851 int32_t lsm6dso_xl_usr_offset_z_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 00852 { 00853 int32_t ret; 00854 ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1); 00855 return ret; 00856 } 00857 00858 /** 00859 * @brief Enables user offset on out.[set] 00860 * 00861 * @param ctx read / write interface definitions 00862 * @param val change the values of usr_off_on_out in reg CTRL7_G 00863 * 00864 */ 00865 int32_t lsm6dso_xl_usr_offset_set(lsm6dso_ctx_t *ctx, uint8_t val) 00866 { 00867 lsm6dso_ctrl7_g_t reg; 00868 int32_t ret; 00869 00870 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 00871 if (ret == 0) { 00872 reg.usr_off_on_out = val; 00873 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 00874 } 00875 return ret; 00876 } 00877 00878 /** 00879 * @brief User offset on out flag.[get] 00880 * 00881 * @param ctx read / write interface definitions 00882 * @param val values of usr_off_on_out in reg CTRL7_G 00883 * 00884 */ 00885 int32_t lsm6dso_xl_usr_offset_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00886 { 00887 lsm6dso_ctrl7_g_t reg; 00888 int32_t ret; 00889 00890 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 00891 *val = reg.usr_off_on_out; 00892 00893 return ret; 00894 } 00895 00896 /** 00897 * @} 00898 * 00899 */ 00900 00901 /** 00902 * @defgroup LSM6DSO_Timestamp 00903 * @brief This section groups all the functions that manage the 00904 * timestamp generation. 00905 * @{ 00906 * 00907 */ 00908 00909 /** 00910 * @brief Enables timestamp counter.[set] 00911 * 00912 * @param ctx read / write interface definitions 00913 * @param val change the values of timestamp_en in reg CTRL10_C 00914 * 00915 */ 00916 int32_t lsm6dso_timestamp_set(lsm6dso_ctx_t *ctx, uint8_t val) 00917 { 00918 lsm6dso_ctrl10_c_t reg; 00919 int32_t ret; 00920 00921 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1); 00922 if (ret == 0) { 00923 reg.timestamp_en = val; 00924 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1); 00925 } 00926 return ret; 00927 } 00928 00929 /** 00930 * @brief Enables timestamp counter.[get] 00931 * 00932 * @param ctx read / write interface definitions 00933 * @param val change the values of timestamp_en in reg CTRL10_C 00934 * 00935 */ 00936 int32_t lsm6dso_timestamp_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00937 { 00938 lsm6dso_ctrl10_c_t reg; 00939 int32_t ret; 00940 00941 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1); 00942 *val = reg.timestamp_en; 00943 00944 return ret; 00945 } 00946 00947 /** 00948 * @brief Timestamp first data output register (r). 00949 * The value is expressed as a 32-bit word and the bit 00950 * resolution is 25 μs.[get] 00951 * 00952 * @param ctx read / write interface definitions 00953 * @param buff buffer that stores data read 00954 * 00955 */ 00956 int32_t lsm6dso_timestamp_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 00957 { 00958 int32_t ret; 00959 ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4); 00960 return ret; 00961 } 00962 00963 /** 00964 * @} 00965 * 00966 */ 00967 00968 /** 00969 * @defgroup LSM6DSO_Data output 00970 * @brief This section groups all the data output functions. 00971 * @{ 00972 * 00973 */ 00974 00975 /** 00976 * @brief Circular burst-mode (rounding) read of the output 00977 * registers.[set] 00978 * 00979 * @param ctx read / write interface definitions 00980 * @param val change the values of rounding in reg CTRL5_C 00981 * 00982 */ 00983 int32_t lsm6dso_rounding_mode_set(lsm6dso_ctx_t *ctx, 00984 lsm6dso_rounding_t val) 00985 { 00986 lsm6dso_ctrl5_c_t reg; 00987 int32_t ret; 00988 00989 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1); 00990 if (ret == 0) { 00991 reg.rounding = (uint8_t)val; 00992 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1); 00993 } 00994 return ret; 00995 } 00996 00997 /** 00998 * @brief Gyroscope UI chain full-scale selection.[get] 00999 * 01000 * @param ctx read / write interface definitions 01001 * @param val Get the values of rounding in reg CTRL5_C 01002 * 01003 */ 01004 int32_t lsm6dso_rounding_mode_get(lsm6dso_ctx_t *ctx, 01005 lsm6dso_rounding_t *val) 01006 { 01007 lsm6dso_ctrl5_c_t reg; 01008 int32_t ret; 01009 01010 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1); 01011 switch (reg.rounding) { 01012 case LSM6DSO_NO_ROUND: 01013 *val = LSM6DSO_NO_ROUND; 01014 break; 01015 case LSM6DSO_ROUND_XL: 01016 *val = LSM6DSO_ROUND_XL; 01017 break; 01018 case LSM6DSO_ROUND_GY: 01019 *val = LSM6DSO_ROUND_GY; 01020 break; 01021 case LSM6DSO_ROUND_GY_XL: 01022 *val = LSM6DSO_ROUND_GY_XL; 01023 break; 01024 default: 01025 *val = LSM6DSO_NO_ROUND; 01026 break; 01027 } 01028 return ret; 01029 } 01030 01031 /** 01032 * @brief Temperature data output register (r). 01033 * L and H registers together express a 16-bit word in two’s 01034 * complement.[get] 01035 * 01036 * @param ctx read / write interface definitions 01037 * @param buff buffer that stores data read 01038 * 01039 */ 01040 int32_t lsm6dso_temperature_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01041 { 01042 int32_t ret; 01043 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2); 01044 return ret; 01045 } 01046 01047 /** 01048 * @brief Angular rate sensor. The value is expressed as a 16-bit 01049 * word in two’s complement.[get] 01050 * 01051 * @param ctx read / write interface definitions 01052 * @param buff buffer that stores data read 01053 * 01054 */ 01055 int32_t lsm6dso_angular_rate_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01056 { 01057 int32_t ret; 01058 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6); 01059 return ret; 01060 } 01061 01062 /** 01063 * @brief Linear acceleration output register. 01064 * The value is expressed as a 16-bit word in two’s complement.[get] 01065 * 01066 * @param ctx read / write interface definitions 01067 * @param buff buffer that stores data read 01068 * 01069 */ 01070 int32_t lsm6dso_acceleration_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01071 { 01072 int32_t ret; 01073 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6); 01074 return ret; 01075 } 01076 01077 /** 01078 * @brief FIFO data output [get] 01079 * 01080 * @param ctx read / write interface definitions 01081 * @param buff buffer that stores data read 01082 * 01083 */ 01084 int32_t lsm6dso_fifo_out_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01085 { 01086 int32_t ret; 01087 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6); 01088 return ret; 01089 } 01090 01091 /** 01092 * @brief Step counter output register.[get] 01093 * 01094 * @param ctx read / write interface definitions 01095 * @param buff buffer that stores data read 01096 * 01097 */ 01098 int32_t lsm6dso_number_of_steps_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01099 { 01100 int32_t ret; 01101 01102 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01103 if (ret == 0) { 01104 ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2); 01105 } 01106 if (ret == 0) { 01107 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01108 } 01109 return ret; 01110 } 01111 01112 /** 01113 * @brief Reset step counter register.[get] 01114 * 01115 * @param ctx read / write interface definitions 01116 * 01117 */ 01118 int32_t lsm6dso_steps_reset(lsm6dso_ctx_t *ctx) 01119 { 01120 lsm6dso_emb_func_src_t reg; 01121 int32_t ret; 01122 01123 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01124 if (ret == 0) { 01125 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)®, 1); 01126 } 01127 if (ret == 0) { 01128 reg.pedo_rst_step = PROPERTY_ENABLE; 01129 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)®, 1); 01130 } 01131 if (ret == 0) { 01132 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01133 } 01134 return ret; 01135 } 01136 01137 /** 01138 * @} 01139 * 01140 */ 01141 01142 /** 01143 * @defgroup LSM6DSO_common 01144 * @brief This section groups common usefull functions. 01145 * @{ 01146 * 01147 */ 01148 01149 /** 01150 * @brief Difference in percentage of the effective ODR(and timestamp rate) 01151 * with respect to the typical. 01152 * Step: 0.15%. 8-bit format, 2's complement.[set] 01153 * 01154 * @param ctx read / write interface definitions 01155 * @param val change the values of freq_fine in reg 01156 * INTERNAL_FREQ_FINE 01157 * 01158 */ 01159 int32_t lsm6dso_odr_cal_reg_set(lsm6dso_ctx_t *ctx, uint8_t val) 01160 { 01161 lsm6dso_internal_freq_fine_t reg; 01162 int32_t ret; 01163 01164 ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t *)®, 1); 01165 if (ret == 0) { 01166 reg.freq_fine = val; 01167 ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, 01168 (uint8_t *)®, 1); 01169 } 01170 return ret; 01171 } 01172 01173 /** 01174 * @brief Difference in percentage of the effective ODR(and timestamp rate) 01175 * with respect to the typical. 01176 * Step: 0.15%. 8-bit format, 2's complement.[get] 01177 * 01178 * @param ctx read / write interface definitions 01179 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE 01180 * 01181 */ 01182 int32_t lsm6dso_odr_cal_reg_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01183 { 01184 lsm6dso_internal_freq_fine_t reg; 01185 int32_t ret; 01186 01187 ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t *)®, 1); 01188 *val = reg.freq_fine; 01189 01190 return ret; 01191 } 01192 01193 01194 /** 01195 * @brief Enable access to the embedded functions/sensor 01196 * hub configuration registers.[set] 01197 * 01198 * @param ctx read / write interface definitions 01199 * @param val change the values of reg_access in 01200 * reg FUNC_CFG_ACCESS 01201 * 01202 */ 01203 int32_t lsm6dso_mem_bank_set(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t val) 01204 { 01205 lsm6dso_func_cfg_access_t reg; 01206 int32_t ret; 01207 01208 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1); 01209 if (ret == 0) { 01210 reg.reg_access = (uint8_t)val; 01211 ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1); 01212 } 01213 return ret; 01214 } 01215 01216 /** 01217 * @brief Enable access to the embedded functions/sensor 01218 * hub configuration registers.[get] 01219 * 01220 * @param ctx read / write interface definitions 01221 * @param val Get the values of reg_access in 01222 * reg FUNC_CFG_ACCESS 01223 * 01224 */ 01225 int32_t lsm6dso_mem_bank_get(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t *val) 01226 { 01227 lsm6dso_func_cfg_access_t reg; 01228 int32_t ret; 01229 01230 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1); 01231 switch (reg.reg_access) { 01232 case LSM6DSO_USER_BANK: 01233 *val = LSM6DSO_USER_BANK; 01234 break; 01235 case LSM6DSO_SENSOR_HUB_BANK: 01236 *val = LSM6DSO_SENSOR_HUB_BANK; 01237 break; 01238 case LSM6DSO_EMBEDDED_FUNC_BANK: 01239 *val = LSM6DSO_EMBEDDED_FUNC_BANK; 01240 break; 01241 default: 01242 *val = LSM6DSO_USER_BANK; 01243 break; 01244 } 01245 return ret; 01246 } 01247 01248 /** 01249 * @brief Write a line(byte) in a page.[set] 01250 * 01251 * @param ctx read / write interface definitions 01252 * @param uint8_t address: page line address 01253 * @param val value to write 01254 * 01255 */ 01256 int32_t lsm6dso_ln_pg_write_byte(lsm6dso_ctx_t *ctx, uint16_t address, 01257 uint8_t *val) 01258 { 01259 lsm6dso_page_rw_t page_rw; 01260 lsm6dso_page_sel_t page_sel; 01261 lsm6dso_page_address_t page_address; 01262 int32_t ret; 01263 01264 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01265 01266 if (ret == 0) { 01267 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01268 } 01269 if (ret == 0) { 01270 page_rw.page_rw = 0x02; /* page_write enable */ 01271 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01272 } 01273 if (ret == 0) { 01274 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1); 01275 } 01276 01277 if (ret == 0) { 01278 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); 01279 page_sel.not_used_01 = 1; 01280 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1); 01281 } 01282 if (ret == 0) { 01283 page_address.page_addr = (uint8_t)address & 0xFFU; 01284 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS, 01285 (uint8_t *)&page_address, 1); 01286 } 01287 if (ret == 0) { 01288 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1); 01289 } 01290 if (ret == 0) { 01291 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01292 } 01293 if (ret == 0) { 01294 page_rw.page_rw = 0x00; /* page_write disable */ 01295 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01296 } 01297 if (ret == 0) { 01298 01299 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01300 } 01301 return ret; 01302 } 01303 01304 /** 01305 * @brief Write buffer in a page.[set] 01306 * 01307 * @param ctx read / write interface definitions 01308 * @param uint8_t address: page line address 01309 * @param uint8_t *buf: buffer to write 01310 * @param uint8_t len: buffer len 01311 * 01312 */ 01313 int32_t lsm6dso_ln_pg_write(lsm6dso_ctx_t *ctx, uint16_t address, 01314 uint8_t *buf, uint8_t len) 01315 { 01316 lsm6dso_page_rw_t page_rw; 01317 lsm6dso_page_sel_t page_sel; 01318 lsm6dso_page_address_t page_address; 01319 uint16_t addr_pointed; 01320 int32_t ret; 01321 uint8_t i ; 01322 01323 addr_pointed = address; 01324 01325 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01326 if (ret == 0) { 01327 01328 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01329 } 01330 if (ret == 0) { 01331 page_rw.page_rw = 0x02; /* page_write enable*/ 01332 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01333 } 01334 if (ret == 0) { 01335 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1); 01336 } 01337 if (ret == 0) { 01338 page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU); 01339 page_sel.not_used_01 = 1; 01340 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1); 01341 } 01342 if (ret == 0) { 01343 page_address.page_addr = (uint8_t)(addr_pointed & 0x00FFU); 01344 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS, 01345 (uint8_t *)&page_address, 1); 01346 } 01347 01348 if (ret == 0) { 01349 for (i = 0; ((i < len) && (ret == 0)); i++) { 01350 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1); 01351 addr_pointed++; 01352 /* Check if page wrap */ 01353 if (((addr_pointed % 0x0100U) == 0x00U) && (ret == 0)) { 01354 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *)&page_sel, 1); 01355 if (ret == 0) { 01356 page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU); 01357 page_sel.not_used_01 = 1; 01358 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, 01359 (uint8_t *)&page_sel, 1); 01360 } 01361 } 01362 } 01363 page_sel.page_sel = 0; 01364 page_sel.not_used_01 = 1; 01365 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1); 01366 } 01367 if (ret == 0) { 01368 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01369 } 01370 if (ret == 0) { 01371 page_rw.page_rw = 0x00; /* page_write disable */ 01372 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01373 } 01374 if (ret == 0) { 01375 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01376 } 01377 return ret; 01378 } 01379 01380 /** 01381 * @brief Read a line(byte) in a page.[get] 01382 * 01383 * @param ctx read / write interface definitions 01384 * @param uint8_t address: page line address 01385 * @param val read value 01386 * 01387 */ 01388 int32_t lsm6dso_ln_pg_read_byte(lsm6dso_ctx_t *ctx, uint16_t address, 01389 uint8_t *val) 01390 { 01391 lsm6dso_page_rw_t page_rw; 01392 lsm6dso_page_sel_t page_sel; 01393 lsm6dso_page_address_t page_address; 01394 int32_t ret; 01395 01396 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01397 if (ret == 0) { 01398 01399 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01400 } 01401 if (ret == 0) { 01402 page_rw.page_rw = 0x01; /* page_read enable*/ 01403 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01404 } 01405 if (ret == 0) { 01406 01407 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1); 01408 } 01409 if (ret == 0) { 01410 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); 01411 page_sel.not_used_01 = 1; 01412 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1); 01413 } 01414 if (ret == 0) { 01415 page_address.page_addr = (uint8_t)address & 0x00FFU; 01416 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS, 01417 (uint8_t *)&page_address, 1); 01418 } 01419 if (ret == 0) { 01420 01421 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, val, 2); 01422 } 01423 if (ret == 0) { 01424 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01425 } 01426 if (ret == 0) { 01427 page_rw.page_rw = 0x00; /* page_read disable */ 01428 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 01429 } 01430 if (ret == 0) { 01431 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01432 } 01433 01434 return ret; 01435 } 01436 01437 /** 01438 * @brief Data-ready pulsed / letched mode.[set] 01439 * 01440 * @param ctx read / write interface definitions 01441 * @param val change the values of 01442 * dataready_pulsed in 01443 * reg COUNTER_BDR_REG1 01444 * 01445 */ 01446 int32_t lsm6dso_data_ready_mode_set(lsm6dso_ctx_t *ctx, 01447 lsm6dso_dataready_pulsed_t val) 01448 { 01449 lsm6dso_counter_bdr_reg1_t reg; 01450 int32_t ret; 01451 01452 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1); 01453 if (ret == 0) { 01454 reg.dataready_pulsed = (uint8_t)val; 01455 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1); 01456 } 01457 return ret; 01458 } 01459 01460 /** 01461 * @brief Data-ready pulsed / letched mode.[get] 01462 * 01463 * @param ctx read / write interface definitions 01464 * @param val Get the values of 01465 * dataready_pulsed in 01466 * reg COUNTER_BDR_REG1 01467 * 01468 */ 01469 int32_t lsm6dso_data_ready_mode_get(lsm6dso_ctx_t *ctx, 01470 lsm6dso_dataready_pulsed_t *val) 01471 { 01472 lsm6dso_counter_bdr_reg1_t reg; 01473 int32_t ret; 01474 01475 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1); 01476 switch (reg.dataready_pulsed) { 01477 case LSM6DSO_DRDY_LATCHED: 01478 *val = LSM6DSO_DRDY_LATCHED; 01479 break; 01480 case LSM6DSO_DRDY_PULSED: 01481 *val = LSM6DSO_DRDY_PULSED; 01482 break; 01483 default: 01484 *val = LSM6DSO_DRDY_LATCHED; 01485 break; 01486 } 01487 return ret; 01488 } 01489 01490 /** 01491 * @brief Device "Who am I".[get] 01492 * 01493 * @param ctx read / write interface definitions 01494 * @param buff buffer that stores data read 01495 * 01496 */ 01497 int32_t lsm6dso_device_id_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01498 { 01499 int32_t ret; 01500 ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1); 01501 return ret; 01502 } 01503 01504 /** 01505 * @brief Software reset. Restore the default values 01506 * in user registers[set] 01507 * 01508 * @param ctx read / write interface definitions 01509 * @param val change the values of sw_reset in reg CTRL3_C 01510 * 01511 */ 01512 int32_t lsm6dso_reset_set(lsm6dso_ctx_t *ctx, uint8_t val) 01513 { 01514 lsm6dso_ctrl3_c_t reg; 01515 int32_t ret; 01516 01517 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 01518 if (ret == 0) { 01519 reg.sw_reset = val; 01520 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 01521 } 01522 01523 return ret; 01524 } 01525 01526 /** 01527 * @brief Software reset. Restore the default values in user registers.[get] 01528 * 01529 * @param ctx read / write interface definitions 01530 * @param val change the values of sw_reset in reg CTRL3_C 01531 * 01532 */ 01533 int32_t lsm6dso_reset_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01534 { 01535 lsm6dso_ctrl3_c_t reg; 01536 int32_t ret; 01537 01538 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 01539 *val = reg.sw_reset; 01540 01541 return ret; 01542 } 01543 01544 /** 01545 * @brief Register address automatically incremented during a multiple byte 01546 * access with a serial interface.[set] 01547 * 01548 * @param ctx read / write interface definitions 01549 * @param val change the values of if_inc in reg CTRL3_C 01550 * 01551 */ 01552 int32_t lsm6dso_auto_increment_set(lsm6dso_ctx_t *ctx, uint8_t val) 01553 { 01554 lsm6dso_ctrl3_c_t reg; 01555 int32_t ret; 01556 01557 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 01558 if (ret == 0) { 01559 reg.if_inc = val; 01560 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 01561 } 01562 return ret; 01563 } 01564 01565 /** 01566 * @brief Register address automatically incremented during a multiple byte 01567 * access with a serial interface.[get] 01568 * 01569 * @param ctx read / write interface definitions 01570 * @param val change the values of if_inc in reg CTRL3_C 01571 * 01572 */ 01573 int32_t lsm6dso_auto_increment_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01574 { 01575 lsm6dso_ctrl3_c_t reg; 01576 int32_t ret; 01577 01578 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 01579 *val = reg.if_inc; 01580 01581 return ret; 01582 } 01583 01584 /** 01585 * @brief Reboot memory content. Reload the calibration parameters.[set] 01586 * 01587 * @param ctx read / write interface definitions 01588 * @param val change the values of boot in reg CTRL3_C 01589 * 01590 */ 01591 int32_t lsm6dso_boot_set(lsm6dso_ctx_t *ctx, uint8_t val) 01592 { 01593 lsm6dso_ctrl3_c_t reg; 01594 int32_t ret; 01595 01596 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 01597 if (ret == 0) { 01598 reg.boot = val; 01599 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 01600 } 01601 return ret; 01602 } 01603 01604 /** 01605 * @brief Reboot memory content. Reload the calibration parameters.[get] 01606 * 01607 * @param ctx read / write interface definitions 01608 * @param val change the values of boot in reg CTRL3_C 01609 * 01610 */ 01611 int32_t lsm6dso_boot_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01612 { 01613 lsm6dso_ctrl3_c_t reg; 01614 int32_t ret; 01615 01616 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 01617 *val = reg.boot; 01618 01619 return ret; 01620 } 01621 01622 /** 01623 * @brief Linear acceleration sensor self-test enable.[set] 01624 * 01625 * @param ctx read / write interface definitions 01626 * @param val change the values of st_xl in reg CTRL5_C 01627 * 01628 */ 01629 int32_t lsm6dso_xl_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t val) 01630 { 01631 lsm6dso_ctrl5_c_t reg; 01632 int32_t ret; 01633 01634 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1); 01635 if (ret == 0) { 01636 reg.st_xl = (uint8_t)val; 01637 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1); 01638 } 01639 return ret; 01640 } 01641 01642 /** 01643 * @brief Linear acceleration sensor self-test enable.[get] 01644 * 01645 * @param ctx read / write interface definitions 01646 * @param val Get the values of st_xl in reg CTRL5_C 01647 * 01648 */ 01649 int32_t lsm6dso_xl_self_test_get(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t *val) 01650 { 01651 lsm6dso_ctrl5_c_t reg; 01652 int32_t ret; 01653 01654 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1); 01655 switch (reg.st_xl) { 01656 case LSM6DSO_XL_ST_DISABLE: 01657 *val = LSM6DSO_XL_ST_DISABLE; 01658 break; 01659 case LSM6DSO_XL_ST_POSITIVE: 01660 *val = LSM6DSO_XL_ST_POSITIVE; 01661 break; 01662 case LSM6DSO_XL_ST_NEGATIVE: 01663 *val = LSM6DSO_XL_ST_NEGATIVE; 01664 break; 01665 default: 01666 *val = LSM6DSO_XL_ST_DISABLE; 01667 break; 01668 } 01669 return ret; 01670 } 01671 01672 /** 01673 * @brief Angular rate sensor self-test enable.[set] 01674 * 01675 * @param ctx read / write interface definitions 01676 * @param val change the values of st_g in reg CTRL5_C 01677 * 01678 */ 01679 int32_t lsm6dso_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t val) 01680 { 01681 lsm6dso_ctrl5_c_t reg; 01682 int32_t ret; 01683 01684 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1); 01685 if (ret == 0) { 01686 reg.st_g = (uint8_t)val; 01687 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1); 01688 } 01689 return ret; 01690 } 01691 01692 /** 01693 * @brief Angular rate sensor self-test enable.[get] 01694 * 01695 * @param ctx read / write interface definitions 01696 * @param val Get the values of st_g in reg CTRL5_C 01697 * 01698 */ 01699 int32_t lsm6dso_gy_self_test_get(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t *val) 01700 { 01701 lsm6dso_ctrl5_c_t reg; 01702 int32_t ret; 01703 01704 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1); 01705 switch (reg.st_g) { 01706 case LSM6DSO_GY_ST_DISABLE: 01707 *val = LSM6DSO_GY_ST_DISABLE; 01708 break; 01709 case LSM6DSO_GY_ST_POSITIVE: 01710 *val = LSM6DSO_GY_ST_POSITIVE; 01711 break; 01712 case LSM6DSO_GY_ST_NEGATIVE: 01713 *val = LSM6DSO_GY_ST_NEGATIVE; 01714 break; 01715 default: 01716 *val = LSM6DSO_GY_ST_DISABLE; 01717 break; 01718 } 01719 return ret; 01720 } 01721 01722 /** 01723 * @} 01724 * 01725 */ 01726 01727 /** 01728 * @defgroup LSM6DSO_filters 01729 * @brief This section group all the functions concerning the 01730 * filters configuration 01731 * @{ 01732 * 01733 */ 01734 01735 /** 01736 * @brief Accelerometer output from LPF2 filtering stage selection.[set] 01737 * 01738 * @param ctx read / write interface definitions 01739 * @param val change the values of lpf2_xl_en in reg CTRL1_XL 01740 * 01741 */ 01742 int32_t lsm6dso_xl_filter_lp2_set(lsm6dso_ctx_t *ctx, uint8_t val) 01743 { 01744 lsm6dso_ctrl1_xl_t reg; 01745 int32_t ret; 01746 01747 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1); 01748 if (ret == 0) { 01749 reg.lpf2_xl_en = val; 01750 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1); 01751 } 01752 return ret; 01753 } 01754 01755 /** 01756 * @brief Accelerometer output from LPF2 filtering stage selection.[get] 01757 * 01758 * @param ctx read / write interface definitions 01759 * @param val change the values of lpf2_xl_en in reg CTRL1_XL 01760 * 01761 */ 01762 int32_t lsm6dso_xl_filter_lp2_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01763 { 01764 lsm6dso_ctrl1_xl_t reg; 01765 int32_t ret; 01766 01767 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1); 01768 *val = reg.lpf2_xl_en; 01769 01770 return ret; 01771 } 01772 01773 /** 01774 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; 01775 * the bandwidth can be selected through FTYPE [2:0] 01776 * in CTRL6_C (15h).[set] 01777 * 01778 * @param ctx read / write interface definitions 01779 * @param val change the values of lpf1_sel_g in reg CTRL4_C 01780 * 01781 */ 01782 int32_t lsm6dso_gy_filter_lp1_set(lsm6dso_ctx_t *ctx, uint8_t val) 01783 { 01784 lsm6dso_ctrl4_c_t reg; 01785 int32_t ret; 01786 01787 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 01788 if (ret == 0) { 01789 reg.lpf1_sel_g = val; 01790 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 01791 } 01792 return ret; 01793 } 01794 01795 /** 01796 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; 01797 * the bandwidth can be selected through FTYPE [2:0] 01798 * in CTRL6_C (15h).[get] 01799 * 01800 * @param ctx read / write interface definitions 01801 * @param val change the values of lpf1_sel_g in reg CTRL4_C 01802 * 01803 */ 01804 int32_t lsm6dso_gy_filter_lp1_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01805 { 01806 lsm6dso_ctrl4_c_t reg; 01807 int32_t ret; 01808 01809 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 01810 *val = reg.lpf1_sel_g; 01811 01812 return ret; 01813 } 01814 01815 /** 01816 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends 01817 * (XL and Gyro independently masked).[set] 01818 * 01819 * @param ctx read / write interface definitions 01820 * @param val change the values of drdy_mask in reg CTRL4_C 01821 * 01822 */ 01823 int32_t lsm6dso_filter_settling_mask_set(lsm6dso_ctx_t *ctx, uint8_t val) 01824 { 01825 lsm6dso_ctrl4_c_t reg; 01826 int32_t ret; 01827 01828 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 01829 if (ret == 0) { 01830 reg.drdy_mask = val; 01831 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 01832 } 01833 return ret; 01834 } 01835 01836 /** 01837 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends 01838 * (XL and Gyro independently masked).[get] 01839 * 01840 * @param ctx read / write interface definitions 01841 * @param val change the values of drdy_mask in reg CTRL4_C 01842 * 01843 */ 01844 int32_t lsm6dso_filter_settling_mask_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01845 { 01846 lsm6dso_ctrl4_c_t reg; 01847 int32_t ret; 01848 01849 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 01850 *val = reg.drdy_mask; 01851 01852 return ret; 01853 } 01854 01855 /** 01856 * @brief Gyroscope lp1 bandwidth.[set] 01857 * 01858 * @param ctx read / write interface definitions 01859 * @param val change the values of ftype in reg CTRL6_C 01860 * 01861 */ 01862 int32_t lsm6dso_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, lsm6dso_ftype_t val) 01863 { 01864 lsm6dso_ctrl6_c_t reg; 01865 int32_t ret; 01866 01867 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1); 01868 if (ret == 0) { 01869 reg.ftype = (uint8_t)val; 01870 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1); 01871 } 01872 return ret; 01873 } 01874 01875 /** 01876 * @brief Gyroscope lp1 bandwidth.[get] 01877 * 01878 * @param ctx read / write interface definitions 01879 * @param val Get the values of ftype in reg CTRL6_C 01880 * 01881 */ 01882 int32_t lsm6dso_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx, lsm6dso_ftype_t *val) 01883 { 01884 lsm6dso_ctrl6_c_t reg; 01885 int32_t ret; 01886 01887 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1); 01888 switch (reg.ftype) { 01889 case LSM6DSO_ULTRA_LIGHT: 01890 *val = LSM6DSO_ULTRA_LIGHT; 01891 break; 01892 case LSM6DSO_VERY_LIGHT: 01893 *val = LSM6DSO_VERY_LIGHT; 01894 break; 01895 case LSM6DSO_LIGHT: 01896 *val = LSM6DSO_LIGHT; 01897 break; 01898 case LSM6DSO_MEDIUM: 01899 *val = LSM6DSO_MEDIUM; 01900 break; 01901 case LSM6DSO_STRONG: 01902 *val = LSM6DSO_STRONG; 01903 break; 01904 case LSM6DSO_VERY_STRONG: 01905 *val = LSM6DSO_VERY_STRONG; 01906 break; 01907 case LSM6DSO_AGGRESSIVE: 01908 *val = LSM6DSO_AGGRESSIVE; 01909 break; 01910 case LSM6DSO_XTREME: 01911 *val = LSM6DSO_XTREME; 01912 break; 01913 default: 01914 *val = LSM6DSO_ULTRA_LIGHT; 01915 break; 01916 } 01917 return ret; 01918 } 01919 01920 /** 01921 * @brief Low pass filter 2 on 6D function selection.[set] 01922 * 01923 * @param ctx read / write interface definitions 01924 * @param val change the values of low_pass_on_6d in reg CTRL8_XL 01925 * 01926 */ 01927 int32_t lsm6dso_xl_lp2_on_6d_set(lsm6dso_ctx_t *ctx, uint8_t val) 01928 { 01929 lsm6dso_ctrl8_xl_t reg; 01930 int32_t ret; 01931 01932 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 01933 if (ret == 0) { 01934 reg.low_pass_on_6d = val; 01935 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 01936 } 01937 return ret; 01938 } 01939 01940 /** 01941 * @brief Low pass filter 2 on 6D function selection.[get] 01942 * 01943 * @param ctx read / write interface definitions 01944 * @param val change the values of low_pass_on_6d in reg CTRL8_XL 01945 * 01946 */ 01947 int32_t lsm6dso_xl_lp2_on_6d_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01948 { 01949 lsm6dso_ctrl8_xl_t reg; 01950 int32_t ret; 01951 01952 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 01953 *val = reg.low_pass_on_6d; 01954 01955 return ret; 01956 } 01957 01958 /** 01959 * @brief Accelerometer slope filter / high-pass filter selection 01960 * on output.[set] 01961 * 01962 * @param ctx read / write interface definitions 01963 * @param val change the values of hp_slope_xl_en 01964 * in reg CTRL8_XL 01965 * 01966 */ 01967 int32_t lsm6dso_xl_hp_path_on_out_set(lsm6dso_ctx_t *ctx, 01968 lsm6dso_hp_slope_xl_en_t val) 01969 { 01970 lsm6dso_ctrl8_xl_t reg; 01971 int32_t ret; 01972 01973 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 01974 if (ret == 0) { 01975 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4; 01976 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5; 01977 reg.hpcf_xl = (uint8_t)val & 0x07U; 01978 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 01979 } 01980 return ret; 01981 } 01982 01983 /** 01984 * @brief Accelerometer slope filter / high-pass filter selection 01985 * on output.[get] 01986 * 01987 * @param ctx read / write interface definitions 01988 * @param val Get the values of hp_slope_xl_en 01989 * in reg CTRL8_XL 01990 * 01991 */ 01992 int32_t lsm6dso_xl_hp_path_on_out_get(lsm6dso_ctx_t *ctx, 01993 lsm6dso_hp_slope_xl_en_t *val) 01994 { 01995 lsm6dso_ctrl8_xl_t reg; 01996 int32_t ret; 01997 01998 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 01999 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) | 02000 reg.hpcf_xl) { 02001 case LSM6DSO_HP_PATH_DISABLE_ON_OUT: 02002 *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT; 02003 break; 02004 case LSM6DSO_SLOPE_ODR_DIV_4: 02005 *val = LSM6DSO_SLOPE_ODR_DIV_4; 02006 break; 02007 case LSM6DSO_HP_ODR_DIV_10: 02008 *val = LSM6DSO_HP_ODR_DIV_10; 02009 break; 02010 case LSM6DSO_HP_ODR_DIV_20: 02011 *val = LSM6DSO_HP_ODR_DIV_20; 02012 break; 02013 case LSM6DSO_HP_ODR_DIV_45: 02014 *val = LSM6DSO_HP_ODR_DIV_45; 02015 break; 02016 case LSM6DSO_HP_ODR_DIV_100: 02017 *val = LSM6DSO_HP_ODR_DIV_100; 02018 break; 02019 case LSM6DSO_HP_ODR_DIV_200: 02020 *val = LSM6DSO_HP_ODR_DIV_200; 02021 break; 02022 case LSM6DSO_HP_ODR_DIV_400: 02023 *val = LSM6DSO_HP_ODR_DIV_400; 02024 break; 02025 case LSM6DSO_HP_ODR_DIV_800: 02026 *val = LSM6DSO_HP_ODR_DIV_800; 02027 break; 02028 case LSM6DSO_HP_REF_MD_ODR_DIV_10: 02029 *val = LSM6DSO_HP_REF_MD_ODR_DIV_10; 02030 break; 02031 case LSM6DSO_HP_REF_MD_ODR_DIV_20: 02032 *val = LSM6DSO_HP_REF_MD_ODR_DIV_20; 02033 break; 02034 case LSM6DSO_HP_REF_MD_ODR_DIV_45: 02035 *val = LSM6DSO_HP_REF_MD_ODR_DIV_45; 02036 break; 02037 case LSM6DSO_HP_REF_MD_ODR_DIV_100: 02038 *val = LSM6DSO_HP_REF_MD_ODR_DIV_100; 02039 break; 02040 case LSM6DSO_HP_REF_MD_ODR_DIV_200: 02041 *val = LSM6DSO_HP_REF_MD_ODR_DIV_200; 02042 break; 02043 case LSM6DSO_HP_REF_MD_ODR_DIV_400: 02044 *val = LSM6DSO_HP_REF_MD_ODR_DIV_400; 02045 break; 02046 case LSM6DSO_HP_REF_MD_ODR_DIV_800: 02047 *val = LSM6DSO_HP_REF_MD_ODR_DIV_800; 02048 break; 02049 case LSM6DSO_LP_ODR_DIV_10: 02050 *val = LSM6DSO_LP_ODR_DIV_10; 02051 break; 02052 case LSM6DSO_LP_ODR_DIV_20: 02053 *val = LSM6DSO_LP_ODR_DIV_20; 02054 break; 02055 case LSM6DSO_LP_ODR_DIV_45: 02056 *val = LSM6DSO_LP_ODR_DIV_45; 02057 break; 02058 case LSM6DSO_LP_ODR_DIV_100: 02059 *val = LSM6DSO_LP_ODR_DIV_100; 02060 break; 02061 case LSM6DSO_LP_ODR_DIV_200: 02062 *val = LSM6DSO_LP_ODR_DIV_200; 02063 break; 02064 case LSM6DSO_LP_ODR_DIV_400: 02065 *val = LSM6DSO_LP_ODR_DIV_400; 02066 break; 02067 case LSM6DSO_LP_ODR_DIV_800: 02068 *val = LSM6DSO_LP_ODR_DIV_800; 02069 break; 02070 default: 02071 *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT; 02072 break; 02073 } 02074 02075 return ret; 02076 } 02077 02078 /** 02079 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. 02080 * The filter sets the second samples after writing this bit. 02081 * Active only during device exit from power-down mode.[set] 02082 * 02083 * @param ctx read / write interface definitions 02084 * @param val change the values of fastsettl_mode_xl in 02085 * reg CTRL8_XL 02086 * 02087 */ 02088 int32_t lsm6dso_xl_fast_settling_set(lsm6dso_ctx_t *ctx, uint8_t val) 02089 { 02090 lsm6dso_ctrl8_xl_t reg; 02091 int32_t ret; 02092 02093 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 02094 if (ret == 0) { 02095 reg.fastsettl_mode_xl = val; 02096 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 02097 } 02098 return ret; 02099 } 02100 02101 /** 02102 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. 02103 * The filter sets the second samples after writing this bit. 02104 * Active only during device exit from power-down mode.[get] 02105 * 02106 * @param ctx read / write interface definitions 02107 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL 02108 * 02109 */ 02110 int32_t lsm6dso_xl_fast_settling_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02111 { 02112 lsm6dso_ctrl8_xl_t reg; 02113 int32_t ret; 02114 02115 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 02116 *val = reg.fastsettl_mode_xl; 02117 02118 return ret; 02119 } 02120 02121 /** 02122 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity 02123 * functions.[set] 02124 * 02125 * @param ctx read / write interface definitions 02126 * @param val change the values of slope_fds in reg TAP_CFG0 02127 * 02128 */ 02129 int32_t lsm6dso_xl_hp_path_internal_set(lsm6dso_ctx_t *ctx, 02130 lsm6dso_slope_fds_t val) 02131 { 02132 lsm6dso_tap_cfg0_t reg; 02133 int32_t ret; 02134 02135 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 02136 if (ret == 0) { 02137 reg.slope_fds = (uint8_t)val; 02138 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 02139 } 02140 return ret; 02141 } 02142 02143 /** 02144 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity 02145 * functions.[get] 02146 * 02147 * @param ctx read / write interface definitions 02148 * @param val Get the values of slope_fds in reg TAP_CFG0 02149 * 02150 */ 02151 int32_t lsm6dso_xl_hp_path_internal_get(lsm6dso_ctx_t *ctx, 02152 lsm6dso_slope_fds_t *val) 02153 { 02154 lsm6dso_tap_cfg0_t reg; 02155 int32_t ret; 02156 02157 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 02158 switch (reg.slope_fds) { 02159 case LSM6DSO_USE_SLOPE: 02160 *val = LSM6DSO_USE_SLOPE; 02161 break; 02162 case LSM6DSO_USE_HPF: 02163 *val = LSM6DSO_USE_HPF; 02164 break; 02165 default: 02166 *val = LSM6DSO_USE_SLOPE; 02167 break; 02168 } 02169 return ret; 02170 } 02171 02172 /** 02173 * @brief Enables gyroscope digital high-pass filter. The filter is 02174 * enabled only if the gyro is in HP mode.[set] 02175 * 02176 * @param ctx read / write interface definitions 02177 * @param val Get the values of hp_en_g and hp_en_g 02178 * in reg CTRL7_G 02179 * 02180 */ 02181 int32_t lsm6dso_gy_hp_path_internal_set(lsm6dso_ctx_t *ctx, 02182 lsm6dso_hpm_g_t val) 02183 { 02184 lsm6dso_ctrl7_g_t reg; 02185 int32_t ret; 02186 02187 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 02188 if (ret == 0) { 02189 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7; 02190 reg.hpm_g = (uint8_t)val & 0x03U; 02191 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 02192 } 02193 return ret; 02194 } 02195 02196 /** 02197 * @brief Enables gyroscope digital high-pass filter. The filter is 02198 * enabled only if the gyro is in HP mode.[get] 02199 * 02200 * @param ctx read / write interface definitions 02201 * @param val Get the values of hp_en_g and hp_en_g 02202 * in reg CTRL7_G 02203 * 02204 */ 02205 int32_t lsm6dso_gy_hp_path_internal_get(lsm6dso_ctx_t *ctx, 02206 lsm6dso_hpm_g_t *val) 02207 { 02208 lsm6dso_ctrl7_g_t reg; 02209 int32_t ret; 02210 02211 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 02212 switch ((reg.hp_en_g << 7) + reg.hpm_g) { 02213 case LSM6DSO_HP_FILTER_NONE: 02214 *val = LSM6DSO_HP_FILTER_NONE; 02215 break; 02216 case LSM6DSO_HP_FILTER_16mHz: 02217 *val = LSM6DSO_HP_FILTER_16mHz; 02218 break; 02219 case LSM6DSO_HP_FILTER_65mHz: 02220 *val = LSM6DSO_HP_FILTER_65mHz; 02221 break; 02222 case LSM6DSO_HP_FILTER_260mHz: 02223 *val = LSM6DSO_HP_FILTER_260mHz; 02224 break; 02225 case LSM6DSO_HP_FILTER_1Hz04: 02226 *val = LSM6DSO_HP_FILTER_1Hz04; 02227 break; 02228 default: 02229 *val = LSM6DSO_HP_FILTER_NONE; 02230 break; 02231 } 02232 return ret; 02233 } 02234 02235 /** 02236 * @} 02237 * 02238 */ 02239 02240 /** 02241 * @defgroup LSM6DSO_ Auxiliary_interface 02242 * @brief This section groups all the functions concerning 02243 * auxiliary interface. 02244 * @{ 02245 * 02246 */ 02247 02248 /** 02249 * @brief aOn auxiliary interface connect/disconnect SDO and OCS 02250 * internal pull-up.[set] 02251 * 02252 * @param ctx read / write interface definitions 02253 * @param val change the values of ois_pu_dis in 02254 * reg PIN_CTRL 02255 * 02256 */ 02257 int32_t lsm6dso_aux_sdo_ocs_mode_set(lsm6dso_ctx_t *ctx, 02258 lsm6dso_ois_pu_dis_t val) 02259 { 02260 lsm6dso_pin_ctrl_t reg; 02261 int32_t ret; 02262 02263 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1); 02264 if (ret == 0) { 02265 reg.ois_pu_dis = (uint8_t)val; 02266 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1); 02267 } 02268 return ret; 02269 } 02270 02271 /** 02272 * @brief On auxiliary interface connect/disconnect SDO and OCS 02273 * internal pull-up.[get] 02274 * 02275 * @param ctx read / write interface definitions 02276 * @param val Get the values of ois_pu_dis in reg PIN_CTRL 02277 * 02278 */ 02279 int32_t lsm6dso_aux_sdo_ocs_mode_get(lsm6dso_ctx_t *ctx, 02280 lsm6dso_ois_pu_dis_t *val) 02281 { 02282 lsm6dso_pin_ctrl_t reg; 02283 int32_t ret; 02284 02285 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1); 02286 switch (reg.ois_pu_dis) { 02287 case LSM6DSO_AUX_PULL_UP_DISC: 02288 *val = LSM6DSO_AUX_PULL_UP_DISC; 02289 break; 02290 case LSM6DSO_AUX_PULL_UP_CONNECT: 02291 *val = LSM6DSO_AUX_PULL_UP_CONNECT; 02292 break; 02293 default: 02294 *val = LSM6DSO_AUX_PULL_UP_DISC; 02295 break; 02296 } 02297 return ret; 02298 } 02299 02300 /** 02301 * @brief OIS chain on aux interface power on mode.[set] 02302 * 02303 * @param ctx read / write interface definitions 02304 * @param val change the values of ois_on in reg CTRL7_G 02305 * 02306 */ 02307 int32_t lsm6dso_aux_pw_on_ctrl_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t val) 02308 { 02309 lsm6dso_ctrl7_g_t reg; 02310 int32_t ret; 02311 02312 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 02313 if (ret == 0) { 02314 reg.ois_on_en = (uint8_t)val & 0x01U; 02315 reg.ois_on = (uint8_t)val & 0x01U; 02316 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 02317 } 02318 return ret; 02319 } 02320 02321 /** 02322 * @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode 02323 * 02324 * @param ctx read / write interface definitions 02325 * @param val Get the values of ois_on in reg CTRL7_G 02326 * 02327 */ 02328 int32_t lsm6dso_aux_pw_on_ctrl_get(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t *val) 02329 { 02330 lsm6dso_ctrl7_g_t reg; 02331 int32_t ret; 02332 02333 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1); 02334 switch (reg.ois_on) { 02335 case LSM6DSO_AUX_ON: 02336 *val = LSM6DSO_AUX_ON; 02337 break; 02338 case LSM6DSO_AUX_ON_BY_AUX_INTERFACE: 02339 *val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE; 02340 break; 02341 default: 02342 *val = LSM6DSO_AUX_ON; 02343 break; 02344 } 02345 02346 return ret; 02347 } 02348 02349 /** 02350 * @brief Accelerometer full-scale management between UI chain and 02351 * OIS chain. When XL UI is on, the full scale is the same 02352 * between UI/OIS and is chosen by the UI CTRL registers; 02353 * when XL UI is in PD, the OIS can choose the FS. 02354 * Full scales are independent between the UI/OIS chain 02355 * but both bound to 8 g.[set] 02356 * 02357 * @param ctx read / write interface definitions 02358 * @param val change the values of xl_fs_mode in 02359 * reg CTRL8_XL 02360 * 02361 */ 02362 int32_t lsm6dso_aux_xl_fs_mode_set(lsm6dso_ctx_t *ctx, 02363 lsm6dso_xl_fs_mode_t val) 02364 { 02365 lsm6dso_ctrl8_xl_t reg; 02366 int32_t ret; 02367 02368 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 02369 if (ret == 0) { 02370 reg.xl_fs_mode = (uint8_t)val; 02371 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 02372 } 02373 return ret; 02374 } 02375 02376 /** 02377 * @brief Accelerometer full-scale management between UI chain and 02378 * OIS chain. When XL UI is on, the full scale is the same 02379 * between UI/OIS and is chosen by the UI CTRL registers; 02380 * when XL UI is in PD, the OIS can choose the FS. 02381 * Full scales are independent between the UI/OIS chain 02382 * but both bound to 8 g.[get] 02383 * 02384 * @param ctx read / write interface definitions 02385 * @param val Get the values of xl_fs_mode in reg CTRL8_XL 02386 * 02387 */ 02388 int32_t lsm6dso_aux_xl_fs_mode_get(lsm6dso_ctx_t *ctx, 02389 lsm6dso_xl_fs_mode_t *val) 02390 { 02391 lsm6dso_ctrl8_xl_t reg; 02392 int32_t ret; 02393 02394 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1); 02395 switch (reg.xl_fs_mode) { 02396 case LSM6DSO_USE_SAME_XL_FS: 02397 *val = LSM6DSO_USE_SAME_XL_FS; 02398 break; 02399 case LSM6DSO_USE_DIFFERENT_XL_FS: 02400 *val = LSM6DSO_USE_DIFFERENT_XL_FS; 02401 break; 02402 default: 02403 *val = LSM6DSO_USE_SAME_XL_FS; 02404 break; 02405 } 02406 02407 return ret; 02408 } 02409 02410 /** 02411 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get] 02412 * 02413 * @param ctx read / write interface definitions 02414 * @param lsm6dso_status_spiaux_t: registers STATUS_SPIAUX 02415 * 02416 */ 02417 int32_t lsm6dso_aux_status_reg_get(lsm6dso_ctx_t *ctx, 02418 lsm6dso_status_spiaux_t *val) 02419 { 02420 int32_t ret; 02421 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *) val, 1); 02422 return ret; 02423 } 02424 02425 /** 02426 * @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available 02427 * 02428 * @param ctx read / write interface definitions 02429 * @param val change the values of xlda in reg STATUS_SPIAUX 02430 * 02431 */ 02432 int32_t lsm6dso_aux_xl_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02433 { 02434 lsm6dso_status_spiaux_t reg; 02435 int32_t ret; 02436 02437 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1); 02438 *val = reg.xlda; 02439 02440 return ret; 02441 } 02442 02443 /** 02444 * @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available. 02445 * 02446 * @param ctx read / write interface definitions 02447 * @param val change the values of gda in reg STATUS_SPIAUX 02448 * 02449 */ 02450 int32_t lsm6dso_aux_gy_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02451 { 02452 lsm6dso_status_spiaux_t reg; 02453 int32_t ret; 02454 02455 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1); 02456 *val = reg.gda; 02457 02458 return ret; 02459 } 02460 02461 /** 02462 * @brief High when the gyroscope output is in the settling phase.[get] 02463 * 02464 * @param ctx read / write interface definitions 02465 * @param val change the values of gyro_settling in reg STATUS_SPIAUX 02466 * 02467 */ 02468 int32_t lsm6dso_aux_gy_flag_settling_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02469 { 02470 lsm6dso_status_spiaux_t reg; 02471 int32_t ret; 02472 02473 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1); 02474 *val = reg.gyro_settling; 02475 02476 return ret; 02477 } 02478 02479 /** 02480 * @brief Selects accelerometer self-test. Effective only if XL OIS 02481 * chain is enabled.[set] 02482 * 02483 * @param ctx read / write interface definitions 02484 * @param val change the values of st_xl_ois in reg INT_OIS 02485 * 02486 */ 02487 int32_t lsm6dso_aux_xl_self_test_set(lsm6dso_ctx_t *ctx, 02488 lsm6dso_st_xl_ois_t val) 02489 { 02490 lsm6dso_int_ois_t reg; 02491 int32_t ret; 02492 02493 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1); 02494 if (ret == 0) { 02495 reg.st_xl_ois = (uint8_t)val; 02496 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1); 02497 } 02498 return ret; 02499 } 02500 02501 /** 02502 * @brief Selects accelerometer self-test. Effective only if XL OIS 02503 * chain is enabled.[get] 02504 * 02505 * @param ctx read / write interface definitions 02506 * @param val Get the values of st_xl_ois in reg INT_OIS 02507 * 02508 */ 02509 int32_t lsm6dso_aux_xl_self_test_get(lsm6dso_ctx_t *ctx, 02510 lsm6dso_st_xl_ois_t *val) 02511 { 02512 lsm6dso_int_ois_t reg; 02513 int32_t ret; 02514 02515 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1); 02516 switch (reg.st_xl_ois) { 02517 case LSM6DSO_AUX_XL_DISABLE: 02518 *val = LSM6DSO_AUX_XL_DISABLE; 02519 break; 02520 case LSM6DSO_AUX_XL_POS: 02521 *val = LSM6DSO_AUX_XL_POS; 02522 break; 02523 case LSM6DSO_AUX_XL_NEG: 02524 *val = LSM6DSO_AUX_XL_NEG; 02525 break; 02526 default: 02527 *val = LSM6DSO_AUX_XL_DISABLE; 02528 break; 02529 } 02530 return ret; 02531 } 02532 02533 /** 02534 * @brief Indicates polarity of DEN signal on OIS chain.[set] 02535 * 02536 * @param ctx read / write interface definitions 02537 * @param val change the values of den_lh_ois in 02538 * reg INT_OIS 02539 * 02540 */ 02541 int32_t lsm6dso_aux_den_polarity_set(lsm6dso_ctx_t *ctx, 02542 lsm6dso_den_lh_ois_t val) 02543 { 02544 lsm6dso_int_ois_t reg; 02545 int32_t ret; 02546 02547 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1); 02548 if (ret == 0) { 02549 reg.den_lh_ois = (uint8_t)val; 02550 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1); 02551 } 02552 return ret; 02553 } 02554 02555 /** 02556 * @brief Indicates polarity of DEN signal on OIS chain.[get] 02557 * 02558 * @param ctx read / write interface definitions 02559 * @param val Get the values of den_lh_ois in reg INT_OIS 02560 * 02561 */ 02562 int32_t lsm6dso_aux_den_polarity_get(lsm6dso_ctx_t *ctx, 02563 lsm6dso_den_lh_ois_t *val) 02564 { 02565 lsm6dso_int_ois_t reg; 02566 int32_t ret; 02567 02568 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1); 02569 switch (reg.den_lh_ois) { 02570 case LSM6DSO_AUX_DEN_ACTIVE_LOW: 02571 *val = LSM6DSO_AUX_DEN_ACTIVE_LOW; 02572 break; 02573 case LSM6DSO_AUX_DEN_ACTIVE_HIGH: 02574 *val = LSM6DSO_AUX_DEN_ACTIVE_HIGH; 02575 break; 02576 default: 02577 *val = LSM6DSO_AUX_DEN_ACTIVE_LOW; 02578 break; 02579 } 02580 return ret; 02581 } 02582 02583 /** 02584 * @brief Configure DEN mode on the OIS chain.[set] 02585 * 02586 * @param ctx read / write interface definitions 02587 * @param val change the values of lvl2_ois in reg INT_OIS 02588 * 02589 */ 02590 int32_t lsm6dso_aux_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t val) 02591 { 02592 lsm6dso_ctrl1_ois_t ctrl1_ois; 02593 lsm6dso_int_ois_t int_ois; 02594 int32_t ret; 02595 02596 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1); 02597 if (ret == 0) { 02598 int_ois.lvl2_ois = (uint8_t)val & 0x01U; 02599 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1); 02600 } 02601 if (ret == 0) { 02602 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1); 02603 } 02604 if (ret == 0) { 02605 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1; 02606 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1); 02607 } 02608 return ret; 02609 } 02610 02611 /** 02612 * @brief Configure DEN mode on the OIS chain.[get] 02613 * 02614 * @param ctx read / write interface definitions 02615 * @param val Get the values of lvl2_ois in reg INT_OIS 02616 * 02617 */ 02618 int32_t lsm6dso_aux_den_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t *val) 02619 { 02620 lsm6dso_ctrl1_ois_t ctrl1_ois; 02621 lsm6dso_int_ois_t int_ois; 02622 int32_t ret; 02623 02624 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1); 02625 if (ret == 0) { 02626 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1); 02627 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) { 02628 case LSM6DSO_AUX_DEN_DISABLE: 02629 *val = LSM6DSO_AUX_DEN_DISABLE; 02630 break; 02631 case LSM6DSO_AUX_DEN_LEVEL_LATCH: 02632 *val = LSM6DSO_AUX_DEN_LEVEL_LATCH; 02633 break; 02634 case LSM6DSO_AUX_DEN_LEVEL_TRIG: 02635 *val = LSM6DSO_AUX_DEN_LEVEL_TRIG; 02636 break; 02637 default: 02638 *val = LSM6DSO_AUX_DEN_DISABLE; 02639 break; 02640 } 02641 } 02642 return ret; 02643 } 02644 02645 /** 02646 * @brief Enables/Disable OIS chain DRDY on INT2 pin. 02647 * This setting has priority over all other INT2 settings.[set] 02648 * 02649 * @param ctx read / write interface definitions 02650 * @param val change the values of int2_drdy_ois in reg INT_OIS 02651 * 02652 */ 02653 int32_t lsm6dso_aux_drdy_on_int2_set(lsm6dso_ctx_t *ctx, uint8_t val) 02654 { 02655 lsm6dso_int_ois_t reg; 02656 int32_t ret; 02657 02658 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1); 02659 if (ret == 0) { 02660 reg.int2_drdy_ois = val; 02661 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1); 02662 } 02663 return ret; 02664 } 02665 02666 /** 02667 * @brief Enables/Disable OIS chain DRDY on INT2 pin. 02668 * This setting has priority over all other INT2 settings.[get] 02669 * 02670 * @param ctx read / write interface definitions 02671 * @param val change the values of int2_drdy_ois in reg INT_OIS 02672 * 02673 */ 02674 int32_t lsm6dso_aux_drdy_on_int2_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02675 { 02676 lsm6dso_int_ois_t reg; 02677 int32_t ret; 02678 02679 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1); 02680 *val = reg.int2_drdy_ois; 02681 02682 return ret; 02683 } 02684 02685 /** 02686 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4 02687 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1). 02688 * When the OIS chain is enabled, the OIS outputs are available 02689 * through the SPI2 in registers OUTX_L_G (22h) through 02690 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and 02691 * LPF1 is dedicated to this chain.[set] 02692 * 02693 * @param ctx read / write interface definitions 02694 * @param val change the values of ois_en_spi2 in 02695 * reg CTRL1_OIS 02696 * 02697 */ 02698 int32_t lsm6dso_aux_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t val) 02699 { 02700 lsm6dso_ctrl1_ois_t reg; 02701 int32_t ret; 02702 02703 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1); 02704 if (ret == 0) { 02705 reg.ois_en_spi2 = (uint8_t)val & 0x01U; 02706 reg.mode4_en = ((uint8_t)val & 0x02U) >> 1; 02707 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1); 02708 } 02709 return ret; 02710 } 02711 02712 /** 02713 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4 02714 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1). 02715 * When the OIS chain is enabled, the OIS outputs are available 02716 * through the SPI2 in registers OUTX_L_G (22h) through 02717 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and 02718 * LPF1 is dedicated to this chain.[get] 02719 * 02720 * @param ctx read / write interface definitions 02721 * @param val Get the values of ois_en_spi2 in 02722 * reg CTRL1_OIS 02723 * 02724 */ 02725 int32_t lsm6dso_aux_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t *val) 02726 { 02727 lsm6dso_ctrl1_ois_t reg; 02728 int32_t ret; 02729 02730 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1); 02731 switch ((reg.mode4_en << 1) | reg.ois_en_spi2) { 02732 case LSM6DSO_AUX_DISABLE: 02733 *val = LSM6DSO_AUX_DISABLE; 02734 break; 02735 case LSM6DSO_MODE_3_GY: 02736 *val = LSM6DSO_MODE_3_GY; 02737 break; 02738 case LSM6DSO_MODE_4_GY_XL: 02739 *val = LSM6DSO_MODE_4_GY_XL; 02740 break; 02741 default: 02742 *val = LSM6DSO_AUX_DISABLE; 02743 break; 02744 } 02745 return ret; 02746 } 02747 02748 /** 02749 * @brief Selects gyroscope OIS chain full-scale.[set] 02750 * 02751 * @param ctx read / write interface definitions 02752 * @param val change the values of fs_g_ois in reg CTRL1_OIS 02753 * 02754 */ 02755 int32_t lsm6dso_aux_gy_full_scale_set(lsm6dso_ctx_t *ctx, 02756 lsm6dso_fs_g_ois_t val) 02757 { 02758 lsm6dso_ctrl1_ois_t reg; 02759 int32_t ret; 02760 02761 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1); 02762 if (ret == 0) { 02763 reg.fs_g_ois = (uint8_t)val; 02764 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1); 02765 } 02766 return ret; 02767 } 02768 02769 /** 02770 * @brief Selects gyroscope OIS chain full-scale.[get] 02771 * 02772 * @param ctx read / write interface definitions 02773 * @param val Get the values of fs_g_ois in reg CTRL1_OIS 02774 * 02775 */ 02776 int32_t lsm6dso_aux_gy_full_scale_get(lsm6dso_ctx_t *ctx, 02777 lsm6dso_fs_g_ois_t *val) 02778 { 02779 lsm6dso_ctrl1_ois_t reg; 02780 int32_t ret; 02781 02782 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1); 02783 switch (reg.fs_g_ois) { 02784 case LSM6DSO_250dps_AUX: 02785 *val = LSM6DSO_250dps_AUX; 02786 break; 02787 case LSM6DSO_125dps_AUX: 02788 *val = LSM6DSO_125dps_AUX; 02789 break; 02790 case LSM6DSO_500dps_AUX: 02791 *val = LSM6DSO_500dps_AUX; 02792 break; 02793 case LSM6DSO_1000dps_AUX: 02794 *val = LSM6DSO_1000dps_AUX; 02795 break; 02796 case LSM6DSO_2000dps_AUX: 02797 *val = LSM6DSO_2000dps_AUX; 02798 break; 02799 default: 02800 *val = LSM6DSO_250dps_AUX; 02801 break; 02802 } 02803 return ret; 02804 } 02805 02806 /** 02807 * @brief SPI2 3- or 4-wire interface.[set] 02808 * 02809 * @param ctx read / write interface definitions 02810 * @param val change the values of sim_ois in reg CTRL1_OIS 02811 * 02812 */ 02813 int32_t lsm6dso_aux_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t val) 02814 { 02815 lsm6dso_ctrl1_ois_t reg; 02816 int32_t ret; 02817 02818 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1); 02819 if (ret == 0) { 02820 reg.sim_ois = (uint8_t)val; 02821 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1); 02822 } 02823 return ret; 02824 } 02825 02826 /** 02827 * @brief SPI2 3- or 4-wire interface.[get] 02828 * 02829 * @param ctx read / write interface definitions 02830 * @param val Get the values of sim_ois in reg CTRL1_OIS 02831 * 02832 */ 02833 int32_t lsm6dso_aux_spi_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t *val) 02834 { 02835 lsm6dso_ctrl1_ois_t reg; 02836 int32_t ret; 02837 02838 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1); 02839 switch (reg.sim_ois) { 02840 case LSM6DSO_AUX_SPI_4_WIRE: 02841 *val = LSM6DSO_AUX_SPI_4_WIRE; 02842 break; 02843 case LSM6DSO_AUX_SPI_3_WIRE: 02844 *val = LSM6DSO_AUX_SPI_3_WIRE; 02845 break; 02846 default: 02847 *val = LSM6DSO_AUX_SPI_4_WIRE; 02848 break; 02849 } 02850 return ret; 02851 } 02852 02853 /** 02854 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set] 02855 * 02856 * @param ctx read / write interface definitions 02857 * @param val change the values of ftype_ois in 02858 * reg CTRL2_OIS 02859 * 02860 */ 02861 int32_t lsm6dso_aux_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, 02862 lsm6dso_ftype_ois_t val) 02863 { 02864 lsm6dso_ctrl2_ois_t reg; 02865 int32_t ret; 02866 02867 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1); 02868 if (ret == 0) { 02869 reg.ftype_ois = (uint8_t)val; 02870 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1); 02871 } 02872 return ret; 02873 } 02874 02875 /** 02876 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get] 02877 * 02878 * @param ctx read / write interface definitions 02879 * @param val Get the values of ftype_ois in reg CTRL2_OIS 02880 * 02881 */ 02882 int32_t lsm6dso_aux_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx, 02883 lsm6dso_ftype_ois_t *val) 02884 { 02885 lsm6dso_ctrl2_ois_t reg; 02886 int32_t ret; 02887 02888 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1); 02889 switch (reg.ftype_ois) { 02890 case LSM6DSO_351Hz39: 02891 *val = LSM6DSO_351Hz39; 02892 break; 02893 case LSM6DSO_236Hz63: 02894 *val = LSM6DSO_236Hz63; 02895 break; 02896 case LSM6DSO_172Hz70: 02897 *val = LSM6DSO_172Hz70; 02898 break; 02899 case LSM6DSO_937Hz91: 02900 *val = LSM6DSO_937Hz91; 02901 break; 02902 default: 02903 *val = LSM6DSO_351Hz39; 02904 break; 02905 } 02906 return ret; 02907 } 02908 02909 /** 02910 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set] 02911 * 02912 * @param ctx read / write interface definitions 02913 * @param val change the values of hpm_ois in reg CTRL2_OIS 02914 * 02915 */ 02916 int32_t lsm6dso_aux_gy_hp_bandwidth_set(lsm6dso_ctx_t *ctx, 02917 lsm6dso_hpm_ois_t val) 02918 { 02919 lsm6dso_ctrl2_ois_t reg; 02920 int32_t ret; 02921 02922 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1); 02923 if (ret == 0) { 02924 reg.hpm_ois = (uint8_t)val & 0x03U; 02925 reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4; 02926 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1); 02927 } 02928 return ret; 02929 } 02930 02931 /** 02932 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get] 02933 * 02934 * @param ctx read / write interface definitions 02935 * @param val Get the values of hpm_ois in reg CTRL2_OIS 02936 * 02937 */ 02938 int32_t lsm6dso_aux_gy_hp_bandwidth_get(lsm6dso_ctx_t *ctx, 02939 lsm6dso_hpm_ois_t *val) 02940 { 02941 lsm6dso_ctrl2_ois_t reg; 02942 int32_t ret; 02943 02944 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1); 02945 switch ((reg.hp_en_ois << 4) | reg.hpm_ois) { 02946 case LSM6DSO_AUX_HP_DISABLE: 02947 *val = LSM6DSO_AUX_HP_DISABLE; 02948 break; 02949 case LSM6DSO_AUX_HP_Hz016: 02950 *val = LSM6DSO_AUX_HP_Hz016; 02951 break; 02952 case LSM6DSO_AUX_HP_Hz065: 02953 *val = LSM6DSO_AUX_HP_Hz065; 02954 break; 02955 case LSM6DSO_AUX_HP_Hz260: 02956 *val = LSM6DSO_AUX_HP_Hz260; 02957 break; 02958 case LSM6DSO_AUX_HP_1Hz040: 02959 *val = LSM6DSO_AUX_HP_1Hz040; 02960 break; 02961 default: 02962 *val = LSM6DSO_AUX_HP_DISABLE; 02963 break; 02964 } 02965 return ret; 02966 } 02967 02968 /** 02969 * @brief Enable / Disables OIS chain clamp. 02970 * Enable: All OIS chain outputs = 8000h 02971 * during self-test; Disable: OIS chain self-test 02972 * outputs dependent from the aux gyro full 02973 * scale selected.[set] 02974 * 02975 * @param ctx read / write interface definitions 02976 * @param val change the values of st_ois_clampdis in 02977 * reg CTRL3_OIS 02978 * 02979 */ 02980 int32_t lsm6dso_aux_gy_clamp_set(lsm6dso_ctx_t *ctx, 02981 lsm6dso_st_ois_clampdis_t val) 02982 { 02983 lsm6dso_ctrl3_ois_t reg; 02984 int32_t ret; 02985 02986 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 02987 if (ret == 0) { 02988 reg.st_ois_clampdis = (uint8_t)val; 02989 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 02990 } 02991 return ret; 02992 } 02993 02994 /** 02995 * @brief Enable / Disables OIS chain clamp. 02996 * Enable: All OIS chain outputs = 8000h 02997 * during self-test; Disable: OIS chain self-test 02998 * outputs dependent from the aux gyro full 02999 * scale selected.[set] 03000 * 03001 * @param ctx read / write interface definitions 03002 * @param val Get the values of st_ois_clampdis in 03003 * reg CTRL3_OIS 03004 * 03005 */ 03006 int32_t lsm6dso_aux_gy_clamp_get(lsm6dso_ctx_t *ctx, 03007 lsm6dso_st_ois_clampdis_t *val) 03008 { 03009 lsm6dso_ctrl3_ois_t reg; 03010 int32_t ret; 03011 03012 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03013 switch (reg.st_ois_clampdis) { 03014 case LSM6DSO_ENABLE_CLAMP: 03015 *val = LSM6DSO_ENABLE_CLAMP; 03016 break; 03017 case LSM6DSO_DISABLE_CLAMP: 03018 *val = LSM6DSO_DISABLE_CLAMP; 03019 break; 03020 default: 03021 *val = LSM6DSO_ENABLE_CLAMP; 03022 break; 03023 } 03024 return ret; 03025 } 03026 03027 /** 03028 * @brief Selects gyroscope OIS chain self-test.[set] 03029 * 03030 * @param ctx read / write interface definitions 03031 * @param val change the values of st_ois in reg CTRL3_OIS 03032 * 03033 */ 03034 int32_t lsm6dso_aux_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_ois_t val) 03035 { 03036 lsm6dso_ctrl3_ois_t reg; 03037 int32_t ret; 03038 03039 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03040 if (ret == 0) { 03041 reg.st_ois = (uint8_t)val; 03042 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03043 } 03044 return ret; 03045 } 03046 03047 /** 03048 * @brief Selects gyroscope OIS chain self-test.[get] 03049 * 03050 * @param ctx read / write interface definitions 03051 * @param val Get the values of st_ois in reg CTRL3_OIS 03052 * 03053 */ 03054 int32_t lsm6dso_aux_gy_self_test_get(lsm6dso_ctx_t *ctx, lsm6dso_st_ois_t *val) 03055 { 03056 lsm6dso_ctrl3_ois_t reg; 03057 int32_t ret; 03058 03059 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03060 switch (reg.st_ois) { 03061 case LSM6DSO_AUX_GY_DISABLE: 03062 *val = LSM6DSO_AUX_GY_DISABLE; 03063 break; 03064 case LSM6DSO_AUX_GY_POS: 03065 *val = LSM6DSO_AUX_GY_POS; 03066 break; 03067 case LSM6DSO_AUX_GY_NEG: 03068 *val = LSM6DSO_AUX_GY_NEG; 03069 break; 03070 default: 03071 *val = LSM6DSO_AUX_GY_DISABLE; 03072 break; 03073 } 03074 return ret; 03075 } 03076 03077 /** 03078 * @brief Selects accelerometer OIS channel bandwidth.[set] 03079 * 03080 * @param ctx read / write interface definitions 03081 * @param val change the values of 03082 * filter_xl_conf_ois in reg CTRL3_OIS 03083 * 03084 */ 03085 int32_t lsm6dso_aux_xl_bandwidth_set(lsm6dso_ctx_t *ctx, 03086 lsm6dso_filter_xl_conf_ois_t val) 03087 { 03088 lsm6dso_ctrl3_ois_t reg; 03089 int32_t ret; 03090 03091 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03092 if (ret == 0) { 03093 reg.filter_xl_conf_ois = (uint8_t)val; 03094 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03095 } 03096 return ret; 03097 } 03098 03099 /** 03100 * @brief Selects accelerometer OIS channel bandwidth.[get] 03101 * 03102 * @param ctx read / write interface definitions 03103 * @param val Get the values of 03104 * filter_xl_conf_ois in reg CTRL3_OIS 03105 * 03106 */ 03107 int32_t lsm6dso_aux_xl_bandwidth_get(lsm6dso_ctx_t *ctx, 03108 lsm6dso_filter_xl_conf_ois_t *val) 03109 { 03110 lsm6dso_ctrl3_ois_t reg; 03111 int32_t ret; 03112 03113 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03114 03115 switch (reg.filter_xl_conf_ois) { 03116 case LSM6DSO_289Hz: 03117 *val = LSM6DSO_289Hz; 03118 break; 03119 case LSM6DSO_258Hz: 03120 *val = LSM6DSO_258Hz; 03121 break; 03122 case LSM6DSO_120Hz: 03123 *val = LSM6DSO_120Hz; 03124 break; 03125 case LSM6DSO_65Hz2: 03126 *val = LSM6DSO_65Hz2; 03127 break; 03128 case LSM6DSO_33Hz2: 03129 *val = LSM6DSO_33Hz2; 03130 break; 03131 case LSM6DSO_16Hz6: 03132 *val = LSM6DSO_16Hz6; 03133 break; 03134 case LSM6DSO_8Hz30: 03135 *val = LSM6DSO_8Hz30; 03136 break; 03137 case LSM6DSO_4Hz15: 03138 *val = LSM6DSO_4Hz15; 03139 break; 03140 default: 03141 *val = LSM6DSO_289Hz; 03142 break; 03143 } 03144 return ret; 03145 } 03146 03147 /** 03148 * @brief Selects accelerometer OIS channel full-scale.[set] 03149 * 03150 * @param ctx read / write interface definitions 03151 * @param val change the values of fs_xl_ois in 03152 * reg CTRL3_OIS 03153 * 03154 */ 03155 int32_t lsm6dso_aux_xl_full_scale_set(lsm6dso_ctx_t *ctx, 03156 lsm6dso_fs_xl_ois_t val) 03157 { 03158 lsm6dso_ctrl3_ois_t reg; 03159 int32_t ret; 03160 03161 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03162 if (ret == 0) { 03163 reg.fs_xl_ois = (uint8_t)val; 03164 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03165 } 03166 return ret; 03167 } 03168 03169 /** 03170 * @brief Selects accelerometer OIS channel full-scale.[get] 03171 * 03172 * @param ctx read / write interface definitions 03173 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS 03174 * 03175 */ 03176 int32_t lsm6dso_aux_xl_full_scale_get(lsm6dso_ctx_t *ctx, 03177 lsm6dso_fs_xl_ois_t *val) 03178 { 03179 lsm6dso_ctrl3_ois_t reg; 03180 int32_t ret; 03181 03182 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1); 03183 switch (reg.fs_xl_ois) { 03184 case LSM6DSO_AUX_2g: 03185 *val = LSM6DSO_AUX_2g; 03186 break; 03187 case LSM6DSO_AUX_16g: 03188 *val = LSM6DSO_AUX_16g; 03189 break; 03190 case LSM6DSO_AUX_4g: 03191 *val = LSM6DSO_AUX_4g; 03192 break; 03193 case LSM6DSO_AUX_8g: 03194 *val = LSM6DSO_AUX_8g; 03195 break; 03196 default: 03197 *val = LSM6DSO_AUX_2g; 03198 break; 03199 } 03200 return ret; 03201 } 03202 03203 /** 03204 * @} 03205 * 03206 */ 03207 03208 /** 03209 * @defgroup LSM6DSO_ main_serial_interface 03210 * @brief This section groups all the functions concerning main 03211 * serial interface management (not auxiliary) 03212 * @{ 03213 * 03214 */ 03215 03216 /** 03217 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] 03218 * 03219 * @param ctx read / write interface definitions 03220 * @param val change the values of sdo_pu_en in 03221 * reg PIN_CTRL 03222 * 03223 */ 03224 int32_t lsm6dso_sdo_sa0_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sdo_pu_en_t val) 03225 { 03226 lsm6dso_pin_ctrl_t reg; 03227 int32_t ret; 03228 03229 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1); 03230 if (ret == 0) { 03231 reg.sdo_pu_en = (uint8_t)val; 03232 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1); 03233 } 03234 return ret; 03235 } 03236 03237 /** 03238 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] 03239 * 03240 * @param ctx read / write interface definitions 03241 * @param val Get the values of sdo_pu_en in reg PIN_CTRL 03242 * 03243 */ 03244 int32_t lsm6dso_sdo_sa0_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_sdo_pu_en_t *val) 03245 { 03246 lsm6dso_pin_ctrl_t reg; 03247 int32_t ret; 03248 03249 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1); 03250 switch (reg.sdo_pu_en) { 03251 case LSM6DSO_PULL_UP_DISC: 03252 *val = LSM6DSO_PULL_UP_DISC; 03253 break; 03254 case LSM6DSO_PULL_UP_CONNECT: 03255 *val = LSM6DSO_PULL_UP_CONNECT; 03256 break; 03257 default: 03258 *val = LSM6DSO_PULL_UP_DISC; 03259 break; 03260 } 03261 return ret; 03262 } 03263 03264 /** 03265 * @brief SPI Serial Interface Mode selection.[set] 03266 * 03267 * @param ctx read / write interface definitions 03268 * @param val change the values of sim in reg CTRL3_C 03269 * 03270 */ 03271 int32_t lsm6dso_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_t val) 03272 { 03273 lsm6dso_ctrl3_c_t reg; 03274 int32_t ret; 03275 03276 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 03277 if (ret == 0) { 03278 reg.sim = (uint8_t)val; 03279 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 03280 } 03281 return ret; 03282 } 03283 03284 /** 03285 * @brief SPI Serial Interface Mode selection.[get] 03286 * 03287 * @param ctx read / write interface definitions 03288 * @param val Get the values of sim in reg CTRL3_C 03289 * 03290 */ 03291 int32_t lsm6dso_spi_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_sim_t *val) 03292 { 03293 lsm6dso_ctrl3_c_t reg; 03294 int32_t ret; 03295 03296 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 03297 switch (reg.sim) { 03298 case LSM6DSO_SPI_4_WIRE: 03299 *val = LSM6DSO_SPI_4_WIRE; 03300 break; 03301 case LSM6DSO_SPI_3_WIRE: 03302 *val = LSM6DSO_SPI_3_WIRE; 03303 break; 03304 default: 03305 *val = LSM6DSO_SPI_4_WIRE; 03306 break; 03307 } 03308 return ret; 03309 } 03310 03311 /** 03312 * @brief Disable / Enable I2C interface.[set] 03313 * 03314 * @param ctx read / write interface definitions 03315 * @param val change the values of i2c_disable in 03316 * reg CTRL4_C 03317 * 03318 */ 03319 int32_t lsm6dso_i2c_interface_set(lsm6dso_ctx_t *ctx, 03320 lsm6dso_i2c_disable_t val) 03321 { 03322 lsm6dso_ctrl4_c_t reg; 03323 int32_t ret; 03324 03325 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 03326 if (ret == 0) { 03327 reg.i2c_disable = (uint8_t)val; 03328 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 03329 } 03330 return ret; 03331 } 03332 03333 /** 03334 * @brief Disable / Enable I2C interface.[get] 03335 * 03336 * @param ctx read / write interface definitions 03337 * @param val Get the values of i2c_disable in 03338 * reg CTRL4_C 03339 * 03340 */ 03341 int32_t lsm6dso_i2c_interface_get(lsm6dso_ctx_t *ctx, 03342 lsm6dso_i2c_disable_t *val) 03343 { 03344 lsm6dso_ctrl4_c_t reg; 03345 int32_t ret; 03346 03347 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 03348 switch (reg.i2c_disable) { 03349 case LSM6DSO_I2C_ENABLE: 03350 *val = LSM6DSO_I2C_ENABLE; 03351 break; 03352 case LSM6DSO_I2C_DISABLE: 03353 *val = LSM6DSO_I2C_DISABLE; 03354 break; 03355 default: 03356 *val = LSM6DSO_I2C_ENABLE; 03357 break; 03358 } 03359 return ret; 03360 } 03361 03362 /** 03363 * @brief I3C Enable/Disable communication protocol[.set] 03364 * 03365 * @param ctx read / write interface definitions 03366 * @param val change the values of i3c_disable 03367 * in reg CTRL9_XL 03368 * 03369 */ 03370 int32_t lsm6dso_i3c_disable_set(lsm6dso_ctx_t *ctx, lsm6dso_i3c_disable_t val) 03371 { 03372 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 03373 lsm6dso_ctrl9_xl_t ctrl9_xl; 03374 int32_t ret; 03375 03376 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); 03377 if (ret == 0) { 03378 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7; 03379 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); 03380 } 03381 if (ret == 0) { 03382 03383 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, 03384 (uint8_t *)&i3c_bus_avb, 1); 03385 } 03386 if (ret == 0) { 03387 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U; 03388 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, 03389 (uint8_t *)&i3c_bus_avb, 1); 03390 } 03391 03392 return ret; 03393 } 03394 03395 /** 03396 * @brief I3C Enable/Disable communication protocol.[get] 03397 * 03398 * @param ctx read / write interface definitions 03399 * @param val change the values of i3c_disable in 03400 * reg CTRL9_XL 03401 * 03402 */ 03403 int32_t lsm6dso_i3c_disable_get(lsm6dso_ctx_t *ctx, lsm6dso_i3c_disable_t *val) 03404 { 03405 lsm6dso_ctrl9_xl_t ctrl9_xl; 03406 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 03407 int32_t ret; 03408 03409 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1); 03410 if (ret == 0) { 03411 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, 03412 (uint8_t *)&i3c_bus_avb, 1); 03413 03414 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) { 03415 case LSM6DSO_I3C_DISABLE: 03416 *val = LSM6DSO_I3C_DISABLE; 03417 break; 03418 case LSM6DSO_I3C_ENABLE_T_50us: 03419 *val = LSM6DSO_I3C_ENABLE_T_50us; 03420 break; 03421 case LSM6DSO_I3C_ENABLE_T_2us: 03422 *val = LSM6DSO_I3C_ENABLE_T_2us; 03423 break; 03424 case LSM6DSO_I3C_ENABLE_T_1ms: 03425 *val = LSM6DSO_I3C_ENABLE_T_1ms; 03426 break; 03427 case LSM6DSO_I3C_ENABLE_T_25ms: 03428 *val = LSM6DSO_I3C_ENABLE_T_25ms; 03429 break; 03430 default: 03431 *val = LSM6DSO_I3C_DISABLE; 03432 break; 03433 } 03434 } 03435 return ret; 03436 } 03437 03438 /** 03439 * @} 03440 * 03441 */ 03442 03443 /** 03444 * @defgroup LSM6DSO_interrupt_pins 03445 * @brief This section groups all the functions that manage interrup pins 03446 * @{ 03447 * 03448 */ 03449 03450 /** 03451 * @brief Connect/Disconnect INT1 internal pull-down.[set] 03452 * 03453 * @param ctx read / write interface definitions 03454 * @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB 03455 * 03456 */ 03457 int32_t lsm6dso_int1_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_int1_pd_en_t val) 03458 { 03459 lsm6dso_i3c_bus_avb_t reg; 03460 int32_t ret; 03461 03462 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1); 03463 if (ret == 0) { 03464 reg.pd_dis_int1 = (uint8_t)val; 03465 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1); 03466 } 03467 return ret; 03468 } 03469 03470 /** 03471 * @brief Connect/Disconnect INT1 internal pull-down.[get] 03472 * 03473 * @param ctx read / write interface definitions 03474 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB 03475 * 03476 */ 03477 int32_t lsm6dso_int1_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_int1_pd_en_t *val) 03478 { 03479 lsm6dso_i3c_bus_avb_t reg; 03480 int32_t ret; 03481 03482 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1); 03483 switch (reg.pd_dis_int1) { 03484 case LSM6DSO_PULL_DOWN_DISC: 03485 *val = LSM6DSO_PULL_DOWN_DISC; 03486 break; 03487 case LSM6DSO_PULL_DOWN_CONNECT: 03488 *val = LSM6DSO_PULL_DOWN_CONNECT; 03489 break; 03490 default: 03491 *val = LSM6DSO_PULL_DOWN_DISC; 03492 break; 03493 } 03494 return ret; 03495 } 03496 03497 /** 03498 * @brief Select the signal that need to route on int1 pad.[set] 03499 * 03500 * @param ctx read / write interface definitions 03501 * @param val struct of registers: INT1_CTRL, 03502 * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A, 03503 * FSM_INT1_B 03504 * 03505 */ 03506 int32_t lsm6dso_pin_int1_route_set(lsm6dso_ctx_t *ctx, 03507 lsm6dso_pin_int1_route_t *val) 03508 { 03509 lsm6dso_pin_int2_route_t pin_int2_route; 03510 lsm6dso_tap_cfg2_t tap_cfg2; 03511 int32_t ret; 03512 03513 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 03514 if (ret == 0) { 03515 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT1, 03516 (uint8_t *)&val->emb_func_int1, 1); 03517 } 03518 if (ret == 0) { 03519 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_A, 03520 (uint8_t *)&val->fsm_int1_a, 1); 03521 } 03522 if (ret == 0) { 03523 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_B, 03524 (uint8_t *)&val->fsm_int1_b, 1); 03525 } 03526 if (ret == 0) { 03527 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 03528 } 03529 03530 if (ret == 0) { 03531 if ((val->emb_func_int1.int1_fsm_lc 03532 | val->emb_func_int1.int1_sig_mot 03533 | val->emb_func_int1.int1_step_detector 03534 | val->emb_func_int1.int1_tilt 03535 | val->fsm_int1_a.int1_fsm1 03536 | val->fsm_int1_a.int1_fsm2 03537 | val->fsm_int1_a.int1_fsm3 03538 | val->fsm_int1_a.int1_fsm4 03539 | val->fsm_int1_a.int1_fsm5 03540 | val->fsm_int1_a.int1_fsm6 03541 | val->fsm_int1_a.int1_fsm7 03542 | val->fsm_int1_a.int1_fsm8 03543 | val->fsm_int1_b.int1_fsm9 03544 | val->fsm_int1_b.int1_fsm10 03545 | val->fsm_int1_b.int1_fsm11 03546 | val->fsm_int1_b.int1_fsm12 03547 | val->fsm_int1_b.int1_fsm13 03548 | val->fsm_int1_b.int1_fsm14 03549 | val->fsm_int1_b.int1_fsm15 03550 | val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE) { 03551 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE; 03552 } else { 03553 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE; 03554 } 03555 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT1_CTRL, 03556 (uint8_t *)&val->int1_ctrl, 1); 03557 } 03558 if (ret == 0) { 03559 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); 03560 } 03561 if (ret == 0) { 03562 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1); 03563 } 03564 03565 if (ret == 0) { 03566 ret = lsm6dso_pin_int2_route_get(ctx, &pin_int2_route); 03567 } 03568 if (ret == 0) { 03569 if ((pin_int2_route.int2_ctrl.int2_cnt_bdr 03570 | pin_int2_route.int2_ctrl.int2_drdy_g 03571 | pin_int2_route.int2_ctrl.int2_drdy_temp 03572 | pin_int2_route.int2_ctrl.int2_drdy_xl 03573 | pin_int2_route.int2_ctrl.int2_fifo_full 03574 | pin_int2_route.int2_ctrl.int2_fifo_ovr 03575 | pin_int2_route.int2_ctrl.int2_fifo_th 03576 | pin_int2_route.md2_cfg.int2_6d 03577 | pin_int2_route.md2_cfg.int2_double_tap 03578 | pin_int2_route.md2_cfg.int2_ff 03579 | pin_int2_route.md2_cfg.int2_wu 03580 | pin_int2_route.md2_cfg.int2_single_tap 03581 | pin_int2_route.md2_cfg.int2_sleep_change 03582 | val->int1_ctrl.den_drdy_flag 03583 | val->int1_ctrl.int1_boot 03584 | val->int1_ctrl.int1_cnt_bdr 03585 | val->int1_ctrl.int1_drdy_g 03586 | val->int1_ctrl.int1_drdy_xl 03587 | val->int1_ctrl.int1_fifo_full 03588 | val->int1_ctrl.int1_fifo_ovr 03589 | val->int1_ctrl.int1_fifo_th 03590 | val->md1_cfg.int1_6d 03591 | val->md1_cfg.int1_double_tap 03592 | val->md1_cfg.int1_ff 03593 | val->md1_cfg.int1_wu 03594 | val->md1_cfg.int1_single_tap 03595 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) { 03596 tap_cfg2.interrupts_enable = PROPERTY_ENABLE; 03597 } else { 03598 tap_cfg2.interrupts_enable = PROPERTY_DISABLE; 03599 } 03600 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1); 03601 } 03602 return ret; 03603 } 03604 03605 /** 03606 * @brief Select the signal that need to route on int1 pad.[get] 03607 * 03608 * @param ctx read / write interface definitions 03609 * @param val struct of registers: INT1_CTRL, MD1_CFG, 03610 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B 03611 * 03612 */ 03613 int32_t lsm6dso_pin_int1_route_get(lsm6dso_ctx_t *ctx, 03614 lsm6dso_pin_int1_route_t *val) 03615 { 03616 int32_t ret; 03617 03618 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 03619 if (ret == 0) { 03620 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT1, 03621 (uint8_t *)&val->emb_func_int1, 1); 03622 } 03623 if (ret == 0) { 03624 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_A, 03625 (uint8_t *)&val->fsm_int1_a, 1); 03626 } 03627 if (ret == 0) { 03628 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_B, 03629 (uint8_t *)&val->fsm_int1_b, 1); 03630 } 03631 if (ret == 0) { 03632 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 03633 } 03634 if (ret == 0) { 03635 03636 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT1_CTRL, 03637 (uint8_t *)&val->int1_ctrl, 1); 03638 } 03639 if (ret == 0) { 03640 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&val->md1_cfg, 1); 03641 } 03642 03643 return ret; 03644 } 03645 03646 /** 03647 * @brief Select the signal that need to route on int2 pad.[set] 03648 * 03649 * @param ctx read / write interface definitions 03650 * @param val union of registers INT2_CTRL, MD2_CFG, 03651 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B 03652 * 03653 */ 03654 int32_t lsm6dso_pin_int2_route_set(lsm6dso_ctx_t *ctx, 03655 lsm6dso_pin_int2_route_t *val) 03656 { 03657 lsm6dso_pin_int1_route_t pin_int1_route; 03658 lsm6dso_tap_cfg2_t tap_cfg2; 03659 int32_t ret; 03660 03661 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 03662 if (ret == 0) { 03663 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT2, 03664 (uint8_t *)&val->emb_func_int2, 1); 03665 } 03666 if (ret == 0) { 03667 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_A, 03668 (uint8_t *)&val->fsm_int2_a, 1); 03669 } 03670 if (ret == 0) { 03671 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_B, 03672 (uint8_t *)&val->fsm_int2_b, 1); 03673 } 03674 if (ret == 0) { 03675 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 03676 } 03677 03678 if (ret == 0) { 03679 if ((val->emb_func_int2.int2_fsm_lc 03680 | val->emb_func_int2.int2_sig_mot 03681 | val->emb_func_int2.int2_step_detector 03682 | val->emb_func_int2.int2_tilt 03683 | val->fsm_int2_a.int2_fsm1 03684 | val->fsm_int2_a.int2_fsm2 03685 | val->fsm_int2_a.int2_fsm3 03686 | val->fsm_int2_a.int2_fsm4 03687 | val->fsm_int2_a.int2_fsm5 03688 | val->fsm_int2_a.int2_fsm6 03689 | val->fsm_int2_a.int2_fsm7 03690 | val->fsm_int2_a.int2_fsm8 03691 | val->fsm_int2_b.int2_fsm9 03692 | val->fsm_int2_b.int2_fsm10 03693 | val->fsm_int2_b.int2_fsm11 03694 | val->fsm_int2_b.int2_fsm12 03695 | val->fsm_int2_b.int2_fsm13 03696 | val->fsm_int2_b.int2_fsm14 03697 | val->fsm_int2_b.int2_fsm15 03698 | val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE) { 03699 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE; 03700 } else { 03701 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE; 03702 } 03703 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, 03704 (uint8_t *)&val->int2_ctrl, 1); 03705 } 03706 if (ret == 0) { 03707 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); 03708 } 03709 if (ret == 0) { 03710 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1); 03711 } 03712 03713 if (ret == 0) { 03714 ret = lsm6dso_pin_int1_route_get(ctx, &pin_int1_route); 03715 } 03716 03717 if (ret == 0) { 03718 if ((val->int2_ctrl.int2_cnt_bdr 03719 | val->int2_ctrl.int2_drdy_g 03720 | val->int2_ctrl.int2_drdy_temp 03721 | val->int2_ctrl.int2_drdy_xl 03722 | val->int2_ctrl.int2_fifo_full 03723 | val->int2_ctrl.int2_fifo_ovr 03724 | val->int2_ctrl.int2_fifo_th 03725 | val->md2_cfg.int2_6d 03726 | val->md2_cfg.int2_double_tap 03727 | val->md2_cfg.int2_ff 03728 | val->md2_cfg.int2_wu 03729 | val->md2_cfg.int2_single_tap 03730 | val->md2_cfg.int2_sleep_change 03731 | pin_int1_route.int1_ctrl.den_drdy_flag 03732 | pin_int1_route.int1_ctrl.int1_boot 03733 | pin_int1_route.int1_ctrl.int1_cnt_bdr 03734 | pin_int1_route.int1_ctrl.int1_drdy_g 03735 | pin_int1_route.int1_ctrl.int1_drdy_xl 03736 | pin_int1_route.int1_ctrl.int1_fifo_full 03737 | pin_int1_route.int1_ctrl.int1_fifo_ovr 03738 | pin_int1_route.int1_ctrl.int1_fifo_th 03739 | pin_int1_route.md1_cfg.int1_6d 03740 | pin_int1_route.md1_cfg.int1_double_tap 03741 | pin_int1_route.md1_cfg.int1_ff 03742 | pin_int1_route.md1_cfg.int1_wu 03743 | pin_int1_route.md1_cfg.int1_single_tap 03744 | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) { 03745 tap_cfg2.interrupts_enable = PROPERTY_ENABLE; 03746 } else { 03747 tap_cfg2.interrupts_enable = PROPERTY_DISABLE; 03748 } 03749 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1); 03750 } 03751 return ret; 03752 } 03753 03754 /** 03755 * @brief Select the signal that need to route on int2 pad.[get] 03756 * 03757 * @param ctx read / write interface definitions 03758 * @param val union of registers INT2_CTRL, MD2_CFG, 03759 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B 03760 * 03761 */ 03762 int32_t lsm6dso_pin_int2_route_get(lsm6dso_ctx_t *ctx, 03763 lsm6dso_pin_int2_route_t *val) 03764 { 03765 int32_t ret; 03766 03767 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 03768 if (ret == 0) { 03769 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT2, 03770 (uint8_t *)&val->emb_func_int2, 1); 03771 } 03772 if (ret == 0) { 03773 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_A, 03774 (uint8_t *)&val->fsm_int2_a, 1); 03775 } 03776 if (ret == 0) { 03777 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_B, 03778 (uint8_t *)&val->fsm_int2_b, 1); 03779 } 03780 if (ret == 0) { 03781 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 03782 } 03783 if (ret == 0) { 03784 03785 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, 03786 (uint8_t *)&val->int2_ctrl, 1); 03787 } 03788 if (ret == 0) { 03789 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&val->md2_cfg, 1); 03790 } 03791 return ret; 03792 } 03793 03794 /** 03795 * @brief Push-pull/open drain selection on interrupt pads.[set] 03796 * 03797 * @param ctx read / write interface definitions 03798 * @param val change the values of pp_od in reg CTRL3_C 03799 * 03800 */ 03801 int32_t lsm6dso_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_pp_od_t val) 03802 { 03803 lsm6dso_ctrl3_c_t reg; 03804 int32_t ret; 03805 03806 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 03807 if (ret == 0) { 03808 reg.pp_od = (uint8_t)val; 03809 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 03810 } 03811 return ret; 03812 } 03813 03814 /** 03815 * @brief Push-pull/open drain selection on interrupt pads.[get] 03816 * 03817 * @param ctx read / write interface definitions 03818 * @param val Get the values of pp_od in reg CTRL3_C 03819 * 03820 */ 03821 int32_t lsm6dso_pin_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_pp_od_t *val) 03822 { 03823 lsm6dso_ctrl3_c_t reg; 03824 int32_t ret; 03825 03826 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 03827 03828 switch (reg.pp_od) { 03829 case LSM6DSO_PUSH_PULL: 03830 *val = LSM6DSO_PUSH_PULL; 03831 break; 03832 case LSM6DSO_OPEN_DRAIN: 03833 *val = LSM6DSO_OPEN_DRAIN; 03834 break; 03835 default: 03836 *val = LSM6DSO_PUSH_PULL; 03837 break; 03838 } 03839 return ret; 03840 } 03841 03842 /** 03843 * @brief Interrupt active-high/low.[set] 03844 * 03845 * @param ctx read / write interface definitions 03846 * @param val change the values of h_lactive in reg CTRL3_C 03847 * 03848 */ 03849 int32_t lsm6dso_pin_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_h_lactive_t val) 03850 { 03851 lsm6dso_ctrl3_c_t reg; 03852 int32_t ret; 03853 03854 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 03855 if (ret == 0) { 03856 reg.h_lactive = (uint8_t)val; 03857 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 03858 } 03859 03860 return ret; 03861 } 03862 03863 /** 03864 * @brief Interrupt active-high/low.[get] 03865 * 03866 * @param ctx read / write interface definitions 03867 * @param val Get the values of h_lactive in reg CTRL3_C 03868 * 03869 */ 03870 int32_t lsm6dso_pin_polarity_get(lsm6dso_ctx_t *ctx, lsm6dso_h_lactive_t *val) 03871 { 03872 lsm6dso_ctrl3_c_t reg; 03873 int32_t ret; 03874 03875 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1); 03876 03877 switch (reg.h_lactive) { 03878 case LSM6DSO_ACTIVE_HIGH: 03879 *val = LSM6DSO_ACTIVE_HIGH; 03880 break; 03881 case LSM6DSO_ACTIVE_LOW: 03882 *val = LSM6DSO_ACTIVE_LOW; 03883 break; 03884 default: 03885 *val = LSM6DSO_ACTIVE_HIGH; 03886 break; 03887 } 03888 return ret; 03889 } 03890 03891 /** 03892 * @brief All interrupt signals become available on INT1 pin.[set] 03893 * 03894 * @param ctx read / write interface definitions 03895 * @param val change the values of int2_on_int1 in reg CTRL4_C 03896 * 03897 */ 03898 int32_t lsm6dso_all_on_int1_set(lsm6dso_ctx_t *ctx, uint8_t val) 03899 { 03900 lsm6dso_ctrl4_c_t reg; 03901 int32_t ret; 03902 03903 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 03904 if (ret == 0) { 03905 reg.int2_on_int1 = val; 03906 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 03907 } 03908 03909 return ret; 03910 } 03911 03912 /** 03913 * @brief All interrupt signals become available on INT1 pin.[get] 03914 * 03915 * @param ctx read / write interface definitions 03916 * @param val change the values of int2_on_int1 in reg CTRL4_C 03917 * 03918 */ 03919 int32_t lsm6dso_all_on_int1_get(lsm6dso_ctx_t *ctx, uint8_t *val) 03920 { 03921 lsm6dso_ctrl4_c_t reg; 03922 int32_t ret; 03923 03924 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 03925 *val = reg.int2_on_int1; 03926 03927 return ret; 03928 } 03929 03930 /** 03931 * @brief Interrupt notification mode.[set] 03932 * 03933 * @param ctx read / write interface definitions 03934 * @param val change the values of lir in reg TAP_CFG0 03935 * 03936 */ 03937 int32_t lsm6dso_int_notification_set(lsm6dso_ctx_t *ctx, lsm6dso_lir_t val) 03938 { 03939 lsm6dso_tap_cfg0_t tap_cfg0; 03940 lsm6dso_page_rw_t page_rw; 03941 int32_t ret; 03942 03943 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); 03944 if (ret == 0) { 03945 tap_cfg0.lir = (uint8_t)val & 0x01U; 03946 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; 03947 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); 03948 } 03949 if (ret == 0) { 03950 03951 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 03952 } 03953 if (ret == 0) { 03954 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 03955 } 03956 if (ret == 0) { 03957 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; 03958 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 03959 } 03960 if (ret == 0) { 03961 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 03962 } 03963 03964 return ret; 03965 } 03966 03967 /** 03968 * @brief Interrupt notification mode.[get] 03969 * 03970 * @param ctx read / write interface definitions 03971 * @param val Get the values of lir in reg TAP_CFG0 03972 * 03973 */ 03974 int32_t lsm6dso_int_notification_get(lsm6dso_ctx_t *ctx, lsm6dso_lir_t *val) 03975 { 03976 lsm6dso_tap_cfg0_t tap_cfg0; 03977 lsm6dso_page_rw_t page_rw; 03978 int32_t ret; 03979 03980 03981 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1); 03982 if (ret == 0) { 03983 03984 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 03985 } 03986 if (ret == 0) { 03987 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 03988 } 03989 if (ret == 0) { 03990 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 03991 } 03992 if (ret == 0) { 03993 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir) { 03994 case LSM6DSO_ALL_INT_PULSED: 03995 *val = LSM6DSO_ALL_INT_PULSED; 03996 break; 03997 case LSM6DSO_BASE_LATCHED_EMB_PULSED: 03998 *val = LSM6DSO_BASE_LATCHED_EMB_PULSED; 03999 break; 04000 case LSM6DSO_BASE_PULSED_EMB_LATCHED: 04001 *val = LSM6DSO_BASE_PULSED_EMB_LATCHED; 04002 break; 04003 case LSM6DSO_ALL_INT_LATCHED: 04004 *val = LSM6DSO_ALL_INT_LATCHED; 04005 break; 04006 default: 04007 *val = LSM6DSO_ALL_INT_PULSED; 04008 break; 04009 } 04010 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 04011 } 04012 if (ret == 0) { 04013 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1); 04014 } 04015 if (ret == 0) { 04016 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 04017 } 04018 04019 return ret; 04020 } 04021 04022 /** 04023 * @} 04024 * 04025 */ 04026 04027 /** 04028 * @defgroup LSM6DSO_Wake_Up_event 04029 * @brief This section groups all the functions that manage the Wake Up 04030 * event generation. 04031 * @{ 04032 * 04033 */ 04034 04035 /** 04036 * @brief Weight of 1 LSB of wakeup threshold.[set] 04037 * 0: 1 LSB =FS_XL / 64 04038 * 1: 1 LSB = FS_XL / 256 04039 * 04040 * @param ctx read / write interface definitions 04041 * @param val change the values of wake_ths_w in 04042 * reg WAKE_UP_DUR 04043 * 04044 */ 04045 int32_t lsm6dso_wkup_ths_weight_set(lsm6dso_ctx_t *ctx, 04046 lsm6dso_wake_ths_w_t val) 04047 { 04048 lsm6dso_wake_up_dur_t reg; 04049 int32_t ret; 04050 04051 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1); 04052 if (ret == 0) { 04053 reg.wake_ths_w = (uint8_t)val; 04054 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1); 04055 } 04056 return ret; 04057 } 04058 04059 /** 04060 * @brief Weight of 1 LSB of wakeup threshold.[get] 04061 * 0: 1 LSB =FS_XL / 64 04062 * 1: 1 LSB = FS_XL / 256 04063 * 04064 * @param ctx read / write interface definitions 04065 * @param val Get the values of wake_ths_w in 04066 * reg WAKE_UP_DUR 04067 * 04068 */ 04069 int32_t lsm6dso_wkup_ths_weight_get(lsm6dso_ctx_t *ctx, 04070 lsm6dso_wake_ths_w_t *val) 04071 { 04072 lsm6dso_wake_up_dur_t reg; 04073 int32_t ret; 04074 04075 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1); 04076 04077 switch (reg.wake_ths_w) { 04078 case LSM6DSO_LSb_FS_DIV_64: 04079 *val = LSM6DSO_LSb_FS_DIV_64; 04080 break; 04081 case LSM6DSO_LSb_FS_DIV_256: 04082 *val = LSM6DSO_LSb_FS_DIV_256; 04083 break; 04084 default: 04085 *val = LSM6DSO_LSb_FS_DIV_64; 04086 break; 04087 } 04088 return ret; 04089 } 04090 04091 /** 04092 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in 04093 * WAKE_UP_DUR.[set] 04094 * 04095 * @param ctx read / write interface definitions 04096 * @param val change the values of wk_ths in reg WAKE_UP_THS 04097 * 04098 */ 04099 int32_t lsm6dso_wkup_threshold_set(lsm6dso_ctx_t *ctx, uint8_t val) 04100 { 04101 lsm6dso_wake_up_ths_t reg; 04102 int32_t ret; 04103 04104 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1); 04105 if (ret == 0) { 04106 reg.wk_ths = val; 04107 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1); 04108 } 04109 return ret; 04110 } 04111 04112 /** 04113 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in 04114 * WAKE_UP_DUR.[get] 04115 * 04116 * @param ctx read / write interface definitions 04117 * @param val change the values of wk_ths in reg WAKE_UP_THS 04118 * 04119 */ 04120 int32_t lsm6dso_wkup_threshold_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04121 { 04122 lsm6dso_wake_up_ths_t reg; 04123 int32_t ret; 04124 04125 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1); 04126 *val = reg.wk_ths; 04127 04128 return ret; 04129 } 04130 04131 /** 04132 * @brief Wake up duration event.[set] 04133 * 1LSb = 1 / ODR 04134 * 04135 * @param ctx read / write interface definitions 04136 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS 04137 * 04138 */ 04139 int32_t lsm6dso_xl_usr_offset_on_wkup_set(lsm6dso_ctx_t *ctx, uint8_t val) 04140 { 04141 lsm6dso_wake_up_ths_t reg; 04142 int32_t ret; 04143 04144 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1); 04145 if (ret == 0) { 04146 reg.usr_off_on_wu = val; 04147 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1); 04148 } 04149 return ret; 04150 } 04151 04152 /** 04153 * @brief Wake up duration event.[get] 04154 * 1LSb = 1 / ODR 04155 * 04156 * @param ctx read / write interface definitions 04157 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS 04158 * 04159 */ 04160 int32_t lsm6dso_xl_usr_offset_on_wkup_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04161 { 04162 lsm6dso_wake_up_ths_t reg; 04163 int32_t ret; 04164 04165 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1); 04166 *val = reg.usr_off_on_wu; 04167 04168 return ret; 04169 } 04170 04171 /** 04172 * @brief Wake up duration event.[set] 04173 * 1LSb = 1 / ODR 04174 * 04175 * @param ctx read / write interface definitions 04176 * @param val change the values of wake_dur in reg WAKE_UP_DUR 04177 * 04178 */ 04179 int32_t lsm6dso_wkup_dur_set(lsm6dso_ctx_t *ctx, uint8_t val) 04180 { 04181 lsm6dso_wake_up_dur_t reg; 04182 int32_t ret; 04183 04184 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1); 04185 if (ret == 0) { 04186 reg.wake_dur = val; 04187 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1); 04188 } 04189 return ret; 04190 } 04191 04192 /** 04193 * @brief Wake up duration event.[get] 04194 * 1LSb = 1 / ODR 04195 * 04196 * @param ctx read / write interface definitions 04197 * @param val change the values of wake_dur in reg WAKE_UP_DUR 04198 * 04199 */ 04200 int32_t lsm6dso_wkup_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04201 { 04202 lsm6dso_wake_up_dur_t reg; 04203 int32_t ret; 04204 04205 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1); 04206 *val = reg.wake_dur; 04207 04208 return ret; 04209 } 04210 04211 /** 04212 * @} 04213 * 04214 */ 04215 04216 /** 04217 * @defgroup LSM6DSO_ Activity/Inactivity_detection 04218 * @brief This section groups all the functions concerning 04219 * activity/inactivity detection. 04220 * @{ 04221 * 04222 */ 04223 04224 /** 04225 * @brief Enables gyroscope Sleep mode.[set] 04226 * 04227 * @param ctx read / write interface definitions 04228 * @param val change the values of sleep_g in reg CTRL4_C 04229 * 04230 */ 04231 int32_t lsm6dso_gy_sleep_mode_set(lsm6dso_ctx_t *ctx, uint8_t val) 04232 { 04233 lsm6dso_ctrl4_c_t reg; 04234 int32_t ret; 04235 04236 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 04237 if (ret == 0) { 04238 reg.sleep_g = val; 04239 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 04240 } 04241 return ret; 04242 } 04243 04244 /** 04245 * @brief Enables gyroscope Sleep mode.[get] 04246 * 04247 * @param ctx read / write interface definitions 04248 * @param val change the values of sleep_g in reg CTRL4_C 04249 * 04250 */ 04251 int32_t lsm6dso_gy_sleep_mode_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04252 { 04253 lsm6dso_ctrl4_c_t reg; 04254 int32_t ret; 04255 04256 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1); 04257 *val = reg.sleep_g; 04258 04259 return ret; 04260 } 04261 04262 /** 04263 * @brief Drives the sleep status instead of 04264 * sleep change on INT pins 04265 * (only if INT1_SLEEP_CHANGE or 04266 * INT2_SLEEP_CHANGE bits are enabled).[set] 04267 * 04268 * @param ctx read / write interface definitions 04269 * @param val change the values of sleep_status_on_int in reg TAP_CFG0 04270 * 04271 */ 04272 int32_t lsm6dso_act_pin_notification_set(lsm6dso_ctx_t *ctx, 04273 lsm6dso_sleep_status_on_int_t val) 04274 { 04275 lsm6dso_tap_cfg0_t reg; 04276 int32_t ret; 04277 04278 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04279 if (ret == 0) { 04280 reg.sleep_status_on_int = (uint8_t)val; 04281 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04282 } 04283 return ret; 04284 } 04285 04286 /** 04287 * @brief Drives the sleep status instead of 04288 * sleep change on INT pins (only if 04289 * INT1_SLEEP_CHANGE or 04290 * INT2_SLEEP_CHANGE bits are enabled).[get] 04291 * 04292 * @param ctx read / write interface definitions 04293 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0 04294 * 04295 */ 04296 int32_t lsm6dso_act_pin_notification_get(lsm6dso_ctx_t *ctx, 04297 lsm6dso_sleep_status_on_int_t *val) 04298 { 04299 lsm6dso_tap_cfg0_t reg; 04300 int32_t ret; 04301 04302 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04303 switch (reg.sleep_status_on_int) { 04304 case LSM6DSO_DRIVE_SLEEP_CHG_EVENT: 04305 *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT; 04306 break; 04307 case LSM6DSO_DRIVE_SLEEP_STATUS: 04308 *val = LSM6DSO_DRIVE_SLEEP_STATUS; 04309 break; 04310 default: 04311 *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT; 04312 break; 04313 } 04314 return ret; 04315 } 04316 04317 /** 04318 * @brief Enable inactivity function.[set] 04319 * 04320 * @param ctx read / write interface definitions 04321 * @param val change the values of inact_en in reg TAP_CFG2 04322 * 04323 */ 04324 int32_t lsm6dso_act_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_inact_en_t val) 04325 { 04326 lsm6dso_tap_cfg2_t reg; 04327 int32_t ret; 04328 04329 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1); 04330 if (ret == 0) { 04331 reg.inact_en = (uint8_t)val; 04332 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1); 04333 } 04334 return ret; 04335 } 04336 04337 /** 04338 * @brief Enable inactivity function.[get] 04339 * 04340 * @param ctx read / write interface definitions 04341 * @param val Get the values of inact_en in reg TAP_CFG2 04342 * 04343 */ 04344 int32_t lsm6dso_act_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_inact_en_t *val) 04345 { 04346 lsm6dso_tap_cfg2_t reg; 04347 int32_t ret; 04348 04349 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1); 04350 switch (reg.inact_en) { 04351 case LSM6DSO_XL_AND_GY_NOT_AFFECTED: 04352 *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED; 04353 break; 04354 case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED: 04355 *val = LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED; 04356 break; 04357 case LSM6DSO_XL_12Hz5_GY_SLEEP: 04358 *val = LSM6DSO_XL_12Hz5_GY_SLEEP; 04359 break; 04360 case LSM6DSO_XL_12Hz5_GY_PD: 04361 *val = LSM6DSO_XL_12Hz5_GY_PD; 04362 break; 04363 default: 04364 *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED; 04365 break; 04366 } 04367 return ret; 04368 } 04369 04370 /** 04371 * @brief Duration to go in sleep mode.[set] 04372 * 1 LSb = 512 / ODR 04373 * 04374 * @param ctx read / write interface definitions 04375 * @param val change the values of sleep_dur in reg WAKE_UP_DUR 04376 * 04377 */ 04378 int32_t lsm6dso_act_sleep_dur_set(lsm6dso_ctx_t *ctx, uint8_t val) 04379 { 04380 lsm6dso_wake_up_dur_t reg; 04381 int32_t ret; 04382 04383 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1); 04384 if (ret == 0) { 04385 reg.sleep_dur = val; 04386 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1); 04387 } 04388 return ret; 04389 } 04390 04391 /** 04392 * @brief Duration to go in sleep mode.[get] 04393 * 1 LSb = 512 / ODR 04394 * 04395 * @param ctx read / write interface definitions 04396 * @param val change the values of sleep_dur in reg WAKE_UP_DUR 04397 * 04398 */ 04399 int32_t lsm6dso_act_sleep_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04400 { 04401 lsm6dso_wake_up_dur_t reg; 04402 int32_t ret; 04403 04404 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1); 04405 *val = reg.sleep_dur; 04406 04407 return ret; 04408 } 04409 04410 /** 04411 * @} 04412 * 04413 */ 04414 04415 /** 04416 * @defgroup LSM6DSO_tap_generator 04417 * @brief This section groups all the functions that manage the 04418 * tap and double tap event generation. 04419 * @{ 04420 * 04421 */ 04422 04423 /** 04424 * @brief Enable Z direction in tap recognition.[set] 04425 * 04426 * @param ctx read / write interface definitions 04427 * @param val change the values of tap_z_en in reg TAP_CFG0 04428 * 04429 */ 04430 int32_t lsm6dso_tap_detection_on_z_set(lsm6dso_ctx_t *ctx, uint8_t val) 04431 { 04432 lsm6dso_tap_cfg0_t reg; 04433 int32_t ret; 04434 04435 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04436 if (ret == 0) { 04437 reg.tap_z_en = val; 04438 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04439 } 04440 return ret; 04441 } 04442 04443 /** 04444 * @brief Enable Z direction in tap recognition.[get] 04445 * 04446 * @param ctx read / write interface definitions 04447 * @param val change the values of tap_z_en in reg TAP_CFG0 04448 * 04449 */ 04450 int32_t lsm6dso_tap_detection_on_z_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04451 { 04452 lsm6dso_tap_cfg0_t reg; 04453 int32_t ret; 04454 04455 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04456 *val = reg.tap_z_en; 04457 04458 return ret; 04459 } 04460 04461 /** 04462 * @brief Enable Y direction in tap recognition.[set] 04463 * 04464 * @param ctx read / write interface definitions 04465 * @param val change the values of tap_y_en in reg TAP_CFG0 04466 * 04467 */ 04468 int32_t lsm6dso_tap_detection_on_y_set(lsm6dso_ctx_t *ctx, uint8_t val) 04469 { 04470 lsm6dso_tap_cfg0_t reg; 04471 int32_t ret; 04472 04473 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04474 if (ret == 0) { 04475 reg.tap_y_en = val; 04476 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04477 } 04478 return ret; 04479 } 04480 04481 /** 04482 * @brief Enable Y direction in tap recognition.[get] 04483 * 04484 * @param ctx read / write interface definitions 04485 * @param val change the values of tap_y_en in reg TAP_CFG0 04486 * 04487 */ 04488 int32_t lsm6dso_tap_detection_on_y_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04489 { 04490 lsm6dso_tap_cfg0_t reg; 04491 int32_t ret; 04492 04493 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04494 *val = reg.tap_y_en; 04495 04496 return ret; 04497 } 04498 04499 /** 04500 * @brief Enable X direction in tap recognition.[set] 04501 * 04502 * @param ctx read / write interface definitions 04503 * @param val change the values of tap_x_en in reg TAP_CFG0 04504 * 04505 */ 04506 int32_t lsm6dso_tap_detection_on_x_set(lsm6dso_ctx_t *ctx, uint8_t val) 04507 { 04508 lsm6dso_tap_cfg0_t reg; 04509 int32_t ret; 04510 04511 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04512 if (ret == 0) { 04513 reg.tap_x_en = val; 04514 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04515 } 04516 return ret; 04517 } 04518 04519 /** 04520 * @brief Enable X direction in tap recognition.[get] 04521 * 04522 * @param ctx read / write interface definitions 04523 * @param val change the values of tap_x_en in reg TAP_CFG0 04524 * 04525 */ 04526 int32_t lsm6dso_tap_detection_on_x_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04527 { 04528 lsm6dso_tap_cfg0_t reg; 04529 int32_t ret; 04530 04531 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1); 04532 *val = reg.tap_x_en; 04533 04534 return ret; 04535 } 04536 04537 /** 04538 * @brief X-axis tap recognition threshold.[set] 04539 * 04540 * @param ctx read / write interface definitions 04541 * @param val change the values of tap_ths_x in reg TAP_CFG1 04542 * 04543 */ 04544 int32_t lsm6dso_tap_threshold_x_set(lsm6dso_ctx_t *ctx, uint8_t val) 04545 { 04546 lsm6dso_tap_cfg1_t reg; 04547 int32_t ret; 04548 04549 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1); 04550 if (ret == 0) { 04551 reg.tap_ths_x = val; 04552 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1); 04553 } 04554 return ret; 04555 } 04556 04557 /** 04558 * @brief X-axis tap recognition threshold.[get] 04559 * 04560 * @param ctx read / write interface definitions 04561 * @param val change the values of tap_ths_x in reg TAP_CFG1 04562 * 04563 */ 04564 int32_t lsm6dso_tap_threshold_x_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04565 { 04566 lsm6dso_tap_cfg1_t reg; 04567 int32_t ret; 04568 04569 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1); 04570 *val = reg.tap_ths_x; 04571 04572 return ret; 04573 } 04574 04575 /** 04576 * @brief Selection of axis priority for TAP detection.[set] 04577 * 04578 * @param ctx read / write interface definitions 04579 * @param val change the values of tap_priority in 04580 * reg TAP_CFG1 04581 * 04582 */ 04583 int32_t lsm6dso_tap_axis_priority_set(lsm6dso_ctx_t *ctx, 04584 lsm6dso_tap_priority_t val) 04585 { 04586 lsm6dso_tap_cfg1_t reg; 04587 int32_t ret; 04588 04589 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1); 04590 if (ret == 0) { 04591 reg.tap_priority = (uint8_t)val; 04592 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1); 04593 } 04594 return ret; 04595 } 04596 04597 /** 04598 * @brief Selection of axis priority for TAP detection.[get] 04599 * 04600 * @param ctx read / write interface definitions 04601 * @param val Get the values of tap_priority in 04602 * reg TAP_CFG1 04603 * 04604 */ 04605 int32_t lsm6dso_tap_axis_priority_get(lsm6dso_ctx_t *ctx, 04606 lsm6dso_tap_priority_t *val) 04607 { 04608 lsm6dso_tap_cfg1_t reg; 04609 int32_t ret; 04610 04611 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1); 04612 switch (reg.tap_priority) { 04613 case LSM6DSO_XYZ: 04614 *val = LSM6DSO_XYZ; 04615 break; 04616 case LSM6DSO_YXZ: 04617 *val = LSM6DSO_YXZ; 04618 break; 04619 case LSM6DSO_XZY: 04620 *val = LSM6DSO_XZY; 04621 break; 04622 case LSM6DSO_ZYX: 04623 *val = LSM6DSO_ZYX; 04624 break; 04625 case LSM6DSO_YZX: 04626 *val = LSM6DSO_YZX; 04627 break; 04628 case LSM6DSO_ZXY: 04629 *val = LSM6DSO_ZXY; 04630 break; 04631 default: 04632 *val = LSM6DSO_XYZ; 04633 break; 04634 } 04635 return ret; 04636 } 04637 04638 /** 04639 * @brief Y-axis tap recognition threshold.[set] 04640 * 04641 * @param ctx read / write interface definitions 04642 * @param val change the values of tap_ths_y in reg TAP_CFG2 04643 * 04644 */ 04645 int32_t lsm6dso_tap_threshold_y_set(lsm6dso_ctx_t *ctx, uint8_t val) 04646 { 04647 lsm6dso_tap_cfg2_t reg; 04648 int32_t ret; 04649 04650 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1); 04651 if (ret == 0) { 04652 reg.tap_ths_y = val; 04653 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1); 04654 } 04655 return ret; 04656 } 04657 04658 /** 04659 * @brief Y-axis tap recognition threshold.[get] 04660 * 04661 * @param ctx read / write interface definitions 04662 * @param val change the values of tap_ths_y in reg TAP_CFG2 04663 * 04664 */ 04665 int32_t lsm6dso_tap_threshold_y_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04666 { 04667 lsm6dso_tap_cfg2_t reg; 04668 int32_t ret; 04669 04670 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1); 04671 *val = reg.tap_ths_y; 04672 04673 return ret; 04674 } 04675 04676 /** 04677 * @brief Z-axis recognition threshold.[set] 04678 * 04679 * @param ctx read / write interface definitions 04680 * @param val change the values of tap_ths_z in reg TAP_THS_6D 04681 * 04682 */ 04683 int32_t lsm6dso_tap_threshold_z_set(lsm6dso_ctx_t *ctx, uint8_t val) 04684 { 04685 lsm6dso_tap_ths_6d_t reg; 04686 int32_t ret; 04687 04688 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1); 04689 if (ret == 0) { 04690 reg.tap_ths_z = val; 04691 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1); 04692 } 04693 return ret; 04694 } 04695 04696 /** 04697 * @brief Z-axis recognition threshold.[get] 04698 * 04699 * @param ctx read / write interface definitions 04700 * @param val change the values of tap_ths_z in reg TAP_THS_6D 04701 * 04702 */ 04703 int32_t lsm6dso_tap_threshold_z_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04704 { 04705 lsm6dso_tap_ths_6d_t reg; 04706 int32_t ret; 04707 04708 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1); 04709 *val = reg.tap_ths_z; 04710 04711 return ret; 04712 } 04713 04714 /** 04715 * @brief Maximum duration is the maximum time of an 04716 * over threshold signal detection to be recognized 04717 * as a tap event. The default value of these bits 04718 * is 00b which corresponds to 4*ODR_XL time. 04719 * If the SHOCK[1:0] bits are set to a different 04720 * value, 1LSB corresponds to 8*ODR_XL time.[set] 04721 * 04722 * @param ctx read / write interface definitions 04723 * @param val change the values of shock in reg INT_DUR2 04724 * 04725 */ 04726 int32_t lsm6dso_tap_shock_set(lsm6dso_ctx_t *ctx, uint8_t val) 04727 { 04728 lsm6dso_int_dur2_t reg; 04729 int32_t ret; 04730 04731 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1); 04732 if (ret == 0) { 04733 reg.shock = val; 04734 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1); 04735 } 04736 return ret; 04737 } 04738 04739 /** 04740 * @brief Maximum duration is the maximum time of an 04741 * over threshold signal detection to be recognized 04742 * as a tap event. The default value of these bits 04743 * is 00b which corresponds to 4*ODR_XL time. 04744 * If the SHOCK[1:0] bits are set to a different 04745 * value, 1LSB corresponds to 8*ODR_XL time.[get] 04746 * 04747 * @param ctx read / write interface definitions 04748 * @param val change the values of shock in reg INT_DUR2 04749 * 04750 */ 04751 int32_t lsm6dso_tap_shock_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04752 { 04753 lsm6dso_int_dur2_t reg; 04754 int32_t ret; 04755 04756 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1); 04757 *val = reg.shock; 04758 04759 return ret; 04760 } 04761 04762 /** 04763 * @brief Quiet time is the time after the first detected 04764 * tap in which there must not be any over threshold 04765 * event. 04766 * The default value of these bits is 00b which 04767 * corresponds to 2*ODR_XL time. If the QUIET[1:0] 04768 * bits are set to a different value, 04769 * 1LSB corresponds to 4*ODR_XL time.[set] 04770 * 04771 * @param ctx read / write interface definitions 04772 * @param val change the values of quiet in reg INT_DUR2 04773 * 04774 */ 04775 int32_t lsm6dso_tap_quiet_set(lsm6dso_ctx_t *ctx, uint8_t val) 04776 { 04777 lsm6dso_int_dur2_t reg; 04778 int32_t ret; 04779 04780 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1); 04781 if (ret == 0) { 04782 reg.quiet = val; 04783 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1); 04784 } 04785 return ret; 04786 } 04787 04788 /** 04789 * @brief Quiet time is the time after the first detected 04790 * tap in which there must not be any over threshold 04791 * event. 04792 * The default value of these bits is 00b which 04793 * corresponds to 2*ODR_XL time. 04794 * If the QUIET[1:0] bits are set to a different 04795 * value, 1LSB corresponds to 4*ODR_XL time.[get] 04796 * 04797 * @param ctx read / write interface definitions 04798 * @param val change the values of quiet in reg INT_DUR2 04799 * 04800 */ 04801 int32_t lsm6dso_tap_quiet_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04802 { 04803 lsm6dso_int_dur2_t reg; 04804 int32_t ret; 04805 04806 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1); 04807 *val = reg.quiet; 04808 04809 return ret; 04810 } 04811 04812 /** 04813 * @brief When double tap recognition is enabled, 04814 * this register expresses the maximum time 04815 * between two consecutive detected taps to 04816 * determine a double tap event. 04817 * The default value of these bits is 0000b which 04818 * corresponds to 16*ODR_XL time. 04819 * If the DUR[3:0] bits are set to a different value, 04820 * 1LSB corresponds to 32*ODR_XL time.[set] 04821 * 04822 * @param ctx read / write interface definitions 04823 * @param val change the values of dur in reg INT_DUR2 04824 * 04825 */ 04826 int32_t lsm6dso_tap_dur_set(lsm6dso_ctx_t *ctx, uint8_t val) 04827 { 04828 lsm6dso_int_dur2_t reg; 04829 int32_t ret; 04830 04831 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1); 04832 if (ret == 0) { 04833 reg.dur = val; 04834 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1); 04835 } 04836 return ret; 04837 } 04838 04839 /** 04840 * @brief When double tap recognition is enabled, 04841 * this register expresses the maximum time 04842 * between two consecutive detected taps to 04843 * determine a double tap event. 04844 * The default value of these bits is 0000b which 04845 * corresponds to 16*ODR_XL time. If the DUR[3:0] 04846 * bits are set to a different value, 04847 * 1LSB corresponds to 32*ODR_XL time.[get] 04848 * 04849 * @param ctx read / write interface definitions 04850 * @param val change the values of dur in reg INT_DUR2 04851 * 04852 */ 04853 int32_t lsm6dso_tap_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04854 { 04855 lsm6dso_int_dur2_t reg; 04856 int32_t ret; 04857 04858 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1); 04859 *val = reg.dur; 04860 04861 return ret; 04862 } 04863 04864 /** 04865 * @brief Single/double-tap event enable.[set] 04866 * 04867 * @param ctx read / write interface definitions 04868 * @param val change the values of single_double_tap in reg WAKE_UP_THS 04869 * 04870 */ 04871 int32_t lsm6dso_tap_mode_set(lsm6dso_ctx_t *ctx, 04872 lsm6dso_single_double_tap_t val) 04873 { 04874 lsm6dso_wake_up_ths_t reg; 04875 int32_t ret; 04876 04877 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1); 04878 if (ret == 0) { 04879 reg.single_double_tap = (uint8_t)val; 04880 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1); 04881 } 04882 return ret; 04883 } 04884 04885 /** 04886 * @brief Single/double-tap event enable.[get] 04887 * 04888 * @param ctx read / write interface definitions 04889 * @param val Get the values of single_double_tap in reg WAKE_UP_THS 04890 * 04891 */ 04892 int32_t lsm6dso_tap_mode_get(lsm6dso_ctx_t *ctx, 04893 lsm6dso_single_double_tap_t *val) 04894 { 04895 lsm6dso_wake_up_ths_t reg; 04896 int32_t ret; 04897 04898 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1); 04899 04900 switch (reg.single_double_tap) { 04901 case LSM6DSO_ONLY_SINGLE: 04902 *val = LSM6DSO_ONLY_SINGLE; 04903 break; 04904 case LSM6DSO_BOTH_SINGLE_DOUBLE: 04905 *val = LSM6DSO_BOTH_SINGLE_DOUBLE; 04906 break; 04907 default: 04908 *val = LSM6DSO_ONLY_SINGLE; 04909 break; 04910 } 04911 04912 return ret; 04913 } 04914 04915 /** 04916 * @} 04917 * 04918 */ 04919 04920 /** 04921 * @defgroup LSM6DSO_ Six_position_detection(6D/4D) 04922 * @brief This section groups all the functions concerning six position 04923 * detection (6D). 04924 * @{ 04925 * 04926 */ 04927 04928 /** 04929 * @brief Threshold for 4D/6D function.[set] 04930 * 04931 * @param ctx read / write interface definitions 04932 * @param val change the values of sixd_ths in reg TAP_THS_6D 04933 * 04934 */ 04935 int32_t lsm6dso_6d_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_sixd_ths_t val) 04936 { 04937 lsm6dso_tap_ths_6d_t reg; 04938 int32_t ret; 04939 04940 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1); 04941 if (ret == 0) { 04942 reg.sixd_ths = (uint8_t)val; 04943 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1); 04944 } 04945 return ret; 04946 } 04947 04948 /** 04949 * @brief Threshold for 4D/6D function.[get] 04950 * 04951 * @param ctx read / write interface definitions 04952 * @param val Get the values of sixd_ths in reg TAP_THS_6D 04953 * 04954 */ 04955 int32_t lsm6dso_6d_threshold_get(lsm6dso_ctx_t *ctx, lsm6dso_sixd_ths_t *val) 04956 { 04957 lsm6dso_tap_ths_6d_t reg; 04958 int32_t ret; 04959 04960 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1); 04961 switch (reg.sixd_ths) { 04962 case LSM6DSO_DEG_80: 04963 *val = LSM6DSO_DEG_80; 04964 break; 04965 case LSM6DSO_DEG_70: 04966 *val = LSM6DSO_DEG_70; 04967 break; 04968 case LSM6DSO_DEG_60: 04969 *val = LSM6DSO_DEG_60; 04970 break; 04971 case LSM6DSO_DEG_50: 04972 *val = LSM6DSO_DEG_50; 04973 break; 04974 default: 04975 *val = LSM6DSO_DEG_80; 04976 break; 04977 } 04978 return ret; 04979 } 04980 04981 /** 04982 * @brief 4D orientation detection enable.[set] 04983 * 04984 * @param ctx read / write interface definitions 04985 * @param val change the values of d4d_en in reg TAP_THS_6D 04986 * 04987 */ 04988 int32_t lsm6dso_4d_mode_set(lsm6dso_ctx_t *ctx, uint8_t val) 04989 { 04990 lsm6dso_tap_ths_6d_t reg; 04991 int32_t ret; 04992 04993 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1); 04994 if (ret == 0) { 04995 reg.d4d_en = val; 04996 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1); 04997 } 04998 return ret; 04999 } 05000 05001 /** 05002 * @brief 4D orientation detection enable.[get] 05003 * 05004 * @param ctx read / write interface definitions 05005 * @param val change the values of d4d_en in reg TAP_THS_6D 05006 * 05007 */ 05008 int32_t lsm6dso_4d_mode_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05009 { 05010 lsm6dso_tap_ths_6d_t reg; 05011 int32_t ret; 05012 05013 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1); 05014 *val = reg.d4d_en; 05015 05016 return ret; 05017 } 05018 05019 /** 05020 * @} 05021 * 05022 */ 05023 05024 /** 05025 * @defgroup LSM6DSO_free_fall 05026 * @brief This section group all the functions concerning the free 05027 * fall detection. 05028 * @{ 05029 * 05030 */ 05031 /** 05032 * @brief Free fall threshold setting.[set] 05033 * 05034 * @param ctx read / write interface definitions 05035 * @param val change the values of ff_ths in reg FREE_FALL 05036 * 05037 */ 05038 int32_t lsm6dso_ff_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_ff_ths_t val) 05039 { 05040 lsm6dso_free_fall_t reg; 05041 int32_t ret; 05042 05043 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1); 05044 if (ret == 0) { 05045 reg.ff_ths = (uint8_t)val; 05046 ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1); 05047 } 05048 return ret; 05049 } 05050 05051 /** 05052 * @brief Free fall threshold setting.[get] 05053 * 05054 * @param ctx read / write interface definitions 05055 * @param val Get the values of ff_ths in reg FREE_FALL 05056 * 05057 */ 05058 int32_t lsm6dso_ff_threshold_get(lsm6dso_ctx_t *ctx, lsm6dso_ff_ths_t *val) 05059 { 05060 lsm6dso_free_fall_t reg; 05061 int32_t ret; 05062 05063 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1); 05064 switch (reg.ff_ths) { 05065 case LSM6DSO_FF_TSH_156mg: 05066 *val = LSM6DSO_FF_TSH_156mg; 05067 break; 05068 case LSM6DSO_FF_TSH_219mg: 05069 *val = LSM6DSO_FF_TSH_219mg; 05070 break; 05071 case LSM6DSO_FF_TSH_250mg: 05072 *val = LSM6DSO_FF_TSH_250mg; 05073 break; 05074 case LSM6DSO_FF_TSH_312mg: 05075 *val = LSM6DSO_FF_TSH_312mg; 05076 break; 05077 case LSM6DSO_FF_TSH_344mg: 05078 *val = LSM6DSO_FF_TSH_344mg; 05079 break; 05080 case LSM6DSO_FF_TSH_406mg: 05081 *val = LSM6DSO_FF_TSH_406mg; 05082 break; 05083 case LSM6DSO_FF_TSH_469mg: 05084 *val = LSM6DSO_FF_TSH_469mg; 05085 break; 05086 case LSM6DSO_FF_TSH_500mg: 05087 *val = LSM6DSO_FF_TSH_500mg; 05088 break; 05089 default: 05090 *val = LSM6DSO_FF_TSH_156mg; 05091 break; 05092 } 05093 return ret; 05094 } 05095 05096 /** 05097 * @brief Free-fall duration event.[set] 05098 * 1LSb = 1 / ODR 05099 * 05100 * @param ctx read / write interface definitions 05101 * @param val change the values of ff_dur in reg FREE_FALL 05102 * 05103 */ 05104 int32_t lsm6dso_ff_dur_set(lsm6dso_ctx_t *ctx, uint8_t val) 05105 { 05106 lsm6dso_wake_up_dur_t wake_up_dur; 05107 lsm6dso_free_fall_t free_fall; 05108 int32_t ret; 05109 05110 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); 05111 if (ret == 0) { 05112 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1); 05113 } 05114 if (ret == 0) { 05115 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; 05116 free_fall.ff_dur = (uint8_t)val & 0x1FU; 05117 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, 05118 (uint8_t *)&wake_up_dur, 1); 05119 } 05120 if (ret == 0) { 05121 ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1); 05122 } 05123 return ret; 05124 } 05125 05126 /** 05127 * @brief Free-fall duration event.[get] 05128 * 1LSb = 1 / ODR 05129 * 05130 * @param ctx read / write interface definitions 05131 * @param val change the values of ff_dur in reg FREE_FALL 05132 * 05133 */ 05134 int32_t lsm6dso_ff_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05135 { 05136 lsm6dso_wake_up_dur_t wake_up_dur; 05137 lsm6dso_free_fall_t free_fall; 05138 int32_t ret; 05139 05140 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1); 05141 if (ret == 0) { 05142 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1); 05143 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; 05144 } 05145 return ret; 05146 } 05147 05148 /** 05149 * @} 05150 * 05151 */ 05152 05153 /** 05154 * @defgroup LSM6DSO_fifo 05155 * @brief This section group all the functions concerning the fifo usage 05156 * @{ 05157 * 05158 */ 05159 05160 /** 05161 * @brief FIFO watermark level selection.[set] 05162 * 05163 * @param ctx read / write interface definitions 05164 * @param val change the values of wtm in reg FIFO_CTRL1 05165 * 05166 */ 05167 int32_t lsm6dso_fifo_watermark_set(lsm6dso_ctx_t *ctx, uint16_t val) 05168 { 05169 lsm6dso_fifo_ctrl1_t fifo_ctrl1; 05170 lsm6dso_fifo_ctrl2_t fifo_ctrl2; 05171 int32_t ret; 05172 05173 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); 05174 if (ret == 0) { 05175 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val; 05176 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8); 05177 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); 05178 } 05179 if (ret == 0) { 05180 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); 05181 } 05182 return ret; 05183 } 05184 05185 /** 05186 * @brief FIFO watermark level selection.[get] 05187 * 05188 * @param ctx read / write interface definitions 05189 * @param val change the values of wtm in reg FIFO_CTRL1 05190 * 05191 */ 05192 int32_t lsm6dso_fifo_watermark_get(lsm6dso_ctx_t *ctx, uint16_t *val) 05193 { 05194 lsm6dso_fifo_ctrl1_t fifo_ctrl1; 05195 lsm6dso_fifo_ctrl2_t fifo_ctrl2; 05196 int32_t ret; 05197 05198 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1); 05199 if (ret == 0) { 05200 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1); 05201 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm; 05202 } 05203 return ret; 05204 } 05205 05206 /** 05207 * @brief FIFO compression feature initialization request [set]. 05208 * 05209 * @param ctx read / write interface definitions 05210 * @param val change the values of FIFO_COMPR_INIT in 05211 * reg EMB_FUNC_INIT_B 05212 * 05213 */ 05214 int32_t lsm6dso_compression_algo_init_set(lsm6dso_ctx_t *ctx, uint8_t val) 05215 { 05216 lsm6dso_emb_func_init_b_t reg; 05217 int32_t ret; 05218 05219 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 05220 if (ret == 0) { 05221 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1); 05222 } 05223 if (ret == 0) { 05224 reg.fifo_compr_init = val; 05225 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1); 05226 } 05227 if (ret == 0) { 05228 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 05229 } 05230 05231 return ret; 05232 } 05233 05234 /** 05235 * @brief FIFO compression feature initialization request [get]. 05236 * 05237 * @param ctx read / write interface definitions 05238 * @param val change the values of FIFO_COMPR_INIT in 05239 * reg EMB_FUNC_INIT_B 05240 * 05241 */ 05242 int32_t lsm6dso_compression_algo_init_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05243 { 05244 lsm6dso_emb_func_init_b_t reg; 05245 int32_t ret; 05246 05247 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 05248 if (ret == 0) { 05249 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1); 05250 } 05251 if (ret == 0) { 05252 *val = reg.fifo_compr_init; 05253 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 05254 } 05255 05256 return ret; 05257 } 05258 05259 /** 05260 * @brief Enable and configure compression algo.[set] 05261 * 05262 * @param ctx read / write interface definitions 05263 * @param val change the values of uncoptr_rate in 05264 * reg FIFO_CTRL2 05265 * 05266 */ 05267 int32_t lsm6dso_compression_algo_set(lsm6dso_ctx_t *ctx, 05268 lsm6dso_uncoptr_rate_t val) 05269 { 05270 lsm6dso_emb_func_en_b_t emb_func_en_b; 05271 lsm6dso_fifo_ctrl2_t fifo_ctrl2; 05272 int32_t ret; 05273 05274 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 05275 if (ret == 0) { 05276 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 05277 (uint8_t *)&emb_func_en_b, 1); 05278 } 05279 if (ret == 0) { 05280 emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2; 05281 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 05282 (uint8_t *)&emb_func_en_b, 1); 05283 } 05284 if (ret == 0) { 05285 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 05286 } 05287 if (ret == 0) { 05288 05289 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, 05290 (uint8_t *)&fifo_ctrl2, 1); 05291 } 05292 if (ret == 0) { 05293 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2; 05294 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U; 05295 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, 05296 (uint8_t *)&fifo_ctrl2, 1); 05297 } 05298 return ret; 05299 } 05300 05301 /** 05302 * @brief Enable and configure compression algo.[get] 05303 * 05304 * @param ctx read / write interface definitions 05305 * @param val Get the values of uncoptr_rate in 05306 * reg FIFO_CTRL2 05307 * 05308 */ 05309 int32_t lsm6dso_compression_algo_get(lsm6dso_ctx_t *ctx, 05310 lsm6dso_uncoptr_rate_t *val) 05311 { 05312 lsm6dso_fifo_ctrl2_t reg; 05313 int32_t ret; 05314 05315 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05316 05317 switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate) { 05318 case LSM6DSO_CMP_DISABLE: 05319 *val = LSM6DSO_CMP_DISABLE; 05320 break; 05321 case LSM6DSO_CMP_ALWAYS: 05322 *val = LSM6DSO_CMP_ALWAYS; 05323 break; 05324 case LSM6DSO_CMP_8_TO_1: 05325 *val = LSM6DSO_CMP_8_TO_1; 05326 break; 05327 case LSM6DSO_CMP_16_TO_1: 05328 *val = LSM6DSO_CMP_16_TO_1; 05329 break; 05330 case LSM6DSO_CMP_32_TO_1: 05331 *val = LSM6DSO_CMP_32_TO_1; 05332 break; 05333 default: 05334 *val = LSM6DSO_CMP_DISABLE; 05335 break; 05336 } 05337 return ret; 05338 } 05339 05340 /** 05341 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] 05342 * 05343 * @param ctx read / write interface definitions 05344 * @param val change the values of odrchg_en in reg FIFO_CTRL2 05345 * 05346 */ 05347 int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(lsm6dso_ctx_t *ctx, 05348 uint8_t val) 05349 { 05350 lsm6dso_fifo_ctrl2_t reg; 05351 int32_t ret; 05352 05353 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05354 if (ret == 0) { 05355 reg.odrchg_en = val; 05356 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05357 } 05358 return ret; 05359 } 05360 05361 /** 05362 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] 05363 * 05364 * @param ctx read / write interface definitions 05365 * @param val change the values of odrchg_en in reg FIFO_CTRL2 05366 * 05367 */ 05368 int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(lsm6dso_ctx_t *ctx, 05369 uint8_t *val) 05370 { 05371 lsm6dso_fifo_ctrl2_t reg; 05372 int32_t ret; 05373 05374 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05375 *val = reg.odrchg_en; 05376 05377 return ret; 05378 } 05379 05380 /** 05381 * @brief Enables/Disables compression algorithm runtime.[set] 05382 * 05383 * @param ctx read / write interface definitions 05384 * @param val change the values of fifo_compr_rt_en in 05385 * reg FIFO_CTRL2 05386 * 05387 */ 05388 int32_t lsm6dso_compression_algo_real_time_set(lsm6dso_ctx_t *ctx, 05389 uint8_t val) 05390 { 05391 lsm6dso_fifo_ctrl2_t reg; 05392 int32_t ret; 05393 05394 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05395 if (ret == 0) { 05396 reg.fifo_compr_rt_en = val; 05397 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05398 } 05399 return ret; 05400 } 05401 05402 /** 05403 * @brief Enables/Disables compression algorithm runtime. [get] 05404 * 05405 * @param ctx read / write interface definitions 05406 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2 05407 * 05408 */ 05409 int32_t lsm6dso_compression_algo_real_time_get(lsm6dso_ctx_t *ctx, 05410 uint8_t *val) 05411 { 05412 lsm6dso_fifo_ctrl2_t reg; 05413 int32_t ret; 05414 05415 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05416 *val = reg.fifo_compr_rt_en; 05417 05418 return ret; 05419 } 05420 05421 /** 05422 * @brief Sensing chain FIFO stop values memorization at 05423 * threshold level.[set] 05424 * 05425 * @param ctx read / write interface definitions 05426 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2 05427 * 05428 */ 05429 int32_t lsm6dso_fifo_stop_on_wtm_set(lsm6dso_ctx_t *ctx, uint8_t val) 05430 { 05431 lsm6dso_fifo_ctrl2_t reg; 05432 int32_t ret; 05433 05434 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05435 if (ret == 0) { 05436 reg.stop_on_wtm = val; 05437 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05438 } 05439 return ret; 05440 } 05441 05442 /** 05443 * @brief Sensing chain FIFO stop values memorization at 05444 * threshold level.[get] 05445 * 05446 * @param ctx read / write interface definitions 05447 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2 05448 * 05449 */ 05450 int32_t lsm6dso_fifo_stop_on_wtm_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05451 { 05452 lsm6dso_fifo_ctrl2_t reg; 05453 int32_t ret; 05454 05455 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1); 05456 *val = reg.stop_on_wtm; 05457 05458 return ret; 05459 } 05460 05461 /** 05462 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05463 * for accelerometer data.[set] 05464 * 05465 * @param ctx read / write interface definitions 05466 * @param val change the values of bdr_xl in reg FIFO_CTRL3 05467 * 05468 */ 05469 int32_t lsm6dso_fifo_xl_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_xl_t val) 05470 { 05471 lsm6dso_fifo_ctrl3_t reg; 05472 int32_t ret; 05473 05474 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1); 05475 if (ret == 0) { 05476 reg.bdr_xl = (uint8_t)val; 05477 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1); 05478 } 05479 return ret; 05480 } 05481 05482 /** 05483 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05484 * for accelerometer data.[get] 05485 * 05486 * @param ctx read / write interface definitions 05487 * @param val Get the values of bdr_xl in reg FIFO_CTRL3 05488 * 05489 */ 05490 int32_t lsm6dso_fifo_xl_batch_get(lsm6dso_ctx_t *ctx, lsm6dso_bdr_xl_t *val) 05491 { 05492 lsm6dso_fifo_ctrl3_t reg; 05493 int32_t ret; 05494 05495 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1); 05496 switch (reg.bdr_xl) { 05497 case LSM6DSO_XL_NOT_BATCHED: 05498 *val = LSM6DSO_XL_NOT_BATCHED; 05499 break; 05500 case LSM6DSO_XL_BATCHED_AT_12Hz5: 05501 *val = LSM6DSO_XL_BATCHED_AT_12Hz5; 05502 break; 05503 case LSM6DSO_XL_BATCHED_AT_26Hz: 05504 *val = LSM6DSO_XL_BATCHED_AT_26Hz; 05505 break; 05506 case LSM6DSO_XL_BATCHED_AT_52Hz: 05507 *val = LSM6DSO_XL_BATCHED_AT_52Hz; 05508 break; 05509 case LSM6DSO_XL_BATCHED_AT_104Hz: 05510 *val = LSM6DSO_XL_BATCHED_AT_104Hz; 05511 break; 05512 case LSM6DSO_XL_BATCHED_AT_208Hz: 05513 *val = LSM6DSO_XL_BATCHED_AT_208Hz; 05514 break; 05515 case LSM6DSO_XL_BATCHED_AT_417Hz: 05516 *val = LSM6DSO_XL_BATCHED_AT_417Hz; 05517 break; 05518 case LSM6DSO_XL_BATCHED_AT_833Hz: 05519 *val = LSM6DSO_XL_BATCHED_AT_833Hz; 05520 break; 05521 case LSM6DSO_XL_BATCHED_AT_1667Hz: 05522 *val = LSM6DSO_XL_BATCHED_AT_1667Hz; 05523 break; 05524 case LSM6DSO_XL_BATCHED_AT_3333Hz: 05525 *val = LSM6DSO_XL_BATCHED_AT_3333Hz; 05526 break; 05527 case LSM6DSO_XL_BATCHED_AT_6667Hz: 05528 *val = LSM6DSO_XL_BATCHED_AT_6667Hz; 05529 break; 05530 case LSM6DSO_XL_BATCHED_AT_6Hz5: 05531 *val = LSM6DSO_XL_BATCHED_AT_6Hz5; 05532 break; 05533 default: 05534 *val = LSM6DSO_XL_NOT_BATCHED; 05535 break; 05536 } 05537 05538 return ret; 05539 } 05540 05541 /** 05542 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05543 * for gyroscope data.[set] 05544 * 05545 * @param ctx read / write interface definitions 05546 * @param val change the values of bdr_gy in reg FIFO_CTRL3 05547 * 05548 */ 05549 int32_t lsm6dso_fifo_gy_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_gy_t val) 05550 { 05551 lsm6dso_fifo_ctrl3_t reg; 05552 int32_t ret; 05553 05554 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1); 05555 if (ret == 0) { 05556 reg.bdr_gy = (uint8_t)val; 05557 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1); 05558 } 05559 return ret; 05560 } 05561 05562 /** 05563 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05564 * for gyroscope data.[get] 05565 * 05566 * @param ctx read / write interface definitions 05567 * @param val Get the values of bdr_gy in reg FIFO_CTRL3 05568 * 05569 */ 05570 int32_t lsm6dso_fifo_gy_batch_get(lsm6dso_ctx_t *ctx, lsm6dso_bdr_gy_t *val) 05571 { 05572 lsm6dso_fifo_ctrl3_t reg; 05573 int32_t ret; 05574 05575 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1); 05576 switch (reg.bdr_gy) { 05577 case LSM6DSO_GY_NOT_BATCHED: 05578 *val = LSM6DSO_GY_NOT_BATCHED; 05579 break; 05580 case LSM6DSO_GY_BATCHED_AT_12Hz5: 05581 *val = LSM6DSO_GY_BATCHED_AT_12Hz5; 05582 break; 05583 case LSM6DSO_GY_BATCHED_AT_26Hz: 05584 *val = LSM6DSO_GY_BATCHED_AT_26Hz; 05585 break; 05586 case LSM6DSO_GY_BATCHED_AT_52Hz: 05587 *val = LSM6DSO_GY_BATCHED_AT_52Hz; 05588 break; 05589 case LSM6DSO_GY_BATCHED_AT_104Hz: 05590 *val = LSM6DSO_GY_BATCHED_AT_104Hz; 05591 break; 05592 case LSM6DSO_GY_BATCHED_AT_208Hz: 05593 *val = LSM6DSO_GY_BATCHED_AT_208Hz; 05594 break; 05595 case LSM6DSO_GY_BATCHED_AT_417Hz: 05596 *val = LSM6DSO_GY_BATCHED_AT_417Hz; 05597 break; 05598 case LSM6DSO_GY_BATCHED_AT_833Hz: 05599 *val = LSM6DSO_GY_BATCHED_AT_833Hz; 05600 break; 05601 case LSM6DSO_GY_BATCHED_AT_1667Hz: 05602 *val = LSM6DSO_GY_BATCHED_AT_1667Hz; 05603 break; 05604 case LSM6DSO_GY_BATCHED_AT_3333Hz: 05605 *val = LSM6DSO_GY_BATCHED_AT_3333Hz; 05606 break; 05607 case LSM6DSO_GY_BATCHED_AT_6667Hz: 05608 *val = LSM6DSO_GY_BATCHED_AT_6667Hz; 05609 break; 05610 case LSM6DSO_GY_BATCHED_AT_6Hz5: 05611 *val = LSM6DSO_GY_BATCHED_AT_6Hz5; 05612 break; 05613 default: 05614 *val = LSM6DSO_GY_NOT_BATCHED; 05615 break; 05616 } 05617 return ret; 05618 } 05619 05620 /** 05621 * @brief FIFO mode selection.[set] 05622 * 05623 * @param ctx read / write interface definitions 05624 * @param val change the values of fifo_mode in reg FIFO_CTRL4 05625 * 05626 */ 05627 int32_t lsm6dso_fifo_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_fifo_mode_t val) 05628 { 05629 lsm6dso_fifo_ctrl4_t reg; 05630 int32_t ret; 05631 05632 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1); 05633 if (ret == 0) { 05634 reg.fifo_mode = (uint8_t)val; 05635 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1); 05636 } 05637 return ret; 05638 } 05639 05640 /** 05641 * @brief FIFO mode selection.[get] 05642 * 05643 * @param ctx read / write interface definitions 05644 * @param val Get the values of fifo_mode in reg FIFO_CTRL4 05645 * 05646 */ 05647 int32_t lsm6dso_fifo_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_fifo_mode_t *val) 05648 { 05649 lsm6dso_fifo_ctrl4_t reg; 05650 int32_t ret; 05651 05652 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1); 05653 05654 switch (reg.fifo_mode) { 05655 case LSM6DSO_BYPASS_MODE: 05656 *val = LSM6DSO_BYPASS_MODE; 05657 break; 05658 case LSM6DSO_FIFO_MODE: 05659 *val = LSM6DSO_FIFO_MODE; 05660 break; 05661 case LSM6DSO_STREAM_TO_FIFO_MODE: 05662 *val = LSM6DSO_STREAM_TO_FIFO_MODE; 05663 break; 05664 case LSM6DSO_BYPASS_TO_STREAM_MODE: 05665 *val = LSM6DSO_BYPASS_TO_STREAM_MODE; 05666 break; 05667 case LSM6DSO_STREAM_MODE: 05668 *val = LSM6DSO_STREAM_MODE; 05669 break; 05670 case LSM6DSO_BYPASS_TO_FIFO_MODE: 05671 *val = LSM6DSO_BYPASS_TO_FIFO_MODE; 05672 break; 05673 default: 05674 *val = LSM6DSO_BYPASS_MODE; 05675 break; 05676 } 05677 return ret; 05678 } 05679 05680 /** 05681 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05682 * for temperature data.[set] 05683 * 05684 * @param ctx read / write interface definitions 05685 * @param val change the values of odr_t_batch in reg FIFO_CTRL4 05686 * 05687 */ 05688 int32_t lsm6dso_fifo_temp_batch_set(lsm6dso_ctx_t *ctx, 05689 lsm6dso_odr_t_batch_t val) 05690 { 05691 lsm6dso_fifo_ctrl4_t reg; 05692 int32_t ret; 05693 05694 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1); 05695 if (ret == 0) { 05696 reg.odr_t_batch = (uint8_t)val; 05697 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1); 05698 } 05699 return ret; 05700 } 05701 05702 /** 05703 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05704 * for temperature data.[get] 05705 * 05706 * @param ctx read / write interface definitions 05707 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4 05708 * 05709 */ 05710 int32_t lsm6dso_fifo_temp_batch_get(lsm6dso_ctx_t *ctx, 05711 lsm6dso_odr_t_batch_t *val) 05712 { 05713 lsm6dso_fifo_ctrl4_t reg; 05714 int32_t ret; 05715 05716 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1); 05717 05718 switch (reg.odr_t_batch) { 05719 case LSM6DSO_TEMP_NOT_BATCHED: 05720 *val = LSM6DSO_TEMP_NOT_BATCHED; 05721 break; 05722 case LSM6DSO_TEMP_BATCHED_AT_1Hz6: 05723 *val = LSM6DSO_TEMP_BATCHED_AT_1Hz6; 05724 break; 05725 case LSM6DSO_TEMP_BATCHED_AT_12Hz5: 05726 *val = LSM6DSO_TEMP_BATCHED_AT_12Hz5; 05727 break; 05728 case LSM6DSO_TEMP_BATCHED_AT_52Hz: 05729 *val = LSM6DSO_TEMP_BATCHED_AT_52Hz; 05730 break; 05731 default: 05732 *val = LSM6DSO_TEMP_NOT_BATCHED; 05733 break; 05734 } 05735 return ret; 05736 } 05737 05738 /** 05739 * @brief Selects decimation for timestamp batching in FIFO. 05740 * Writing rate will be the maximum rate between XL and 05741 * GYRO BDR divided by decimation decoder.[set] 05742 * 05743 * @param ctx read / write interface definitions 05744 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4 05745 * 05746 */ 05747 int32_t lsm6dso_fifo_timestamp_decimation_set(lsm6dso_ctx_t *ctx, 05748 lsm6dso_odr_ts_batch_t val) 05749 { 05750 lsm6dso_fifo_ctrl4_t reg; 05751 int32_t ret; 05752 05753 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1); 05754 if (ret == 0) { 05755 reg.odr_ts_batch = (uint8_t)val; 05756 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1); 05757 } 05758 return ret; 05759 } 05760 05761 /** 05762 * @brief Selects decimation for timestamp batching in FIFO. 05763 * Writing rate will be the maximum rate between XL and 05764 * GYRO BDR divided by decimation decoder.[get] 05765 * 05766 * @param ctx read / write interface definitions 05767 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4 05768 * 05769 */ 05770 int32_t lsm6dso_fifo_timestamp_decimation_get(lsm6dso_ctx_t *ctx, 05771 lsm6dso_odr_ts_batch_t *val) 05772 { 05773 lsm6dso_fifo_ctrl4_t reg; 05774 int32_t ret; 05775 05776 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1); 05777 switch (reg.odr_ts_batch) { 05778 case LSM6DSO_NO_DECIMATION: 05779 *val = LSM6DSO_NO_DECIMATION; 05780 break; 05781 case LSM6DSO_DEC_1: 05782 *val = LSM6DSO_DEC_1; 05783 break; 05784 case LSM6DSO_DEC_8: 05785 *val = LSM6DSO_DEC_8; 05786 break; 05787 case LSM6DSO_DEC_32: 05788 *val = LSM6DSO_DEC_32; 05789 break; 05790 default: 05791 *val = LSM6DSO_NO_DECIMATION; 05792 break; 05793 } 05794 return ret; 05795 } 05796 05797 /** 05798 * @brief Selects the trigger for the internal counter of batching events 05799 * between XL and gyro.[set] 05800 * 05801 * @param ctx read / write interface definitions 05802 * @param val change the values of trig_counter_bdr 05803 * in reg COUNTER_BDR_REG1 05804 * 05805 */ 05806 int32_t lsm6dso_fifo_cnt_event_batch_set(lsm6dso_ctx_t *ctx, 05807 lsm6dso_trig_counter_bdr_t val) 05808 { 05809 lsm6dso_counter_bdr_reg1_t reg; 05810 int32_t ret; 05811 05812 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1); 05813 if (ret == 0) { 05814 reg.trig_counter_bdr = (uint8_t)val; 05815 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1); 05816 } 05817 return ret; 05818 } 05819 05820 /** 05821 * @brief Selects the trigger for the internal counter of batching events 05822 * between XL and gyro.[get] 05823 * 05824 * @param ctx read / write interface definitions 05825 * @param val Get the values of trig_counter_bdr 05826 * in reg COUNTER_BDR_REG1 05827 * 05828 */ 05829 int32_t lsm6dso_fifo_cnt_event_batch_get(lsm6dso_ctx_t *ctx, 05830 lsm6dso_trig_counter_bdr_t *val) 05831 { 05832 lsm6dso_counter_bdr_reg1_t reg; 05833 int32_t ret; 05834 05835 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1); 05836 switch (reg.trig_counter_bdr) { 05837 case LSM6DSO_XL_BATCH_EVENT: 05838 *val = LSM6DSO_XL_BATCH_EVENT; 05839 break; 05840 case LSM6DSO_GYRO_BATCH_EVENT: 05841 *val = LSM6DSO_GYRO_BATCH_EVENT; 05842 break; 05843 default: 05844 *val = LSM6DSO_XL_BATCH_EVENT; 05845 break; 05846 } 05847 return ret; 05848 } 05849 05850 /** 05851 * @brief Resets the internal counter of batching vents for a single sensor. 05852 * This bit is automatically reset to zero if it was set to ‘1’.[set] 05853 * 05854 * @param ctx read / write interface definitions 05855 * @param val change the values of rst_counter_bdr in 05856 * reg COUNTER_BDR_REG1 05857 * 05858 */ 05859 int32_t lsm6dso_rst_batch_counter_set(lsm6dso_ctx_t *ctx, uint8_t val) 05860 { 05861 lsm6dso_counter_bdr_reg1_t reg; 05862 int32_t ret; 05863 05864 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1); 05865 if (ret == 0) { 05866 reg.rst_counter_bdr = val; 05867 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1); 05868 } 05869 return ret; 05870 } 05871 05872 /** 05873 * @brief Resets the internal counter of batching events for a single sensor. 05874 * This bit is automatically reset to zero if it was set to ‘1’.[get] 05875 * 05876 * @param ctx read / write interface definitions 05877 * @param val change the values of rst_counter_bdr in 05878 * reg COUNTER_BDR_REG1 05879 * 05880 */ 05881 int32_t lsm6dso_rst_batch_counter_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05882 { 05883 lsm6dso_counter_bdr_reg1_t reg; 05884 int32_t ret; 05885 05886 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1); 05887 *val = reg.rst_counter_bdr; 05888 05889 return ret; 05890 } 05891 05892 /** 05893 * @brief Batch data rate counter.[set] 05894 * 05895 * @param ctx read / write interface definitions 05896 * @param val change the values of cnt_bdr_th in 05897 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1. 05898 * 05899 */ 05900 int32_t lsm6dso_batch_counter_threshold_set(lsm6dso_ctx_t *ctx, uint16_t val) 05901 { 05902 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1; 05903 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2; 05904 int32_t ret; 05905 05906 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, 05907 (uint8_t *)&counter_bdr_reg1, 1); 05908 if (ret == 0) { 05909 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val; 05910 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8; 05911 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, 05912 (uint8_t *)&counter_bdr_reg1, 1); 05913 } 05914 if (ret == 0) { 05915 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG2, 05916 (uint8_t *)&counter_bdr_reg2, 1); 05917 } 05918 return ret; 05919 } 05920 05921 /** 05922 * @brief Batch data rate counter.[get] 05923 * 05924 * @param ctx read / write interface definitions 05925 * @param val change the values of cnt_bdr_th in 05926 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1. 05927 * 05928 */ 05929 int32_t lsm6dso_batch_counter_threshold_get(lsm6dso_ctx_t *ctx, uint16_t *val) 05930 { 05931 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1; 05932 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2; 05933 int32_t ret; 05934 05935 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, 05936 (uint8_t *)&counter_bdr_reg1, 1); 05937 if (ret == 0) { 05938 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2, 05939 (uint8_t *)&counter_bdr_reg2, 1); 05940 05941 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8) 05942 + (uint16_t)counter_bdr_reg2.cnt_bdr_th; 05943 } 05944 05945 return ret; 05946 } 05947 05948 /** 05949 * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get] 05950 * 05951 * @param ctx read / write interface definitions 05952 * @param val change the values of diff_fifo in reg FIFO_STATUS1 05953 * 05954 */ 05955 int32_t lsm6dso_fifo_data_level_get(lsm6dso_ctx_t *ctx, uint16_t *val) 05956 { 05957 lsm6dso_fifo_status1_t fifo_status1; 05958 lsm6dso_fifo_status2_t fifo_status2; 05959 int32_t ret; 05960 05961 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1, 05962 (uint8_t *)&fifo_status1, 1); 05963 if (ret == 0) { 05964 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, 05965 (uint8_t *)&fifo_status2, 1); 05966 *val = ((uint16_t)fifo_status2.diff_fifo << 8) + 05967 (uint16_t)fifo_status1.diff_fifo; 05968 } 05969 return ret; 05970 } 05971 05972 /** 05973 * @brief FIFO status.[get] 05974 * 05975 * @param ctx read / write interface definitions 05976 * @param val registers FIFO_STATUS2 05977 * 05978 */ 05979 int32_t lsm6dso_fifo_status_get(lsm6dso_ctx_t *ctx, 05980 lsm6dso_fifo_status2_t *val) 05981 { 05982 int32_t ret; 05983 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *) val, 1); 05984 return ret; 05985 } 05986 05987 /** 05988 * @brief Smart FIFO full status.[get] 05989 * 05990 * @param ctx read / write interface definitions 05991 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2 05992 * 05993 */ 05994 int32_t lsm6dso_fifo_full_flag_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05995 { 05996 lsm6dso_fifo_status2_t reg; 05997 int32_t ret; 05998 05999 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)®, 1); 06000 *val = reg.fifo_full_ia; 06001 06002 return ret; 06003 } 06004 06005 /** 06006 * @brief FIFO overrun status.[get] 06007 * 06008 * @param ctx read / write interface definitions 06009 * @param val change the values of fifo_over_run_latched in 06010 * reg FIFO_STATUS2 06011 * 06012 */ 06013 int32_t lsm6dso_fifo_ovr_flag_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06014 { 06015 lsm6dso_fifo_status2_t reg; 06016 int32_t ret; 06017 06018 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)®, 1); 06019 *val = reg.fifo_ovr_ia; 06020 06021 return ret; 06022 } 06023 06024 /** 06025 * @brief FIFO watermark status.[get] 06026 * 06027 * @param ctx read / write interface definitions 06028 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2 06029 * 06030 */ 06031 int32_t lsm6dso_fifo_wtm_flag_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06032 { 06033 lsm6dso_fifo_status2_t reg; 06034 int32_t ret; 06035 06036 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)®, 1); 06037 *val = reg.fifo_wtm_ia; 06038 06039 return ret; 06040 } 06041 06042 /** 06043 * @brief Identifies the sensor in FIFO_DATA_OUT.[get] 06044 * 06045 * @param ctx read / write interface definitions 06046 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG 06047 * 06048 */ 06049 int32_t lsm6dso_fifo_sensor_tag_get(lsm6dso_ctx_t *ctx, 06050 lsm6dso_fifo_tag_t *val) 06051 { 06052 lsm6dso_fifo_data_out_tag_t reg; 06053 int32_t ret; 06054 06055 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG, (uint8_t *)®, 1); 06056 switch (reg.tag_sensor) { 06057 case LSM6DSO_GYRO_NC_TAG: 06058 *val = LSM6DSO_GYRO_NC_TAG; 06059 break; 06060 case LSM6DSO_XL_NC_TAG: 06061 *val = LSM6DSO_XL_NC_TAG; 06062 break; 06063 case LSM6DSO_TEMPERATURE_TAG: 06064 *val = LSM6DSO_TEMPERATURE_TAG; 06065 break; 06066 case LSM6DSO_CFG_CHANGE_TAG: 06067 *val = LSM6DSO_CFG_CHANGE_TAG; 06068 break; 06069 case LSM6DSO_XL_NC_T_2_TAG: 06070 *val = LSM6DSO_XL_NC_T_2_TAG; 06071 break; 06072 case LSM6DSO_XL_NC_T_1_TAG: 06073 *val = LSM6DSO_XL_NC_T_1_TAG; 06074 break; 06075 case LSM6DSO_XL_2XC_TAG: 06076 *val = LSM6DSO_XL_2XC_TAG; 06077 break; 06078 case LSM6DSO_XL_3XC_TAG: 06079 *val = LSM6DSO_XL_3XC_TAG; 06080 break; 06081 case LSM6DSO_GYRO_NC_T_2_TAG: 06082 *val = LSM6DSO_GYRO_NC_T_2_TAG; 06083 break; 06084 case LSM6DSO_GYRO_NC_T_1_TAG: 06085 *val = LSM6DSO_GYRO_NC_T_1_TAG; 06086 break; 06087 case LSM6DSO_GYRO_2XC_TAG: 06088 *val = LSM6DSO_GYRO_2XC_TAG; 06089 break; 06090 case LSM6DSO_GYRO_3XC_TAG: 06091 *val = LSM6DSO_GYRO_3XC_TAG; 06092 break; 06093 case LSM6DSO_SENSORHUB_SLAVE0_TAG: 06094 *val = LSM6DSO_SENSORHUB_SLAVE0_TAG; 06095 break; 06096 case LSM6DSO_SENSORHUB_SLAVE1_TAG: 06097 *val = LSM6DSO_SENSORHUB_SLAVE1_TAG; 06098 break; 06099 case LSM6DSO_SENSORHUB_SLAVE2_TAG: 06100 *val = LSM6DSO_SENSORHUB_SLAVE2_TAG; 06101 break; 06102 case LSM6DSO_SENSORHUB_SLAVE3_TAG: 06103 *val = LSM6DSO_SENSORHUB_SLAVE3_TAG; 06104 break; 06105 case LSM6DSO_STEP_CPUNTER_TAG: 06106 *val = LSM6DSO_STEP_CPUNTER_TAG; 06107 break; 06108 case LSM6DSO_GAME_ROTATION_TAG: 06109 *val = LSM6DSO_GAME_ROTATION_TAG; 06110 break; 06111 case LSM6DSO_GEOMAG_ROTATION_TAG: 06112 *val = LSM6DSO_GEOMAG_ROTATION_TAG; 06113 break; 06114 case LSM6DSO_ROTATION_TAG: 06115 *val = LSM6DSO_ROTATION_TAG; 06116 break; 06117 case LSM6DSO_SENSORHUB_NACK_TAG: 06118 *val = LSM6DSO_SENSORHUB_NACK_TAG; 06119 break; 06120 default: 06121 *val = LSM6DSO_GYRO_NC_TAG; 06122 break; 06123 } 06124 return ret; 06125 } 06126 06127 /** 06128 * @brief : Enable FIFO batching of pedometer embedded 06129 * function values.[set] 06130 * 06131 * @param ctx read / write interface definitions 06132 * @param val change the values of gbias_fifo_en in 06133 * reg LSM6DSO_EMB_FUNC_FIFO_CFG 06134 * 06135 */ 06136 int32_t lsm6dso_fifo_pedo_batch_set(lsm6dso_ctx_t *ctx, uint8_t val) 06137 { 06138 lsm6dso_emb_func_fifo_cfg_t reg; 06139 int32_t ret; 06140 06141 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06142 if (ret == 0) { 06143 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t *)®, 1); 06144 } 06145 if (ret == 0) { 06146 reg.pedo_fifo_en = val; 06147 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, 06148 (uint8_t *)®, 1); 06149 } 06150 if (ret == 0) { 06151 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06152 } 06153 return ret; 06154 } 06155 06156 /** 06157 * @brief Enable FIFO batching of pedometer embedded function values.[get] 06158 * 06159 * @param ctx read / write interface definitions 06160 * @param val change the values of pedo_fifo_en in 06161 * reg LSM6DSO_EMB_FUNC_FIFO_CFG 06162 * 06163 */ 06164 int32_t lsm6dso_fifo_pedo_batch_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06165 { 06166 lsm6dso_emb_func_fifo_cfg_t reg; 06167 int32_t ret; 06168 06169 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06170 if (ret == 0) { 06171 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t *)®, 1); 06172 } 06173 if (ret == 0) { 06174 *val = reg.pedo_fifo_en; 06175 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06176 } 06177 return ret; 06178 } 06179 06180 /** 06181 * @brief Enable FIFO batching data of first slave.[set] 06182 * 06183 * @param ctx read / write interface definitions 06184 * @param val change the values of batch_ext_sens_0_en in 06185 * reg SLV0_CONFIG 06186 * 06187 */ 06188 int32_t lsm6dso_sh_batch_slave_0_set(lsm6dso_ctx_t *ctx, uint8_t val) 06189 { 06190 lsm6dso_slv0_config_t reg; 06191 int32_t ret; 06192 06193 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06194 if (ret == 0) { 06195 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1); 06196 } 06197 if (ret == 0) { 06198 reg.batch_ext_sens_0_en = val; 06199 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1); 06200 } 06201 if (ret == 0) { 06202 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06203 } 06204 return ret; 06205 } 06206 06207 /** 06208 * @brief Enable FIFO batching data of first slave.[get] 06209 * 06210 * @param ctx read / write interface definitions 06211 * @param val change the values of batch_ext_sens_0_en in 06212 * reg SLV0_CONFIG 06213 * 06214 */ 06215 int32_t lsm6dso_sh_batch_slave_0_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06216 { 06217 lsm6dso_slv0_config_t reg; 06218 int32_t ret; 06219 06220 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06221 if (ret == 0) { 06222 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1); 06223 } 06224 if (ret == 0) { 06225 *val = reg.batch_ext_sens_0_en; 06226 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06227 } 06228 return ret; 06229 } 06230 06231 /** 06232 * @brief Enable FIFO batching data of second slave.[set] 06233 * 06234 * @param ctx read / write interface definitions 06235 * @param val change the values of batch_ext_sens_1_en in 06236 * reg SLV1_CONFIG 06237 * 06238 */ 06239 int32_t lsm6dso_sh_batch_slave_1_set(lsm6dso_ctx_t *ctx, uint8_t val) 06240 { 06241 lsm6dso_slv1_config_t reg; 06242 int32_t ret; 06243 06244 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06245 if (ret == 0) { 06246 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1); 06247 } 06248 if (ret == 0) { 06249 reg.batch_ext_sens_1_en = val; 06250 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1); 06251 } 06252 if (ret == 0) { 06253 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06254 } 06255 06256 return ret; 06257 } 06258 06259 /** 06260 * @brief Enable FIFO batching data of second slave.[get] 06261 * 06262 * @param ctx read / write interface definitions 06263 * @param val change the values of batch_ext_sens_1_en in 06264 * reg SLV1_CONFIG 06265 * 06266 */ 06267 int32_t lsm6dso_sh_batch_slave_1_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06268 { 06269 lsm6dso_slv1_config_t reg; 06270 int32_t ret; 06271 06272 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06273 if (ret == 0) { 06274 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1); 06275 *val = reg.batch_ext_sens_1_en; 06276 } 06277 if (ret == 0) { 06278 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06279 } 06280 return ret; 06281 } 06282 06283 /** 06284 * @brief Enable FIFO batching data of third slave.[set] 06285 * 06286 * @param ctx read / write interface definitions 06287 * @param val change the values of batch_ext_sens_2_en in 06288 * reg SLV2_CONFIG 06289 * 06290 */ 06291 int32_t lsm6dso_sh_batch_slave_2_set(lsm6dso_ctx_t *ctx, uint8_t val) 06292 { 06293 lsm6dso_slv2_config_t reg; 06294 int32_t ret; 06295 06296 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06297 06298 if (ret == 0) { 06299 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)®, 1); 06300 } 06301 if (ret == 0) { 06302 reg.batch_ext_sens_2_en = val; 06303 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)®, 1); 06304 } 06305 if (ret == 0) { 06306 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06307 } 06308 return ret; 06309 } 06310 06311 /** 06312 * @brief Enable FIFO batching data of third slave.[get] 06313 * 06314 * @param ctx read / write interface definitions 06315 * @param val change the values of batch_ext_sens_2_en in 06316 * reg SLV2_CONFIG 06317 * 06318 */ 06319 int32_t lsm6dso_sh_batch_slave_2_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06320 { 06321 lsm6dso_slv2_config_t reg; 06322 int32_t ret; 06323 06324 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06325 if (ret == 0) { 06326 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)®, 1); 06327 } 06328 if (ret == 0) { 06329 *val = reg.batch_ext_sens_2_en; 06330 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06331 } 06332 06333 return ret; 06334 } 06335 06336 /** 06337 * @brief Enable FIFO batching data of fourth slave.[set] 06338 * 06339 * @param ctx read / write interface definitions 06340 * @param val change the values of batch_ext_sens_3_en 06341 * in reg SLV3_CONFIG 06342 * 06343 */ 06344 int32_t lsm6dso_sh_batch_slave_3_set(lsm6dso_ctx_t *ctx, uint8_t val) 06345 { 06346 lsm6dso_slv3_config_t reg; 06347 int32_t ret; 06348 06349 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06350 if (ret == 0) { 06351 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)®, 1); 06352 } 06353 if (ret == 0) { 06354 reg.batch_ext_sens_3_en = val; 06355 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)®, 1); 06356 } 06357 if (ret == 0) { 06358 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06359 } 06360 06361 return ret; 06362 } 06363 06364 /** 06365 * @brief Enable FIFO batching data of fourth slave.[get] 06366 * 06367 * @param ctx read / write interface definitions 06368 * @param val change the values of batch_ext_sens_3_en in 06369 * reg SLV3_CONFIG 06370 * 06371 */ 06372 int32_t lsm6dso_sh_batch_slave_3_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06373 { 06374 lsm6dso_slv3_config_t reg; 06375 int32_t ret; 06376 06377 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06378 if (ret == 0) { 06379 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)®, 1); 06380 } 06381 if (ret == 0) { 06382 *val = reg.batch_ext_sens_3_en; 06383 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06384 } 06385 06386 return ret; 06387 } 06388 06389 /** 06390 * @} 06391 * 06392 */ 06393 06394 /** 06395 * @defgroup LSM6DSO_DEN_functionality 06396 * @brief This section groups all the functions concerning 06397 * DEN functionality. 06398 * @{ 06399 * 06400 */ 06401 06402 /** 06403 * @brief DEN functionality marking mode.[set] 06404 * 06405 * @param ctx read / write interface definitions 06406 * @param val change the values of den_mode in reg CTRL6_C 06407 * 06408 */ 06409 int32_t lsm6dso_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_den_mode_t val) 06410 { 06411 lsm6dso_ctrl6_c_t reg; 06412 int32_t ret; 06413 06414 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1); 06415 if (ret == 0) { 06416 reg.den_mode = (uint8_t)val; 06417 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1); 06418 } 06419 06420 return ret; 06421 } 06422 06423 /** 06424 * @brief DEN functionality marking mode.[get] 06425 * 06426 * @param ctx read / write interface definitions 06427 * @param val Get the values of den_mode in reg CTRL6_C 06428 * 06429 */ 06430 int32_t lsm6dso_den_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_den_mode_t *val) 06431 { 06432 lsm6dso_ctrl6_c_t reg; 06433 int32_t ret; 06434 06435 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1); 06436 06437 switch (reg.den_mode) { 06438 case LSM6DSO_DEN_DISABLE: 06439 *val = LSM6DSO_DEN_DISABLE; 06440 break; 06441 case LSM6DSO_LEVEL_FIFO: 06442 *val = LSM6DSO_LEVEL_FIFO; 06443 break; 06444 case LSM6DSO_LEVEL_LETCHED: 06445 *val = LSM6DSO_LEVEL_LETCHED; 06446 break; 06447 case LSM6DSO_LEVEL_TRIGGER: 06448 *val = LSM6DSO_LEVEL_TRIGGER; 06449 break; 06450 case LSM6DSO_EDGE_TRIGGER: 06451 *val = LSM6DSO_EDGE_TRIGGER; 06452 break; 06453 default: 06454 *val = LSM6DSO_DEN_DISABLE; 06455 break; 06456 } 06457 return ret; 06458 } 06459 06460 /** 06461 * @brief DEN active level configuration.[set] 06462 * 06463 * @param ctx read / write interface definitions 06464 * @param val change the values of den_lh in reg CTRL9_XL 06465 * 06466 */ 06467 int32_t lsm6dso_den_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_den_lh_t val) 06468 { 06469 lsm6dso_ctrl9_xl_t reg; 06470 int32_t ret; 06471 06472 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06473 if (ret == 0) { 06474 reg.den_lh = (uint8_t)val; 06475 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06476 } 06477 06478 return ret; 06479 } 06480 06481 /** 06482 * @brief DEN active level configuration.[get] 06483 * 06484 * @param ctx read / write interface definitions 06485 * @param val Get the values of den_lh in reg CTRL9_XL 06486 * 06487 */ 06488 int32_t lsm6dso_den_polarity_get(lsm6dso_ctx_t *ctx, lsm6dso_den_lh_t *val) 06489 { 06490 lsm6dso_ctrl9_xl_t reg; 06491 int32_t ret; 06492 06493 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06494 06495 switch (reg.den_lh) { 06496 case LSM6DSO_DEN_ACT_LOW: 06497 *val = LSM6DSO_DEN_ACT_LOW; 06498 break; 06499 case LSM6DSO_DEN_ACT_HIGH: 06500 *val = LSM6DSO_DEN_ACT_HIGH; 06501 break; 06502 default: 06503 *val = LSM6DSO_DEN_ACT_LOW; 06504 break; 06505 } 06506 return ret; 06507 } 06508 06509 /** 06510 * @brief DEN enable.[set] 06511 * 06512 * @param ctx read / write interface definitions 06513 * @param val change the values of den_xl_g in reg CTRL9_XL 06514 * 06515 */ 06516 int32_t lsm6dso_den_enable_set(lsm6dso_ctx_t *ctx, lsm6dso_den_xl_g_t val) 06517 { 06518 lsm6dso_ctrl9_xl_t reg; 06519 int32_t ret; 06520 06521 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06522 if (ret == 0) { 06523 reg.den_xl_g = (uint8_t)val; 06524 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06525 } 06526 06527 return ret; 06528 } 06529 06530 /** 06531 * @brief DEN enable.[get] 06532 * 06533 * @param ctx read / write interface definitions 06534 * @param val Get the values of den_xl_g in reg CTRL9_XL 06535 * 06536 */ 06537 int32_t lsm6dso_den_enable_get(lsm6dso_ctx_t *ctx, lsm6dso_den_xl_g_t *val) 06538 { 06539 lsm6dso_ctrl9_xl_t reg; 06540 int32_t ret; 06541 06542 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06543 06544 switch (reg.den_xl_g) { 06545 case LSM6DSO_STAMP_IN_GY_DATA: 06546 *val = LSM6DSO_STAMP_IN_GY_DATA; 06547 break; 06548 case LSM6DSO_STAMP_IN_XL_DATA: 06549 *val = LSM6DSO_STAMP_IN_XL_DATA; 06550 break; 06551 case LSM6DSO_STAMP_IN_GY_XL_DATA: 06552 *val = LSM6DSO_STAMP_IN_GY_XL_DATA; 06553 break; 06554 default: 06555 *val = LSM6DSO_STAMP_IN_GY_DATA; 06556 break; 06557 } 06558 return ret; 06559 } 06560 06561 /** 06562 * @brief DEN value stored in LSB of X-axis.[set] 06563 * 06564 * @param ctx read / write interface definitions 06565 * @param val change the values of den_z in reg CTRL9_XL 06566 * 06567 */ 06568 int32_t lsm6dso_den_mark_axis_x_set(lsm6dso_ctx_t *ctx, uint8_t val) 06569 { 06570 lsm6dso_ctrl9_xl_t reg; 06571 int32_t ret; 06572 06573 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06574 if (ret == 0) { 06575 reg.den_z = val; 06576 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06577 } 06578 06579 return ret; 06580 } 06581 06582 /** 06583 * @brief DEN value stored in LSB of X-axis.[get] 06584 * 06585 * @param ctx read / write interface definitions 06586 * @param val change the values of den_z in reg CTRL9_XL 06587 * 06588 */ 06589 int32_t lsm6dso_den_mark_axis_x_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06590 { 06591 lsm6dso_ctrl9_xl_t reg; 06592 int32_t ret; 06593 06594 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06595 *val = reg.den_z; 06596 06597 return ret; 06598 } 06599 06600 /** 06601 * @brief DEN value stored in LSB of Y-axis.[set] 06602 * 06603 * @param ctx read / write interface definitions 06604 * @param val change the values of den_y in reg CTRL9_XL 06605 * 06606 */ 06607 int32_t lsm6dso_den_mark_axis_y_set(lsm6dso_ctx_t *ctx, uint8_t val) 06608 { 06609 lsm6dso_ctrl9_xl_t reg; 06610 int32_t ret; 06611 06612 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06613 if (ret == 0) { 06614 reg.den_y = val; 06615 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06616 } 06617 06618 return ret; 06619 } 06620 06621 /** 06622 * @brief DEN value stored in LSB of Y-axis.[get] 06623 * 06624 * @param ctx read / write interface definitions 06625 * @param val change the values of den_y in reg CTRL9_XL 06626 * 06627 */ 06628 int32_t lsm6dso_den_mark_axis_y_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06629 { 06630 lsm6dso_ctrl9_xl_t reg; 06631 int32_t ret; 06632 06633 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06634 *val = reg.den_y; 06635 06636 return ret; 06637 } 06638 06639 /** 06640 * @brief DEN value stored in LSB of Z-axis.[set] 06641 * 06642 * @param ctx read / write interface definitions 06643 * @param val change the values of den_x in reg CTRL9_XL 06644 * 06645 */ 06646 int32_t lsm6dso_den_mark_axis_z_set(lsm6dso_ctx_t *ctx, uint8_t val) 06647 { 06648 lsm6dso_ctrl9_xl_t reg; 06649 int32_t ret; 06650 06651 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06652 if (ret == 0) { 06653 reg.den_x = val; 06654 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06655 } 06656 06657 return ret; 06658 } 06659 06660 /** 06661 * @brief DEN value stored in LSB of Z-axis.[get] 06662 * 06663 * @param ctx read / write interface definitions 06664 * @param val change the values of den_x in reg CTRL9_XL 06665 * 06666 */ 06667 int32_t lsm6dso_den_mark_axis_z_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06668 { 06669 lsm6dso_ctrl9_xl_t reg; 06670 int32_t ret; 06671 06672 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1); 06673 *val = reg.den_x; 06674 06675 return ret; 06676 } 06677 06678 /** 06679 * @} 06680 * 06681 */ 06682 06683 /** 06684 * @defgroup LSM6DSO_Pedometer 06685 * @brief This section groups all the functions that manage pedometer. 06686 * @{ 06687 * 06688 */ 06689 06690 /** 06691 * @brief Enable pedometer algorithm.[set] 06692 * 06693 * @param ctx read / write interface definitions 06694 * @param val turn on and configure pedometer 06695 * 06696 */ 06697 int32_t lsm6dso_pedo_sens_set(lsm6dso_ctx_t *ctx, lsm6dso_pedo_md_t val) 06698 { 06699 lsm6dso_emb_func_en_a_t emb_func_en_a; 06700 lsm6dso_emb_func_en_b_t emb_func_en_b; 06701 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg; 06702 int32_t ret; 06703 06704 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, 06705 (uint8_t *)&pedo_cmd_reg); 06706 if (ret == 0) { 06707 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06708 } 06709 if (ret == 0) { 06710 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, 06711 (uint8_t *)&emb_func_en_a, 1); 06712 } 06713 if (ret == 0) { 06714 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 06715 (uint8_t *)&emb_func_en_b, 1); 06716 06717 emb_func_en_a.pedo_en = (uint8_t)val & 0x01U; 06718 emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U) >> 1; 06719 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4; 06720 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5; 06721 } 06722 if (ret == 0) { 06723 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, 06724 (uint8_t *)&emb_func_en_a, 1); 06725 } 06726 if (ret == 0) { 06727 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 06728 (uint8_t *)&emb_func_en_b, 1); 06729 } 06730 if (ret == 0) { 06731 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06732 } 06733 if (ret == 0) { 06734 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG, 06735 (uint8_t *)&pedo_cmd_reg); 06736 } 06737 return ret; 06738 } 06739 06740 /** 06741 * @brief Enable pedometer algorithm.[get] 06742 * 06743 * @param ctx read / write interface definitions 06744 * @param val turn on and configure pedometer 06745 * 06746 */ 06747 int32_t lsm6dso_pedo_sens_get(lsm6dso_ctx_t *ctx, lsm6dso_pedo_md_t *val) 06748 { 06749 lsm6dso_emb_func_en_a_t emb_func_en_a; 06750 lsm6dso_emb_func_en_b_t emb_func_en_b; 06751 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg; 06752 int32_t ret; 06753 06754 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, 06755 (uint8_t *)&pedo_cmd_reg); 06756 if (ret == 0) { 06757 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06758 } 06759 if (ret == 0) { 06760 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, 06761 (uint8_t *)&emb_func_en_a, 1); 06762 } 06763 if (ret == 0) { 06764 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 06765 (uint8_t *)&emb_func_en_b, 1); 06766 } 06767 if (ret == 0) { 06768 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06769 } 06770 switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en << 4) | 06771 (emb_func_en_b.pedo_adv_en << 1) | emb_func_en_a.pedo_en) { 06772 case LSM6DSO_PEDO_DISABLE: 06773 *val = LSM6DSO_PEDO_DISABLE; 06774 break; 06775 case LSM6DSO_PEDO_BASE_MODE: 06776 *val = LSM6DSO_PEDO_BASE_MODE; 06777 break; 06778 case LSM6DSO_PEDO_ADV_MODE: 06779 *val = LSM6DSO_PEDO_ADV_MODE; 06780 break; 06781 case LSM6DSO_FALSE_STEP_REJ: 06782 *val = LSM6DSO_FALSE_STEP_REJ; 06783 break; 06784 case LSM6DSO_FALSE_STEP_REJ_ADV_MODE: 06785 *val = LSM6DSO_FALSE_STEP_REJ_ADV_MODE; 06786 break; 06787 default: 06788 *val = LSM6DSO_PEDO_DISABLE; 06789 break; 06790 } 06791 return ret; 06792 } 06793 06794 /** 06795 * @brief Interrupt status bit for step detection.[get] 06796 * 06797 * @param ctx read / write interface definitions 06798 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS 06799 * 06800 */ 06801 int32_t lsm6dso_pedo_step_detect_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06802 { 06803 lsm6dso_emb_func_status_t reg; 06804 int32_t ret; 06805 06806 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06807 if (ret == 0) { 06808 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1); 06809 } 06810 if (ret == 0) { 06811 *val = reg.is_step_det; 06812 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06813 } 06814 06815 return ret; 06816 } 06817 06818 /** 06819 * @brief Pedometer debounce configuration register (r/w).[set] 06820 * 06821 * @param ctx read / write interface definitions 06822 * @param buff buffer that contains data to write 06823 * 06824 */ 06825 int32_t lsm6dso_pedo_debounce_steps_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 06826 { 06827 int32_t ret; 06828 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff); 06829 return ret; 06830 } 06831 06832 /** 06833 * @brief Pedometer debounce configuration register (r/w).[get] 06834 * 06835 * @param ctx read / write interface definitions 06836 * @param buff buffer that stores data read 06837 * 06838 */ 06839 int32_t lsm6dso_pedo_debounce_steps_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 06840 { 06841 int32_t ret; 06842 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff); 06843 return ret; 06844 } 06845 06846 /** 06847 * @brief Time period register for step detection on delta time (r/w).[set] 06848 * 06849 * @param ctx read / write interface definitions 06850 * @param buff buffer that contains data to write 06851 * 06852 */ 06853 int32_t lsm6dso_pedo_steps_period_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 06854 { 06855 int32_t ret; 06856 uint8_t index; 06857 06858 index = 0x00U; 06859 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]); 06860 if (ret == 0) { 06861 index++; 06862 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H, 06863 &buff[index]); 06864 } 06865 return ret; 06866 } 06867 06868 /** 06869 * @brief Time period register for step detection on delta time (r/w).[get] 06870 * 06871 * @param ctx read / write interface definitions 06872 * @param buff buffer that stores data read 06873 * 06874 */ 06875 int32_t lsm6dso_pedo_steps_period_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 06876 { 06877 int32_t ret; 06878 uint8_t index; 06879 06880 index = 0x00U; 06881 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]); 06882 if (ret == 0) { 06883 index++; 06884 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H, 06885 &buff[index]); 06886 } 06887 return ret; 06888 } 06889 06890 /** 06891 * @brief Set when user wants to generate interrupt on count overflow 06892 * event/every step.[set] 06893 * 06894 * @param ctx read / write interface definitions 06895 * @param val change the values of carry_count_en in reg PEDO_CMD_REG 06896 * 06897 */ 06898 int32_t lsm6dso_pedo_int_mode_set(lsm6dso_ctx_t *ctx, 06899 lsm6dso_carry_count_en_t val) 06900 { 06901 lsm6dso_pedo_cmd_reg_t reg; 06902 int32_t ret; 06903 06904 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t *)®); 06905 if (ret == 0) { 06906 reg.carry_count_en = (uint8_t)val; 06907 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG, 06908 (uint8_t *)®); 06909 } 06910 return ret; 06911 } 06912 06913 /** 06914 * @brief Set when user wants to generate interrupt on count overflow 06915 * event/every step.[get] 06916 * 06917 * @param ctx read / write interface definitions 06918 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG 06919 * 06920 */ 06921 int32_t lsm6dso_pedo_int_mode_get(lsm6dso_ctx_t *ctx, 06922 lsm6dso_carry_count_en_t *val) 06923 { 06924 lsm6dso_pedo_cmd_reg_t reg; 06925 int32_t ret; 06926 06927 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t *)®); 06928 switch (reg.carry_count_en) { 06929 case LSM6DSO_EVERY_STEP: 06930 *val = LSM6DSO_EVERY_STEP; 06931 break; 06932 case LSM6DSO_COUNT_OVERFLOW: 06933 *val = LSM6DSO_COUNT_OVERFLOW; 06934 break; 06935 default: 06936 *val = LSM6DSO_EVERY_STEP; 06937 break; 06938 } 06939 return ret; 06940 } 06941 06942 /** 06943 * @} 06944 * 06945 */ 06946 06947 /** 06948 * @defgroup LSM6DSO_significant_motion 06949 * @brief This section groups all the functions that manage the 06950 * significant motion detection. 06951 * @{ 06952 * 06953 */ 06954 06955 /** 06956 * @brief Enable significant motion detection function.[set] 06957 * 06958 * @param ctx read / write interface definitions 06959 * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A 06960 * 06961 */ 06962 int32_t lsm6dso_motion_sens_set(lsm6dso_ctx_t *ctx, uint8_t val) 06963 { 06964 lsm6dso_emb_func_en_a_t reg; 06965 int32_t ret; 06966 06967 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06968 if (ret == 0) { 06969 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)®, 1); 06970 } 06971 if (ret == 0) { 06972 reg.sign_motion_en = val; 06973 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)®, 1); 06974 } 06975 if (ret == 0) { 06976 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06977 } 06978 return ret; 06979 } 06980 06981 /** 06982 * @brief Enable significant motion detection function.[get] 06983 * 06984 * @param ctx read / write interface definitions 06985 * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A 06986 * 06987 */ 06988 int32_t lsm6dso_motion_sens_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06989 { 06990 lsm6dso_emb_func_en_a_t reg; 06991 int32_t ret; 06992 06993 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06994 if (ret == 0) { 06995 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)®, 1); 06996 } 06997 if (ret == 0) { 06998 *val = reg.sign_motion_en; 06999 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07000 } 07001 return ret; 07002 } 07003 07004 /** 07005 * @brief Interrupt status bit for significant motion detection.[get] 07006 * 07007 * @param ctx read / write interface definitions 07008 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS 07009 * 07010 */ 07011 int32_t lsm6dso_motion_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 07012 { 07013 lsm6dso_emb_func_status_t reg; 07014 int32_t ret; 07015 07016 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07017 if (ret == 0) { 07018 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1); 07019 } 07020 if (ret == 0) { 07021 *val = reg.is_sigmot; 07022 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07023 } 07024 07025 return ret; 07026 } 07027 07028 /** 07029 * @} 07030 * 07031 */ 07032 07033 /** 07034 * @defgroup LSM6DSO_tilt_detection 07035 * @brief This section groups all the functions that manage the tilt 07036 * event detection. 07037 * @{ 07038 * 07039 */ 07040 07041 /** 07042 * @brief Enable tilt calculation.[set] 07043 * 07044 * @param ctx read / write interface definitions 07045 * @param val change the values of tilt_en in reg EMB_FUNC_EN_A 07046 * 07047 */ 07048 int32_t lsm6dso_tilt_sens_set(lsm6dso_ctx_t *ctx, uint8_t val) 07049 { 07050 lsm6dso_emb_func_en_a_t reg; 07051 int32_t ret; 07052 07053 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07054 if (ret == 0) { 07055 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)®, 1); 07056 } 07057 if (ret == 0) { 07058 reg.tilt_en = val; 07059 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)®, 1); 07060 } 07061 if (ret == 0) { 07062 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07063 } 07064 return ret; 07065 } 07066 07067 /** 07068 * @brief Enable tilt calculation.[get] 07069 * 07070 * @param ctx read / write interface definitions 07071 * @param val change the values of tilt_en in reg EMB_FUNC_EN_A 07072 * 07073 */ 07074 int32_t lsm6dso_tilt_sens_get(lsm6dso_ctx_t *ctx, uint8_t *val) 07075 { 07076 lsm6dso_emb_func_en_a_t reg; 07077 int32_t ret; 07078 07079 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07080 if (ret == 0) { 07081 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)®, 1); 07082 } 07083 if (ret == 0) { 07084 *val = reg.tilt_en; 07085 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07086 } 07087 07088 return ret; 07089 } 07090 07091 /** 07092 * @brief Interrupt status bit for tilt detection.[get] 07093 * 07094 * @param ctx read / write interface definitions 07095 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS 07096 * 07097 */ 07098 int32_t lsm6dso_tilt_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 07099 { 07100 lsm6dso_emb_func_status_t reg; 07101 int32_t ret; 07102 07103 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07104 if (ret == 0) { 07105 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1); 07106 } 07107 if (ret == 0) { 07108 *val = reg.is_tilt; 07109 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07110 } 07111 07112 return ret; 07113 } 07114 07115 /** 07116 * @} 07117 * 07118 */ 07119 07120 /** 07121 * @defgroup LSM6DSO_ magnetometer_sensor 07122 * @brief This section groups all the functions that manage additional 07123 * magnetometer sensor. 07124 * @{ 07125 * 07126 */ 07127 07128 /** 07129 * @brief External magnetometer sensitivity value register.[set] 07130 * 07131 * @param ctx read / write interface definitions 07132 * @param buff buffer that contains data to write 07133 * 07134 */ 07135 int32_t lsm6dso_mag_sensitivity_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 07136 { 07137 int32_t ret; 07138 uint8_t index; 07139 07140 index = 0x00U; 07141 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L, 07142 &buff[index]); 07143 if (ret == 0) { 07144 index++; 07145 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H, 07146 &buff[index]); 07147 } 07148 07149 return ret; 07150 } 07151 07152 /** 07153 * @brief External magnetometer sensitivity value register.[get] 07154 * 07155 * @param ctx read / write interface definitions 07156 * @param buff buffer that stores data read 07157 * 07158 */ 07159 int32_t lsm6dso_mag_sensitivity_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 07160 { 07161 int32_t ret; 07162 uint8_t index; 07163 07164 index = 0x00U; 07165 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L, 07166 &buff[index]); 07167 if (ret == 0) { 07168 index++; 07169 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H, 07170 &buff[index]); 07171 } 07172 07173 return ret; 07174 } 07175 07176 /** 07177 * @brief Offset for hard-iron compensation register (r/w).[set] 07178 * 07179 * @param ctx read / write interface definitions 07180 * @param buff buffer that contains data to write 07181 * 07182 */ 07183 int32_t lsm6dso_mag_offset_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 07184 { 07185 int32_t ret; 07186 uint8_t index; 07187 07188 index = 0x00U; 07189 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]); 07190 if (ret == 0) { 07191 index++; 07192 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]); 07193 } 07194 if (ret == 0) { 07195 index++; 07196 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]); 07197 } 07198 if (ret == 0) { 07199 index++; 07200 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]); 07201 } 07202 if (ret == 0) { 07203 index++; 07204 07205 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]); 07206 } 07207 if (ret == 0) { 07208 index++; 07209 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]); 07210 } 07211 07212 return ret; 07213 } 07214 07215 /** 07216 * @brief Offset for hard-iron compensation register (r/w).[get] 07217 * 07218 * @param ctx read / write interface definitions 07219 * @param buff buffer that stores data read 07220 * 07221 */ 07222 int32_t lsm6dso_mag_offset_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 07223 { 07224 int32_t ret; 07225 uint8_t index; 07226 07227 index = 0x00U; 07228 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]); 07229 if (ret == 0) { 07230 index++; 07231 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]); 07232 } 07233 if (ret == 0) { 07234 index++; 07235 07236 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]); 07237 } 07238 if (ret == 0) { 07239 index++; 07240 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]); 07241 } 07242 if (ret == 0) { 07243 index++; 07244 07245 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]); 07246 } 07247 if (ret == 0) { 07248 index++; 07249 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]); 07250 } 07251 return ret; 07252 } 07253 07254 /** 07255 * @brief Soft-iron (3x3 symmetric) matrix correction 07256 * register (r/w). The value is expressed as 07257 * half-precision floating-point format: 07258 * SEEEEEFFFFFFFFFF 07259 * S: 1 sign bit; 07260 * E: 5 exponent bits; 07261 * F: 10 fraction bits).[set] 07262 * 07263 * @param ctx read / write interface definitions 07264 * @param buff buffer that contains data to write 07265 * 07266 */ 07267 int32_t lsm6dso_mag_soft_iron_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 07268 { 07269 int32_t ret; 07270 uint8_t index; 07271 07272 index = 0x00U; 07273 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]); 07274 if (ret == 0) { 07275 index++; 07276 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]); 07277 } 07278 if (ret == 0) { 07279 index++; 07280 07281 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]); 07282 } 07283 if (ret == 0) { 07284 index++; 07285 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]); 07286 } 07287 if (ret == 0) { 07288 index++; 07289 07290 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]); 07291 } 07292 if (ret == 0) { 07293 index++; 07294 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]); 07295 } 07296 if (ret == 0) { 07297 index++; 07298 07299 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]); 07300 } 07301 if (ret == 0) { 07302 index++; 07303 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]); 07304 } 07305 if (ret == 0) { 07306 index++; 07307 07308 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]); 07309 } 07310 if (ret == 0) { 07311 index++; 07312 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]); 07313 } 07314 if (ret == 0) { 07315 index++; 07316 07317 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]); 07318 } 07319 if (ret == 0) { 07320 index++; 07321 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]); 07322 } 07323 07324 return ret; 07325 } 07326 07327 /** 07328 * @brief Soft-iron (3x3 symmetric) matrix 07329 * correction register (r/w). 07330 * The value is expressed as half-precision 07331 * floating-point format: 07332 * SEEEEEFFFFFFFFFF 07333 * S: 1 sign bit; 07334 * E: 5 exponent bits; 07335 * F: 10 fraction bits.[get] 07336 * 07337 * @param ctx read / write interface definitions 07338 * @param buff buffer that stores data read 07339 * 07340 */ 07341 int32_t lsm6dso_mag_soft_iron_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 07342 { 07343 int32_t ret; 07344 uint8_t index; 07345 07346 index = 0x00U; 07347 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]); 07348 if (ret == 0) { 07349 index++; 07350 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]); 07351 } 07352 if (ret == 0) { 07353 index++; 07354 07355 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]); 07356 } 07357 if (ret == 0) { 07358 index++; 07359 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]); 07360 } 07361 if (ret == 0) { 07362 index++; 07363 07364 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]); 07365 } 07366 if (ret == 0) { 07367 index++; 07368 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]); 07369 } 07370 if (ret == 0) { 07371 index++; 07372 07373 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]); 07374 } 07375 if (ret == 0) { 07376 index++; 07377 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]); 07378 } 07379 if (ret == 0) { 07380 index++; 07381 07382 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]); 07383 } 07384 if (ret == 0) { 07385 index++; 07386 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]); 07387 } 07388 if (ret == 0) { 07389 index++; 07390 07391 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]); 07392 } 07393 if (ret == 0) { 07394 index++; 07395 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]); 07396 } 07397 07398 return ret; 07399 } 07400 07401 /** 07402 * @brief Magnetometer Z-axis coordinates 07403 * rotation (to be aligned to 07404 * accelerometer/gyroscope axes 07405 * orientation).[set] 07406 * 07407 * @param ctx read / write interface definitions 07408 * @param val change the values of mag_z_axis in reg MAG_CFG_A 07409 * 07410 */ 07411 int32_t lsm6dso_mag_z_orient_set(lsm6dso_ctx_t *ctx, lsm6dso_mag_z_axis_t val) 07412 { 07413 lsm6dso_mag_cfg_a_t reg; 07414 int32_t ret; 07415 07416 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)®); 07417 if (ret == 0) { 07418 reg.mag_z_axis = (uint8_t) val; 07419 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)®); 07420 } 07421 07422 return ret; 07423 } 07424 07425 /** 07426 * @brief Magnetometer Z-axis coordinates 07427 * rotation (to be aligned to 07428 * accelerometer/gyroscope axes 07429 * orientation).[get] 07430 * 07431 * @param ctx read / write interface definitions 07432 * @param val Get the values of mag_z_axis in reg MAG_CFG_A 07433 * 07434 */ 07435 int32_t lsm6dso_mag_z_orient_get(lsm6dso_ctx_t *ctx, 07436 lsm6dso_mag_z_axis_t *val) 07437 { 07438 lsm6dso_mag_cfg_a_t reg; 07439 int32_t ret; 07440 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)®); 07441 switch (reg.mag_z_axis) { 07442 case LSM6DSO_Z_EQ_Y: 07443 *val = LSM6DSO_Z_EQ_Y; 07444 break; 07445 case LSM6DSO_Z_EQ_MIN_Y: 07446 *val = LSM6DSO_Z_EQ_MIN_Y; 07447 break; 07448 case LSM6DSO_Z_EQ_X: 07449 *val = LSM6DSO_Z_EQ_X; 07450 break; 07451 case LSM6DSO_Z_EQ_MIN_X: 07452 *val = LSM6DSO_Z_EQ_MIN_X; 07453 break; 07454 case LSM6DSO_Z_EQ_MIN_Z: 07455 *val = LSM6DSO_Z_EQ_MIN_Z; 07456 break; 07457 case LSM6DSO_Z_EQ_Z: 07458 *val = LSM6DSO_Z_EQ_Z; 07459 break; 07460 default: 07461 *val = LSM6DSO_Z_EQ_Y; 07462 break; 07463 } 07464 return ret; 07465 } 07466 07467 /** 07468 * @brief Magnetometer Y-axis coordinates 07469 * rotation (to be aligned to 07470 * accelerometer/gyroscope axes 07471 * orientation).[set] 07472 * 07473 * @param ctx read / write interface definitions 07474 * @param val change the values of mag_y_axis in reg MAG_CFG_A 07475 * 07476 */ 07477 int32_t lsm6dso_mag_y_orient_set(lsm6dso_ctx_t *ctx, 07478 lsm6dso_mag_y_axis_t val) 07479 { 07480 lsm6dso_mag_cfg_a_t reg; 07481 int32_t ret; 07482 07483 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)®); 07484 if (ret == 0) { 07485 reg.mag_y_axis = (uint8_t)val; 07486 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *) ®); 07487 } 07488 return ret; 07489 } 07490 07491 /** 07492 * @brief Magnetometer Y-axis coordinates 07493 * rotation (to be aligned to 07494 * accelerometer/gyroscope axes 07495 * orientation).[get] 07496 * 07497 * @param ctx read / write interface definitions 07498 * @param val Get the values of mag_y_axis in reg MAG_CFG_A 07499 * 07500 */ 07501 int32_t lsm6dso_mag_y_orient_get(lsm6dso_ctx_t *ctx, 07502 lsm6dso_mag_y_axis_t *val) 07503 { 07504 lsm6dso_mag_cfg_a_t reg; 07505 int32_t ret; 07506 07507 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)®); 07508 switch (reg.mag_y_axis) { 07509 case LSM6DSO_Y_EQ_Y: 07510 *val = LSM6DSO_Y_EQ_Y; 07511 break; 07512 case LSM6DSO_Y_EQ_MIN_Y: 07513 *val = LSM6DSO_Y_EQ_MIN_Y; 07514 break; 07515 case LSM6DSO_Y_EQ_X: 07516 *val = LSM6DSO_Y_EQ_X; 07517 break; 07518 case LSM6DSO_Y_EQ_MIN_X: 07519 *val = LSM6DSO_Y_EQ_MIN_X; 07520 break; 07521 case LSM6DSO_Y_EQ_MIN_Z: 07522 *val = LSM6DSO_Y_EQ_MIN_Z; 07523 break; 07524 case LSM6DSO_Y_EQ_Z: 07525 *val = LSM6DSO_Y_EQ_Z; 07526 break; 07527 default: 07528 *val = LSM6DSO_Y_EQ_Y; 07529 break; 07530 } 07531 return ret; 07532 } 07533 07534 /** 07535 * @brief Magnetometer X-axis coordinates 07536 * rotation (to be aligned to 07537 * accelerometer/gyroscope axes 07538 * orientation).[set] 07539 * 07540 * @param ctx read / write interface definitions 07541 * @param val change the values of mag_x_axis in reg MAG_CFG_B 07542 * 07543 */ 07544 int32_t lsm6dso_mag_x_orient_set(lsm6dso_ctx_t *ctx, 07545 lsm6dso_mag_x_axis_t val) 07546 { 07547 lsm6dso_mag_cfg_b_t reg; 07548 int32_t ret; 07549 07550 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t *)®); 07551 if (ret == 0) { 07552 reg.mag_x_axis = (uint8_t)val; 07553 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t *)®); 07554 } 07555 return ret; 07556 } 07557 07558 /** 07559 * @brief Magnetometer X-axis coordinates 07560 * rotation (to be aligned to 07561 * accelerometer/gyroscope axes 07562 * orientation).[get] 07563 * 07564 * @param ctx read / write interface definitions 07565 * @param val Get the values of mag_x_axis in reg MAG_CFG_B 07566 * 07567 */ 07568 int32_t lsm6dso_mag_x_orient_get(lsm6dso_ctx_t *ctx, 07569 lsm6dso_mag_x_axis_t *val) 07570 { 07571 lsm6dso_mag_cfg_b_t reg; 07572 int32_t ret; 07573 07574 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t *)®); 07575 switch (reg.mag_x_axis) { 07576 case LSM6DSO_X_EQ_Y: 07577 *val = LSM6DSO_X_EQ_Y; 07578 break; 07579 case LSM6DSO_X_EQ_MIN_Y: 07580 *val = LSM6DSO_X_EQ_MIN_Y; 07581 break; 07582 case LSM6DSO_X_EQ_X: 07583 *val = LSM6DSO_X_EQ_X; 07584 break; 07585 case LSM6DSO_X_EQ_MIN_X: 07586 *val = LSM6DSO_X_EQ_MIN_X; 07587 break; 07588 case LSM6DSO_X_EQ_MIN_Z: 07589 *val = LSM6DSO_X_EQ_MIN_Z; 07590 break; 07591 case LSM6DSO_X_EQ_Z: 07592 *val = LSM6DSO_X_EQ_Z; 07593 break; 07594 default: 07595 *val = LSM6DSO_X_EQ_Y; 07596 break; 07597 } 07598 return ret; 07599 } 07600 07601 /** 07602 * @} 07603 * 07604 */ 07605 07606 /** 07607 * @defgroup LSM6DSO_significant_motion 07608 * @brief This section groups all the functions that manage the 07609 * state_machine. 07610 * @{ 07611 * 07612 */ 07613 07614 /** 07615 * @brief Interrupt status bit for FSM long counter 07616 * timeout interrupt event.[get] 07617 * 07618 * @param ctx read / write interface definitions 07619 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS 07620 * 07621 */ 07622 int32_t lsm6dso_long_cnt_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 07623 { 07624 lsm6dso_emb_func_status_t reg; 07625 int32_t ret; 07626 07627 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07628 if (ret == 0) { 07629 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1); 07630 } 07631 if (ret == 0) { 07632 *val = reg.is_fsm_lc; 07633 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07634 } 07635 return ret; 07636 } 07637 07638 /** 07639 * @brief Final State Machine global enable.[set] 07640 * 07641 * @param ctx read / write interface definitions 07642 * @param val change the values of fsm_en in reg EMB_FUNC_EN_B 07643 * 07644 */ 07645 int32_t lsm6dso_emb_fsm_en_set(lsm6dso_ctx_t *ctx, uint8_t val) 07646 { 07647 int32_t ret; 07648 lsm6dso_emb_func_en_b_t reg; 07649 07650 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07651 if (ret == 0) { 07652 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)®, 1); 07653 } 07654 if (ret == 0) { 07655 reg.fsm_en = val; 07656 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)®, 1); 07657 } 07658 if (ret == 0) { 07659 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07660 } 07661 return ret; 07662 } 07663 07664 /** 07665 * @brief Final State Machine global enable.[get] 07666 * 07667 * @param ctx read / write interface definitions 07668 * @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B 07669 * 07670 */ 07671 int32_t lsm6dso_emb_fsm_en_get(lsm6dso_ctx_t *ctx, uint8_t *val) 07672 { 07673 int32_t ret; 07674 lsm6dso_emb_func_en_b_t reg; 07675 07676 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07677 if (ret == 0) { 07678 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)®, 1); 07679 } 07680 if (ret == 0) { 07681 *val = reg.fsm_en; 07682 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)®, 1); 07683 } 07684 if (ret == 0) { 07685 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07686 } 07687 07688 return ret; 07689 } 07690 07691 /** 07692 * @brief Final State Machine enable.[set] 07693 * 07694 * @param ctx read / write interface definitions 07695 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B 07696 * 07697 */ 07698 int32_t lsm6dso_fsm_enable_set(lsm6dso_ctx_t *ctx, 07699 lsm6dso_emb_fsm_enable_t *val) 07700 { 07701 int32_t ret; 07702 lsm6dso_emb_func_en_b_t reg; 07703 07704 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07705 if (ret == 0) { 07706 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A, 07707 (uint8_t *)&val->fsm_enable_a, 1); 07708 } 07709 if (ret == 0) { 07710 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B, 07711 (uint8_t *)&val->fsm_enable_b, 1); 07712 } 07713 if (ret == 0) { 07714 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)®, 1); 07715 } 07716 if (ret == 0) { 07717 if ((val->fsm_enable_a.fsm1_en | 07718 val->fsm_enable_a.fsm2_en | 07719 val->fsm_enable_a.fsm3_en | 07720 val->fsm_enable_a.fsm4_en | 07721 val->fsm_enable_a.fsm5_en | 07722 val->fsm_enable_a.fsm6_en | 07723 val->fsm_enable_a.fsm7_en | 07724 val->fsm_enable_a.fsm8_en | 07725 val->fsm_enable_b.fsm9_en | 07726 val->fsm_enable_b.fsm10_en | 07727 val->fsm_enable_b.fsm11_en | 07728 val->fsm_enable_b.fsm12_en | 07729 val->fsm_enable_b.fsm13_en | 07730 val->fsm_enable_b.fsm14_en | 07731 val->fsm_enable_b.fsm15_en | 07732 val->fsm_enable_b.fsm16_en) 07733 != PROPERTY_DISABLE) { 07734 reg.fsm_en = PROPERTY_ENABLE; 07735 } else { 07736 reg.fsm_en = PROPERTY_DISABLE; 07737 } 07738 07739 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)®, 1); 07740 } 07741 if (ret == 0) { 07742 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07743 } 07744 07745 return ret; 07746 } 07747 07748 /** 07749 * @brief Final State Machine enable.[get] 07750 * 07751 * @param ctx read / write interface definitions 07752 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B 07753 * 07754 */ 07755 int32_t lsm6dso_fsm_enable_get(lsm6dso_ctx_t *ctx, 07756 lsm6dso_emb_fsm_enable_t *val) 07757 { 07758 int32_t ret; 07759 07760 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07761 if (ret == 0) { 07762 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t *) val, 2); 07763 } 07764 if (ret == 0) { 07765 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07766 } 07767 return ret; 07768 } 07769 07770 /** 07771 * @brief FSM long counter status register. Long counter value is an 07772 * unsigned integer value (16-bit format).[set] 07773 * 07774 * @param ctx read / write interface definitions 07775 * @param buff buffer that contains data to write 07776 * 07777 */ 07778 int32_t lsm6dso_long_cnt_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 07779 { 07780 int32_t ret; 07781 07782 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07783 if (ret == 0) { 07784 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2); 07785 } 07786 if (ret == 0) { 07787 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07788 } 07789 07790 return ret; 07791 } 07792 07793 /** 07794 * @brief FSM long counter status register. Long counter value is an 07795 * unsigned integer value (16-bit format).[get] 07796 * 07797 * @param ctx read / write interface definitions 07798 * @param buff buffer that stores data read 07799 * 07800 */ 07801 int32_t lsm6dso_long_cnt_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 07802 { 07803 int32_t ret; 07804 07805 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07806 if (ret == 0) { 07807 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2); 07808 } 07809 if (ret == 0) { 07810 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07811 } 07812 07813 return ret; 07814 } 07815 07816 /** 07817 * @brief Clear FSM long counter value.[set] 07818 * 07819 * @param ctx read / write interface definitions 07820 * @param val change the values of fsm_lc_clr in 07821 * reg FSM_LONG_COUNTER_CLEAR 07822 * 07823 */ 07824 int32_t lsm6dso_long_clr_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val) 07825 { 07826 lsm6dso_fsm_long_counter_clear_t reg; 07827 int32_t ret; 07828 07829 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07830 if (ret == 0) { 07831 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR, 07832 (uint8_t *)®, 1); 07833 } 07834 if (ret == 0) { 07835 reg. fsm_lc_clr = (uint8_t)val; 07836 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR, 07837 (uint8_t *)®, 1); 07838 } 07839 if (ret == 0) { 07840 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07841 } 07842 return ret; 07843 } 07844 07845 /** 07846 * @brief Clear FSM long counter value.[get] 07847 * 07848 * @param ctx read / write interface definitions 07849 * @param val Get the values of fsm_lc_clr in 07850 * reg FSM_LONG_COUNTER_CLEAR 07851 * 07852 */ 07853 int32_t lsm6dso_long_clr_get(lsm6dso_ctx_t *ctx, lsm6dso_fsm_lc_clr_t *val) 07854 { 07855 lsm6dso_fsm_long_counter_clear_t reg; 07856 int32_t ret; 07857 07858 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07859 if (ret == 0) { 07860 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR, 07861 (uint8_t *)®, 1); 07862 } 07863 if (ret == 0) { 07864 switch (reg.fsm_lc_clr) { 07865 case LSM6DSO_LC_NORMAL: 07866 *val = LSM6DSO_LC_NORMAL; 07867 break; 07868 case LSM6DSO_LC_CLEAR: 07869 *val = LSM6DSO_LC_CLEAR; 07870 break; 07871 case LSM6DSO_LC_CLEAR_DONE: 07872 *val = LSM6DSO_LC_CLEAR_DONE; 07873 break; 07874 default: 07875 *val = LSM6DSO_LC_NORMAL; 07876 break; 07877 } 07878 } 07879 07880 if (ret == 0) { 07881 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07882 } 07883 07884 return ret; 07885 } 07886 07887 /** 07888 * @brief FSM output registers[get] 07889 * 07890 * @param ctx read / write interface definitions 07891 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16 07892 * 07893 */ 07894 int32_t lsm6dso_fsm_out_get(lsm6dso_ctx_t *ctx, lsm6dso_fsm_out_t *val) 07895 { 07896 int32_t ret; 07897 07898 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07899 if (ret == 0) { 07900 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t *)val, 16); 07901 } 07902 if (ret == 0) { 07903 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07904 } 07905 07906 return ret; 07907 } 07908 07909 /** 07910 * @brief Finite State Machine ODR configuration.[set] 07911 * 07912 * @param ctx read / write interface definitions 07913 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B 07914 * 07915 */ 07916 int32_t lsm6dso_fsm_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_odr_t val) 07917 { 07918 lsm6dso_emb_func_odr_cfg_b_t reg; 07919 int32_t ret; 07920 07921 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07922 if (ret == 0) { 07923 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, 07924 (uint8_t *)®, 1); 07925 } 07926 if (ret == 0) { 07927 reg.not_used_01 = 3; /* set default values */ 07928 reg.not_used_02 = 2; /* set default values */ 07929 reg.fsm_odr = (uint8_t)val; 07930 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, 07931 (uint8_t *)®, 1); 07932 } 07933 if (ret == 0) { 07934 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07935 } 07936 return ret; 07937 } 07938 07939 /** 07940 * @brief Finite State Machine ODR configuration.[get] 07941 * 07942 * @param ctx read / write interface definitions 07943 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B 07944 * 07945 */ 07946 int32_t lsm6dso_fsm_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_fsm_odr_t *val) 07947 { 07948 lsm6dso_emb_func_odr_cfg_b_t reg; 07949 int32_t ret; 07950 07951 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07952 if (ret == 0) { 07953 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, 07954 (uint8_t *)®, 1); 07955 } 07956 if (ret == 0) { 07957 switch (reg.fsm_odr) { 07958 case LSM6DSO_ODR_FSM_12Hz5: 07959 *val = LSM6DSO_ODR_FSM_12Hz5; 07960 break; 07961 case LSM6DSO_ODR_FSM_26Hz: 07962 *val = LSM6DSO_ODR_FSM_26Hz; 07963 break; 07964 case LSM6DSO_ODR_FSM_52Hz: 07965 *val = LSM6DSO_ODR_FSM_52Hz; 07966 break; 07967 case LSM6DSO_ODR_FSM_104Hz: 07968 *val = LSM6DSO_ODR_FSM_104Hz; 07969 break; 07970 default: 07971 *val = LSM6DSO_ODR_FSM_12Hz5; 07972 break; 07973 } 07974 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07975 } 07976 07977 return ret; 07978 } 07979 07980 /** 07981 * @brief FSM initialization request.[set] 07982 * 07983 * @param ctx read / write interface definitions 07984 * @param val change the values of fsm_init in reg FSM_INIT 07985 * 07986 */ 07987 int32_t lsm6dso_fsm_init_set(lsm6dso_ctx_t *ctx, uint8_t val) 07988 { 07989 lsm6dso_emb_func_init_b_t reg; 07990 int32_t ret; 07991 07992 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07993 if (ret == 0) { 07994 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1); 07995 } 07996 if (ret == 0) { 07997 reg.fsm_init = val; 07998 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1); 07999 } 08000 if (ret == 0) { 08001 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08002 } 08003 08004 return ret; 08005 } 08006 08007 /** 08008 * @brief FSM initialization request.[get] 08009 * 08010 * @param ctx read / write interface definitions 08011 * @param val change the values of fsm_init in reg FSM_INIT 08012 * 08013 */ 08014 int32_t lsm6dso_fsm_init_get(lsm6dso_ctx_t *ctx, uint8_t *val) 08015 { 08016 lsm6dso_emb_func_init_b_t reg; 08017 int32_t ret; 08018 08019 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 08020 if (ret == 0) { 08021 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1); 08022 } 08023 if (ret == 0) { 08024 *val = reg.fsm_init; 08025 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08026 } 08027 return ret; 08028 } 08029 08030 /** 08031 * @brief FSM long counter timeout register (r/w). The long counter 08032 * timeout value is an unsigned integer value (16-bit format). 08033 * When the long counter value reached this value, 08034 * the FSM generates an interrupt.[set] 08035 * 08036 * @param ctx read / write interface definitions 08037 * @param val the value of long counter 08038 * 08039 */ 08040 int32_t lsm6dso_long_cnt_int_value_set(lsm6dso_ctx_t *ctx, uint16_t val) 08041 { 08042 int32_t ret; 08043 uint8_t add_l; 08044 uint8_t add_h; 08045 08046 add_h = (uint8_t)((val & 0xFF00U) >> 8); 08047 add_l = (uint8_t)(val & 0x00FFU); 08048 08049 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l); 08050 if (ret == 0) { 08051 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h); 08052 } 08053 08054 return ret; 08055 } 08056 08057 /** 08058 * @brief FSM long counter timeout register (r/w). The long counter 08059 * timeout value is an unsigned integer value (16-bit format). 08060 * When the long counter value reached this value, 08061 * the FSM generates an interrupt.[get] 08062 * 08063 * @param ctx read / write interface definitions 08064 * @param val buffer that stores the value of long counter 08065 * 08066 */ 08067 int32_t lsm6dso_long_cnt_int_value_get(lsm6dso_ctx_t *ctx, uint16_t *val) 08068 { 08069 int32_t ret; 08070 uint8_t add_l; 08071 uint8_t add_h; 08072 08073 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l); 08074 if (ret == 0) { 08075 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h); 08076 *val = add_h; 08077 *val = *val << 8; 08078 *val += add_l; 08079 } 08080 08081 return ret; 08082 } 08083 08084 /** 08085 * @brief FSM number of programs register.[set] 08086 * 08087 * @param ctx read / write interface definitions 08088 * @param val value to write 08089 * 08090 */ 08091 int32_t lsm6dso_fsm_number_of_programs_set(lsm6dso_ctx_t *ctx, uint8_t val) 08092 { 08093 int32_t ret; 08094 08095 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_PROGRAMS, &val); 08096 08097 return ret; 08098 } 08099 08100 /** 08101 * @brief FSM number of programs register.[get] 08102 * 08103 * @param ctx read / write interface definitions 08104 * @param val buffer that stores data read. 08105 * 08106 */ 08107 int32_t lsm6dso_fsm_number_of_programs_get(lsm6dso_ctx_t *ctx, uint8_t *val) 08108 { 08109 int32_t ret; 08110 08111 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_PROGRAMS, val); 08112 08113 return ret; 08114 } 08115 08116 /** 08117 * @brief FSM start address register (r/w). 08118 * First available address is 0x033C.[set] 08119 * 08120 * @param ctx read / write interface definitions 08121 * @param val the value of start address 08122 * 08123 */ 08124 int32_t lsm6dso_fsm_start_address_set(lsm6dso_ctx_t *ctx, uint16_t val) 08125 { 08126 int32_t ret; 08127 uint8_t add_l; 08128 uint8_t add_h; 08129 08130 add_h = (uint8_t)((val & 0xFF00U) >> 8); 08131 add_l = (uint8_t)(val & 0x00FFU); 08132 08133 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l); 08134 if (ret == 0) { 08135 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h); 08136 } 08137 return ret; 08138 } 08139 08140 /** 08141 * @brief FSM start address register (r/w). 08142 * First available address is 0x033C.[get] 08143 * 08144 * @param ctx read / write interface definitions 08145 * @param val buffer the value of start address. 08146 * 08147 */ 08148 int32_t lsm6dso_fsm_start_address_get(lsm6dso_ctx_t *ctx, uint16_t *val) 08149 { 08150 int32_t ret; 08151 uint8_t add_l; 08152 uint8_t add_h; 08153 08154 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l); 08155 if (ret == 0) { 08156 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h); 08157 *val = add_h; 08158 *val = *val << 8; 08159 *val += add_l; 08160 } 08161 return ret; 08162 } 08163 08164 /** 08165 * @} 08166 * 08167 */ 08168 08169 /** 08170 * @defgroup LSM6DSO_Sensor_hub 08171 * @brief This section groups all the functions that manage the 08172 * sensor hub. 08173 * @{ 08174 * 08175 */ 08176 08177 /** 08178 * @brief Sensor hub output registers.[get] 08179 * 08180 * @param ctx read / write interface definitions 08181 * @param val values read from registers SENSOR_HUB_1 to SENSOR_HUB_18 08182 * @param len number of consecutive register to read (max 18) 08183 * 08184 */ 08185 int32_t lsm6dso_sh_read_data_raw_get(lsm6dso_ctx_t *ctx, uint8_t *val, 08186 uint8_t len) 08187 { 08188 int32_t ret; 08189 08190 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08191 if (ret == 0) { 08192 ret = lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t *) val, len); 08193 } 08194 if (ret == 0) { 08195 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08196 } 08197 08198 return ret; 08199 } 08200 08201 /** 08202 * @brief Number of external sensors to be read by the sensor hub.[set] 08203 * 08204 * @param ctx read / write interface definitions 08205 * @param val change the values of aux_sens_on in reg MASTER_CONFIG 08206 * 08207 */ 08208 int32_t lsm6dso_sh_slave_connected_set(lsm6dso_ctx_t *ctx, 08209 lsm6dso_aux_sens_on_t val) 08210 { 08211 lsm6dso_master_config_t reg; 08212 int32_t ret; 08213 08214 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08215 if (ret == 0) { 08216 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08217 } 08218 if (ret == 0) { 08219 reg.aux_sens_on = (uint8_t)val; 08220 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08221 } 08222 if (ret == 0) { 08223 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08224 } 08225 return ret; 08226 } 08227 08228 /** 08229 * @brief Number of external sensors to be read by the sensor hub.[get] 08230 * 08231 * @param ctx read / write interface definitions 08232 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG 08233 * 08234 */ 08235 int32_t lsm6dso_sh_slave_connected_get(lsm6dso_ctx_t *ctx, 08236 lsm6dso_aux_sens_on_t *val) 08237 { 08238 lsm6dso_master_config_t reg; 08239 int32_t ret; 08240 08241 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08242 if (ret == 0) { 08243 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08244 } 08245 if (ret == 0) { 08246 switch (reg.aux_sens_on) { 08247 case LSM6DSO_SLV_0: 08248 *val = LSM6DSO_SLV_0; 08249 break; 08250 case LSM6DSO_SLV_0_1: 08251 *val = LSM6DSO_SLV_0_1; 08252 break; 08253 case LSM6DSO_SLV_0_1_2: 08254 *val = LSM6DSO_SLV_0_1_2; 08255 break; 08256 case LSM6DSO_SLV_0_1_2_3: 08257 *val = LSM6DSO_SLV_0_1_2_3; 08258 break; 08259 default: 08260 *val = LSM6DSO_SLV_0; 08261 break; 08262 } 08263 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08264 } 08265 08266 return ret; 08267 } 08268 08269 /** 08270 * @brief Sensor hub I2C master enable.[set] 08271 * 08272 * @param ctx read / write interface definitions 08273 * @param val change the values of master_on in reg MASTER_CONFIG 08274 * 08275 */ 08276 int32_t lsm6dso_sh_master_set(lsm6dso_ctx_t *ctx, uint8_t val) 08277 { 08278 lsm6dso_master_config_t reg; 08279 int32_t ret; 08280 08281 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08282 if (ret == 0) { 08283 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08284 } 08285 if (ret == 0) { 08286 reg.master_on = val; 08287 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08288 } 08289 if (ret == 0) { 08290 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08291 } 08292 return ret; 08293 } 08294 08295 /** 08296 * @brief Sensor hub I2C master enable.[get] 08297 * 08298 * @param ctx read / write interface definitions 08299 * @param val change the values of master_on in reg MASTER_CONFIG 08300 * 08301 */ 08302 int32_t lsm6dso_sh_master_get(lsm6dso_ctx_t *ctx, uint8_t *val) 08303 { 08304 lsm6dso_master_config_t reg; 08305 int32_t ret; 08306 08307 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08308 if (ret == 0) { 08309 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08310 } 08311 if (ret == 0) { 08312 *val = reg.master_on; 08313 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08314 } 08315 08316 return ret; 08317 } 08318 08319 /** 08320 * @brief Master I2C pull-up enable.[set] 08321 * 08322 * @param ctx read / write interface definitions 08323 * @param val change the values of shub_pu_en in reg MASTER_CONFIG 08324 * 08325 */ 08326 int32_t lsm6dso_sh_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_pu_en_t val) 08327 { 08328 lsm6dso_master_config_t reg; 08329 int32_t ret; 08330 08331 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08332 if (ret == 0) { 08333 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08334 } 08335 if (ret == 0) { 08336 reg.shub_pu_en = (uint8_t)val; 08337 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08338 } 08339 if (ret == 0) { 08340 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08341 } 08342 08343 return ret; 08344 } 08345 08346 /** 08347 * @brief Master I2C pull-up enable.[get] 08348 * 08349 * @param ctx read / write interface definitions 08350 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG 08351 * 08352 */ 08353 int32_t lsm6dso_sh_pin_mode_get(lsm6dso_ctx_t *ctx, 08354 lsm6dso_shub_pu_en_t *val) 08355 { 08356 lsm6dso_master_config_t reg; 08357 int32_t ret; 08358 08359 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08360 if (ret == 0) { 08361 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08362 } 08363 if (ret == 0) { 08364 switch (reg.shub_pu_en) { 08365 case LSM6DSO_EXT_PULL_UP: 08366 *val = LSM6DSO_EXT_PULL_UP; 08367 break; 08368 case LSM6DSO_INTERNAL_PULL_UP: 08369 *val = LSM6DSO_INTERNAL_PULL_UP; 08370 break; 08371 default: 08372 *val = LSM6DSO_EXT_PULL_UP; 08373 break; 08374 } 08375 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08376 } 08377 08378 return ret; 08379 } 08380 08381 /** 08382 * @brief I2C interface pass-through.[set] 08383 * 08384 * @param ctx read / write interface definitions 08385 * @param val change the values of pass_through_mode in 08386 * reg MASTER_CONFIG 08387 * 08388 */ 08389 int32_t lsm6dso_sh_pass_through_set(lsm6dso_ctx_t *ctx, uint8_t val) 08390 { 08391 lsm6dso_master_config_t reg; 08392 int32_t ret; 08393 08394 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08395 if (ret == 0) { 08396 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08397 } 08398 if (ret == 0) { 08399 reg.pass_through_mode = val; 08400 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08401 } 08402 if (ret == 0) { 08403 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08404 } 08405 08406 return ret; 08407 } 08408 08409 /** 08410 * @brief I2C interface pass-through.[get] 08411 * 08412 * @param ctx read / write interface definitions 08413 * @param val change the values of pass_through_mode in 08414 * reg MASTER_CONFIG 08415 * 08416 */ 08417 int32_t lsm6dso_sh_pass_through_get(lsm6dso_ctx_t *ctx, uint8_t *val) 08418 { 08419 lsm6dso_master_config_t reg; 08420 int32_t ret; 08421 08422 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08423 if (ret == 0) { 08424 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08425 } 08426 if (ret == 0) { 08427 *val = reg.pass_through_mode; 08428 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08429 } 08430 08431 return ret; 08432 } 08433 08434 /** 08435 * @brief Sensor hub trigger signal selection.[set] 08436 * 08437 * @param ctx read / write interface definitions 08438 * @param val change the values of start_config in reg MASTER_CONFIG 08439 * 08440 */ 08441 int32_t lsm6dso_sh_syncro_mode_set(lsm6dso_ctx_t *ctx, 08442 lsm6dso_start_config_t val) 08443 { 08444 lsm6dso_master_config_t reg; 08445 int32_t ret; 08446 08447 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08448 if (ret == 0) { 08449 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08450 } 08451 if (ret == 0) { 08452 reg.start_config = (uint8_t)val; 08453 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08454 } 08455 if (ret == 0) { 08456 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08457 } 08458 08459 return ret; 08460 } 08461 08462 /** 08463 * @brief Sensor hub trigger signal selection.[get] 08464 * 08465 * @param ctx read / write interface definitions 08466 * @param val Get the values of start_config in reg MASTER_CONFIG 08467 * 08468 */ 08469 int32_t lsm6dso_sh_syncro_mode_get(lsm6dso_ctx_t *ctx, 08470 lsm6dso_start_config_t *val) 08471 { 08472 lsm6dso_master_config_t reg; 08473 int32_t ret; 08474 08475 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08476 if (ret == 0) { 08477 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08478 } 08479 if (ret == 0) { 08480 switch (reg.start_config) { 08481 case LSM6DSO_EXT_ON_INT2_PIN: 08482 *val = LSM6DSO_EXT_ON_INT2_PIN; 08483 break; 08484 case LSM6DSO_XL_GY_DRDY: 08485 *val = LSM6DSO_XL_GY_DRDY; 08486 break; 08487 default: 08488 *val = LSM6DSO_EXT_ON_INT2_PIN; 08489 break; 08490 } 08491 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08492 } 08493 return ret; 08494 } 08495 08496 /** 08497 * @brief Slave 0 write operation is performed only at the first 08498 * sensor hub cycle.[set] 08499 * 08500 * @param ctx read / write interface definitions 08501 * @param val change the values of write_once in reg MASTER_CONFIG 08502 * 08503 */ 08504 int32_t lsm6dso_sh_write_mode_set(lsm6dso_ctx_t *ctx, 08505 lsm6dso_write_once_t val) 08506 { 08507 lsm6dso_master_config_t reg; 08508 int32_t ret; 08509 08510 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08511 if (ret == 0) { 08512 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08513 } 08514 if (ret == 0) { 08515 reg.write_once = (uint8_t)val; 08516 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08517 } 08518 if (ret == 0) { 08519 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08520 } 08521 08522 return ret; 08523 } 08524 08525 /** 08526 * @brief Slave 0 write operation is performed only at the first sensor 08527 * hub cycle.[get] 08528 * 08529 * @param ctx read / write interface definitions 08530 * @param val Get the values of write_once in reg MASTER_CONFIG 08531 * 08532 */ 08533 int32_t lsm6dso_sh_write_mode_get(lsm6dso_ctx_t *ctx, 08534 lsm6dso_write_once_t *val) 08535 { 08536 lsm6dso_master_config_t reg; 08537 int32_t ret; 08538 08539 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08540 if (ret == 0) { 08541 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08542 } 08543 if (ret == 0) { 08544 switch (reg.write_once) { 08545 case LSM6DSO_EACH_SH_CYCLE: 08546 *val = LSM6DSO_EACH_SH_CYCLE; 08547 break; 08548 case LSM6DSO_ONLY_FIRST_CYCLE: 08549 *val = LSM6DSO_ONLY_FIRST_CYCLE; 08550 break; 08551 default: 08552 *val = LSM6DSO_EACH_SH_CYCLE; 08553 break; 08554 } 08555 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08556 } 08557 08558 return ret; 08559 } 08560 08561 /** 08562 * @brief Reset Master logic and output registers.[set] 08563 * 08564 * @param ctx read / write interface definitions 08565 * 08566 */ 08567 int32_t lsm6dso_sh_reset_set(lsm6dso_ctx_t *ctx) 08568 { 08569 lsm6dso_master_config_t reg; 08570 int32_t ret; 08571 08572 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08573 if (ret == 0) { 08574 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08575 } 08576 if (ret == 0) { 08577 reg.rst_master_regs = PROPERTY_ENABLE; 08578 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08579 } 08580 if (ret == 0) { 08581 reg.rst_master_regs = PROPERTY_DISABLE; 08582 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08583 } 08584 if (ret == 0) { 08585 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08586 } 08587 08588 return ret; 08589 } 08590 08591 /** 08592 * @brief Reset Master logic and output registers.[get] 08593 * 08594 * @param ctx read / write interface definitions 08595 * @param val change the values of rst_master_regs in reg MASTER_CONFIG 08596 * 08597 */ 08598 int32_t lsm6dso_sh_reset_get(lsm6dso_ctx_t *ctx, uint8_t *val) 08599 { 08600 lsm6dso_master_config_t reg; 08601 int32_t ret; 08602 08603 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08604 if (ret == 0) { 08605 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1); 08606 } 08607 if (ret == 0) { 08608 *val = reg.rst_master_regs; 08609 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08610 } 08611 return ret; 08612 } 08613 08614 /** 08615 * @brief Rate at which the master communicates.[set] 08616 * 08617 * @param ctx read / write interface definitions 08618 * @param val change the values of shub_odr in reg slv1_CONFIG 08619 * 08620 */ 08621 int32_t lsm6dso_sh_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_odr_t val) 08622 { 08623 lsm6dso_slv0_config_t reg; 08624 int32_t ret; 08625 08626 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08627 if (ret == 0) { 08628 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1); 08629 } 08630 if (ret == 0) { 08631 reg.shub_odr = (uint8_t)val; 08632 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1); 08633 } 08634 if (ret == 0) { 08635 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08636 } 08637 08638 return ret; 08639 } 08640 08641 /** 08642 * @brief Rate at which the master communicates.[get] 08643 * 08644 * @param ctx read / write interface definitions 08645 * @param val Get the values of shub_odr in reg slv1_CONFIG 08646 * 08647 */ 08648 int32_t lsm6dso_sh_data_rate_get(lsm6dso_ctx_t *ctx, 08649 lsm6dso_shub_odr_t *val) 08650 { 08651 lsm6dso_slv0_config_t reg; 08652 int32_t ret; 08653 08654 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08655 if (ret == 0) { 08656 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1); 08657 } 08658 if (ret == 0) { 08659 switch (reg.shub_odr) { 08660 case LSM6DSO_SH_ODR_104Hz: 08661 *val = LSM6DSO_SH_ODR_104Hz; 08662 break; 08663 case LSM6DSO_SH_ODR_52Hz: 08664 *val = LSM6DSO_SH_ODR_52Hz; 08665 break; 08666 case LSM6DSO_SH_ODR_26Hz: 08667 *val = LSM6DSO_SH_ODR_26Hz; 08668 break; 08669 case LSM6DSO_SH_ODR_13Hz: 08670 *val = LSM6DSO_SH_ODR_13Hz; 08671 break; 08672 default: 08673 *val = LSM6DSO_SH_ODR_104Hz; 08674 break; 08675 } 08676 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08677 } 08678 08679 return ret; 08680 } 08681 08682 /** 08683 * @brief Configure slave 0 for perform a write.[set] 08684 * 08685 * @param ctx read / write interface definitions 08686 * @param val a structure that contain 08687 * - uint8_t slv1_add; 8 bit i2c device address 08688 * - uint8_t slv1_subadd; 8 bit register device address 08689 * - uint8_t slv1_data; 8 bit data to write 08690 * 08691 */ 08692 int32_t lsm6dso_sh_cfg_write(lsm6dso_ctx_t *ctx, lsm6dso_sh_cfg_write_t *val) 08693 { 08694 lsm6dso_slv0_add_t reg; 08695 int32_t ret; 08696 08697 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08698 if (ret == 0) { 08699 reg.slave0 = val->slv0_add; 08700 reg.rw_0 = 0; 08701 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)®, 1); 08702 } 08703 if (ret == 0) { 08704 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD, 08705 &(val->slv0_subadd), 1); 08706 } 08707 if (ret == 0) { 08708 ret = lsm6dso_write_reg(ctx, LSM6DSO_DATAWRITE_SLV0, 08709 &(val->slv0_data), 1); 08710 } 08711 if (ret == 0) { 08712 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08713 } 08714 return ret; 08715 } 08716 08717 /** 08718 * @brief Configure slave 0 for perform a read.[set] 08719 * 08720 * @param ctx read / write interface definitions 08721 * @param val Structure that contain 08722 * - uint8_t slv1_add; 8 bit i2c device address 08723 * - uint8_t slv1_subadd; 8 bit register device address 08724 * - uint8_t slv1_len; num of bit to read 08725 * 08726 */ 08727 int32_t lsm6dso_sh_slv0_cfg_read(lsm6dso_ctx_t *ctx, 08728 lsm6dso_sh_cfg_read_t *val) 08729 { 08730 lsm6dso_slv0_add_t slv0_add; 08731 lsm6dso_slv0_config_t slv0_config; 08732 int32_t ret; 08733 08734 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08735 if (ret == 0) { 08736 slv0_add.slave0 = val->slv_add; 08737 slv0_add.rw_0 = 1; 08738 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)&slv0_add, 1); 08739 } 08740 if (ret == 0) { 08741 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD, 08742 &(val->slv_subadd), 1); 08743 } 08744 if (ret == 0) { 08745 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, 08746 (uint8_t *)&slv0_config, 1); 08747 } 08748 if (ret == 0) { 08749 slv0_config.slave0_numop = val->slv_len; 08750 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, 08751 (uint8_t *)&slv0_config, 1); 08752 } 08753 if (ret == 0) { 08754 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08755 } 08756 08757 return ret; 08758 } 08759 08760 /** 08761 * @brief Configure slave 0 for perform a write/read.[set] 08762 * 08763 * @param ctx read / write interface definitions 08764 * @param val Structure that contain 08765 * - uint8_t slv1_add; 8 bit i2c device address 08766 * - uint8_t slv1_subadd; 8 bit register device address 08767 * - uint8_t slv1_len; num of bit to read 08768 * 08769 */ 08770 int32_t lsm6dso_sh_slv1_cfg_read(lsm6dso_ctx_t *ctx, 08771 lsm6dso_sh_cfg_read_t *val) 08772 { 08773 lsm6dso_slv1_add_t slv1_add; 08774 lsm6dso_slv1_config_t slv1_config; 08775 int32_t ret; 08776 08777 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08778 if (ret == 0) { 08779 slv1_add.slave1_add = val->slv_add; 08780 slv1_add.r_1 = 1; 08781 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_ADD, (uint8_t *)&slv1_add, 1); 08782 } 08783 if (ret == 0) { 08784 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_SUBADD, 08785 &(val->slv_subadd), 1); 08786 } 08787 if (ret == 0) { 08788 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, 08789 (uint8_t *)&slv1_config, 1); 08790 } 08791 if (ret == 0) { 08792 slv1_config.slave1_numop = val->slv_len; 08793 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, 08794 (uint8_t *)&slv1_config, 1); 08795 } 08796 if (ret == 0) { 08797 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08798 } 08799 08800 return ret; 08801 } 08802 08803 /** 08804 * @brief Configure slave 0 for perform a write/read.[set] 08805 * 08806 * @param ctx read / write interface definitions 08807 * @param val Structure that contain 08808 * - uint8_t slv2_add; 8 bit i2c device address 08809 * - uint8_t slv2_subadd; 8 bit register device address 08810 * - uint8_t slv2_len; num of bit to read 08811 * 08812 */ 08813 int32_t lsm6dso_sh_slv2_cfg_read(lsm6dso_ctx_t *ctx, 08814 lsm6dso_sh_cfg_read_t *val) 08815 { 08816 lsm6dso_slv2_add_t slv2_add; 08817 lsm6dso_slv2_config_t slv2_config; 08818 int32_t ret; 08819 08820 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08821 if (ret == 0) { 08822 slv2_add.slave2_add = val->slv_add; 08823 slv2_add.r_2 = 1; 08824 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_ADD, (uint8_t *)&slv2_add, 1); 08825 } 08826 if (ret == 0) { 08827 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_SUBADD, 08828 &(val->slv_subadd), 1); 08829 } 08830 if (ret == 0) { 08831 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, 08832 (uint8_t *)&slv2_config, 1); 08833 } 08834 if (ret == 0) { 08835 slv2_config.slave2_numop = val->slv_len; 08836 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, 08837 (uint8_t *)&slv2_config, 1); 08838 } 08839 if (ret == 0) { 08840 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08841 } 08842 return ret; 08843 } 08844 08845 /** 08846 * @brief Configure slave 0 for perform a write/read.[set] 08847 * 08848 * @param ctx read / write interface definitions 08849 * @param val Structure that contain 08850 * - uint8_t slv3_add; 8 bit i2c device address 08851 * - uint8_t slv3_subadd; 8 bit register device address 08852 * - uint8_t slv3_len; num of bit to read 08853 * 08854 */ 08855 int32_t lsm6dso_sh_slv3_cfg_read(lsm6dso_ctx_t *ctx, 08856 lsm6dso_sh_cfg_read_t *val) 08857 { 08858 lsm6dso_slv3_add_t slv3_add; 08859 lsm6dso_slv3_config_t slv3_config; 08860 int32_t ret; 08861 08862 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08863 if (ret == 0) { 08864 slv3_add.slave3_add = val->slv_add; 08865 slv3_add.r_3 = 1; 08866 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_ADD, (uint8_t *)&slv3_add, 1); 08867 } 08868 if (ret == 0) { 08869 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_SUBADD, 08870 &(val->slv_subadd), 1); 08871 } 08872 if (ret == 0) { 08873 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, 08874 (uint8_t *)&slv3_config, 1); 08875 } 08876 if (ret == 0) { 08877 slv3_config.slave3_numop = val->slv_len; 08878 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, 08879 (uint8_t *)&slv3_config, 1); 08880 } 08881 if (ret == 0) { 08882 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08883 } 08884 return ret; 08885 } 08886 08887 /** 08888 * @brief Sensor hub source register.[get] 08889 * 08890 * @param ctx read / write interface definitions 08891 * @param val union of registers from STATUS_MASTER to 08892 * 08893 */ 08894 int32_t lsm6dso_sh_status_get(lsm6dso_ctx_t *ctx, 08895 lsm6dso_status_master_t *val) 08896 { 08897 int32_t ret; 08898 08899 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08900 if (ret == 0) { 08901 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER, (uint8_t *) val, 1); 08902 } 08903 if (ret == 0) { 08904 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08905 } 08906 08907 return ret; 08908 } 08909 08910 /** 08911 * @} 08912 * 08913 */ 08914 08915 /** 08916 * @} 08917 * 08918 */ 08919 08920 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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