J&W / FXAS21002CQ

Library to access multiple giro - with ability to setup them when starting

FXAS21002CQ.h@2:606d0965f546, 2015-08-24 (annotated)

Committer:
Pythia
Date:
Mon Aug 24 14:29:35 2015 +0000
Revision:
2:606d0965f546
Parent:
1:816ba6bfbb20 
Initial version of the software

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pythia 0:8aa01dbab64e 1 /* FXAS21002CQ sensor driver
Pythia 0:8aa01dbab64e 2 * Copyright (c) 2015 WD
Pythia 0:8aa01dbab64e 3 *
Pythia 0:8aa01dbab64e 4 * Unless required by applicable law or agreed to in writing, software
Pythia 0:8aa01dbab64e 5 * distributed under the License is distributed on an "AS IS" BASIS,
Pythia 0:8aa01dbab64e 6 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pythia 0:8aa01dbab64e 7 * See the License for the specific language governing permissions and
Pythia 0:8aa01dbab64e 8 * limitations under the License.
Pythia 0:8aa01dbab64e 9 */
Pythia 0:8aa01dbab64e 10
Pythia 0:8aa01dbab64e 11 #ifndef FXAS21002CQ_H
Pythia 0:8aa01dbab64e 12 #define FXAS21002CQ_H
Pythia 0:8aa01dbab64e 13
Pythia 0:8aa01dbab64e 14 #include "mbed.h"
Pythia 0:8aa01dbab64e 15 #include "MotionSensor.h"
Pythia 0:8aa01dbab64e 16
Pythia 0:8aa01dbab64e 17 // FXAS21002CQ I2C address
Pythia 0:8aa01dbab64e 18 #define FXAS21002CQ_SLAVE_ADDR0 (0x20<<1) // with pins SA0=0,
Pythia 0:8aa01dbab64e 19 #define FXAS21002CQ_SLAVE_ADDR1 (0x21<<1) // with pins SA0=1,
Pythia 0:8aa01dbab64e 20 // FXAS21002CQ internal register addresses
Pythia 0:8aa01dbab64e 21 #define FXAS21002CQ_STATUS 0x00
Pythia 0:8aa01dbab64e 22 #define FXAS21002CQ_OUT_X_MSB 0x01
Pythia 0:8aa01dbab64e 23 #define FXAS21002CQ_OUT_X_LSB 0x02
Pythia 0:8aa01dbab64e 24 #define FXAS21002CQ_OUT_Y_MSB 0x03
Pythia 0:8aa01dbab64e 25 #define FXAS21002CQ_OUT_Y_LSB 0x04
Pythia 0:8aa01dbab64e 26 #define FXAS21002CQ_OUT_Z_MSB 0x05
Pythia 0:8aa01dbab64e 27 #define FXAS21002CQ_OUT_Z_LSB 0x06
Pythia 0:8aa01dbab64e 28 #define FXAS21002CQ_DR_STATUS 0x07
Pythia 0:8aa01dbab64e 29 #define FXAS21002CQ_F_STATUS 0x08
Pythia 0:8aa01dbab64e 30 #define FXAS21002CQ_F_SETUP 0x09
Pythia 0:8aa01dbab64e 31 #define FXAS21002CQ_F_EVENT 0x0A
Pythia 0:8aa01dbab64e 32 #define FXAS21002CQ_INT_SRC_FLAG 0x0B
Pythia 0:8aa01dbab64e 33 #define FXAS21002CQ_WHO_AM_I 0x0C
Pythia 0:8aa01dbab64e 34 #define FXAS21002CQ_CTRL_REG0 0x0D
Pythia 0:8aa01dbab64e 35 #define FXAS21002CQ_RT_CFG 0x0E
Pythia 0:8aa01dbab64e 36 #define FXAS21002CQ_RT_SRC 0x0F
Pythia 0:8aa01dbab64e 37 #define FXAS21002CQ_RT_THS 0x10
Pythia 0:8aa01dbab64e 38 #define FXAS21002CQ_RT_COUNT 0x11
Pythia 0:8aa01dbab64e 39 #define FXAS21002CQ_TEMP 0x12
Pythia 0:8aa01dbab64e 40 #define FXAS21002CQ_CTRL_REG1 0x13
Pythia 0:8aa01dbab64e 41 #define FXAS21002CQ_CTRL_REG2 0x14
Pythia 0:8aa01dbab64e 42 #define FXAS21002CQ_CTRL_REG3 0x15
Pythia 0:8aa01dbab64e 43
Pythia 1:816ba6bfbb20 44 enum FXAS21002CQ_F_SETUP_struct_F_MODE {DISABLED_BUFFER=0, CIRCULAR_BUFFER=1, STOP_BUFFER=2};
Pythia 1:816ba6bfbb20 45
Pythia 1:816ba6bfbb20 46 struct FXAS21002CQ_F_SETUP_struct
Pythia 1:816ba6bfbb20 47 {
Pythia 1:816ba6bfbb20 48 enum FXAS21002CQ_F_SETUP_struct_F_MODE F_MODE; // Bit 7,6
Pythia 1:816ba6bfbb20 49 uint8_t F_WMRK; // Bit 5-0 0- LSB
Pythia 1:816ba6bfbb20 50 };
Pythia 1:816ba6bfbb20 51
Pythia 1:816ba6bfbb20 52 enum FXAS21002CQ_CTRL_REG0_struct_BW{HIGH_BW=0, MEDIUM_BW=1, LOW_BW=2};
Pythia 1:816ba6bfbb20 53 enum FXAS21002CQ_CTRL_REG0_struct_SPIW{SPI4=0, SPI3=1};
Pythia 1:816ba6bfbb20 54 enum FXAS21002CQ_CTRL_REG0_struct_SEL{HIGH_HP=0, MEDIUM_HIGH_HP=1, MEDIUM_LOW_HP=2, LOW_HP=3};
Pythia 1:816ba6bfbb20 55 enum FXAS21002CQ_CTRL_REG0_struct_HPF_EN{DISABLED_HP=0, ENABLED_HP=1};
Pythia 1:816ba6bfbb20 56 enum FXAS21002CQ_CTRL_REG0_struct_FS{RANGE_2000=0, RANGE_1000=1, RANGE_500=2, RANGE_250=3};
Pythia 1:816ba6bfbb20 57
Pythia 1:816ba6bfbb20 58 struct FXAS21002CQ_CTRL_REG0_struct
Pythia 1:816ba6bfbb20 59 {
Pythia 1:816ba6bfbb20 60 enum FXAS21002CQ_CTRL_REG0_struct_BW BW; // Bit 7, 6
Pythia 1:816ba6bfbb20 61 enum FXAS21002CQ_CTRL_REG0_struct_SPIW SPIW; // Bit 5
Pythia 1:816ba6bfbb20 62 enum FXAS21002CQ_CTRL_REG0_struct_SEL SEL; // Bit 4, 3
Pythia 1:816ba6bfbb20 63 enum FXAS21002CQ_CTRL_REG0_struct_HPF_EN HPF_EN; // Bit 2
Pythia 1:816ba6bfbb20 64 enum FXAS21002CQ_CTRL_REG0_struct_FS FS; // Bit 1, 0
Pythia 1:816ba6bfbb20 65 };
Pythia 1:816ba6bfbb20 66
Pythia 1:816ba6bfbb20 67 enum FXAS21002CQ_RT_CFG_struct_ELE{DISABLED_ELE=0, ENABLED_ELE=1};
Pythia 1:816ba6bfbb20 68 enum FXAS21002CQ_RT_CFG_struct_ZTEVE{DISABLED_ZTEVE=0, ENABLED_ZTEVE=1};
Pythia 1:816ba6bfbb20 69 enum FXAS21002CQ_RT_CFG_struct_YTEVE{DISABLED_YTEVE=0, ENABLED_YTEVE=1};
Pythia 1:816ba6bfbb20 70 enum FXAS21002CQ_RT_CFG_struct_XTEVE{DISABLED_XTEVE=0, ENABLED_XTEVE=1};
Pythia 1:816ba6bfbb20 71
Pythia 1:816ba6bfbb20 72 struct FXAS21002CQ_RT_CFG_struct
Pythia 1:816ba6bfbb20 73 {
Pythia 1:816ba6bfbb20 74 enum FXAS21002CQ_RT_CFG_struct_ELE ELE; // Bit 3
Pythia 1:816ba6bfbb20 75 enum FXAS21002CQ_RT_CFG_struct_ZTEVE ZTEVE; // Bit 2
Pythia 1:816ba6bfbb20 76 enum FXAS21002CQ_RT_CFG_struct_YTEVE YTEVE; // Bit 1
Pythia 1:816ba6bfbb20 77 enum FXAS21002CQ_RT_CFG_struct_XTEVE XTEVE; // Bit 2
Pythia 1:816ba6bfbb20 78 };
Pythia 1:816ba6bfbb20 79
Pythia 1:816ba6bfbb20 80 enum FXAS21002CQ_RT_THS_struct_DBCNTM {CLEAR_CNT=0, DECREMENT_CNT=1};
Pythia 1:816ba6bfbb20 81
Pythia 1:816ba6bfbb20 82 struct FXAS21002CQ_RT_THS_struct
Pythia 1:816ba6bfbb20 83 {
Pythia 1:816ba6bfbb20 84 enum FXAS21002CQ_RT_THS_struct_DBCNTM DBCNTM; // Bit 7
Pythia 1:816ba6bfbb20 85 uint8_t THS; // Bit 6-0
Pythia 1:816ba6bfbb20 86 };
Pythia 1:816ba6bfbb20 87
Pythia 1:816ba6bfbb20 88 struct FXAS21002CQ_RT_COUNT_struct
Pythia 1:816ba6bfbb20 89 {
Pythia 1:816ba6bfbb20 90 uint8_t D; // Bit 7-0
Pythia 1:816ba6bfbb20 91 };
Pythia 1:816ba6bfbb20 92
Pythia 1:816ba6bfbb20 93 enum FXAS21002CQ_CTRL_REG1_struct_RST {NOT_RST=0, CHIP_RST=1};
Pythia 1:816ba6bfbb20 94 enum FXAS21002CQ_CTRL_REG1_struct_ST {NOT_SELF_TEST=0, SELF_TEST=1};
Pythia 1:816ba6bfbb20 95 enum FXAS21002CQ_CTRL_REG1_struct_DR {ODR_800=0, ODR_400=1, ODR_200=2, ODR_100=3, ODR_50=4, ODR_25=5, ODR_12_5=6, ODR_12_5_7=7};
Pythia 1:816ba6bfbb20 96 enum FXAS21002CQ_CTRL_REG1_struct_ACTIVE {NOT_ACTIVE_GYRO=0, ACTIVE_GYRO=1};
Pythia 1:816ba6bfbb20 97 enum FXAS21002CQ_CTRL_REG1_struct_READY{STANDBY_GYRO=0, READY_GYRO=1};
Pythia 1:816ba6bfbb20 98
Pythia 1:816ba6bfbb20 99 struct FXAS21002CQ_CTRL_REG1_struct
Pythia 1:816ba6bfbb20 100 {
Pythia 1:816ba6bfbb20 101 enum FXAS21002CQ_CTRL_REG1_struct_RST RST; // Bit 6
Pythia 1:816ba6bfbb20 102 enum FXAS21002CQ_CTRL_REG1_struct_ST ST; // Bit 5
Pythia 1:816ba6bfbb20 103 enum FXAS21002CQ_CTRL_REG1_struct_DR DR; // Bit 4-2
Pythia 1:816ba6bfbb20 104 enum FXAS21002CQ_CTRL_REG1_struct_ACTIVE ACTIVE; // Bit 1
Pythia 1:816ba6bfbb20 105 enum FXAS21002CQ_CTRL_REG1_struct_READY READY; // Bit 0
Pythia 1:816ba6bfbb20 106 };
Pythia 1:816ba6bfbb20 107
Pythia 1:816ba6bfbb20 108 enum FXAS21002CQ_CTRL_REG2_struct_INT_CFG_FIFO{FIFO_TO_INT2=0, FIFO_TO_INT1=1};
Pythia 1:816ba6bfbb20 109 enum FXAS21002CQ_CTRL_REG2_struct_INT_EN_FIFO{FIFO_INT_DISABLE=0, FIFO_INT_ENABLE=1};
Pythia 1:816ba6bfbb20 110 enum FXAS21002CQ_CTRL_REG2_struct_INT_CFG_RT{RATE_TO_INT2=0, RATE_TO_INT1=1};
Pythia 1:816ba6bfbb20 111 enum FXAS21002CQ_CTRL_REG2_struct_INT_EN_RT{RATE_INT_DISABLE=0, RATE_INT_ENABLE=1};
Pythia 1:816ba6bfbb20 112 enum FXAS21002CQ_CTRL_REG2_struct_INT_CFG_DRDY{DRDY_TO_INT2=0, DRDY_TO_INT1=1};
Pythia 1:816ba6bfbb20 113 enum FXAS21002CQ_CTRL_REG2_struct_INT_EN_DRDY{DRDY_INT_DISABLE=0, DRDY_INT_ENABLE=1};
Pythia 1:816ba6bfbb20 114 enum FXAS21002CQ_CTRL_REG2_struct_IPOL{INT_ACT_LOW=0, INT_ACT_HIGH=1};
Pythia 1:816ba6bfbb20 115 enum FXAS21002CQ_CTRL_REG2_struct_PP_OD{INT_PUSH_PULL=0, INT_OPEN_DRAIN=1};
Pythia 1:816ba6bfbb20 116
Pythia 1:816ba6bfbb20 117 struct FXAS21002CQ_CTRL_REG2_struct
Pythia 1:816ba6bfbb20 118 {
Pythia 1:816ba6bfbb20 119 enum FXAS21002CQ_CTRL_REG2_struct_INT_CFG_FIFO INT_CFG_FIFO; // Bit 7
Pythia 1:816ba6bfbb20 120 enum FXAS21002CQ_CTRL_REG2_struct_INT_EN_FIFO INT_EN_FIFO; // Bit 6
Pythia 1:816ba6bfbb20 121 enum FXAS21002CQ_CTRL_REG2_struct_INT_CFG_RT INT_CFG_RT; // Bit 5
Pythia 1:816ba6bfbb20 122 enum FXAS21002CQ_CTRL_REG2_struct_INT_EN_RT INT_EN_RT; // Bit 4
Pythia 1:816ba6bfbb20 123 enum FXAS21002CQ_CTRL_REG2_struct_INT_CFG_DRDY INT_CFG_DRDY; // Bit 3
Pythia 1:816ba6bfbb20 124 enum FXAS21002CQ_CTRL_REG2_struct_INT_EN_DRDY INT_EN_DRDY; // Bit 2
Pythia 1:816ba6bfbb20 125 enum FXAS21002CQ_CTRL_REG2_struct_IPOL IPOL; // Bit 1
Pythia 1:816ba6bfbb20 126 enum FXAS21002CQ_CTRL_REG2_struct_PP_OD PP_OD; // Bit 0
Pythia 1:816ba6bfbb20 127 };
Pythia 1:816ba6bfbb20 128
Pythia 1:816ba6bfbb20 129 enum FXAS21002CQ_CTRL_REG3_struct_WRAPTOONE {WRAP_TO_ZERO=0, WRAP_TO_ONE=1};
Pythia 1:816ba6bfbb20 130 enum FXAS21002CQ_CTRL_REG3_struct_EXTCTRLEN {INT2_IS_INTERUPT=0, INT2_IS_POWER_CTRL=1};
Pythia 1:816ba6bfbb20 131 enum FXAS21002CQ_CTRL_REG3_struct_FS_DOUBLE {NOT_DOUBLE_RANGE=0, DOUBLE_RANGE=1};
Pythia 1:816ba6bfbb20 132
Pythia 1:816ba6bfbb20 133 struct FXAS21002CQ_CTRL_REG3_struct
Pythia 1:816ba6bfbb20 134 {
Pythia 1:816ba6bfbb20 135 enum FXAS21002CQ_CTRL_REG3_struct_WRAPTOONE WRAPTOONE; // Bit 3
Pythia 1:816ba6bfbb20 136 enum FXAS21002CQ_CTRL_REG3_struct_EXTCTRLEN EXTCTRLEN; // Bit 2
Pythia 1:816ba6bfbb20 137 enum FXAS21002CQ_CTRL_REG3_struct_FS_DOUBLE FS_DOUBLE; // Bit 0
Pythia 1:816ba6bfbb20 138 };
Pythia 1:816ba6bfbb20 139
Pythia 0:8aa01dbab64e 140 struct FXAS21002CQ_Config_struct
Pythia 0:8aa01dbab64e 141 {
Pythia 1:816ba6bfbb20 142 struct FXAS21002CQ_F_SETUP_struct F_SETUP;
Pythia 1:816ba6bfbb20 143 struct FXAS21002CQ_CTRL_REG0_struct CTRL_REG0;
Pythia 1:816ba6bfbb20 144 struct FXAS21002CQ_RT_CFG_struct RT_CFG;
Pythia 1:816ba6bfbb20 145 struct FXAS21002CQ_RT_THS_struct RT_THS;
Pythia 1:816ba6bfbb20 146 struct FXAS21002CQ_RT_COUNT_struct RT_COUNT;
Pythia 1:816ba6bfbb20 147 struct FXAS21002CQ_CTRL_REG1_struct CTRL_REG1;
Pythia 1:816ba6bfbb20 148 struct FXAS21002CQ_CTRL_REG2_struct CTRL_REG2;
Pythia 1:816ba6bfbb20 149 struct FXAS21002CQ_CTRL_REG3_struct CTRL_REG3;
Pythia 1:816ba6bfbb20 150 };
Pythia 0:8aa01dbab64e 151
Pythia 1:816ba6bfbb20 152 extern struct FXAS21002CQ_Config_struct FXAS21002CQ_Config;
Pythia 0:8aa01dbab64e 153
Pythia 0:8aa01dbab64e 154 /** FXAS21002CQ giro example
Pythia 0:8aa01dbab64e 155 @code
Pythia 0:8aa01dbab64e 156 #include "mbed.h"
Pythia 1:816ba6bfbb20 157 #include "FXAS21002CQ.h"
Pythia 0:8aa01dbab64e 158 I2C i2c(PTE25, PTE24);
Pythia 1:816ba6bfbb20 159 FXAS21002CQ_Giro giro(i2c, FXAS21002CQ_SLAVE_ADDR0); // Configured for the STTBC-AGM01
Pythia 0:8aa01dbab64e 160 int main(void)
Pythia 0:8aa01dbab64e 161 {
Pythia 1:816ba6bfbb20 162 motion_data_units_t giro_data;
Pythia 1:816ba6bfbb20 163 motion_data_counts_t giro_raw;
Pythia 1:816ba6bfbb20 164 float fgX, fgY, fgZ, tmp_float;
Pythia 1:816ba6bfbb20 165 int16_t rgX, rgY, rgZ, tmp_int;
Pythia 0:8aa01dbab64e 166 giro.enable();
Pythia 0:8aa01dbab64e 167 while (true) {
Pythia 0:8aa01dbab64e 168 // counts based results
Pythia 1:816ba6bfbb20 169 giro.getAxis(giro_raw);
Pythia 1:816ba6bfbb20 170 giro.getX(rgX);
Pythia 1:816ba6bfbb20 171 giro.getY(rgY);
Pythia 1:816ba6bfbb20 172 giro.getZ(rgZ);
Pythia 0:8aa01dbab64e 173 // unit based results
Pythia 1:816ba6bfbb20 174 giro.getAxis(giro_data);
Pythia 1:816ba6bfbb20 175 giro.getX(fgX);
Pythia 1:816ba6bfbb20 176 giro.getY(fgY);
Pythia 1:816ba6bfbb20 177 giro.getZ(fgZ);
Pythia 0:8aa01dbab64e 178 wait(0.1f);
Pythia 0:8aa01dbab64e 179 }
Pythia 0:8aa01dbab64e 180 }
Pythia 0:8aa01dbab64e 181 @endcode
Pythia 0:8aa01dbab64e 182 */
Pythia 0:8aa01dbab64e 183
Pythia 2:606d0965f546 184 /** FXAS21002CQ driver class
Pythia 0:8aa01dbab64e 185 */
Pythia 0:8aa01dbab64e 186 class FXAS21002CQ : public MotionSensor
Pythia 0:8aa01dbab64e 187 {
Pythia 0:8aa01dbab64e 188 public:
Pythia 0:8aa01dbab64e 189
Pythia 0:8aa01dbab64e 190 /** Read a device register
Pythia 0:8aa01dbab64e 191 @param addr The address to read from
Pythia 0:8aa01dbab64e 192 @param data The data to read from it
Pythia 0:8aa01dbab64e 193 @param len The amount of data to read from it
Pythia 0:8aa01dbab64e 194 @return 0 if successful, negative number otherwise
Pythia 0:8aa01dbab64e 195 */
Pythia 0:8aa01dbab64e 196 void readRegs(uint8_t addr, uint8_t *data, uint32_t len) ;
Pythia 0:8aa01dbab64e 197
Pythia 0:8aa01dbab64e 198 /** Read the ID from a whoAmI register
Pythia 0:8aa01dbab64e 199 @return The device whoAmI register contents
Pythia 0:8aa01dbab64e 200 */
Pythia 2:606d0965f546 201 virtual uint8_t whoAmI(void) ;
Pythia 0:8aa01dbab64e 202
Pythia 0:8aa01dbab64e 203 virtual void enable(void) const;
Pythia 0:8aa01dbab64e 204 virtual void disable(void) const;
Pythia 0:8aa01dbab64e 205 virtual uint32_t sampleRate(uint32_t frequency) const;
Pythia 0:8aa01dbab64e 206 virtual uint32_t dataReady(void) const;
Pythia 0:8aa01dbab64e 207
Pythia 0:8aa01dbab64e 208 virtual int16_t getX(int16_t &x) const;
Pythia 0:8aa01dbab64e 209 virtual int16_t getY(int16_t &y) const;
Pythia 0:8aa01dbab64e 210 virtual int16_t getZ(int16_t &z) const;
Pythia 0:8aa01dbab64e 211 virtual float getX(float &x) const;
Pythia 0:8aa01dbab64e 212 virtual float getY(float &y) const;
Pythia 0:8aa01dbab64e 213 virtual float getZ(float &z) const;
Pythia 0:8aa01dbab64e 214 virtual void getAxis(motion_data_counts_t &xyz) const;
Pythia 0:8aa01dbab64e 215 virtual void getAxis(motion_data_units_t &xyz) const;
Pythia 0:8aa01dbab64e 216
Pythia 0:8aa01dbab64e 217 int8_t getTemperature(void);
Pythia 0:8aa01dbab64e 218
Pythia 0:8aa01dbab64e 219 /** FXAS21002CQ constructor
Pythia 0:8aa01dbab64e 220 @param i2c a configured i2c object
Pythia 0:8aa01dbab64e 221 @param addr addr of the I2C peripheral as wired
Pythia 0:8aa01dbab64e 222 */
Pythia 2:606d0965f546 223 FXAS21002CQ(I2C &i2c, const uint8_t addr);
Pythia 2:606d0965f546 224 FXAS21002CQ(I2C &i2c, const uint8_t addr, const struct FXAS21002CQ_Config_struct &FXAS21002CQ_Config);
Pythia 0:8aa01dbab64e 225
Pythia 0:8aa01dbab64e 226 /** FXAS21002CQ deconstructor
Pythia 0:8aa01dbab64e 227 */
Pythia 0:8aa01dbab64e 228 ~FXAS21002CQ();
Pythia 0:8aa01dbab64e 229
Pythia 0:8aa01dbab64e 230 protected:
Pythia 0:8aa01dbab64e 231 I2C *_i2c;
Pythia 0:8aa01dbab64e 232 uint8_t _addr;
Pythia 0:8aa01dbab64e 233
Pythia 0:8aa01dbab64e 234 void writeRegs(uint8_t *data, uint32_t len) const;
Pythia 0:8aa01dbab64e 235 int16_t getSensorAxis(uint8_t addr) const;
Pythia 0:8aa01dbab64e 236 };
Pythia 0:8aa01dbab64e 237
Pythia 0:8aa01dbab64e 238 #endif