JNP3_IOT_2016Z / nRF24L01P

support for auto ACK and retransmissions added

Dependents:   JNP3_IOT_6_RADIO_ECHO_FIXED nRF24L01P_NET_GW nRF24L01P_NET_SENSOR Kubus ... more

Fork of nRF24L01P by Owen Edwards

nRF24L01P.cpp@9:a7764d1566f7, 2017-12-21 (annotated)

Committer:
ttajmajer
Date:
Thu Dec 21 13:01:40 2017 +0000
Revision:
9:a7764d1566f7
Parent:
8:f8621be17645 
added support for dynamic payload

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Owen 0:8ae48233b4e4 1 /**
Owen 0:8ae48233b4e4 2 * @file nRF24L01P.cpp
Owen 0:8ae48233b4e4 3 *
Owen 0:8ae48233b4e4 4 * @author Owen Edwards
Owen 0:8ae48233b4e4 5 *
Owen 0:8ae48233b4e4 6 * @section LICENSE
Owen 0:8ae48233b4e4 7 *
Owen 0:8ae48233b4e4 8 * Copyright (c) 2010 Owen Edwards
Owen 0:8ae48233b4e4 9 *
Owen 0:8ae48233b4e4 10 * This program is free software: you can redistribute it and/or modify
Owen 0:8ae48233b4e4 11 * it under the terms of the GNU General Public License as published by
Owen 0:8ae48233b4e4 12 * the Free Software Foundation, either version 3 of the License, or
Owen 0:8ae48233b4e4 13 * (at your option) any later version.
Owen 0:8ae48233b4e4 14 *
Owen 0:8ae48233b4e4 15 * This program is distributed in the hope that it will be useful,
Owen 0:8ae48233b4e4 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Owen 0:8ae48233b4e4 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Owen 0:8ae48233b4e4 18 * GNU General Public License for more details.
Owen 0:8ae48233b4e4 19 *
Owen 0:8ae48233b4e4 20 * You should have received a copy of the GNU General Public License
Owen 0:8ae48233b4e4 21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
Owen 0:8ae48233b4e4 22 *
Owen 0:8ae48233b4e4 23 * The above copyright notice and this permission notice shall be included in
Owen 0:8ae48233b4e4 24 * all copies or substantial portions of the Software.
Owen 0:8ae48233b4e4 25 *
Owen 0:8ae48233b4e4 26 * @section DESCRIPTION
Owen 0:8ae48233b4e4 27 *
Owen 0:8ae48233b4e4 28 * nRF24L01+ Single Chip 2.4GHz Transceiver from Nordic Semiconductor.
Owen 0:8ae48233b4e4 29 *
Owen 0:8ae48233b4e4 30 * Datasheet:
Owen 0:8ae48233b4e4 31 *
Owen 0:8ae48233b4e4 32 * http://www.nordicsemi.no/files/Product/data_sheet/nRF24L01P_Product_Specification_1_0.pdf
Owen 0:8ae48233b4e4 33 */
Owen 0:8ae48233b4e4 34
Owen 0:8ae48233b4e4 35 /**
Owen 0:8ae48233b4e4 36 * Includes
Owen 0:8ae48233b4e4 37 */
Owen 0:8ae48233b4e4 38 #include "nRF24L01P.h"
Owen 0:8ae48233b4e4 39
Owen 0:8ae48233b4e4 40 /**
Owen 0:8ae48233b4e4 41 * Defines
Owen 0:8ae48233b4e4 42 *
Owen 0:8ae48233b4e4 43 * (Note that all defines here start with an underscore, e.g. '_NRF24L01P_MODE_UNKNOWN',
Owen 0:8ae48233b4e4 44 * and are local to this library. The defines in the nRF24L01P.h file do not start
Owen 0:8ae48233b4e4 45 * with the underscore, and can be used by code to access this library.)
Owen 0:8ae48233b4e4 46 */
Owen 0:8ae48233b4e4 47
Owen 0:8ae48233b4e4 48 typedef enum {
Owen 0:8ae48233b4e4 49 _NRF24L01P_MODE_UNKNOWN,
Owen 0:8ae48233b4e4 50 _NRF24L01P_MODE_POWER_DOWN,
Owen 0:8ae48233b4e4 51 _NRF24L01P_MODE_STANDBY,
Owen 0:8ae48233b4e4 52 _NRF24L01P_MODE_RX,
Owen 0:8ae48233b4e4 53 _NRF24L01P_MODE_TX,
Owen 0:8ae48233b4e4 54 } nRF24L01P_Mode_Type;
Owen 0:8ae48233b4e4 55
Owen 0:8ae48233b4e4 56 /*
Owen 0:8ae48233b4e4 57 * The following FIFOs are present in nRF24L01+:
Owen 0:8ae48233b4e4 58 * TX three level, 32 byte FIFO
Owen 0:8ae48233b4e4 59 * RX three level, 32 byte FIFO
Owen 0:8ae48233b4e4 60 */
Owen 0:8ae48233b4e4 61 #define _NRF24L01P_TX_FIFO_COUNT 3
Owen 0:8ae48233b4e4 62 #define _NRF24L01P_RX_FIFO_COUNT 3
Owen 0:8ae48233b4e4 63
Owen 0:8ae48233b4e4 64 #define _NRF24L01P_TX_FIFO_SIZE 32
Owen 0:8ae48233b4e4 65 #define _NRF24L01P_RX_FIFO_SIZE 32
Owen 0:8ae48233b4e4 66
Owen 0:8ae48233b4e4 67 #define _NRF24L01P_SPI_MAX_DATA_RATE 10000000
Owen 0:8ae48233b4e4 68
Owen 0:8ae48233b4e4 69 #define _NRF24L01P_SPI_CMD_RD_REG 0x00
Owen 0:8ae48233b4e4 70 #define _NRF24L01P_SPI_CMD_WR_REG 0x20
Owen 0:8ae48233b4e4 71 #define _NRF24L01P_SPI_CMD_RD_RX_PAYLOAD 0x61
Owen 0:8ae48233b4e4 72 #define _NRF24L01P_SPI_CMD_WR_TX_PAYLOAD 0xa0
Owen 0:8ae48233b4e4 73 #define _NRF24L01P_SPI_CMD_FLUSH_TX 0xe1
Owen 0:8ae48233b4e4 74 #define _NRF24L01P_SPI_CMD_FLUSH_RX 0xe2
Owen 0:8ae48233b4e4 75 #define _NRF24L01P_SPI_CMD_REUSE_TX_PL 0xe3
Owen 0:8ae48233b4e4 76 #define _NRF24L01P_SPI_CMD_R_RX_PL_WID 0x60
Owen 0:8ae48233b4e4 77 #define _NRF24L01P_SPI_CMD_W_ACK_PAYLOAD 0xa8
Owen 0:8ae48233b4e4 78 #define _NRF24L01P_SPI_CMD_W_TX_PYLD_NO_ACK 0xb0
Owen 0:8ae48233b4e4 79 #define _NRF24L01P_SPI_CMD_NOP 0xff
Owen 0:8ae48233b4e4 80
Owen 0:8ae48233b4e4 81
Owen 0:8ae48233b4e4 82 #define _NRF24L01P_REG_CONFIG 0x00
Owen 0:8ae48233b4e4 83 #define _NRF24L01P_REG_EN_AA 0x01
Owen 0:8ae48233b4e4 84 #define _NRF24L01P_REG_EN_RXADDR 0x02
Owen 0:8ae48233b4e4 85 #define _NRF24L01P_REG_SETUP_AW 0x03
Owen 0:8ae48233b4e4 86 #define _NRF24L01P_REG_SETUP_RETR 0x04
Owen 0:8ae48233b4e4 87 #define _NRF24L01P_REG_RF_CH 0x05
Owen 0:8ae48233b4e4 88 #define _NRF24L01P_REG_RF_SETUP 0x06
Owen 0:8ae48233b4e4 89 #define _NRF24L01P_REG_STATUS 0x07
Owen 0:8ae48233b4e4 90 #define _NRF24L01P_REG_OBSERVE_TX 0x08
Owen 0:8ae48233b4e4 91 #define _NRF24L01P_REG_RPD 0x09
Owen 0:8ae48233b4e4 92 #define _NRF24L01P_REG_RX_ADDR_P0 0x0a
Owen 0:8ae48233b4e4 93 #define _NRF24L01P_REG_RX_ADDR_P1 0x0b
Owen 0:8ae48233b4e4 94 #define _NRF24L01P_REG_RX_ADDR_P2 0x0c
Owen 0:8ae48233b4e4 95 #define _NRF24L01P_REG_RX_ADDR_P3 0x0d
Owen 0:8ae48233b4e4 96 #define _NRF24L01P_REG_RX_ADDR_P4 0x0e
Owen 0:8ae48233b4e4 97 #define _NRF24L01P_REG_RX_ADDR_P5 0x0f
Owen 0:8ae48233b4e4 98 #define _NRF24L01P_REG_TX_ADDR 0x10
Owen 0:8ae48233b4e4 99 #define _NRF24L01P_REG_RX_PW_P0 0x11
Owen 0:8ae48233b4e4 100 #define _NRF24L01P_REG_RX_PW_P1 0x12
Owen 0:8ae48233b4e4 101 #define _NRF24L01P_REG_RX_PW_P2 0x13
Owen 0:8ae48233b4e4 102 #define _NRF24L01P_REG_RX_PW_P3 0x14
Owen 0:8ae48233b4e4 103 #define _NRF24L01P_REG_RX_PW_P4 0x15
Owen 0:8ae48233b4e4 104 #define _NRF24L01P_REG_RX_PW_P5 0x16
Owen 0:8ae48233b4e4 105 #define _NRF24L01P_REG_FIFO_STATUS 0x17
Owen 0:8ae48233b4e4 106 #define _NRF24L01P_REG_DYNPD 0x1c
Owen 0:8ae48233b4e4 107 #define _NRF24L01P_REG_FEATURE 0x1d
Owen 0:8ae48233b4e4 108
Owen 0:8ae48233b4e4 109 #define _NRF24L01P_REG_ADDRESS_MASK 0x1f
Owen 0:8ae48233b4e4 110
Owen 0:8ae48233b4e4 111 // CONFIG register:
Owen 0:8ae48233b4e4 112 #define _NRF24L01P_CONFIG_PRIM_RX (1<<0)
Owen 0:8ae48233b4e4 113 #define _NRF24L01P_CONFIG_PWR_UP (1<<1)
Owen 0:8ae48233b4e4 114 #define _NRF24L01P_CONFIG_CRC0 (1<<2)
Owen 0:8ae48233b4e4 115 #define _NRF24L01P_CONFIG_EN_CRC (1<<3)
Owen 0:8ae48233b4e4 116 #define _NRF24L01P_CONFIG_MASK_MAX_RT (1<<4)
Owen 0:8ae48233b4e4 117 #define _NRF24L01P_CONFIG_MASK_TX_DS (1<<5)
Owen 0:8ae48233b4e4 118 #define _NRF24L01P_CONFIG_MASK_RX_DR (1<<6)
Owen 0:8ae48233b4e4 119
Owen 0:8ae48233b4e4 120 #define _NRF24L01P_CONFIG_CRC_MASK (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0)
Owen 0:8ae48233b4e4 121 #define _NRF24L01P_CONFIG_CRC_NONE (0)
Owen 0:8ae48233b4e4 122 #define _NRF24L01P_CONFIG_CRC_8BIT (_NRF24L01P_CONFIG_EN_CRC)
Owen 0:8ae48233b4e4 123 #define _NRF24L01P_CONFIG_CRC_16BIT (_NRF24L01P_CONFIG_EN_CRC|_NRF24L01P_CONFIG_CRC0)
Owen 0:8ae48233b4e4 124
Owen 0:8ae48233b4e4 125 // EN_AA register:
Owen 0:8ae48233b4e4 126 #define _NRF24L01P_EN_AA_NONE 0
Owen 0:8ae48233b4e4 127
Owen 0:8ae48233b4e4 128 // EN_RXADDR register:
Owen 0:8ae48233b4e4 129 #define _NRF24L01P_EN_RXADDR_NONE 0
Owen 0:8ae48233b4e4 130
Owen 0:8ae48233b4e4 131 // SETUP_AW register:
Owen 0:8ae48233b4e4 132 #define _NRF24L01P_SETUP_AW_AW_MASK (0x3<<0)
Owen 0:8ae48233b4e4 133 #define _NRF24L01P_SETUP_AW_AW_3BYTE (0x1<<0)
Owen 0:8ae48233b4e4 134 #define _NRF24L01P_SETUP_AW_AW_4BYTE (0x2<<0)
Owen 0:8ae48233b4e4 135 #define _NRF24L01P_SETUP_AW_AW_5BYTE (0x3<<0)
Owen 0:8ae48233b4e4 136
Owen 0:8ae48233b4e4 137 // SETUP_RETR register:
Owen 0:8ae48233b4e4 138 #define _NRF24L01P_SETUP_RETR_NONE 0
Owen 0:8ae48233b4e4 139
Owen 0:8ae48233b4e4 140 // RF_SETUP register:
Owen 0:8ae48233b4e4 141 #define _NRF24L01P_RF_SETUP_RF_PWR_MASK (0x3<<1)
Owen 0:8ae48233b4e4 142 #define _NRF24L01P_RF_SETUP_RF_PWR_0DBM (0x3<<1)
Owen 0:8ae48233b4e4 143 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM (0x2<<1)
Owen 0:8ae48233b4e4 144 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM (0x1<<1)
Owen 0:8ae48233b4e4 145 #define _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM (0x0<<1)
Owen 0:8ae48233b4e4 146
Owen 0:8ae48233b4e4 147 #define _NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT (1 << 3)
Owen 0:8ae48233b4e4 148 #define _NRF24L01P_RF_SETUP_RF_DR_LOW_BIT (1 << 5)
Owen 0:8ae48233b4e4 149 #define _NRF24L01P_RF_SETUP_RF_DR_MASK (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT|_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
Owen 0:8ae48233b4e4 150 #define _NRF24L01P_RF_SETUP_RF_DR_250KBPS (_NRF24L01P_RF_SETUP_RF_DR_LOW_BIT)
Owen 0:8ae48233b4e4 151 #define _NRF24L01P_RF_SETUP_RF_DR_1MBPS (0)
Owen 0:8ae48233b4e4 152 #define _NRF24L01P_RF_SETUP_RF_DR_2MBPS (_NRF24L01P_RF_SETUP_RF_DR_HIGH_BIT)
Owen 0:8ae48233b4e4 153
Owen 0:8ae48233b4e4 154 // STATUS register:
Owen 0:8ae48233b4e4 155 #define _NRF24L01P_STATUS_TX_FULL (1<<0)
Owen 0:8ae48233b4e4 156 #define _NRF24L01P_STATUS_RX_P_NO (0x7<<1)
Owen 0:8ae48233b4e4 157 #define _NRF24L01P_STATUS_MAX_RT (1<<4)
Owen 0:8ae48233b4e4 158 #define _NRF24L01P_STATUS_TX_DS (1<<5)
Owen 0:8ae48233b4e4 159 #define _NRF24L01P_STATUS_RX_DR (1<<6)
Owen 0:8ae48233b4e4 160
Owen 0:8ae48233b4e4 161 // RX_PW_P0..RX_PW_P5 registers:
Owen 0:8ae48233b4e4 162 #define _NRF24L01P_RX_PW_Px_MASK 0x3F
Owen 0:8ae48233b4e4 163
Owen 0:8ae48233b4e4 164 #define _NRF24L01P_TIMING_Tundef2pd_us 100000 // 100mS
Owen 0:8ae48233b4e4 165 #define _NRF24L01P_TIMING_Tstby2a_us 130 // 130uS
Owen 0:8ae48233b4e4 166 #define _NRF24L01P_TIMING_Thce_us 10 // 10uS
Owen 0:8ae48233b4e4 167 #define _NRF24L01P_TIMING_Tpd2stby_us 4500 // 4.5mS worst case
Owen 0:8ae48233b4e4 168 #define _NRF24L01P_TIMING_Tpece2csn_us 4 // 4uS
Owen 0:8ae48233b4e4 169
Owen 0:8ae48233b4e4 170 /**
Owen 0:8ae48233b4e4 171 * Methods
Owen 0:8ae48233b4e4 172 */
Owen 0:8ae48233b4e4 173
Owen 0:8ae48233b4e4 174 nRF24L01P::nRF24L01P(PinName mosi,
Owen 0:8ae48233b4e4 175 PinName miso,
Owen 0:8ae48233b4e4 176 PinName sck,
Owen 0:8ae48233b4e4 177 PinName csn,
Owen 0:8ae48233b4e4 178 PinName ce,
Owen 0:8ae48233b4e4 179 PinName irq) : spi_(mosi, miso, sck), nCS_(csn), ce_(ce), nIRQ_(irq) {
Owen 0:8ae48233b4e4 180
Owen 0:8ae48233b4e4 181 mode = _NRF24L01P_MODE_UNKNOWN;
Owen 0:8ae48233b4e4 182
Owen 0:8ae48233b4e4 183 disable();
Owen 0:8ae48233b4e4 184
Owen 0:8ae48233b4e4 185 nCS_ = 1;
Owen 0:8ae48233b4e4 186
Owen 0:8ae48233b4e4 187 spi_.frequency(_NRF24L01P_SPI_MAX_DATA_RATE/5); // 2Mbit, 1/5th the maximum transfer rate for the SPI bus
Owen 0:8ae48233b4e4 188 spi_.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
Owen 0:8ae48233b4e4 189
Owen 0:8ae48233b4e4 190 wait_us(_NRF24L01P_TIMING_Tundef2pd_us); // Wait for Power-on reset
Owen 0:8ae48233b4e4 191
Owen 0:8ae48233b4e4 192 setRegister(_NRF24L01P_REG_CONFIG, 0); // Power Down
ttajmajer 2:3012f09dfcc2 193
ttajmajer 2:3012f09dfcc2 194 // Wait until the nRF24L01+ powers down
ttajmajer 2:3012f09dfcc2 195 wait_us( _NRF24L01P_TIMING_Tpd2stby_us ); // This *may* not be necessary (no timing is shown in the Datasheet), but just to be safe
Owen 0:8ae48233b4e4 196
Owen 0:8ae48233b4e4 197 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_MAX_RT|_NRF24L01P_STATUS_TX_DS|_NRF24L01P_STATUS_RX_DR); // Clear any pending interrupts
ttajmajer 2:3012f09dfcc2 198
ttajmajer 2:3012f09dfcc2 199 //flush FIFO
ttajmajer 2:3012f09dfcc2 200 nCS_ = 0;
ttajmajer 2:3012f09dfcc2 201 spi_.write(_NRF24L01P_SPI_CMD_FLUSH_TX);
ttajmajer 2:3012f09dfcc2 202 nCS_ = 1;
ttajmajer 2:3012f09dfcc2 203 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
ttajmajer 2:3012f09dfcc2 204 nCS_ = 0;
ttajmajer 2:3012f09dfcc2 205 spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX);
ttajmajer 2:3012f09dfcc2 206 nCS_ = 1;
ttajmajer 2:3012f09dfcc2 207 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
ttajmajer 2:3012f09dfcc2 208
Owen 0:8ae48233b4e4 209
Owen 0:8ae48233b4e4 210 //
Owen 0:8ae48233b4e4 211 // Setup default configuration
Owen 0:8ae48233b4e4 212 //
Owen 0:8ae48233b4e4 213 disableAllRxPipes();
Owen 0:8ae48233b4e4 214 setRfFrequency();
Owen 0:8ae48233b4e4 215 setRfOutputPower();
Owen 0:8ae48233b4e4 216 setAirDataRate();
Owen 0:8ae48233b4e4 217 setCrcWidth();
Owen 0:8ae48233b4e4 218 setTxAddress();
Owen 0:8ae48233b4e4 219 setRxAddress();
Owen 0:8ae48233b4e4 220 disableAutoAcknowledge();
Owen 0:8ae48233b4e4 221 disableAutoRetransmit();
Owen 0:8ae48233b4e4 222 setTransferSize();
ttajmajer 8:f8621be17645 223
ttajmajer 8:f8621be17645 224 a_retr_enabled = true;
Owen 0:8ae48233b4e4 225
Owen 0:8ae48233b4e4 226 mode = _NRF24L01P_MODE_POWER_DOWN;
Owen 0:8ae48233b4e4 227
Owen 0:8ae48233b4e4 228 }
Owen 0:8ae48233b4e4 229
Owen 0:8ae48233b4e4 230
Owen 0:8ae48233b4e4 231 void nRF24L01P::powerUp(void) {
Owen 0:8ae48233b4e4 232
Owen 0:8ae48233b4e4 233 int config = getRegister(_NRF24L01P_REG_CONFIG);
Owen 0:8ae48233b4e4 234
Owen 0:8ae48233b4e4 235 config |= _NRF24L01P_CONFIG_PWR_UP;
Owen 0:8ae48233b4e4 236
Owen 0:8ae48233b4e4 237 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 238
Owen 0:8ae48233b4e4 239 // Wait until the nRF24L01+ powers up
Owen 0:8ae48233b4e4 240 wait_us( _NRF24L01P_TIMING_Tpd2stby_us );
Owen 0:8ae48233b4e4 241
Owen 0:8ae48233b4e4 242 mode = _NRF24L01P_MODE_STANDBY;
Owen 0:8ae48233b4e4 243
Owen 0:8ae48233b4e4 244 }
Owen 0:8ae48233b4e4 245
Owen 0:8ae48233b4e4 246
Owen 0:8ae48233b4e4 247 void nRF24L01P::powerDown(void) {
Owen 0:8ae48233b4e4 248
Owen 0:8ae48233b4e4 249 int config = getRegister(_NRF24L01P_REG_CONFIG);
Owen 0:8ae48233b4e4 250
Owen 0:8ae48233b4e4 251 config &= ~_NRF24L01P_CONFIG_PWR_UP;
Owen 0:8ae48233b4e4 252
Owen 0:8ae48233b4e4 253 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 254
Owen 0:8ae48233b4e4 255 // Wait until the nRF24L01+ powers down
Owen 0:8ae48233b4e4 256 wait_us( _NRF24L01P_TIMING_Tpd2stby_us ); // This *may* not be necessary (no timing is shown in the Datasheet), but just to be safe
Owen 0:8ae48233b4e4 257
Owen 0:8ae48233b4e4 258 mode = _NRF24L01P_MODE_POWER_DOWN;
Owen 0:8ae48233b4e4 259
Owen 0:8ae48233b4e4 260 }
Owen 0:8ae48233b4e4 261
Owen 0:8ae48233b4e4 262
Owen 0:8ae48233b4e4 263 void nRF24L01P::setReceiveMode(void) {
Owen 0:8ae48233b4e4 264
Owen 0:8ae48233b4e4 265 if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
Owen 0:8ae48233b4e4 266
Owen 0:8ae48233b4e4 267 int config = getRegister(_NRF24L01P_REG_CONFIG);
Owen 0:8ae48233b4e4 268
Owen 0:8ae48233b4e4 269 config |= _NRF24L01P_CONFIG_PRIM_RX;
Owen 0:8ae48233b4e4 270
Owen 0:8ae48233b4e4 271 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 272
Owen 0:8ae48233b4e4 273 mode = _NRF24L01P_MODE_RX;
Owen 0:8ae48233b4e4 274
Owen 0:8ae48233b4e4 275 }
Owen 0:8ae48233b4e4 276
Owen 0:8ae48233b4e4 277
Owen 0:8ae48233b4e4 278 void nRF24L01P::setTransmitMode(void) {
Owen 0:8ae48233b4e4 279
Owen 0:8ae48233b4e4 280 if ( _NRF24L01P_MODE_POWER_DOWN == mode ) powerUp();
Owen 0:8ae48233b4e4 281
Owen 0:8ae48233b4e4 282 int config = getRegister(_NRF24L01P_REG_CONFIG);
Owen 0:8ae48233b4e4 283
Owen 0:8ae48233b4e4 284 config &= ~_NRF24L01P_CONFIG_PRIM_RX;
Owen 0:8ae48233b4e4 285
Owen 0:8ae48233b4e4 286 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 287
Owen 0:8ae48233b4e4 288 mode = _NRF24L01P_MODE_TX;
Owen 0:8ae48233b4e4 289
Owen 0:8ae48233b4e4 290 }
Owen 0:8ae48233b4e4 291
Owen 0:8ae48233b4e4 292
Owen 0:8ae48233b4e4 293 void nRF24L01P::enable(void) {
Owen 0:8ae48233b4e4 294
Owen 0:8ae48233b4e4 295 ce_ = 1;
Owen 0:8ae48233b4e4 296 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
Owen 0:8ae48233b4e4 297
Owen 0:8ae48233b4e4 298 }
Owen 0:8ae48233b4e4 299
Owen 0:8ae48233b4e4 300
Owen 0:8ae48233b4e4 301 void nRF24L01P::disable(void) {
Owen 0:8ae48233b4e4 302
Owen 0:8ae48233b4e4 303 ce_ = 0;
Owen 0:8ae48233b4e4 304
Owen 0:8ae48233b4e4 305 }
Owen 0:8ae48233b4e4 306
Owen 0:8ae48233b4e4 307 void nRF24L01P::setRfFrequency(int frequency) {
Owen 0:8ae48233b4e4 308
Owen 0:8ae48233b4e4 309 if ( ( frequency < NRF24L01P_MIN_RF_FREQUENCY ) || ( frequency > NRF24L01P_MAX_RF_FREQUENCY ) ) {
Owen 0:8ae48233b4e4 310
Owen 0:8ae48233b4e4 311 error( "nRF24L01P: Invalid RF Frequency setting %d\r\n", frequency );
Owen 0:8ae48233b4e4 312 return;
Owen 0:8ae48233b4e4 313
Owen 0:8ae48233b4e4 314 }
Owen 0:8ae48233b4e4 315
Owen 0:8ae48233b4e4 316 int channel = ( frequency - NRF24L01P_MIN_RF_FREQUENCY ) & 0x7F;
Owen 0:8ae48233b4e4 317
Owen 0:8ae48233b4e4 318 setRegister(_NRF24L01P_REG_RF_CH, channel);
Owen 0:8ae48233b4e4 319
Owen 0:8ae48233b4e4 320 }
Owen 0:8ae48233b4e4 321
Owen 0:8ae48233b4e4 322
Owen 0:8ae48233b4e4 323 int nRF24L01P::getRfFrequency(void) {
Owen 0:8ae48233b4e4 324
Owen 0:8ae48233b4e4 325 int channel = getRegister(_NRF24L01P_REG_RF_CH) & 0x7F;
Owen 0:8ae48233b4e4 326
Owen 0:8ae48233b4e4 327 return ( channel + NRF24L01P_MIN_RF_FREQUENCY );
Owen 0:8ae48233b4e4 328
Owen 0:8ae48233b4e4 329 }
Owen 0:8ae48233b4e4 330
Owen 0:8ae48233b4e4 331
Owen 0:8ae48233b4e4 332 void nRF24L01P::setRfOutputPower(int power) {
Owen 0:8ae48233b4e4 333
Owen 0:8ae48233b4e4 334 int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_PWR_MASK;
Owen 0:8ae48233b4e4 335
Owen 0:8ae48233b4e4 336 switch ( power ) {
Owen 0:8ae48233b4e4 337
Owen 0:8ae48233b4e4 338 case NRF24L01P_TX_PWR_ZERO_DB:
Owen 0:8ae48233b4e4 339 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_0DBM;
Owen 0:8ae48233b4e4 340 break;
Owen 0:8ae48233b4e4 341
Owen 0:8ae48233b4e4 342 case NRF24L01P_TX_PWR_MINUS_6_DB:
Owen 0:8ae48233b4e4 343 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM;
Owen 0:8ae48233b4e4 344 break;
Owen 0:8ae48233b4e4 345
Owen 0:8ae48233b4e4 346 case NRF24L01P_TX_PWR_MINUS_12_DB:
Owen 0:8ae48233b4e4 347 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM;
Owen 0:8ae48233b4e4 348 break;
Owen 0:8ae48233b4e4 349
Owen 0:8ae48233b4e4 350 case NRF24L01P_TX_PWR_MINUS_18_DB:
Owen 0:8ae48233b4e4 351 rfSetup |= _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM;
Owen 0:8ae48233b4e4 352 break;
Owen 0:8ae48233b4e4 353
Owen 0:8ae48233b4e4 354 default:
Owen 0:8ae48233b4e4 355 error( "nRF24L01P: Invalid RF Output Power setting %d\r\n", power );
Owen 0:8ae48233b4e4 356 return;
Owen 0:8ae48233b4e4 357
Owen 0:8ae48233b4e4 358 }
Owen 0:8ae48233b4e4 359
Owen 0:8ae48233b4e4 360 setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
Owen 0:8ae48233b4e4 361
Owen 0:8ae48233b4e4 362 }
Owen 0:8ae48233b4e4 363
Owen 0:8ae48233b4e4 364
Owen 0:8ae48233b4e4 365 int nRF24L01P::getRfOutputPower(void) {
Owen 0:8ae48233b4e4 366
Owen 0:8ae48233b4e4 367 int rfPwr = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_PWR_MASK;
Owen 0:8ae48233b4e4 368
Owen 0:8ae48233b4e4 369 switch ( rfPwr ) {
Owen 0:8ae48233b4e4 370
Owen 0:8ae48233b4e4 371 case _NRF24L01P_RF_SETUP_RF_PWR_0DBM:
Owen 0:8ae48233b4e4 372 return NRF24L01P_TX_PWR_ZERO_DB;
Owen 0:8ae48233b4e4 373
Owen 0:8ae48233b4e4 374 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_6DBM:
Owen 0:8ae48233b4e4 375 return NRF24L01P_TX_PWR_MINUS_6_DB;
Owen 0:8ae48233b4e4 376
Owen 0:8ae48233b4e4 377 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_12DBM:
Owen 0:8ae48233b4e4 378 return NRF24L01P_TX_PWR_MINUS_12_DB;
Owen 0:8ae48233b4e4 379
Owen 0:8ae48233b4e4 380 case _NRF24L01P_RF_SETUP_RF_PWR_MINUS_18DBM:
Owen 0:8ae48233b4e4 381 return NRF24L01P_TX_PWR_MINUS_18_DB;
Owen 0:8ae48233b4e4 382
Owen 0:8ae48233b4e4 383 default:
Owen 0:8ae48233b4e4 384 error( "nRF24L01P: Unknown RF Output Power value %d\r\n", rfPwr );
Owen 0:8ae48233b4e4 385 return 0;
Owen 0:8ae48233b4e4 386
Owen 0:8ae48233b4e4 387 }
Owen 0:8ae48233b4e4 388 }
Owen 0:8ae48233b4e4 389
Owen 0:8ae48233b4e4 390
Owen 0:8ae48233b4e4 391 void nRF24L01P::setAirDataRate(int rate) {
Owen 0:8ae48233b4e4 392
Owen 0:8ae48233b4e4 393 int rfSetup = getRegister(_NRF24L01P_REG_RF_SETUP) & ~_NRF24L01P_RF_SETUP_RF_DR_MASK;
Owen 0:8ae48233b4e4 394
Owen 0:8ae48233b4e4 395 switch ( rate ) {
Owen 0:8ae48233b4e4 396
Owen 0:8ae48233b4e4 397 case NRF24L01P_DATARATE_250_KBPS:
Owen 0:8ae48233b4e4 398 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_250KBPS;
Owen 0:8ae48233b4e4 399 break;
Owen 0:8ae48233b4e4 400
Owen 0:8ae48233b4e4 401 case NRF24L01P_DATARATE_1_MBPS:
Owen 0:8ae48233b4e4 402 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_1MBPS;
Owen 0:8ae48233b4e4 403 break;
Owen 0:8ae48233b4e4 404
Owen 0:8ae48233b4e4 405 case NRF24L01P_DATARATE_2_MBPS:
Owen 0:8ae48233b4e4 406 rfSetup |= _NRF24L01P_RF_SETUP_RF_DR_2MBPS;
Owen 0:8ae48233b4e4 407 break;
Owen 0:8ae48233b4e4 408
Owen 0:8ae48233b4e4 409 default:
Owen 0:8ae48233b4e4 410 error( "nRF24L01P: Invalid Air Data Rate setting %d\r\n", rate );
Owen 0:8ae48233b4e4 411 return;
Owen 0:8ae48233b4e4 412
Owen 0:8ae48233b4e4 413 }
Owen 0:8ae48233b4e4 414
Owen 0:8ae48233b4e4 415 setRegister(_NRF24L01P_REG_RF_SETUP, rfSetup);
Owen 0:8ae48233b4e4 416
Owen 0:8ae48233b4e4 417 }
Owen 0:8ae48233b4e4 418
Owen 0:8ae48233b4e4 419
Owen 0:8ae48233b4e4 420 int nRF24L01P::getAirDataRate(void) {
Owen 0:8ae48233b4e4 421
Owen 0:8ae48233b4e4 422 int rfDataRate = getRegister(_NRF24L01P_REG_RF_SETUP) & _NRF24L01P_RF_SETUP_RF_DR_MASK;
Owen 0:8ae48233b4e4 423
Owen 0:8ae48233b4e4 424 switch ( rfDataRate ) {
Owen 0:8ae48233b4e4 425
Owen 0:8ae48233b4e4 426 case _NRF24L01P_RF_SETUP_RF_DR_250KBPS:
Owen 0:8ae48233b4e4 427 return NRF24L01P_DATARATE_250_KBPS;
Owen 0:8ae48233b4e4 428
Owen 0:8ae48233b4e4 429 case _NRF24L01P_RF_SETUP_RF_DR_1MBPS:
Owen 0:8ae48233b4e4 430 return NRF24L01P_DATARATE_1_MBPS;
Owen 0:8ae48233b4e4 431
Owen 0:8ae48233b4e4 432 case _NRF24L01P_RF_SETUP_RF_DR_2MBPS:
Owen 0:8ae48233b4e4 433 return NRF24L01P_DATARATE_2_MBPS;
Owen 0:8ae48233b4e4 434
Owen 0:8ae48233b4e4 435 default:
Owen 0:8ae48233b4e4 436 error( "nRF24L01P: Unknown Air Data Rate value %d\r\n", rfDataRate );
Owen 0:8ae48233b4e4 437 return 0;
Owen 0:8ae48233b4e4 438
Owen 0:8ae48233b4e4 439 }
Owen 0:8ae48233b4e4 440 }
Owen 0:8ae48233b4e4 441
Owen 0:8ae48233b4e4 442
Owen 0:8ae48233b4e4 443 void nRF24L01P::setCrcWidth(int width) {
Owen 0:8ae48233b4e4 444
Owen 0:8ae48233b4e4 445 int config = getRegister(_NRF24L01P_REG_CONFIG) & ~_NRF24L01P_CONFIG_CRC_MASK;
Owen 0:8ae48233b4e4 446
Owen 0:8ae48233b4e4 447 switch ( width ) {
Owen 0:8ae48233b4e4 448
Owen 0:8ae48233b4e4 449 case NRF24L01P_CRC_NONE:
Owen 0:8ae48233b4e4 450 config |= _NRF24L01P_CONFIG_CRC_NONE;
Owen 0:8ae48233b4e4 451 break;
Owen 0:8ae48233b4e4 452
Owen 0:8ae48233b4e4 453 case NRF24L01P_CRC_8_BIT:
Owen 0:8ae48233b4e4 454 config |= _NRF24L01P_CONFIG_CRC_8BIT;
Owen 0:8ae48233b4e4 455 break;
Owen 0:8ae48233b4e4 456
Owen 0:8ae48233b4e4 457 case NRF24L01P_CRC_16_BIT:
Owen 0:8ae48233b4e4 458 config |= _NRF24L01P_CONFIG_CRC_16BIT;
Owen 0:8ae48233b4e4 459 break;
Owen 0:8ae48233b4e4 460
Owen 0:8ae48233b4e4 461 default:
Owen 0:8ae48233b4e4 462 error( "nRF24L01P: Invalid CRC Width setting %d\r\n", width );
Owen 0:8ae48233b4e4 463 return;
Owen 0:8ae48233b4e4 464
Owen 0:8ae48233b4e4 465 }
Owen 0:8ae48233b4e4 466
Owen 0:8ae48233b4e4 467 setRegister(_NRF24L01P_REG_CONFIG, config);
Owen 0:8ae48233b4e4 468
Owen 0:8ae48233b4e4 469 }
Owen 0:8ae48233b4e4 470
Owen 0:8ae48233b4e4 471
Owen 0:8ae48233b4e4 472 int nRF24L01P::getCrcWidth(void) {
Owen 0:8ae48233b4e4 473
Owen 0:8ae48233b4e4 474 int crcWidth = getRegister(_NRF24L01P_REG_CONFIG) & _NRF24L01P_CONFIG_CRC_MASK;
Owen 0:8ae48233b4e4 475
Owen 0:8ae48233b4e4 476 switch ( crcWidth ) {
Owen 0:8ae48233b4e4 477
Owen 0:8ae48233b4e4 478 case _NRF24L01P_CONFIG_CRC_NONE:
Owen 0:8ae48233b4e4 479 return NRF24L01P_CRC_NONE;
Owen 0:8ae48233b4e4 480
Owen 0:8ae48233b4e4 481 case _NRF24L01P_CONFIG_CRC_8BIT:
Owen 0:8ae48233b4e4 482 return NRF24L01P_CRC_8_BIT;
Owen 0:8ae48233b4e4 483
Owen 0:8ae48233b4e4 484 case _NRF24L01P_CONFIG_CRC_16BIT:
Owen 0:8ae48233b4e4 485 return NRF24L01P_CRC_16_BIT;
Owen 0:8ae48233b4e4 486
Owen 0:8ae48233b4e4 487 default:
Owen 0:8ae48233b4e4 488 error( "nRF24L01P: Unknown CRC Width value %d\r\n", crcWidth );
Owen 0:8ae48233b4e4 489 return 0;
Owen 0:8ae48233b4e4 490
Owen 0:8ae48233b4e4 491 }
Owen 0:8ae48233b4e4 492 }
Owen 0:8ae48233b4e4 493
Owen 0:8ae48233b4e4 494
Owen 0:8ae48233b4e4 495 void nRF24L01P::setTransferSize(int size, int pipe) {
Owen 0:8ae48233b4e4 496
Owen 0:8ae48233b4e4 497 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 498
Owen 0:8ae48233b4e4 499 error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 500 return;
Owen 0:8ae48233b4e4 501
Owen 0:8ae48233b4e4 502 }
Owen 0:8ae48233b4e4 503
Owen 0:8ae48233b4e4 504 if ( ( size < 0 ) || ( size > _NRF24L01P_RX_FIFO_SIZE ) ) {
Owen 0:8ae48233b4e4 505
Owen 0:8ae48233b4e4 506 error( "nRF24L01P: Invalid Transfer Size setting %d\r\n", size );
Owen 0:8ae48233b4e4 507 return;
Owen 0:8ae48233b4e4 508
Owen 0:8ae48233b4e4 509 }
Owen 0:8ae48233b4e4 510
Owen 0:8ae48233b4e4 511 int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
Owen 0:8ae48233b4e4 512
Owen 0:8ae48233b4e4 513 setRegister(rxPwPxRegister, ( size & _NRF24L01P_RX_PW_Px_MASK ) );
Owen 0:8ae48233b4e4 514
Owen 0:8ae48233b4e4 515 }
Owen 0:8ae48233b4e4 516
Owen 0:8ae48233b4e4 517
Owen 0:8ae48233b4e4 518 int nRF24L01P::getTransferSize(int pipe) {
Owen 0:8ae48233b4e4 519
Owen 0:8ae48233b4e4 520 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 521
Owen 0:8ae48233b4e4 522 error( "nRF24L01P: Invalid Transfer Size pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 523 return 0;
Owen 0:8ae48233b4e4 524
Owen 0:8ae48233b4e4 525 }
Owen 0:8ae48233b4e4 526
Owen 0:8ae48233b4e4 527 int rxPwPxRegister = _NRF24L01P_REG_RX_PW_P0 + ( pipe - NRF24L01P_PIPE_P0 );
Owen 0:8ae48233b4e4 528
Owen 0:8ae48233b4e4 529 int size = getRegister(rxPwPxRegister);
Owen 0:8ae48233b4e4 530
Owen 0:8ae48233b4e4 531 return ( size & _NRF24L01P_RX_PW_Px_MASK );
Owen 0:8ae48233b4e4 532
Owen 0:8ae48233b4e4 533 }
Owen 0:8ae48233b4e4 534
Owen 0:8ae48233b4e4 535
Owen 0:8ae48233b4e4 536 void nRF24L01P::disableAllRxPipes(void) {
Owen 0:8ae48233b4e4 537
Owen 0:8ae48233b4e4 538 setRegister(_NRF24L01P_REG_EN_RXADDR, _NRF24L01P_EN_RXADDR_NONE);
Owen 0:8ae48233b4e4 539
Owen 0:8ae48233b4e4 540 }
Owen 0:8ae48233b4e4 541
Owen 0:8ae48233b4e4 542
Owen 0:8ae48233b4e4 543 void nRF24L01P::disableAutoAcknowledge(void) {
Owen 0:8ae48233b4e4 544
Owen 0:8ae48233b4e4 545 setRegister(_NRF24L01P_REG_EN_AA, _NRF24L01P_EN_AA_NONE);
Owen 0:8ae48233b4e4 546
Owen 0:8ae48233b4e4 547 }
Owen 0:8ae48233b4e4 548
Owen 0:8ae48233b4e4 549
Owen 0:8ae48233b4e4 550 void nRF24L01P::enableAutoAcknowledge(int pipe) {
Owen 0:8ae48233b4e4 551
Owen 0:8ae48233b4e4 552 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 553
Owen 0:8ae48233b4e4 554 error( "nRF24L01P: Invalid Enable AutoAcknowledge pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 555 return;
Owen 0:8ae48233b4e4 556
Owen 0:8ae48233b4e4 557 }
Owen 0:8ae48233b4e4 558
Owen 0:8ae48233b4e4 559 int enAA = getRegister(_NRF24L01P_REG_EN_AA);
Owen 0:8ae48233b4e4 560
Owen 0:8ae48233b4e4 561 enAA |= ( 1 << (pipe - NRF24L01P_PIPE_P0) );
Owen 0:8ae48233b4e4 562
Owen 0:8ae48233b4e4 563 setRegister(_NRF24L01P_REG_EN_AA, enAA);
Owen 0:8ae48233b4e4 564
Owen 0:8ae48233b4e4 565 }
Owen 0:8ae48233b4e4 566
ttajmajer 9:a7764d1566f7 567 void nRF24L01P::enableDynamicPayload(int pipe) {
ttajmajer 9:a7764d1566f7 568
ttajmajer 9:a7764d1566f7 569 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
ttajmajer 9:a7764d1566f7 570
ttajmajer 9:a7764d1566f7 571 error( "nRF24L01P: Invalid Enable AutoAcknowledge pipe number %d\r\n", pipe );
ttajmajer 9:a7764d1566f7 572 return;
ttajmajer 9:a7764d1566f7 573
ttajmajer 9:a7764d1566f7 574 }
ttajmajer 9:a7764d1566f7 575
ttajmajer 9:a7764d1566f7 576 int feature = getRegister(_NRF24L01P_REG_FEATURE);
ttajmajer 9:a7764d1566f7 577 feature |= ( 1 << 2 );
ttajmajer 9:a7764d1566f7 578 setRegister(_NRF24L01P_REG_FEATURE, feature);
ttajmajer 9:a7764d1566f7 579
ttajmajer 9:a7764d1566f7 580 int dynpd = getRegister(_NRF24L01P_REG_DYNPD);
ttajmajer 9:a7764d1566f7 581 dynpd |= ( 1 << (pipe - NRF24L01P_PIPE_P0) );
ttajmajer 9:a7764d1566f7 582 setRegister(_NRF24L01P_REG_DYNPD, dynpd);
ttajmajer 9:a7764d1566f7 583
ttajmajer 9:a7764d1566f7 584 }
ttajmajer 9:a7764d1566f7 585
ttajmajer 9:a7764d1566f7 586
ttajmajer 9:a7764d1566f7 587 void nRF24L01P::disableDynamicPayload(void) {
ttajmajer 9:a7764d1566f7 588
ttajmajer 9:a7764d1566f7 589 int feature = getRegister(_NRF24L01P_REG_FEATURE);
ttajmajer 9:a7764d1566f7 590 feature &= !( 1 << 2 );
ttajmajer 9:a7764d1566f7 591 setRegister(_NRF24L01P_REG_FEATURE, feature);
ttajmajer 9:a7764d1566f7 592 }
ttajmajer 9:a7764d1566f7 593
Owen 0:8ae48233b4e4 594
Owen 0:8ae48233b4e4 595 void nRF24L01P::disableAutoRetransmit(void) {
Owen 0:8ae48233b4e4 596
Owen 0:8ae48233b4e4 597 setRegister(_NRF24L01P_REG_SETUP_RETR, _NRF24L01P_SETUP_RETR_NONE);
ttajmajer 8:f8621be17645 598 a_retr_enabled = false;
Owen 0:8ae48233b4e4 599
Owen 0:8ae48233b4e4 600 }
Owen 0:8ae48233b4e4 601
ttajmajer 1:781a7eef8610 602 void nRF24L01P::enableAutoRetransmit(int delay, int count) {
ttajmajer 1:781a7eef8610 603 delay = (0x00F0 & (delay << 4));
ttajmajer 1:781a7eef8610 604 count = (0x000F & count);
ttajmajer 1:781a7eef8610 605
ttajmajer 1:781a7eef8610 606 setRegister(_NRF24L01P_REG_SETUP_RETR, delay|count);
ttajmajer 8:f8621be17645 607 a_retr_enabled = true;
ttajmajer 1:781a7eef8610 608
ttajmajer 1:781a7eef8610 609 }
ttajmajer 1:781a7eef8610 610
ttajmajer 1:781a7eef8610 611 int nRF24L01P::getRetrCount(){
ttajmajer 1:781a7eef8610 612 return getRegister(_NRF24L01P_REG_OBSERVE_TX) & 0x0F;
ttajmajer 1:781a7eef8610 613 }
ttajmajer 1:781a7eef8610 614
Owen 0:8ae48233b4e4 615 void nRF24L01P::setRxAddress(unsigned long long address, int width, int pipe) {
Owen 0:8ae48233b4e4 616
Owen 0:8ae48233b4e4 617 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 618
Owen 0:8ae48233b4e4 619 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 620 return;
Owen 0:8ae48233b4e4 621
Owen 0:8ae48233b4e4 622 }
Owen 0:8ae48233b4e4 623
Owen 0:8ae48233b4e4 624 if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) {
Owen 0:8ae48233b4e4 625
Owen 0:8ae48233b4e4 626 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
Owen 0:8ae48233b4e4 627
Owen 0:8ae48233b4e4 628 switch ( width ) {
Owen 0:8ae48233b4e4 629
Owen 0:8ae48233b4e4 630 case 3:
Owen 0:8ae48233b4e4 631 setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE;
Owen 0:8ae48233b4e4 632 break;
Owen 0:8ae48233b4e4 633
Owen 0:8ae48233b4e4 634 case 4:
Owen 0:8ae48233b4e4 635 setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE;
Owen 0:8ae48233b4e4 636 break;
Owen 0:8ae48233b4e4 637
Owen 0:8ae48233b4e4 638 case 5:
Owen 0:8ae48233b4e4 639 setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE;
Owen 0:8ae48233b4e4 640 break;
Owen 0:8ae48233b4e4 641
Owen 0:8ae48233b4e4 642 default:
Owen 0:8ae48233b4e4 643 error( "nRF24L01P: Invalid setRxAddress width setting %d\r\n", width );
Owen 0:8ae48233b4e4 644 return;
Owen 0:8ae48233b4e4 645
Owen 0:8ae48233b4e4 646 }
Owen 0:8ae48233b4e4 647
Owen 0:8ae48233b4e4 648 setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
Owen 0:8ae48233b4e4 649
Owen 0:8ae48233b4e4 650 } else {
Owen 0:8ae48233b4e4 651
Owen 0:8ae48233b4e4 652 width = 1;
Owen 0:8ae48233b4e4 653
Owen 0:8ae48233b4e4 654 }
Owen 0:8ae48233b4e4 655
Owen 0:8ae48233b4e4 656 int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
Owen 0:8ae48233b4e4 657
Owen 0:8ae48233b4e4 658 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 659
Owen 0:8ae48233b4e4 660 nCS_ = 0;
Owen 0:8ae48233b4e4 661
Owen 0:8ae48233b4e4 662 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 663
Owen 0:8ae48233b4e4 664 while ( width-- > 0 ) {
Owen 0:8ae48233b4e4 665
Owen 0:8ae48233b4e4 666 //
Owen 0:8ae48233b4e4 667 // LSByte first
Owen 0:8ae48233b4e4 668 //
Owen 0:8ae48233b4e4 669 spi_.write((int) (address & 0xFF));
Owen 0:8ae48233b4e4 670 address >>= 8;
Owen 0:8ae48233b4e4 671
Owen 0:8ae48233b4e4 672 }
Owen 0:8ae48233b4e4 673
Owen 0:8ae48233b4e4 674 nCS_ = 1;
Owen 0:8ae48233b4e4 675
Owen 0:8ae48233b4e4 676 int enRxAddr = getRegister(_NRF24L01P_REG_EN_RXADDR);
Owen 0:8ae48233b4e4 677
Owen 0:8ae48233b4e4 678 enRxAddr |= (1 << ( pipe - NRF24L01P_PIPE_P0 ) );
Owen 0:8ae48233b4e4 679
Owen 0:8ae48233b4e4 680 setRegister(_NRF24L01P_REG_EN_RXADDR, enRxAddr);
Owen 0:8ae48233b4e4 681 }
Owen 0:8ae48233b4e4 682
ttajmajer 4:d1c0020f1c87 683 void nRF24L01P::disablePipeRX(int pipe) {
ttajmajer 4:d1c0020f1c87 684
ttajmajer 4:d1c0020f1c87 685 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
ttajmajer 4:d1c0020f1c87 686 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
ttajmajer 4:d1c0020f1c87 687 return;
ttajmajer 4:d1c0020f1c87 688 }
ttajmajer 4:d1c0020f1c87 689
ttajmajer 4:d1c0020f1c87 690 int enRxAddr = getRegister(_NRF24L01P_REG_EN_RXADDR);
ttajmajer 4:d1c0020f1c87 691
ttajmajer 4:d1c0020f1c87 692 enRxAddr &= ~(1 << ( pipe - NRF24L01P_PIPE_P0 ) );
ttajmajer 4:d1c0020f1c87 693
ttajmajer 4:d1c0020f1c87 694 setRegister(_NRF24L01P_REG_EN_RXADDR, enRxAddr);
ttajmajer 4:d1c0020f1c87 695
ttajmajer 4:d1c0020f1c87 696 }
ttajmajer 4:d1c0020f1c87 697
ttajmajer 4:d1c0020f1c87 698 void nRF24L01P::enablePipeRX(int pipe) {
ttajmajer 4:d1c0020f1c87 699
ttajmajer 4:d1c0020f1c87 700 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
ttajmajer 4:d1c0020f1c87 701 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
ttajmajer 4:d1c0020f1c87 702 return;
ttajmajer 4:d1c0020f1c87 703 }
ttajmajer 4:d1c0020f1c87 704
ttajmajer 4:d1c0020f1c87 705 int enRxAddr = getRegister(_NRF24L01P_REG_EN_RXADDR);
ttajmajer 4:d1c0020f1c87 706
ttajmajer 4:d1c0020f1c87 707 enRxAddr |= (1 << ( pipe - NRF24L01P_PIPE_P0 ) );
ttajmajer 4:d1c0020f1c87 708
ttajmajer 4:d1c0020f1c87 709 setRegister(_NRF24L01P_REG_EN_RXADDR, enRxAddr);
ttajmajer 4:d1c0020f1c87 710
ttajmajer 4:d1c0020f1c87 711 }
ttajmajer 4:d1c0020f1c87 712
Owen 0:8ae48233b4e4 713 /*
Owen 0:8ae48233b4e4 714 * This version of setRxAddress is just a wrapper for the version that takes 'long long's,
Owen 0:8ae48233b4e4 715 * in case the main code doesn't want to deal with long long's.
Owen 0:8ae48233b4e4 716 */
Owen 0:8ae48233b4e4 717 void nRF24L01P::setRxAddress(unsigned long msb_address, unsigned long lsb_address, int width, int pipe) {
Owen 0:8ae48233b4e4 718
Owen 0:8ae48233b4e4 719 unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 );
Owen 0:8ae48233b4e4 720
Owen 0:8ae48233b4e4 721 setRxAddress(address, width, pipe);
Owen 0:8ae48233b4e4 722
Owen 0:8ae48233b4e4 723 }
Owen 0:8ae48233b4e4 724
Owen 0:8ae48233b4e4 725
Owen 0:8ae48233b4e4 726 /*
Owen 0:8ae48233b4e4 727 * This version of setTxAddress is just a wrapper for the version that takes 'long long's,
Owen 0:8ae48233b4e4 728 * in case the main code doesn't want to deal with long long's.
Owen 0:8ae48233b4e4 729 */
Owen 0:8ae48233b4e4 730 void nRF24L01P::setTxAddress(unsigned long msb_address, unsigned long lsb_address, int width) {
Owen 0:8ae48233b4e4 731
Owen 0:8ae48233b4e4 732 unsigned long long address = ( ( (unsigned long long) msb_address ) << 32 ) | ( ( (unsigned long long) lsb_address ) << 0 );
Owen 0:8ae48233b4e4 733
Owen 0:8ae48233b4e4 734 setTxAddress(address, width);
Owen 0:8ae48233b4e4 735
Owen 0:8ae48233b4e4 736 }
Owen 0:8ae48233b4e4 737
Owen 0:8ae48233b4e4 738
Owen 0:8ae48233b4e4 739 void nRF24L01P::setTxAddress(unsigned long long address, int width) {
Owen 0:8ae48233b4e4 740
Owen 0:8ae48233b4e4 741 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & ~_NRF24L01P_SETUP_AW_AW_MASK;
Owen 0:8ae48233b4e4 742
Owen 0:8ae48233b4e4 743 switch ( width ) {
Owen 0:8ae48233b4e4 744
Owen 0:8ae48233b4e4 745 case 3:
Owen 0:8ae48233b4e4 746 setupAw |= _NRF24L01P_SETUP_AW_AW_3BYTE;
Owen 0:8ae48233b4e4 747 break;
Owen 0:8ae48233b4e4 748
Owen 0:8ae48233b4e4 749 case 4:
Owen 0:8ae48233b4e4 750 setupAw |= _NRF24L01P_SETUP_AW_AW_4BYTE;
Owen 0:8ae48233b4e4 751 break;
Owen 0:8ae48233b4e4 752
Owen 0:8ae48233b4e4 753 case 5:
Owen 0:8ae48233b4e4 754 setupAw |= _NRF24L01P_SETUP_AW_AW_5BYTE;
Owen 0:8ae48233b4e4 755 break;
Owen 0:8ae48233b4e4 756
Owen 0:8ae48233b4e4 757 default:
Owen 0:8ae48233b4e4 758 error( "nRF24L01P: Invalid setTxAddress width setting %d\r\n", width );
Owen 0:8ae48233b4e4 759 return;
Owen 0:8ae48233b4e4 760
Owen 0:8ae48233b4e4 761 }
Owen 0:8ae48233b4e4 762
Owen 0:8ae48233b4e4 763 setRegister(_NRF24L01P_REG_SETUP_AW, setupAw);
Owen 0:8ae48233b4e4 764
Owen 0:8ae48233b4e4 765 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 766
Owen 0:8ae48233b4e4 767 nCS_ = 0;
Owen 0:8ae48233b4e4 768
Owen 0:8ae48233b4e4 769 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 770
Owen 0:8ae48233b4e4 771 while ( width-- > 0 ) {
Owen 0:8ae48233b4e4 772
Owen 0:8ae48233b4e4 773 //
Owen 0:8ae48233b4e4 774 // LSByte first
Owen 0:8ae48233b4e4 775 //
Owen 0:8ae48233b4e4 776 spi_.write((int) (address & 0xFF));
Owen 0:8ae48233b4e4 777 address >>= 8;
Owen 0:8ae48233b4e4 778
Owen 0:8ae48233b4e4 779 }
Owen 0:8ae48233b4e4 780
Owen 0:8ae48233b4e4 781 nCS_ = 1;
Owen 0:8ae48233b4e4 782
Owen 0:8ae48233b4e4 783 }
Owen 0:8ae48233b4e4 784
Owen 0:8ae48233b4e4 785
Owen 0:8ae48233b4e4 786 unsigned long long nRF24L01P::getRxAddress(int pipe) {
Owen 0:8ae48233b4e4 787
Owen 0:8ae48233b4e4 788 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 789
Owen 0:8ae48233b4e4 790 error( "nRF24L01P: Invalid setRxAddress pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 791 return 0;
Owen 0:8ae48233b4e4 792
Owen 0:8ae48233b4e4 793 }
Owen 0:8ae48233b4e4 794
Owen 0:8ae48233b4e4 795 int width;
Owen 0:8ae48233b4e4 796
Owen 0:8ae48233b4e4 797 if ( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) {
Owen 0:8ae48233b4e4 798
Owen 0:8ae48233b4e4 799 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
Owen 0:8ae48233b4e4 800
Owen 0:8ae48233b4e4 801 switch ( setupAw ) {
Owen 0:8ae48233b4e4 802
Owen 0:8ae48233b4e4 803 case _NRF24L01P_SETUP_AW_AW_3BYTE:
Owen 0:8ae48233b4e4 804 width = 3;
Owen 0:8ae48233b4e4 805 break;
Owen 0:8ae48233b4e4 806
Owen 0:8ae48233b4e4 807 case _NRF24L01P_SETUP_AW_AW_4BYTE:
Owen 0:8ae48233b4e4 808 width = 4;
Owen 0:8ae48233b4e4 809 break;
Owen 0:8ae48233b4e4 810
Owen 0:8ae48233b4e4 811 case _NRF24L01P_SETUP_AW_AW_5BYTE:
Owen 0:8ae48233b4e4 812 width = 5;
Owen 0:8ae48233b4e4 813 break;
Owen 0:8ae48233b4e4 814
Owen 0:8ae48233b4e4 815 default:
Owen 0:8ae48233b4e4 816 error( "nRF24L01P: Unknown getRxAddress width value %d\r\n", setupAw );
Owen 0:8ae48233b4e4 817 return 0;
Owen 0:8ae48233b4e4 818
Owen 0:8ae48233b4e4 819 }
Owen 0:8ae48233b4e4 820
Owen 0:8ae48233b4e4 821 } else {
Owen 0:8ae48233b4e4 822
Owen 0:8ae48233b4e4 823 width = 1;
Owen 0:8ae48233b4e4 824
Owen 0:8ae48233b4e4 825 }
Owen 0:8ae48233b4e4 826
Owen 0:8ae48233b4e4 827 int rxAddrPxRegister = _NRF24L01P_REG_RX_ADDR_P0 + ( pipe - NRF24L01P_PIPE_P0 );
Owen 0:8ae48233b4e4 828
Owen 0:8ae48233b4e4 829 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (rxAddrPxRegister & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 830
Owen 0:8ae48233b4e4 831 unsigned long long address = 0;
Owen 0:8ae48233b4e4 832
Owen 0:8ae48233b4e4 833 nCS_ = 0;
Owen 0:8ae48233b4e4 834
Owen 0:8ae48233b4e4 835 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 836
Owen 0:8ae48233b4e4 837 for ( int i=0; i<width; i++ ) {
Owen 0:8ae48233b4e4 838
Owen 0:8ae48233b4e4 839 //
Owen 0:8ae48233b4e4 840 // LSByte first
Owen 0:8ae48233b4e4 841 //
Owen 0:8ae48233b4e4 842 address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
Owen 0:8ae48233b4e4 843
Owen 0:8ae48233b4e4 844 }
Owen 0:8ae48233b4e4 845
Owen 0:8ae48233b4e4 846 nCS_ = 1;
Owen 0:8ae48233b4e4 847
Owen 0:8ae48233b4e4 848 if ( !( ( pipe == NRF24L01P_PIPE_P0 ) || ( pipe == NRF24L01P_PIPE_P1 ) ) ) {
Owen 0:8ae48233b4e4 849
Owen 0:8ae48233b4e4 850 address |= ( getRxAddress(NRF24L01P_PIPE_P1) & ~((unsigned long long) 0xFF) );
Owen 0:8ae48233b4e4 851
Owen 0:8ae48233b4e4 852 }
Owen 0:8ae48233b4e4 853
Owen 0:8ae48233b4e4 854 return address;
Owen 0:8ae48233b4e4 855
Owen 0:8ae48233b4e4 856 }
Owen 0:8ae48233b4e4 857
Owen 0:8ae48233b4e4 858
Owen 0:8ae48233b4e4 859 unsigned long long nRF24L01P::getTxAddress(void) {
Owen 0:8ae48233b4e4 860
Owen 0:8ae48233b4e4 861 int setupAw = getRegister(_NRF24L01P_REG_SETUP_AW) & _NRF24L01P_SETUP_AW_AW_MASK;
Owen 0:8ae48233b4e4 862
Owen 0:8ae48233b4e4 863 int width;
Owen 0:8ae48233b4e4 864
Owen 0:8ae48233b4e4 865 switch ( setupAw ) {
Owen 0:8ae48233b4e4 866
Owen 0:8ae48233b4e4 867 case _NRF24L01P_SETUP_AW_AW_3BYTE:
Owen 0:8ae48233b4e4 868 width = 3;
Owen 0:8ae48233b4e4 869 break;
Owen 0:8ae48233b4e4 870
Owen 0:8ae48233b4e4 871 case _NRF24L01P_SETUP_AW_AW_4BYTE:
Owen 0:8ae48233b4e4 872 width = 4;
Owen 0:8ae48233b4e4 873 break;
Owen 0:8ae48233b4e4 874
Owen 0:8ae48233b4e4 875 case _NRF24L01P_SETUP_AW_AW_5BYTE:
Owen 0:8ae48233b4e4 876 width = 5;
Owen 0:8ae48233b4e4 877 break;
Owen 0:8ae48233b4e4 878
Owen 0:8ae48233b4e4 879 default:
Owen 0:8ae48233b4e4 880 error( "nRF24L01P: Unknown getTxAddress width value %d\r\n", setupAw );
Owen 0:8ae48233b4e4 881 return 0;
Owen 0:8ae48233b4e4 882
Owen 0:8ae48233b4e4 883 }
Owen 0:8ae48233b4e4 884
Owen 0:8ae48233b4e4 885 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (_NRF24L01P_REG_TX_ADDR & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 886
Owen 0:8ae48233b4e4 887 unsigned long long address = 0;
Owen 0:8ae48233b4e4 888
Owen 0:8ae48233b4e4 889 nCS_ = 0;
Owen 0:8ae48233b4e4 890
Owen 0:8ae48233b4e4 891 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 892
Owen 0:8ae48233b4e4 893 for ( int i=0; i<width; i++ ) {
Owen 0:8ae48233b4e4 894
Owen 0:8ae48233b4e4 895 //
Owen 0:8ae48233b4e4 896 // LSByte first
Owen 0:8ae48233b4e4 897 //
Owen 0:8ae48233b4e4 898 address |= ( ( (unsigned long long)( spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF ) ) << (i*8) );
Owen 0:8ae48233b4e4 899
Owen 0:8ae48233b4e4 900 }
Owen 0:8ae48233b4e4 901
Owen 0:8ae48233b4e4 902 nCS_ = 1;
Owen 0:8ae48233b4e4 903
Owen 0:8ae48233b4e4 904 return address;
Owen 0:8ae48233b4e4 905 }
Owen 0:8ae48233b4e4 906
Owen 0:8ae48233b4e4 907
Owen 0:8ae48233b4e4 908 bool nRF24L01P::readable(int pipe) {
Owen 0:8ae48233b4e4 909
Owen 0:8ae48233b4e4 910 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 911
Owen 0:8ae48233b4e4 912 error( "nRF24L01P: Invalid readable pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 913 return false;
Owen 0:8ae48233b4e4 914
Owen 0:8ae48233b4e4 915 }
Owen 0:8ae48233b4e4 916
Owen 0:8ae48233b4e4 917 int status = getStatusRegister();
Owen 0:8ae48233b4e4 918
Owen 0:8ae48233b4e4 919 return ( ( status & _NRF24L01P_STATUS_RX_DR ) && ( ( ( status & _NRF24L01P_STATUS_RX_P_NO ) >> 1 ) == ( pipe & 0x7 ) ) );
Owen 0:8ae48233b4e4 920
Owen 0:8ae48233b4e4 921 }
Owen 0:8ae48233b4e4 922
Owen 0:8ae48233b4e4 923
Owen 0:8ae48233b4e4 924 int nRF24L01P::write(int pipe, char *data, int count) {
ttajmajer 1:781a7eef8610 925
Owen 0:8ae48233b4e4 926 // Note: the pipe number is ignored in a Transmit / write
Owen 0:8ae48233b4e4 927
Owen 0:8ae48233b4e4 928 //
Owen 0:8ae48233b4e4 929 // Save the CE state
Owen 0:8ae48233b4e4 930 //
Owen 0:8ae48233b4e4 931 int originalCe = ce_;
Owen 0:8ae48233b4e4 932 disable();
Owen 0:8ae48233b4e4 933
Owen 0:8ae48233b4e4 934 if ( count <= 0 ) return 0;
Owen 0:8ae48233b4e4 935
Owen 0:8ae48233b4e4 936 if ( count > _NRF24L01P_TX_FIFO_SIZE ) count = _NRF24L01P_TX_FIFO_SIZE;
Owen 0:8ae48233b4e4 937
Owen 0:8ae48233b4e4 938 // Clear the Status bit
Owen 0:8ae48233b4e4 939 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
ttajmajer 8:f8621be17645 940 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_MAX_RT);
Owen 0:8ae48233b4e4 941
Owen 0:8ae48233b4e4 942 nCS_ = 0;
Owen 0:8ae48233b4e4 943
Owen 0:8ae48233b4e4 944 int status = spi_.write(_NRF24L01P_SPI_CMD_WR_TX_PAYLOAD);
Owen 0:8ae48233b4e4 945
Owen 0:8ae48233b4e4 946 for ( int i = 0; i < count; i++ ) {
Owen 0:8ae48233b4e4 947
Owen 0:8ae48233b4e4 948 spi_.write(*data++);
Owen 0:8ae48233b4e4 949
Owen 0:8ae48233b4e4 950 }
Owen 0:8ae48233b4e4 951
Owen 0:8ae48233b4e4 952 nCS_ = 1;
Owen 0:8ae48233b4e4 953
Owen 0:8ae48233b4e4 954 int originalMode = mode;
Owen 0:8ae48233b4e4 955 setTransmitMode();
Owen 0:8ae48233b4e4 956
Owen 0:8ae48233b4e4 957 enable();
Owen 0:8ae48233b4e4 958 wait_us(_NRF24L01P_TIMING_Thce_us);
Owen 0:8ae48233b4e4 959 disable();
Owen 0:8ae48233b4e4 960
ttajmajer 1:781a7eef8610 961 while ( !( getStatusRegister() & (_NRF24L01P_STATUS_TX_DS | _NRF24L01P_STATUS_MAX_RT) ) ) {
Owen 0:8ae48233b4e4 962 }
ttajmajer 1:781a7eef8610 963
ttajmajer 8:f8621be17645 964 int s = getStatusRegister();
ttajmajer 8:f8621be17645 965
ttajmajer 8:f8621be17645 966 if (s & _NRF24L01P_STATUS_MAX_RT){
ttajmajer 8:f8621be17645 967 //max retransmissions
ttajmajer 7:434a1c2ff406 968 flushTx();
ttajmajer 1:781a7eef8610 969 count = -1;
ttajmajer 7:434a1c2ff406 970 }
Owen 0:8ae48233b4e4 971
Owen 0:8ae48233b4e4 972 // Clear the Status bit
Owen 0:8ae48233b4e4 973 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
ttajmajer 1:781a7eef8610 974 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_MAX_RT);
Owen 0:8ae48233b4e4 975
Owen 0:8ae48233b4e4 976 if ( originalMode == _NRF24L01P_MODE_RX ) {
Owen 0:8ae48233b4e4 977
Owen 0:8ae48233b4e4 978 setReceiveMode();
Owen 0:8ae48233b4e4 979
Owen 0:8ae48233b4e4 980 }
Owen 0:8ae48233b4e4 981
Owen 0:8ae48233b4e4 982 ce_ = originalCe;
Owen 0:8ae48233b4e4 983 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
Owen 0:8ae48233b4e4 984
Owen 0:8ae48233b4e4 985 return count;
Owen 0:8ae48233b4e4 986
Owen 0:8ae48233b4e4 987 }
Owen 0:8ae48233b4e4 988
Owen 0:8ae48233b4e4 989
Owen 0:8ae48233b4e4 990 int nRF24L01P::read(int pipe, char *data, int count) {
Owen 0:8ae48233b4e4 991
Owen 0:8ae48233b4e4 992 if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
Owen 0:8ae48233b4e4 993
Owen 0:8ae48233b4e4 994 error( "nRF24L01P: Invalid read pipe number %d\r\n", pipe );
Owen 0:8ae48233b4e4 995 return -1;
Owen 0:8ae48233b4e4 996
Owen 0:8ae48233b4e4 997 }
Owen 0:8ae48233b4e4 998
Owen 0:8ae48233b4e4 999 if ( count <= 0 ) return 0;
Owen 0:8ae48233b4e4 1000
Owen 0:8ae48233b4e4 1001 if ( count > _NRF24L01P_RX_FIFO_SIZE ) count = _NRF24L01P_RX_FIFO_SIZE;
Owen 0:8ae48233b4e4 1002
Owen 0:8ae48233b4e4 1003 if ( readable(pipe) ) {
Owen 0:8ae48233b4e4 1004
Owen 0:8ae48233b4e4 1005 nCS_ = 0;
Owen 0:8ae48233b4e4 1006
Owen 0:8ae48233b4e4 1007 int status = spi_.write(_NRF24L01P_SPI_CMD_R_RX_PL_WID);
Owen 0:8ae48233b4e4 1008
jackmax 3:3f6bf32d36c2 1009 int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP) & 0xFF;
Owen 0:8ae48233b4e4 1010
Owen 0:8ae48233b4e4 1011 nCS_ = 1;
Owen 0:8ae48233b4e4 1012
Owen 0:8ae48233b4e4 1013 if ( ( rxPayloadWidth < 0 ) || ( rxPayloadWidth > _NRF24L01P_RX_FIFO_SIZE ) ) {
Owen 0:8ae48233b4e4 1014
Owen 0:8ae48233b4e4 1015 // Received payload error: need to flush the FIFO
Owen 0:8ae48233b4e4 1016
Owen 0:8ae48233b4e4 1017 nCS_ = 0;
Owen 0:8ae48233b4e4 1018
Owen 0:8ae48233b4e4 1019 int status = spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX);
Owen 0:8ae48233b4e4 1020
Owen 0:8ae48233b4e4 1021 int rxPayloadWidth = spi_.write(_NRF24L01P_SPI_CMD_NOP);
Owen 0:8ae48233b4e4 1022
Owen 0:8ae48233b4e4 1023 nCS_ = 1;
Owen 0:8ae48233b4e4 1024
Owen 0:8ae48233b4e4 1025 //
Owen 0:8ae48233b4e4 1026 // At this point, we should retry the reception,
Owen 0:8ae48233b4e4 1027 // but for now we'll just fall through...
Owen 0:8ae48233b4e4 1028 //
Owen 0:8ae48233b4e4 1029
Owen 0:8ae48233b4e4 1030 } else {
Owen 0:8ae48233b4e4 1031
Owen 0:8ae48233b4e4 1032 if ( rxPayloadWidth < count ) count = rxPayloadWidth;
Owen 0:8ae48233b4e4 1033
Owen 0:8ae48233b4e4 1034 nCS_ = 0;
Owen 0:8ae48233b4e4 1035
Owen 0:8ae48233b4e4 1036 int status = spi_.write(_NRF24L01P_SPI_CMD_RD_RX_PAYLOAD);
Owen 0:8ae48233b4e4 1037
Owen 0:8ae48233b4e4 1038 for ( int i = 0; i < count; i++ ) {
Owen 0:8ae48233b4e4 1039
Owen 0:8ae48233b4e4 1040 *data++ = spi_.write(_NRF24L01P_SPI_CMD_NOP);
Owen 0:8ae48233b4e4 1041
Owen 0:8ae48233b4e4 1042 }
Owen 0:8ae48233b4e4 1043
Owen 0:8ae48233b4e4 1044 nCS_ = 1;
Owen 0:8ae48233b4e4 1045
Owen 0:8ae48233b4e4 1046 // Clear the Status bit
Owen 0:8ae48233b4e4 1047 setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_RX_DR);
Owen 0:8ae48233b4e4 1048
Owen 0:8ae48233b4e4 1049 return count;
Owen 0:8ae48233b4e4 1050
Owen 0:8ae48233b4e4 1051 }
Owen 0:8ae48233b4e4 1052
Owen 0:8ae48233b4e4 1053 } else {
Owen 0:8ae48233b4e4 1054
Owen 0:8ae48233b4e4 1055 //
Owen 0:8ae48233b4e4 1056 // What should we do if there is no 'readable' data?
Owen 0:8ae48233b4e4 1057 // We could wait for data to arrive, but for now, we'll
Owen 0:8ae48233b4e4 1058 // just return with no data.
Owen 0:8ae48233b4e4 1059 //
Owen 0:8ae48233b4e4 1060 return 0;
Owen 0:8ae48233b4e4 1061
Owen 0:8ae48233b4e4 1062 }
Owen 0:8ae48233b4e4 1063
Owen 0:8ae48233b4e4 1064 //
Owen 0:8ae48233b4e4 1065 // We get here because an error condition occured;
Owen 0:8ae48233b4e4 1066 // We could wait for data to arrive, but for now, we'll
Owen 0:8ae48233b4e4 1067 // just return with no data.
Owen 0:8ae48233b4e4 1068 //
Owen 0:8ae48233b4e4 1069 return -1;
Owen 0:8ae48233b4e4 1070
Owen 0:8ae48233b4e4 1071 }
Owen 0:8ae48233b4e4 1072
ttajmajer 7:434a1c2ff406 1073 bool nRF24L01P::getRPD(){
ttajmajer 7:434a1c2ff406 1074 uint8_t rpd = getRegister(_NRF24L01P_REG_RPD);
ttajmajer 7:434a1c2ff406 1075 return (rpd>0);
ttajmajer 7:434a1c2ff406 1076 }
ttajmajer 7:434a1c2ff406 1077
ttajmajer 7:434a1c2ff406 1078 uint8_t nRF24L01P::getRSSI(){
ttajmajer 7:434a1c2ff406 1079 uint8_t rssi =0;
ttajmajer 7:434a1c2ff406 1080 for(int i=0; i<256; i++){
ttajmajer 7:434a1c2ff406 1081 rssi += getRPD();
ttajmajer 7:434a1c2ff406 1082 wait_us(50);
ttajmajer 7:434a1c2ff406 1083 flushRx();
ttajmajer 7:434a1c2ff406 1084 }
ttajmajer 7:434a1c2ff406 1085 return rssi;
ttajmajer 7:434a1c2ff406 1086 }
ttajmajer 7:434a1c2ff406 1087
ttajmajer 7:434a1c2ff406 1088 void nRF24L01P::flushRx(void)
ttajmajer 7:434a1c2ff406 1089 {
ttajmajer 7:434a1c2ff406 1090 nCS_ = 0;
ttajmajer 7:434a1c2ff406 1091 spi_.write(_NRF24L01P_SPI_CMD_FLUSH_RX);
ttajmajer 7:434a1c2ff406 1092 nCS_ = 1;
ttajmajer 7:434a1c2ff406 1093 }
ttajmajer 7:434a1c2ff406 1094
ttajmajer 7:434a1c2ff406 1095 void nRF24L01P::flushTx(void)
ttajmajer 7:434a1c2ff406 1096 {
ttajmajer 7:434a1c2ff406 1097 nCS_ = 0;
ttajmajer 7:434a1c2ff406 1098 spi_.write(_NRF24L01P_SPI_CMD_FLUSH_TX);
ttajmajer 7:434a1c2ff406 1099 nCS_ = 1;
ttajmajer 7:434a1c2ff406 1100 }
ttajmajer 7:434a1c2ff406 1101
ttajmajer 7:434a1c2ff406 1102
Owen 0:8ae48233b4e4 1103 void nRF24L01P::setRegister(int regAddress, int regData) {
Owen 0:8ae48233b4e4 1104
Owen 0:8ae48233b4e4 1105 //
Owen 0:8ae48233b4e4 1106 // Save the CE state
Owen 0:8ae48233b4e4 1107 //
Owen 0:8ae48233b4e4 1108 int originalCe = ce_;
Owen 0:8ae48233b4e4 1109 disable();
Owen 0:8ae48233b4e4 1110
Owen 0:8ae48233b4e4 1111 int cn = (_NRF24L01P_SPI_CMD_WR_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 1112
Owen 0:8ae48233b4e4 1113 nCS_ = 0;
Owen 0:8ae48233b4e4 1114
Owen 0:8ae48233b4e4 1115 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 1116
Owen 0:8ae48233b4e4 1117 spi_.write(regData & 0xFF);
Owen 0:8ae48233b4e4 1118
Owen 0:8ae48233b4e4 1119 nCS_ = 1;
Owen 0:8ae48233b4e4 1120
Owen 0:8ae48233b4e4 1121 ce_ = originalCe;
Owen 0:8ae48233b4e4 1122 wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
Owen 0:8ae48233b4e4 1123
Owen 0:8ae48233b4e4 1124 }
Owen 0:8ae48233b4e4 1125
Owen 0:8ae48233b4e4 1126
Owen 0:8ae48233b4e4 1127 int nRF24L01P::getRegister(int regAddress) {
Owen 0:8ae48233b4e4 1128
Owen 0:8ae48233b4e4 1129 int cn = (_NRF24L01P_SPI_CMD_RD_REG | (regAddress & _NRF24L01P_REG_ADDRESS_MASK));
Owen 0:8ae48233b4e4 1130
Owen 0:8ae48233b4e4 1131 nCS_ = 0;
Owen 0:8ae48233b4e4 1132
Owen 0:8ae48233b4e4 1133 int status = spi_.write(cn);
Owen 0:8ae48233b4e4 1134
Owen 0:8ae48233b4e4 1135 int dn = spi_.write(_NRF24L01P_SPI_CMD_NOP);
Owen 0:8ae48233b4e4 1136
Owen 0:8ae48233b4e4 1137 nCS_ = 1;
Owen 0:8ae48233b4e4 1138
Owen 0:8ae48233b4e4 1139 return dn;
Owen 0:8ae48233b4e4 1140
Owen 0:8ae48233b4e4 1141 }
Owen 0:8ae48233b4e4 1142
Owen 0:8ae48233b4e4 1143 int nRF24L01P::getStatusRegister(void) {
Owen 0:8ae48233b4e4 1144
Owen 0:8ae48233b4e4 1145 nCS_ = 0;
Owen 0:8ae48233b4e4 1146
Owen 0:8ae48233b4e4 1147 int status = spi_.write(_NRF24L01P_SPI_CMD_NOP);
Owen 0:8ae48233b4e4 1148
Owen 0:8ae48233b4e4 1149 nCS_ = 1;
Owen 0:8ae48233b4e4 1150
Owen 0:8ae48233b4e4 1151 return status;
Owen 0:8ae48233b4e4 1152
Owen 0:8ae48233b4e4 1153 }