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targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/adc/fsl_adc_features.h@146:f64d43ff0c18, 2014-04-02 (annotated)

Committer:
mbed_official
Date:
Wed Apr 02 21:00:08 2014 +0100
Revision:
146:f64d43ff0c18
Synchronized with git revision d537c51d26da35e031d537f7fc90380fc74cb207



Full URL: https://github.com/mbedmicro/mbed/commit/d537c51d26da35e031d537f7fc90380fc74cb207/



target K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30 #if !defined(__FSL_ADC_FEATURES_H__)
mbed_official 146:f64d43ff0c18 31 #define __FSL_ADC_FEATURES_H__
mbed_official 146:f64d43ff0c18 32
mbed_official 146:f64d43ff0c18 33 #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
mbed_official 146:f64d43ff0c18 34 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
mbed_official 146:f64d43ff0c18 35 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
mbed_official 146:f64d43ff0c18 36 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
mbed_official 146:f64d43ff0c18 37 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
mbed_official 146:f64d43ff0c18 38 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || \
mbed_official 146:f64d43ff0c18 39 defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
mbed_official 146:f64d43ff0c18 40 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
mbed_official 146:f64d43ff0c18 41 defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || \
mbed_official 146:f64d43ff0c18 42 defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
mbed_official 146:f64d43ff0c18 43 defined(CPU_MK64FX512VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
mbed_official 146:f64d43ff0c18 44 defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
mbed_official 146:f64d43ff0c18 45 defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || \
mbed_official 146:f64d43ff0c18 46 defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || \
mbed_official 146:f64d43ff0c18 47 defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || \
mbed_official 146:f64d43ff0c18 48 defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
mbed_official 146:f64d43ff0c18 49 defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) || defined(CPU_MKV31F256VLH12) || \
mbed_official 146:f64d43ff0c18 50 defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || defined(CPU_MKV31F512VLL12)
mbed_official 146:f64d43ff0c18 51 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA).*/
mbed_official 146:f64d43ff0c18 52 #define FSL_FEATURE_ADC_HAS_PGA (0)
mbed_official 146:f64d43ff0c18 53 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]).*/
mbed_official 146:f64d43ff0c18 54 #define FSL_FEATURE_ADC_HAS_DMA (1)
mbed_official 146:f64d43ff0c18 55 /* @brief Has differential mode (bitfield SC1x[DIFF]).*/
mbed_official 146:f64d43ff0c18 56 #define FSL_FEATURE_ADC_HAS_DIFF_MODE (1)
mbed_official 146:f64d43ff0c18 57 /* @brief Has FIFO (bit SC4[AFDEP]).*/
mbed_official 146:f64d43ff0c18 58 #define FSL_FEATURE_ADC_HAS_FIFO (0)
mbed_official 146:f64d43ff0c18 59 /* @brief FIFO size if available (bitfield SC4[AFDEP]).*/
mbed_official 146:f64d43ff0c18 60 #define FSL_FEATURE_ADC_FIFO_SIZE (0)
mbed_official 146:f64d43ff0c18 61 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]).*/
mbed_official 146:f64d43ff0c18 62 #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
mbed_official 146:f64d43ff0c18 63 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE].*/
mbed_official 146:f64d43ff0c18 64 #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
mbed_official 146:f64d43ff0c18 65 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx).*/
mbed_official 146:f64d43ff0c18 66 #define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
mbed_official 146:f64d43ff0c18 67 /* @brief Has HW averaging (bit SC3[AVGE]).*/
mbed_official 146:f64d43ff0c18 68 #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
mbed_official 146:f64d43ff0c18 69 /* @brief Has offset correction (register OFS).*/
mbed_official 146:f64d43ff0c18 70 #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
mbed_official 146:f64d43ff0c18 71 /* @brief Maximum ADC resolution.*/
mbed_official 146:f64d43ff0c18 72 #define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
mbed_official 146:f64d43ff0c18 73 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers).*/
mbed_official 146:f64d43ff0c18 74 #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
mbed_official 146:f64d43ff0c18 75 #elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
mbed_official 146:f64d43ff0c18 76 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || \
mbed_official 146:f64d43ff0c18 77 defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || \
mbed_official 146:f64d43ff0c18 78 defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || \
mbed_official 146:f64d43ff0c18 79 defined(CPU_MKL05Z32VLF4)
mbed_official 146:f64d43ff0c18 80 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA).*/
mbed_official 146:f64d43ff0c18 81 #define FSL_FEATURE_ADC_HAS_PGA (0)
mbed_official 146:f64d43ff0c18 82 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]).*/
mbed_official 146:f64d43ff0c18 83 #define FSL_FEATURE_ADC_HAS_DMA (1)
mbed_official 146:f64d43ff0c18 84 /* @brief Has differential mode (bitfield SC1x[DIFF]).*/
mbed_official 146:f64d43ff0c18 85 #define FSL_FEATURE_ADC_HAS_DIFF_MODE (0)
mbed_official 146:f64d43ff0c18 86 /* @brief Has FIFO (bit SC4[AFDEP]).*/
mbed_official 146:f64d43ff0c18 87 #define FSL_FEATURE_ADC_HAS_FIFO (0)
mbed_official 146:f64d43ff0c18 88 /* @brief FIFO size if available (bitfield SC4[AFDEP]).*/
mbed_official 146:f64d43ff0c18 89 #define FSL_FEATURE_ADC_FIFO_SIZE (0)
mbed_official 146:f64d43ff0c18 90 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]).*/
mbed_official 146:f64d43ff0c18 91 #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
mbed_official 146:f64d43ff0c18 92 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE].*/
mbed_official 146:f64d43ff0c18 93 #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
mbed_official 146:f64d43ff0c18 94 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx).*/
mbed_official 146:f64d43ff0c18 95 #define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
mbed_official 146:f64d43ff0c18 96 /* @brief Has HW averaging (bit SC3[AVGE]).*/
mbed_official 146:f64d43ff0c18 97 #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
mbed_official 146:f64d43ff0c18 98 /* @brief Has offset correction (register OFS).*/
mbed_official 146:f64d43ff0c18 99 #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
mbed_official 146:f64d43ff0c18 100 /* @brief Maximum ADC resolution.*/
mbed_official 146:f64d43ff0c18 101 #define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
mbed_official 146:f64d43ff0c18 102 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers).*/
mbed_official 146:f64d43ff0c18 103 #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
mbed_official 146:f64d43ff0c18 104 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
mbed_official 146:f64d43ff0c18 105 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
mbed_official 146:f64d43ff0c18 106 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA).*/
mbed_official 146:f64d43ff0c18 107 #define FSL_FEATURE_ADC_HAS_PGA (1)
mbed_official 146:f64d43ff0c18 108 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]).*/
mbed_official 146:f64d43ff0c18 109 #define FSL_FEATURE_ADC_HAS_DMA (1)
mbed_official 146:f64d43ff0c18 110 /* @brief Has differential mode (bitfield SC1x[DIFF]).*/
mbed_official 146:f64d43ff0c18 111 #define FSL_FEATURE_ADC_HAS_DIFF_MODE (1)
mbed_official 146:f64d43ff0c18 112 /* @brief Has FIFO (bit SC4[AFDEP]).*/
mbed_official 146:f64d43ff0c18 113 #define FSL_FEATURE_ADC_HAS_FIFO (0)
mbed_official 146:f64d43ff0c18 114 /* @brief FIFO size if available (bitfield SC4[AFDEP]).*/
mbed_official 146:f64d43ff0c18 115 #define FSL_FEATURE_ADC_FIFO_SIZE (0)
mbed_official 146:f64d43ff0c18 116 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]).*/
mbed_official 146:f64d43ff0c18 117 #define FSL_FEATURE_ADC_HAS_MUX_SELECT (1)
mbed_official 146:f64d43ff0c18 118 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE].*/
mbed_official 146:f64d43ff0c18 119 #define FSL_FEATURE_ADC_HAS_HW_TRIGGER_MASK (0)
mbed_official 146:f64d43ff0c18 120 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx).*/
mbed_official 146:f64d43ff0c18 121 #define FSL_FEATURE_ADC_HAS_CALIBRATION (1)
mbed_official 146:f64d43ff0c18 122 /* @brief Has HW averaging (bit SC3[AVGE]).*/
mbed_official 146:f64d43ff0c18 123 #define FSL_FEATURE_ADC_HAS_HW_AVERAGE (1)
mbed_official 146:f64d43ff0c18 124 /* @brief Has offset correction (register OFS).*/
mbed_official 146:f64d43ff0c18 125 #define FSL_FEATURE_ADC_HAS_OFFSET_CORRECTION (1)
mbed_official 146:f64d43ff0c18 126 /* @brief Maximum ADC resolution.*/
mbed_official 146:f64d43ff0c18 127 #define FSL_FEATURE_ADC_MAX_RESOLUTION (16)
mbed_official 146:f64d43ff0c18 128 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers).*/
mbed_official 146:f64d43ff0c18 129 #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (2)
mbed_official 146:f64d43ff0c18 130 #else
mbed_official 146:f64d43ff0c18 131 #error "No valid CPU defined!"
mbed_official 146:f64d43ff0c18 132 #endif
mbed_official 146:f64d43ff0c18 133
mbed_official 146:f64d43ff0c18 134 #endif /* __FSL_ADC_FEATURES_H__*/
mbed_official 146:f64d43ff0c18 135 /*******************************************************************************
mbed_official 146:f64d43ff0c18 136 * EOF
mbed_official 146:f64d43ff0c18 137 ******************************************************************************/
mbed_official 146:f64d43ff0c18 138