mbed-ton | Mbed

IOTON Technology » Code » mbed-ton

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h@168:1dc8c8bdd03d, 2017-06-29 (annotated)

Committer:: krebyy
Date:: Thu Jun 29 20:34:04 2017 +0000
Revision:: 168:1dc8c8bdd03d
Parent:: 167:e84263d55307

First commit - mbed for TON Board V1.2

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/**
AnnaBridge	167:e84263d55307	2	******************************************************************************
AnnaBridge	167:e84263d55307	3	* @file stm32f4xx_ll_dac.h
AnnaBridge	167:e84263d55307	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.7.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
AnnaBridge	167:e84263d55307	7	* @brief Header file of DAC LL module.
AnnaBridge	167:e84263d55307	8	******************************************************************************
AnnaBridge	167:e84263d55307	9	* @attention
AnnaBridge	167:e84263d55307	10	*
AnnaBridge	167:e84263d55307	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	167:e84263d55307	12	*
AnnaBridge	167:e84263d55307	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	167:e84263d55307	14	* are permitted provided that the following conditions are met:
AnnaBridge	167:e84263d55307	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	167:e84263d55307	16	* this list of conditions and the following disclaimer.
AnnaBridge	167:e84263d55307	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	167:e84263d55307	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	167:e84263d55307	19	* and/or other materials provided with the distribution.
AnnaBridge	167:e84263d55307	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	167:e84263d55307	21	* may be used to endorse or promote products derived from this software
AnnaBridge	167:e84263d55307	22	* without specific prior written permission.
AnnaBridge	167:e84263d55307	23	*
AnnaBridge	167:e84263d55307	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	167:e84263d55307	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	167:e84263d55307	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	167:e84263d55307	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	167:e84263d55307	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	167:e84263d55307	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	167:e84263d55307	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	167:e84263d55307	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	167:e84263d55307	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	167:e84263d55307	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	167:e84263d55307	34	*
AnnaBridge	167:e84263d55307	35	******************************************************************************
AnnaBridge	167:e84263d55307	36	*/
AnnaBridge	167:e84263d55307	37
AnnaBridge	167:e84263d55307	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	167:e84263d55307	39	#ifndef __STM32F4xx_LL_DAC_H
AnnaBridge	167:e84263d55307	40	#define __STM32F4xx_LL_DAC_H
AnnaBridge	167:e84263d55307	41
AnnaBridge	167:e84263d55307	42	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	43	extern "C" {
AnnaBridge	167:e84263d55307	44	#endif
AnnaBridge	167:e84263d55307	45
AnnaBridge	167:e84263d55307	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	47	#include "stm32f4xx.h"
AnnaBridge	167:e84263d55307	48
AnnaBridge	167:e84263d55307	49	/** @addtogroup STM32F4xx_LL_Driver
AnnaBridge	167:e84263d55307	50	* @{
AnnaBridge	167:e84263d55307	51	*/
AnnaBridge	167:e84263d55307	52
AnnaBridge	167:e84263d55307	53	#if defined(DAC)
AnnaBridge	167:e84263d55307	54
AnnaBridge	167:e84263d55307	55	/** @defgroup DAC_LL DAC
AnnaBridge	167:e84263d55307	56	* @{
AnnaBridge	167:e84263d55307	57	*/
AnnaBridge	167:e84263d55307	58
AnnaBridge	167:e84263d55307	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	61
AnnaBridge	167:e84263d55307	62	/* Private constants ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	63	/** @defgroup DAC_LL_Private_Constants DAC Private Constants
AnnaBridge	167:e84263d55307	64	* @{
AnnaBridge	167:e84263d55307	65	*/
AnnaBridge	167:e84263d55307	66
AnnaBridge	167:e84263d55307	67	/* Internal masks for DAC channels definition */
AnnaBridge	167:e84263d55307	68	/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
AnnaBridge	167:e84263d55307	69	/* - channel bits position into register CR */
AnnaBridge	167:e84263d55307	70	/* - channel bits position into register SWTRIG */
AnnaBridge	167:e84263d55307	71	/* - channel register offset of data holding register DHRx */
AnnaBridge	167:e84263d55307	72	/* - channel register offset of data output register DORx */
AnnaBridge	167:e84263d55307	73	#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
AnnaBridge	167:e84263d55307	74	#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
AnnaBridge	167:e84263d55307	75	#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET \| DAC_CR_CH2_BITOFFSET)
AnnaBridge	167:e84263d55307	76
AnnaBridge	167:e84263d55307	77	#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
AnnaBridge	167:e84263d55307	78	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	79	#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
AnnaBridge	167:e84263d55307	80	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 \| DAC_SWTR_CH2)
AnnaBridge	167:e84263d55307	81	#else
AnnaBridge	167:e84263d55307	82	#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
AnnaBridge	167:e84263d55307	83	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	84
AnnaBridge	167:e84263d55307	85	#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
AnnaBridge	167:e84263d55307	86	#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	167:e84263d55307	87	#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	167:e84263d55307	88	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	89	#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
AnnaBridge	167:e84263d55307	90	#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge	167:e84263d55307	91	#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge	167:e84263d55307	92	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	93	#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
AnnaBridge	167:e84263d55307	94	#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
AnnaBridge	167:e84263d55307	95	#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
AnnaBridge	167:e84263d55307	96	#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK \| DAC_REG_DHR12LX_REGOFFSET_MASK \| DAC_REG_DHR8RX_REGOFFSET_MASK)
AnnaBridge	167:e84263d55307	97
AnnaBridge	167:e84263d55307	98	#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
AnnaBridge	167:e84263d55307	99	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	100	#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
AnnaBridge	167:e84263d55307	101	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DOR2_REGOFFSET)
AnnaBridge	167:e84263d55307	102	#else
AnnaBridge	167:e84263d55307	103	#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET)
AnnaBridge	167:e84263d55307	104	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	105
AnnaBridge	167:e84263d55307	106	/* DAC registers bits positions */
AnnaBridge	167:e84263d55307	107	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	108	#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
AnnaBridge	167:e84263d55307	109	#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
AnnaBridge	167:e84263d55307	110	#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
AnnaBridge	167:e84263d55307	111	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	112
AnnaBridge	167:e84263d55307	113	/* Miscellaneous data */
AnnaBridge	167:e84263d55307	114	#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
AnnaBridge	167:e84263d55307	115
AnnaBridge	167:e84263d55307	116	/**
AnnaBridge	167:e84263d55307	117	* @}
AnnaBridge	167:e84263d55307	118	*/
AnnaBridge	167:e84263d55307	119
AnnaBridge	167:e84263d55307	120
AnnaBridge	167:e84263d55307	121	/* Private macros ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	122	/** @defgroup DAC_LL_Private_Macros DAC Private Macros
AnnaBridge	167:e84263d55307	123	* @{
AnnaBridge	167:e84263d55307	124	*/
AnnaBridge	167:e84263d55307	125
AnnaBridge	167:e84263d55307	126	/**
AnnaBridge	167:e84263d55307	127	* @brief Driver macro reserved for internal use: isolate bits with the
AnnaBridge	167:e84263d55307	128	* selected mask and shift them to the register LSB
AnnaBridge	167:e84263d55307	129	* (shift mask on register position bit 0).
AnnaBridge	167:e84263d55307	130	* @param __BITS__ Bits in register 32 bits
AnnaBridge	167:e84263d55307	131	* @param __MASK__ Mask in register 32 bits
AnnaBridge	167:e84263d55307	132	* @retval Bits in register 32 bits
AnnaBridge	167:e84263d55307	133	*/
AnnaBridge	167:e84263d55307	134	#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
AnnaBridge	167:e84263d55307	135	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
AnnaBridge	167:e84263d55307	136
AnnaBridge	167:e84263d55307	137	/**
AnnaBridge	167:e84263d55307	138	* @brief Driver macro reserved for internal use: set a pointer to
AnnaBridge	167:e84263d55307	139	* a register from a register basis from which an offset
AnnaBridge	167:e84263d55307	140	* is applied.
AnnaBridge	167:e84263d55307	141	* @param __REG__ Register basis from which the offset is applied.
AnnaBridge	167:e84263d55307	142	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
AnnaBridge	167:e84263d55307	143	* @retval Pointer to register address
AnnaBridge	167:e84263d55307	144	*/
AnnaBridge	167:e84263d55307	145	#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
AnnaBridge	167:e84263d55307	146	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
AnnaBridge	167:e84263d55307	147
AnnaBridge	167:e84263d55307	148	/**
AnnaBridge	167:e84263d55307	149	* @}
AnnaBridge	167:e84263d55307	150	*/
AnnaBridge	167:e84263d55307	151
AnnaBridge	167:e84263d55307	152
AnnaBridge	167:e84263d55307	153	/* Exported types ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	154	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	155	/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
AnnaBridge	167:e84263d55307	156	* @{
AnnaBridge	167:e84263d55307	157	*/
AnnaBridge	167:e84263d55307	158
AnnaBridge	167:e84263d55307	159	/**
AnnaBridge	167:e84263d55307	160	* @brief Structure definition of some features of DAC instance.
AnnaBridge	167:e84263d55307	161	*/
AnnaBridge	167:e84263d55307	162	typedef struct
AnnaBridge	167:e84263d55307	163	{
AnnaBridge	167:e84263d55307	164	uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
AnnaBridge	167:e84263d55307	165	This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
AnnaBridge	167:e84263d55307	166
AnnaBridge	167:e84263d55307	167	This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
AnnaBridge	167:e84263d55307	168
AnnaBridge	167:e84263d55307	169	uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge	167:e84263d55307	170	This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
AnnaBridge	167:e84263d55307	171
AnnaBridge	167:e84263d55307	172	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
AnnaBridge	167:e84263d55307	173
AnnaBridge	167:e84263d55307	174	uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge	167:e84263d55307	175	If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
AnnaBridge	167:e84263d55307	176	If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
AnnaBridge	167:e84263d55307	177	@note If waveform automatic generation mode is disabled, this parameter is discarded.
AnnaBridge	167:e84263d55307	178
AnnaBridge	167:e84263d55307	179	This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
AnnaBridge	167:e84263d55307	180
AnnaBridge	167:e84263d55307	181	uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
AnnaBridge	167:e84263d55307	182	This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
AnnaBridge	167:e84263d55307	183
AnnaBridge	167:e84263d55307	184	This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
AnnaBridge	167:e84263d55307	185
AnnaBridge	167:e84263d55307	186	} LL_DAC_InitTypeDef;
AnnaBridge	167:e84263d55307	187
AnnaBridge	167:e84263d55307	188	/**
AnnaBridge	167:e84263d55307	189	* @}
AnnaBridge	167:e84263d55307	190	*/
AnnaBridge	167:e84263d55307	191	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	192
AnnaBridge	167:e84263d55307	193	/* Exported constants --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	194	/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
AnnaBridge	167:e84263d55307	195	* @{
AnnaBridge	167:e84263d55307	196	*/
AnnaBridge	167:e84263d55307	197
AnnaBridge	167:e84263d55307	198	/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
AnnaBridge	167:e84263d55307	199	* @brief Flags defines which can be used with LL_DAC_ReadReg function
AnnaBridge	167:e84263d55307	200	* @{
AnnaBridge	167:e84263d55307	201	*/
AnnaBridge	167:e84263d55307	202	/* DAC channel 1 flags */
AnnaBridge	167:e84263d55307	203	#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /!< DAC channel 1 flag DMA underrun /
AnnaBridge	167:e84263d55307	204
AnnaBridge	167:e84263d55307	205	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	206	/* DAC channel 2 flags */
AnnaBridge	167:e84263d55307	207	#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /!< DAC channel 2 flag DMA underrun /
AnnaBridge	167:e84263d55307	208	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	209	/**
AnnaBridge	167:e84263d55307	210	* @}
AnnaBridge	167:e84263d55307	211	*/
AnnaBridge	167:e84263d55307	212
AnnaBridge	167:e84263d55307	213	/** @defgroup DAC_LL_EC_IT DAC interruptions
AnnaBridge	167:e84263d55307	214	* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
AnnaBridge	167:e84263d55307	215	* @{
AnnaBridge	167:e84263d55307	216	*/
AnnaBridge	167:e84263d55307	217	#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /!< DAC channel 1 interruption DMA underrun /
AnnaBridge	167:e84263d55307	218	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	219	#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /!< DAC channel 2 interruption DMA underrun /
AnnaBridge	167:e84263d55307	220	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	221	/**
AnnaBridge	167:e84263d55307	222	* @}
AnnaBridge	167:e84263d55307	223	*/
AnnaBridge	167:e84263d55307	224
AnnaBridge	167:e84263d55307	225	/** @defgroup DAC_LL_EC_CHANNEL DAC channels
AnnaBridge	167:e84263d55307	226	* @{
AnnaBridge	167:e84263d55307	227	*/
AnnaBridge	167:e84263d55307	228	#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET \| DAC_REG_DHR12R1_REGOFFSET \| DAC_REG_DHR12L1_REGOFFSET \| DAC_REG_DHR8R1_REGOFFSET \| DAC_CR_CH1_BITOFFSET \| DAC_SWTR_CH1) /!< DAC channel 1 /
AnnaBridge	167:e84263d55307	229	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	230	#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET \| DAC_REG_DHR12R2_REGOFFSET \| DAC_REG_DHR12L2_REGOFFSET \| DAC_REG_DHR8R2_REGOFFSET \| DAC_CR_CH2_BITOFFSET \| DAC_SWTR_CH2) /!< DAC channel 2 /
AnnaBridge	167:e84263d55307	231	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	232	/**
AnnaBridge	167:e84263d55307	233	* @}
AnnaBridge	167:e84263d55307	234	*/
AnnaBridge	167:e84263d55307	235
AnnaBridge	167:e84263d55307	236	/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
AnnaBridge	167:e84263d55307	237	* @{
AnnaBridge	167:e84263d55307	238	*/
AnnaBridge	167:e84263d55307	239	#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger internal (SW start) /
AnnaBridge	167:e84263d55307	240	#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /!< DAC channel conversion trigger from external IP: TIM2 TRGO. /
AnnaBridge	167:e84263d55307	241	#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM8 TRGO. /
AnnaBridge	167:e84263d55307	242	#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM4 TRGO. /
AnnaBridge	167:e84263d55307	243	#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /!< DAC channel conversion trigger from external IP: TIM6 TRGO. /
AnnaBridge	167:e84263d55307	244	#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: TIM7 TRGO. /
AnnaBridge	167:e84263d55307	245	#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 \| DAC_CR_TSEL1_0) /!< DAC channel conversion trigger from external IP: TIM5 TRGO. /
AnnaBridge	167:e84263d55307	246	#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 \| DAC_CR_TSEL1_1 ) /!< DAC channel conversion trigger from external IP: external interrupt line 9. /
AnnaBridge	167:e84263d55307	247	/**
AnnaBridge	167:e84263d55307	248	* @}
AnnaBridge	167:e84263d55307	249	*/
AnnaBridge	167:e84263d55307	250
AnnaBridge	167:e84263d55307	251	/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
AnnaBridge	167:e84263d55307	252	* @{
AnnaBridge	167:e84263d55307	253	*/
AnnaBridge	167:e84263d55307	254	#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /!< DAC channel wave auto generation mode disabled. /
AnnaBridge	167:e84263d55307	255	#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /!< DAC channel wave auto generation mode enabled, set generated noise waveform. /
AnnaBridge	167:e84263d55307	256	#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /!< DAC channel wave auto generation mode enabled, set generated triangle waveform. /
AnnaBridge	167:e84263d55307	257	/**
AnnaBridge	167:e84263d55307	258	* @}
AnnaBridge	167:e84263d55307	259	*/
AnnaBridge	167:e84263d55307	260
AnnaBridge	167:e84263d55307	261	/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
AnnaBridge	167:e84263d55307	262	* @{
AnnaBridge	167:e84263d55307	263	*/
AnnaBridge	167:e84263d55307	264	#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel /
AnnaBridge	167:e84263d55307	265	#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	266	#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	267	#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	268	#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	269	#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	270	#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	271	#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	272	#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	273	#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	274	#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	275	#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel /
AnnaBridge	167:e84263d55307	276	/**
AnnaBridge	167:e84263d55307	277	* @}
AnnaBridge	167:e84263d55307	278	*/
AnnaBridge	167:e84263d55307	279
AnnaBridge	167:e84263d55307	280	/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
AnnaBridge	167:e84263d55307	281	* @{
AnnaBridge	167:e84263d55307	282	*/
AnnaBridge	167:e84263d55307	283	#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	284	#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	285	#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	286	#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	287	#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	288	#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	289	#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	290	#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	291	#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	292	#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	293	#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 ) /!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	294	#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 \| DAC_CR_MAMP1_1 \| DAC_CR_MAMP1_0) /!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel /
AnnaBridge	167:e84263d55307	295	/**
AnnaBridge	167:e84263d55307	296	* @}
AnnaBridge	167:e84263d55307	297	*/
AnnaBridge	167:e84263d55307	298
AnnaBridge	167:e84263d55307	299	/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
AnnaBridge	167:e84263d55307	300	* @{
AnnaBridge	167:e84263d55307	301	*/
AnnaBridge	167:e84263d55307	302	#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption /
AnnaBridge	167:e84263d55307	303	#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption /
AnnaBridge	167:e84263d55307	304	/**
AnnaBridge	167:e84263d55307	305	* @}
AnnaBridge	167:e84263d55307	306	*/
AnnaBridge	167:e84263d55307	307
AnnaBridge	167:e84263d55307	308
AnnaBridge	167:e84263d55307	309	/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
AnnaBridge	167:e84263d55307	310	* @{
AnnaBridge	167:e84263d55307	311	*/
AnnaBridge	167:e84263d55307	312	#define LL_DAC_RESOLUTION_12B 0x00000000U /!< DAC channel resolution 12 bits /
AnnaBridge	167:e84263d55307	313	#define LL_DAC_RESOLUTION_8B 0x00000002U /!< DAC channel resolution 8 bits /
AnnaBridge	167:e84263d55307	314	/**
AnnaBridge	167:e84263d55307	315	* @}
AnnaBridge	167:e84263d55307	316	*/
AnnaBridge	167:e84263d55307	317
AnnaBridge	167:e84263d55307	318	/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
AnnaBridge	167:e84263d55307	319	* @{
AnnaBridge	167:e84263d55307	320	*/
AnnaBridge	167:e84263d55307	321	/* List of DAC registers intended to be used (most commonly) with */
AnnaBridge	167:e84263d55307	322	/* DMA transfer. */
AnnaBridge	167:e84263d55307	323	/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
AnnaBridge	167:e84263d55307	324	#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /!< DAC channel data holding register 12 bits right aligned /
AnnaBridge	167:e84263d55307	325	#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /!< DAC channel data holding register 12 bits left aligned /
AnnaBridge	167:e84263d55307	326	#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /!< DAC channel data holding register 8 bits right aligned /
AnnaBridge	167:e84263d55307	327	/**
AnnaBridge	167:e84263d55307	328	* @}
AnnaBridge	167:e84263d55307	329	*/
AnnaBridge	167:e84263d55307	330
AnnaBridge	167:e84263d55307	331	/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
AnnaBridge	167:e84263d55307	332	* @note Only DAC IP HW delays are defined in DAC LL driver driver,
AnnaBridge	167:e84263d55307	333	* not timeout values.
AnnaBridge	167:e84263d55307	334	* For details on delays values, refer to descriptions in source code
AnnaBridge	167:e84263d55307	335	* above each literal definition.
AnnaBridge	167:e84263d55307	336	* @{
AnnaBridge	167:e84263d55307	337	*/
AnnaBridge	167:e84263d55307	338
AnnaBridge	167:e84263d55307	339	/* Delay for DAC channel voltage settling time from DAC channel startup */
AnnaBridge	167:e84263d55307	340	/* (transition from disable to enable). */
AnnaBridge	167:e84263d55307	341	/* Note: DAC channel startup time depends on board application environment: */
AnnaBridge	167:e84263d55307	342	/* impedance connected to DAC channel output. */
AnnaBridge	167:e84263d55307	343	/* The delay below is specified under conditions: */
AnnaBridge	167:e84263d55307	344	/* - voltage maximum transition (lowest to highest value) */
AnnaBridge	167:e84263d55307	345	/* - until voltage reaches final value +-1LSB */
AnnaBridge	167:e84263d55307	346	/* - DAC channel output buffer enabled */
AnnaBridge	167:e84263d55307	347	/* - load impedance of 5kOhm (min), 50pF (max) */
AnnaBridge	167:e84263d55307	348	/* Literal set to maximum value (refer to device datasheet, */
AnnaBridge	167:e84263d55307	349	/* parameter "tWAKEUP"). */
AnnaBridge	167:e84263d55307	350	/* Unit: us */
AnnaBridge	167:e84263d55307	351	#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) /
AnnaBridge	167:e84263d55307	352
AnnaBridge	167:e84263d55307	353	/* Delay for DAC channel voltage settling time. */
AnnaBridge	167:e84263d55307	354	/* Note: DAC channel startup time depends on board application environment: */
AnnaBridge	167:e84263d55307	355	/* impedance connected to DAC channel output. */
AnnaBridge	167:e84263d55307	356	/* The delay below is specified under conditions: */
AnnaBridge	167:e84263d55307	357	/* - voltage maximum transition (lowest to highest value) */
AnnaBridge	167:e84263d55307	358	/* - until voltage reaches final value +-1LSB */
AnnaBridge	167:e84263d55307	359	/* - DAC channel output buffer enabled */
AnnaBridge	167:e84263d55307	360	/* - load impedance of 5kOhm min, 50pF max */
AnnaBridge	167:e84263d55307	361	/* Literal set to maximum value (refer to device datasheet, */
AnnaBridge	167:e84263d55307	362	/* parameter "tSETTLING"). */
AnnaBridge	167:e84263d55307	363	/* Unit: us */
AnnaBridge	167:e84263d55307	364	#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /!< Delay for DAC channel voltage settling time /
AnnaBridge	167:e84263d55307	365	/**
AnnaBridge	167:e84263d55307	366	* @}
AnnaBridge	167:e84263d55307	367	*/
AnnaBridge	167:e84263d55307	368
AnnaBridge	167:e84263d55307	369	/**
AnnaBridge	167:e84263d55307	370	* @}
AnnaBridge	167:e84263d55307	371	*/
AnnaBridge	167:e84263d55307	372
AnnaBridge	167:e84263d55307	373	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	374	/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
AnnaBridge	167:e84263d55307	375	* @{
AnnaBridge	167:e84263d55307	376	*/
AnnaBridge	167:e84263d55307	377
AnnaBridge	167:e84263d55307	378	/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
AnnaBridge	167:e84263d55307	379	* @{
AnnaBridge	167:e84263d55307	380	*/
AnnaBridge	167:e84263d55307	381
AnnaBridge	167:e84263d55307	382	/**
AnnaBridge	167:e84263d55307	383	* @brief Write a value in DAC register
AnnaBridge	167:e84263d55307	384	* @param __INSTANCE__ DAC Instance
AnnaBridge	167:e84263d55307	385	* @param __REG__ Register to be written
AnnaBridge	167:e84263d55307	386	* @param __VALUE__ Value to be written in the register
AnnaBridge	167:e84263d55307	387	* @retval None
AnnaBridge	167:e84263d55307	388	*/
AnnaBridge	167:e84263d55307	389	#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	167:e84263d55307	390
AnnaBridge	167:e84263d55307	391	/**
AnnaBridge	167:e84263d55307	392	* @brief Read a value in DAC register
AnnaBridge	167:e84263d55307	393	* @param __INSTANCE__ DAC Instance
AnnaBridge	167:e84263d55307	394	* @param __REG__ Register to be read
AnnaBridge	167:e84263d55307	395	* @retval Register value
AnnaBridge	167:e84263d55307	396	*/
AnnaBridge	167:e84263d55307	397	#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	167:e84263d55307	398
AnnaBridge	167:e84263d55307	399	/**
AnnaBridge	167:e84263d55307	400	* @}
AnnaBridge	167:e84263d55307	401	*/
AnnaBridge	167:e84263d55307	402
AnnaBridge	167:e84263d55307	403	/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
AnnaBridge	167:e84263d55307	404	* @{
AnnaBridge	167:e84263d55307	405	*/
AnnaBridge	167:e84263d55307	406
AnnaBridge	167:e84263d55307	407	/**
AnnaBridge	167:e84263d55307	408	* @brief Helper macro to get DAC channel number in decimal format
AnnaBridge	167:e84263d55307	409	* from literals LL_DAC_CHANNEL_x.
AnnaBridge	167:e84263d55307	410	* Example:
AnnaBridge	167:e84263d55307	411	* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
AnnaBridge	167:e84263d55307	412	* will return decimal number "1".
AnnaBridge	167:e84263d55307	413	* @note The input can be a value from functions where a channel
AnnaBridge	167:e84263d55307	414	* number is returned.
AnnaBridge	167:e84263d55307	415	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	416	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	417	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	418	*
AnnaBridge	167:e84263d55307	419	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	420	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	421	* @retval 1...2 (value "2" depending on DAC channel 2 availability)
AnnaBridge	167:e84263d55307	422	*/
AnnaBridge	167:e84263d55307	423	#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
AnnaBridge	167:e84263d55307	424	((__CHANNEL__) & DAC_SWTR_CHX_MASK)
AnnaBridge	167:e84263d55307	425
AnnaBridge	167:e84263d55307	426	/**
AnnaBridge	167:e84263d55307	427	* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
AnnaBridge	167:e84263d55307	428	* from number in decimal format.
AnnaBridge	167:e84263d55307	429	* Example:
AnnaBridge	167:e84263d55307	430	* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
AnnaBridge	167:e84263d55307	431	* will return a data equivalent to "LL_DAC_CHANNEL_1".
AnnaBridge	167:e84263d55307	432	* @note If the input parameter does not correspond to a DAC channel,
AnnaBridge	167:e84263d55307	433	* this macro returns value '0'.
AnnaBridge	167:e84263d55307	434	* @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability)
AnnaBridge	167:e84263d55307	435	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	436	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	437	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	438	*
AnnaBridge	167:e84263d55307	439	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	440	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	441	*/
AnnaBridge	167:e84263d55307	442	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	443	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
AnnaBridge	167:e84263d55307	444	(((__DECIMAL_NB__) == 1U) \
AnnaBridge	167:e84263d55307	445	? ( \
AnnaBridge	167:e84263d55307	446	LL_DAC_CHANNEL_1 \
AnnaBridge	167:e84263d55307	447	) \
AnnaBridge	167:e84263d55307	448	: \
AnnaBridge	167:e84263d55307	449	(((__DECIMAL_NB__) == 2U) \
AnnaBridge	167:e84263d55307	450	? ( \
AnnaBridge	167:e84263d55307	451	LL_DAC_CHANNEL_2 \
AnnaBridge	167:e84263d55307	452	) \
AnnaBridge	167:e84263d55307	453	: \
AnnaBridge	167:e84263d55307	454	( \
AnnaBridge	167:e84263d55307	455	0 \
AnnaBridge	167:e84263d55307	456	) \
AnnaBridge	167:e84263d55307	457	) \
AnnaBridge	167:e84263d55307	458	)
AnnaBridge	167:e84263d55307	459	#else
AnnaBridge	167:e84263d55307	460	#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
AnnaBridge	167:e84263d55307	461	(((__DECIMAL_NB__) == 1U) \
AnnaBridge	167:e84263d55307	462	? ( \
AnnaBridge	167:e84263d55307	463	LL_DAC_CHANNEL_1 \
AnnaBridge	167:e84263d55307	464	) \
AnnaBridge	167:e84263d55307	465	: \
AnnaBridge	167:e84263d55307	466	( \
AnnaBridge	167:e84263d55307	467	0 \
AnnaBridge	167:e84263d55307	468	) \
AnnaBridge	167:e84263d55307	469	)
AnnaBridge	167:e84263d55307	470	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	471
AnnaBridge	167:e84263d55307	472	/**
AnnaBridge	167:e84263d55307	473	* @brief Helper macro to define the DAC conversion data full-scale digital
AnnaBridge	167:e84263d55307	474	* value corresponding to the selected DAC resolution.
AnnaBridge	167:e84263d55307	475	* @note DAC conversion data full-scale corresponds to voltage range
AnnaBridge	167:e84263d55307	476	* determined by analog voltage references Vref+ and Vref-
AnnaBridge	167:e84263d55307	477	* (refer to reference manual).
AnnaBridge	167:e84263d55307	478	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	479	* @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge	167:e84263d55307	480	* @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge	167:e84263d55307	481	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
AnnaBridge	167:e84263d55307	482	*/
AnnaBridge	167:e84263d55307	483	#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge	167:e84263d55307	484	((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
AnnaBridge	167:e84263d55307	485
AnnaBridge	167:e84263d55307	486	/**
AnnaBridge	167:e84263d55307	487	* @brief Helper macro to calculate the DAC conversion data (unit: digital
AnnaBridge	167:e84263d55307	488	* value) corresponding to a voltage (unit: mVolt).
AnnaBridge	167:e84263d55307	489	* @note This helper macro is intended to provide input data in voltage
AnnaBridge	167:e84263d55307	490	* rather than digital value,
AnnaBridge	167:e84263d55307	491	* to be used with LL DAC functions such as
AnnaBridge	167:e84263d55307	492	* @ref LL_DAC_ConvertData12RightAligned().
AnnaBridge	167:e84263d55307	493	* @note Analog reference voltage (Vref+) must be either known from
AnnaBridge	167:e84263d55307	494	* user board environment or can be calculated using ADC measurement
AnnaBridge	167:e84263d55307	495	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
AnnaBridge	167:e84263d55307	496	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
AnnaBridge	167:e84263d55307	497	* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
AnnaBridge	167:e84263d55307	498	* (unit: mVolt).
AnnaBridge	167:e84263d55307	499	* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	500	* @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge	167:e84263d55307	501	* @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge	167:e84263d55307	502	* @retval DAC conversion data (unit: digital value)
AnnaBridge	167:e84263d55307	503	*/
AnnaBridge	167:e84263d55307	504	#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
AnnaBridge	167:e84263d55307	505	__DAC_VOLTAGE__,\
AnnaBridge	167:e84263d55307	506	__DAC_RESOLUTION__) \
AnnaBridge	167:e84263d55307	507	((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge	167:e84263d55307	508	/ (__VREFANALOG_VOLTAGE__) \
AnnaBridge	167:e84263d55307	509	)
AnnaBridge	167:e84263d55307	510
AnnaBridge	167:e84263d55307	511	/**
AnnaBridge	167:e84263d55307	512	* @}
AnnaBridge	167:e84263d55307	513	*/
AnnaBridge	167:e84263d55307	514
AnnaBridge	167:e84263d55307	515	/**
AnnaBridge	167:e84263d55307	516	* @}
AnnaBridge	167:e84263d55307	517	*/
AnnaBridge	167:e84263d55307	518
AnnaBridge	167:e84263d55307	519
AnnaBridge	167:e84263d55307	520	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	521	/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
AnnaBridge	167:e84263d55307	522	* @{
AnnaBridge	167:e84263d55307	523	*/
AnnaBridge	167:e84263d55307	524	/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
AnnaBridge	167:e84263d55307	525	* @{
AnnaBridge	167:e84263d55307	526	*/
AnnaBridge	167:e84263d55307	527
AnnaBridge	167:e84263d55307	528	/**
AnnaBridge	167:e84263d55307	529	* @brief Set the conversion trigger source for the selected DAC channel.
AnnaBridge	167:e84263d55307	530	* @note For conversion trigger source to be effective, DAC trigger
AnnaBridge	167:e84263d55307	531	* must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge	167:e84263d55307	532	* @note To set conversion trigger source, DAC channel must be disabled.
AnnaBridge	167:e84263d55307	533	* Otherwise, the setting is discarded.
AnnaBridge	167:e84263d55307	534	* @note Availability of parameters of trigger sources from timer
AnnaBridge	167:e84263d55307	535	* depends on timers availability on the selected device.
AnnaBridge	167:e84263d55307	536	* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
AnnaBridge	167:e84263d55307	537	* CR TSEL2 LL_DAC_SetTriggerSource
AnnaBridge	167:e84263d55307	538	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	539	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	540	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	541	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	542	*
AnnaBridge	167:e84263d55307	543	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	544	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	545	* @param TriggerSource This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	546	* @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge	167:e84263d55307	547	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
AnnaBridge	167:e84263d55307	548	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge	167:e84263d55307	549	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge	167:e84263d55307	550	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
AnnaBridge	167:e84263d55307	551	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
AnnaBridge	167:e84263d55307	552	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge	167:e84263d55307	553	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
AnnaBridge	167:e84263d55307	554	* @retval None
AnnaBridge	167:e84263d55307	555	*/
AnnaBridge	167:e84263d55307	556	__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
AnnaBridge	167:e84263d55307	557	{
AnnaBridge	167:e84263d55307	558	MODIFY_REG(DACx->CR,
AnnaBridge	167:e84263d55307	559	DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	167:e84263d55307	560	TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	561	}
AnnaBridge	167:e84263d55307	562
AnnaBridge	167:e84263d55307	563	/**
AnnaBridge	167:e84263d55307	564	* @brief Get the conversion trigger source for the selected DAC channel.
AnnaBridge	167:e84263d55307	565	* @note For conversion trigger source to be effective, DAC trigger
AnnaBridge	167:e84263d55307	566	* must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge	167:e84263d55307	567	* @note Availability of parameters of trigger sources from timer
AnnaBridge	167:e84263d55307	568	* depends on timers availability on the selected device.
AnnaBridge	167:e84263d55307	569	* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
AnnaBridge	167:e84263d55307	570	* CR TSEL2 LL_DAC_GetTriggerSource
AnnaBridge	167:e84263d55307	571	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	572	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	573	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	574	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	575	*
AnnaBridge	167:e84263d55307	576	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	577	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	578	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	579	* @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge	167:e84263d55307	580	* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
AnnaBridge	167:e84263d55307	581	* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge	167:e84263d55307	582	* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge	167:e84263d55307	583	* @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
AnnaBridge	167:e84263d55307	584	* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
AnnaBridge	167:e84263d55307	585	* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge	167:e84263d55307	586	* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
AnnaBridge	167:e84263d55307	587	*/
AnnaBridge	167:e84263d55307	588	__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	589	{
AnnaBridge	167:e84263d55307	590	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	167:e84263d55307	591	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	167:e84263d55307	592	);
AnnaBridge	167:e84263d55307	593	}
AnnaBridge	167:e84263d55307	594
AnnaBridge	167:e84263d55307	595	/**
AnnaBridge	167:e84263d55307	596	* @brief Set the waveform automatic generation mode
AnnaBridge	167:e84263d55307	597	* for the selected DAC channel.
AnnaBridge	167:e84263d55307	598	* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
AnnaBridge	167:e84263d55307	599	* CR WAVE2 LL_DAC_SetWaveAutoGeneration
AnnaBridge	167:e84263d55307	600	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	601	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	602	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	603	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	604	*
AnnaBridge	167:e84263d55307	605	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	606	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	607	* @param WaveAutoGeneration This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	608	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge	167:e84263d55307	609	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge	167:e84263d55307	610	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge	167:e84263d55307	611	* @retval None
AnnaBridge	167:e84263d55307	612	*/
AnnaBridge	167:e84263d55307	613	__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
AnnaBridge	167:e84263d55307	614	{
AnnaBridge	167:e84263d55307	615	MODIFY_REG(DACx->CR,
AnnaBridge	167:e84263d55307	616	DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	167:e84263d55307	617	WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	618	}
AnnaBridge	167:e84263d55307	619
AnnaBridge	167:e84263d55307	620	/**
AnnaBridge	167:e84263d55307	621	* @brief Get the waveform automatic generation mode
AnnaBridge	167:e84263d55307	622	* for the selected DAC channel.
AnnaBridge	167:e84263d55307	623	* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
AnnaBridge	167:e84263d55307	624	* CR WAVE2 LL_DAC_GetWaveAutoGeneration
AnnaBridge	167:e84263d55307	625	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	626	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	627	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	628	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	629	*
AnnaBridge	167:e84263d55307	630	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	631	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	632	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	633	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge	167:e84263d55307	634	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge	167:e84263d55307	635	* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge	167:e84263d55307	636	*/
AnnaBridge	167:e84263d55307	637	__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	638	{
AnnaBridge	167:e84263d55307	639	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	167:e84263d55307	640	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	167:e84263d55307	641	);
AnnaBridge	167:e84263d55307	642	}
AnnaBridge	167:e84263d55307	643
AnnaBridge	167:e84263d55307	644	/**
AnnaBridge	167:e84263d55307	645	* @brief Set the noise waveform generation for the selected DAC channel:
AnnaBridge	167:e84263d55307	646	* Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge	167:e84263d55307	647	* @note For wave generation to be effective, DAC channel
AnnaBridge	167:e84263d55307	648	* wave generation mode must be enabled using
AnnaBridge	167:e84263d55307	649	* function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge	167:e84263d55307	650	* @note This setting can be set when the selected DAC channel is disabled
AnnaBridge	167:e84263d55307	651	* (otherwise, the setting operation is ignored).
AnnaBridge	167:e84263d55307	652	* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
AnnaBridge	167:e84263d55307	653	* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
AnnaBridge	167:e84263d55307	654	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	655	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	656	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	657	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	658	*
AnnaBridge	167:e84263d55307	659	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	660	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	661	* @param NoiseLFSRMask This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	662	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge	167:e84263d55307	663	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge	167:e84263d55307	664	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge	167:e84263d55307	665	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge	167:e84263d55307	666	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge	167:e84263d55307	667	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge	167:e84263d55307	668	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge	167:e84263d55307	669	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge	167:e84263d55307	670	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge	167:e84263d55307	671	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge	167:e84263d55307	672	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge	167:e84263d55307	673	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge	167:e84263d55307	674	* @retval None
AnnaBridge	167:e84263d55307	675	*/
AnnaBridge	167:e84263d55307	676	__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
AnnaBridge	167:e84263d55307	677	{
AnnaBridge	167:e84263d55307	678	MODIFY_REG(DACx->CR,
AnnaBridge	167:e84263d55307	679	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	167:e84263d55307	680	NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	681	}
AnnaBridge	167:e84263d55307	682
AnnaBridge	167:e84263d55307	683	/**
AnnaBridge	167:e84263d55307	684	* @brief Set the noise waveform generation for the selected DAC channel:
AnnaBridge	167:e84263d55307	685	* Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge	167:e84263d55307	686	* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
AnnaBridge	167:e84263d55307	687	* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
AnnaBridge	167:e84263d55307	688	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	689	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	690	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	691	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	692	*
AnnaBridge	167:e84263d55307	693	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	694	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	695	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	696	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge	167:e84263d55307	697	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge	167:e84263d55307	698	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge	167:e84263d55307	699	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge	167:e84263d55307	700	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge	167:e84263d55307	701	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge	167:e84263d55307	702	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge	167:e84263d55307	703	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge	167:e84263d55307	704	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge	167:e84263d55307	705	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge	167:e84263d55307	706	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge	167:e84263d55307	707	* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge	167:e84263d55307	708	*/
AnnaBridge	167:e84263d55307	709	__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	710	{
AnnaBridge	167:e84263d55307	711	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	167:e84263d55307	712	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	167:e84263d55307	713	);
AnnaBridge	167:e84263d55307	714	}
AnnaBridge	167:e84263d55307	715
AnnaBridge	167:e84263d55307	716	/**
AnnaBridge	167:e84263d55307	717	* @brief Set the triangle waveform generation for the selected DAC channel:
AnnaBridge	167:e84263d55307	718	* triangle mode and amplitude.
AnnaBridge	167:e84263d55307	719	* @note For wave generation to be effective, DAC channel
AnnaBridge	167:e84263d55307	720	* wave generation mode must be enabled using
AnnaBridge	167:e84263d55307	721	* function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge	167:e84263d55307	722	* @note This setting can be set when the selected DAC channel is disabled
AnnaBridge	167:e84263d55307	723	* (otherwise, the setting operation is ignored).
AnnaBridge	167:e84263d55307	724	* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
AnnaBridge	167:e84263d55307	725	* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
AnnaBridge	167:e84263d55307	726	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	727	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	728	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	729	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	730	*
AnnaBridge	167:e84263d55307	731	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	732	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	733	* @param TriangleAmplitude This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	734	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge	167:e84263d55307	735	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge	167:e84263d55307	736	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge	167:e84263d55307	737	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge	167:e84263d55307	738	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge	167:e84263d55307	739	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge	167:e84263d55307	740	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge	167:e84263d55307	741	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge	167:e84263d55307	742	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge	167:e84263d55307	743	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge	167:e84263d55307	744	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge	167:e84263d55307	745	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge	167:e84263d55307	746	* @retval None
AnnaBridge	167:e84263d55307	747	*/
AnnaBridge	167:e84263d55307	748	__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
AnnaBridge	167:e84263d55307	749	{
AnnaBridge	167:e84263d55307	750	MODIFY_REG(DACx->CR,
AnnaBridge	167:e84263d55307	751	DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	167:e84263d55307	752	TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	753	}
AnnaBridge	167:e84263d55307	754
AnnaBridge	167:e84263d55307	755	/**
AnnaBridge	167:e84263d55307	756	* @brief Set the triangle waveform generation for the selected DAC channel:
AnnaBridge	167:e84263d55307	757	* triangle mode and amplitude.
AnnaBridge	167:e84263d55307	758	* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
AnnaBridge	167:e84263d55307	759	* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
AnnaBridge	167:e84263d55307	760	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	761	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	762	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	763	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	764	*
AnnaBridge	167:e84263d55307	765	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	766	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	767	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	768	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge	167:e84263d55307	769	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge	167:e84263d55307	770	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge	167:e84263d55307	771	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge	167:e84263d55307	772	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge	167:e84263d55307	773	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge	167:e84263d55307	774	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge	167:e84263d55307	775	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge	167:e84263d55307	776	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge	167:e84263d55307	777	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge	167:e84263d55307	778	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge	167:e84263d55307	779	* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge	167:e84263d55307	780	*/
AnnaBridge	167:e84263d55307	781	__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	782	{
AnnaBridge	167:e84263d55307	783	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	167:e84263d55307	784	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	167:e84263d55307	785	);
AnnaBridge	167:e84263d55307	786	}
AnnaBridge	167:e84263d55307	787
AnnaBridge	167:e84263d55307	788	/**
AnnaBridge	167:e84263d55307	789	* @brief Set the output buffer for the selected DAC channel.
AnnaBridge	167:e84263d55307	790	* @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
AnnaBridge	167:e84263d55307	791	* CR BOFF2 LL_DAC_SetOutputBuffer
AnnaBridge	167:e84263d55307	792	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	793	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	794	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	795	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	796	*
AnnaBridge	167:e84263d55307	797	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	798	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	799	* @param OutputBuffer This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	800	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	167:e84263d55307	801	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	167:e84263d55307	802	* @retval None
AnnaBridge	167:e84263d55307	803	*/
AnnaBridge	167:e84263d55307	804	__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
AnnaBridge	167:e84263d55307	805	{
AnnaBridge	167:e84263d55307	806	MODIFY_REG(DACx->CR,
AnnaBridge	167:e84263d55307	807	DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge	167:e84263d55307	808	OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	809	}
AnnaBridge	167:e84263d55307	810
AnnaBridge	167:e84263d55307	811	/**
AnnaBridge	167:e84263d55307	812	* @brief Get the output buffer state for the selected DAC channel.
AnnaBridge	167:e84263d55307	813	* @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
AnnaBridge	167:e84263d55307	814	* CR BOFF2 LL_DAC_GetOutputBuffer
AnnaBridge	167:e84263d55307	815	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	816	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	817	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	818	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	819	*
AnnaBridge	167:e84263d55307	820	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	821	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	822	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	823	* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge	167:e84263d55307	824	* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge	167:e84263d55307	825	*/
AnnaBridge	167:e84263d55307	826	__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	827	{
AnnaBridge	167:e84263d55307	828	return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	167:e84263d55307	829	>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge	167:e84263d55307	830	);
AnnaBridge	167:e84263d55307	831	}
AnnaBridge	167:e84263d55307	832
AnnaBridge	167:e84263d55307	833	/**
AnnaBridge	167:e84263d55307	834	* @}
AnnaBridge	167:e84263d55307	835	*/
AnnaBridge	167:e84263d55307	836
AnnaBridge	167:e84263d55307	837	/** @defgroup DAC_LL_EF_DMA_Management DMA Management
AnnaBridge	167:e84263d55307	838	* @{
AnnaBridge	167:e84263d55307	839	*/
AnnaBridge	167:e84263d55307	840
AnnaBridge	167:e84263d55307	841	/**
AnnaBridge	167:e84263d55307	842	* @brief Enable DAC DMA transfer request of the selected channel.
AnnaBridge	167:e84263d55307	843	* @note To configure DMA source address (peripheral address),
AnnaBridge	167:e84263d55307	844	* use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge	167:e84263d55307	845	* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
AnnaBridge	167:e84263d55307	846	* CR DMAEN2 LL_DAC_EnableDMAReq
AnnaBridge	167:e84263d55307	847	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	848	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	849	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	850	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	851	*
AnnaBridge	167:e84263d55307	852	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	853	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	854	* @retval None
AnnaBridge	167:e84263d55307	855	*/
AnnaBridge	167:e84263d55307	856	__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	857	{
AnnaBridge	167:e84263d55307	858	SET_BIT(DACx->CR,
AnnaBridge	167:e84263d55307	859	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	860	}
AnnaBridge	167:e84263d55307	861
AnnaBridge	167:e84263d55307	862	/**
AnnaBridge	167:e84263d55307	863	* @brief Disable DAC DMA transfer request of the selected channel.
AnnaBridge	167:e84263d55307	864	* @note To configure DMA source address (peripheral address),
AnnaBridge	167:e84263d55307	865	* use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge	167:e84263d55307	866	* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
AnnaBridge	167:e84263d55307	867	* CR DMAEN2 LL_DAC_DisableDMAReq
AnnaBridge	167:e84263d55307	868	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	869	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	870	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	871	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	872	*
AnnaBridge	167:e84263d55307	873	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	874	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	875	* @retval None
AnnaBridge	167:e84263d55307	876	*/
AnnaBridge	167:e84263d55307	877	__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	878	{
AnnaBridge	167:e84263d55307	879	CLEAR_BIT(DACx->CR,
AnnaBridge	167:e84263d55307	880	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	881	}
AnnaBridge	167:e84263d55307	882
AnnaBridge	167:e84263d55307	883	/**
AnnaBridge	167:e84263d55307	884	* @brief Get DAC DMA transfer request state of the selected channel.
AnnaBridge	167:e84263d55307	885	* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
AnnaBridge	167:e84263d55307	886	* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
AnnaBridge	167:e84263d55307	887	* CR DMAEN2 LL_DAC_IsDMAReqEnabled
AnnaBridge	167:e84263d55307	888	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	889	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	890	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	891	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	892	*
AnnaBridge	167:e84263d55307	893	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	894	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	895	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	896	*/
AnnaBridge	167:e84263d55307	897	__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	898	{
AnnaBridge	167:e84263d55307	899	return (READ_BIT(DACx->CR,
AnnaBridge	167:e84263d55307	900	DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	167:e84263d55307	901	== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge	167:e84263d55307	902	}
AnnaBridge	167:e84263d55307	903
AnnaBridge	167:e84263d55307	904	/**
AnnaBridge	167:e84263d55307	905	* @brief Function to help to configure DMA transfer to DAC: retrieve the
AnnaBridge	167:e84263d55307	906	* DAC register address from DAC instance and a list of DAC registers
AnnaBridge	167:e84263d55307	907	* intended to be used (most commonly) with DMA transfer.
AnnaBridge	167:e84263d55307	908	* @note These DAC registers are data holding registers:
AnnaBridge	167:e84263d55307	909	* when DAC conversion is requested, DAC generates a DMA transfer
AnnaBridge	167:e84263d55307	910	* request to have data available in DAC data holding registers.
AnnaBridge	167:e84263d55307	911	* @note This macro is intended to be used with LL DMA driver, refer to
AnnaBridge	167:e84263d55307	912	* function "LL_DMA_ConfigAddresses()".
AnnaBridge	167:e84263d55307	913	* Example:
AnnaBridge	167:e84263d55307	914	* LL_DMA_ConfigAddresses(DMA1,
AnnaBridge	167:e84263d55307	915	* LL_DMA_CHANNEL_1,
AnnaBridge	167:e84263d55307	916	* (uint32_t)&< array or variable >,
AnnaBridge	167:e84263d55307	917	* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
AnnaBridge	167:e84263d55307	918	* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
AnnaBridge	167:e84263d55307	919	* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	167:e84263d55307	920	* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	167:e84263d55307	921	* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	167:e84263d55307	922	* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	167:e84263d55307	923	* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge	167:e84263d55307	924	* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
AnnaBridge	167:e84263d55307	925	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	926	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	927	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	928	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	929	*
AnnaBridge	167:e84263d55307	930	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	931	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	932	* @param Register This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	933	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
AnnaBridge	167:e84263d55307	934	* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
AnnaBridge	167:e84263d55307	935	* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
AnnaBridge	167:e84263d55307	936	* @retval DAC register address
AnnaBridge	167:e84263d55307	937	*/
AnnaBridge	167:e84263d55307	938	__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
AnnaBridge	167:e84263d55307	939	{
AnnaBridge	167:e84263d55307	940	/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
AnnaBridge	167:e84263d55307	941	/* DAC channel selected. */
AnnaBridge	167:e84263d55307	942	return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
AnnaBridge	167:e84263d55307	943	}
AnnaBridge	167:e84263d55307	944	/**
AnnaBridge	167:e84263d55307	945	* @}
AnnaBridge	167:e84263d55307	946	*/
AnnaBridge	167:e84263d55307	947
AnnaBridge	167:e84263d55307	948	/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
AnnaBridge	167:e84263d55307	949	* @{
AnnaBridge	167:e84263d55307	950	*/
AnnaBridge	167:e84263d55307	951
AnnaBridge	167:e84263d55307	952	/**
AnnaBridge	167:e84263d55307	953	* @brief Enable DAC selected channel.
AnnaBridge	167:e84263d55307	954	* @rmtoll CR EN1 LL_DAC_Enable\n
AnnaBridge	167:e84263d55307	955	* CR EN2 LL_DAC_Enable
AnnaBridge	167:e84263d55307	956	* @note After enable from off state, DAC channel requires a delay
AnnaBridge	167:e84263d55307	957	* for output voltage to reach accuracy +/- 1 LSB.
AnnaBridge	167:e84263d55307	958	* Refer to device datasheet, parameter "tWAKEUP".
AnnaBridge	167:e84263d55307	959	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	960	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	961	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	962	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	963	*
AnnaBridge	167:e84263d55307	964	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	965	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	966	* @retval None
AnnaBridge	167:e84263d55307	967	*/
AnnaBridge	167:e84263d55307	968	__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	969	{
AnnaBridge	167:e84263d55307	970	SET_BIT(DACx->CR,
AnnaBridge	167:e84263d55307	971	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	972	}
AnnaBridge	167:e84263d55307	973
AnnaBridge	167:e84263d55307	974	/**
AnnaBridge	167:e84263d55307	975	* @brief Disable DAC selected channel.
AnnaBridge	167:e84263d55307	976	* @rmtoll CR EN1 LL_DAC_Disable\n
AnnaBridge	167:e84263d55307	977	* CR EN2 LL_DAC_Disable
AnnaBridge	167:e84263d55307	978	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	979	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	980	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	981	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	982	*
AnnaBridge	167:e84263d55307	983	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	984	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	985	* @retval None
AnnaBridge	167:e84263d55307	986	*/
AnnaBridge	167:e84263d55307	987	__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	988	{
AnnaBridge	167:e84263d55307	989	CLEAR_BIT(DACx->CR,
AnnaBridge	167:e84263d55307	990	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	991	}
AnnaBridge	167:e84263d55307	992
AnnaBridge	167:e84263d55307	993	/**
AnnaBridge	167:e84263d55307	994	* @brief Get DAC enable state of the selected channel.
AnnaBridge	167:e84263d55307	995	* (0: DAC channel is disabled, 1: DAC channel is enabled)
AnnaBridge	167:e84263d55307	996	* @rmtoll CR EN1 LL_DAC_IsEnabled\n
AnnaBridge	167:e84263d55307	997	* CR EN2 LL_DAC_IsEnabled
AnnaBridge	167:e84263d55307	998	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	999	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1000	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	1001	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	1002	*
AnnaBridge	167:e84263d55307	1003	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	1004	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	1005	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1006	*/
AnnaBridge	167:e84263d55307	1007	__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	1008	{
AnnaBridge	167:e84263d55307	1009	return (READ_BIT(DACx->CR,
AnnaBridge	167:e84263d55307	1010	DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	167:e84263d55307	1011	== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge	167:e84263d55307	1012	}
AnnaBridge	167:e84263d55307	1013
AnnaBridge	167:e84263d55307	1014	/**
AnnaBridge	167:e84263d55307	1015	* @brief Enable DAC trigger of the selected channel.
AnnaBridge	167:e84263d55307	1016	* @note - If DAC trigger is disabled, DAC conversion is performed
AnnaBridge	167:e84263d55307	1017	* automatically once the data holding register is updated,
AnnaBridge	167:e84263d55307	1018	* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge	167:e84263d55307	1019	* @ref LL_DAC_ConvertData12RightAligned(), ...
AnnaBridge	167:e84263d55307	1020	* - If DAC trigger is enabled, DAC conversion is performed
AnnaBridge	167:e84263d55307	1021	* only when a hardware of software trigger event is occurring.
AnnaBridge	167:e84263d55307	1022	* Select trigger source using
AnnaBridge	167:e84263d55307	1023	* function @ref LL_DAC_SetTriggerSource().
AnnaBridge	167:e84263d55307	1024	* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
AnnaBridge	167:e84263d55307	1025	* CR TEN2 LL_DAC_EnableTrigger
AnnaBridge	167:e84263d55307	1026	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1027	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1028	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	1029	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	1030	*
AnnaBridge	167:e84263d55307	1031	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	1032	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	1033	* @retval None
AnnaBridge	167:e84263d55307	1034	*/
AnnaBridge	167:e84263d55307	1035	__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	1036	{
AnnaBridge	167:e84263d55307	1037	SET_BIT(DACx->CR,
AnnaBridge	167:e84263d55307	1038	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	1039	}
AnnaBridge	167:e84263d55307	1040
AnnaBridge	167:e84263d55307	1041	/**
AnnaBridge	167:e84263d55307	1042	* @brief Disable DAC trigger of the selected channel.
AnnaBridge	167:e84263d55307	1043	* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
AnnaBridge	167:e84263d55307	1044	* CR TEN2 LL_DAC_DisableTrigger
AnnaBridge	167:e84263d55307	1045	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1046	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1047	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	1048	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	1049	*
AnnaBridge	167:e84263d55307	1050	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	1051	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	1052	* @retval None
AnnaBridge	167:e84263d55307	1053	*/
AnnaBridge	167:e84263d55307	1054	__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	1055	{
AnnaBridge	167:e84263d55307	1056	CLEAR_BIT(DACx->CR,
AnnaBridge	167:e84263d55307	1057	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge	167:e84263d55307	1058	}
AnnaBridge	167:e84263d55307	1059
AnnaBridge	167:e84263d55307	1060	/**
AnnaBridge	167:e84263d55307	1061	* @brief Get DAC trigger state of the selected channel.
AnnaBridge	167:e84263d55307	1062	* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
AnnaBridge	167:e84263d55307	1063	* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
AnnaBridge	167:e84263d55307	1064	* CR TEN2 LL_DAC_IsTriggerEnabled
AnnaBridge	167:e84263d55307	1065	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1066	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1067	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	1068	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	1069	*
AnnaBridge	167:e84263d55307	1070	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	1071	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	1072	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1073	*/
AnnaBridge	167:e84263d55307	1074	__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	1075	{
AnnaBridge	167:e84263d55307	1076	return (READ_BIT(DACx->CR,
AnnaBridge	167:e84263d55307	1077	DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge	167:e84263d55307	1078	== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge	167:e84263d55307	1079	}
AnnaBridge	167:e84263d55307	1080
AnnaBridge	167:e84263d55307	1081	/**
AnnaBridge	167:e84263d55307	1082	* @brief Trig DAC conversion by software for the selected DAC channel.
AnnaBridge	167:e84263d55307	1083	* @note Preliminarily, DAC trigger must be set to software trigger
AnnaBridge	167:e84263d55307	1084	* using function @ref LL_DAC_SetTriggerSource()
AnnaBridge	167:e84263d55307	1085	* with parameter "LL_DAC_TRIGGER_SOFTWARE".
AnnaBridge	167:e84263d55307	1086	* and DAC trigger must be enabled using
AnnaBridge	167:e84263d55307	1087	* function @ref LL_DAC_EnableTrigger().
AnnaBridge	167:e84263d55307	1088	* @note For devices featuring DAC with 2 channels: this function
AnnaBridge	167:e84263d55307	1089	* can perform a SW start of both DAC channels simultaneously.
AnnaBridge	167:e84263d55307	1090	* Two channels can be selected as parameter.
AnnaBridge	167:e84263d55307	1091	* Example: (LL_DAC_CHANNEL_1 \| LL_DAC_CHANNEL_2)
AnnaBridge	167:e84263d55307	1092	* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
AnnaBridge	167:e84263d55307	1093	* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
AnnaBridge	167:e84263d55307	1094	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1095	* @param DAC_Channel This parameter can a combination of the following values:
AnnaBridge	167:e84263d55307	1096	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	1097	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	1098	*
AnnaBridge	167:e84263d55307	1099	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	1100	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	1101	* @retval None
AnnaBridge	167:e84263d55307	1102	*/
AnnaBridge	167:e84263d55307	1103	__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	1104	{
AnnaBridge	167:e84263d55307	1105	SET_BIT(DACx->SWTRIGR,
AnnaBridge	167:e84263d55307	1106	(DAC_Channel & DAC_SWTR_CHX_MASK));
AnnaBridge	167:e84263d55307	1107	}
AnnaBridge	167:e84263d55307	1108
AnnaBridge	167:e84263d55307	1109	/**
AnnaBridge	167:e84263d55307	1110	* @brief Set the data to be loaded in the data holding register
AnnaBridge	167:e84263d55307	1111	* in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge	167:e84263d55307	1112	* for the selected DAC channel.
AnnaBridge	167:e84263d55307	1113	* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
AnnaBridge	167:e84263d55307	1114	* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
AnnaBridge	167:e84263d55307	1115	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1116	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1117	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	1118	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	1119	*
AnnaBridge	167:e84263d55307	1120	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	1121	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	1122	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	167:e84263d55307	1123	* @retval None
AnnaBridge	167:e84263d55307	1124	*/
AnnaBridge	167:e84263d55307	1125	__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	167:e84263d55307	1126	{
AnnaBridge	167:e84263d55307	1127	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
AnnaBridge	167:e84263d55307	1128
AnnaBridge	167:e84263d55307	1129	MODIFY_REG(*preg,
AnnaBridge	167:e84263d55307	1130	DAC_DHR12R1_DACC1DHR,
AnnaBridge	167:e84263d55307	1131	Data);
AnnaBridge	167:e84263d55307	1132	}
AnnaBridge	167:e84263d55307	1133
AnnaBridge	167:e84263d55307	1134	/**
AnnaBridge	167:e84263d55307	1135	* @brief Set the data to be loaded in the data holding register
AnnaBridge	167:e84263d55307	1136	* in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge	167:e84263d55307	1137	* for the selected DAC channel.
AnnaBridge	167:e84263d55307	1138	* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
AnnaBridge	167:e84263d55307	1139	* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
AnnaBridge	167:e84263d55307	1140	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1141	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1142	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	1143	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	1144	*
AnnaBridge	167:e84263d55307	1145	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	1146	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	1147	* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	167:e84263d55307	1148	* @retval None
AnnaBridge	167:e84263d55307	1149	*/
AnnaBridge	167:e84263d55307	1150	__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	167:e84263d55307	1151	{
AnnaBridge	167:e84263d55307	1152	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
AnnaBridge	167:e84263d55307	1153
AnnaBridge	167:e84263d55307	1154	MODIFY_REG(*preg,
AnnaBridge	167:e84263d55307	1155	DAC_DHR12L1_DACC1DHR,
AnnaBridge	167:e84263d55307	1156	Data);
AnnaBridge	167:e84263d55307	1157	}
AnnaBridge	167:e84263d55307	1158
AnnaBridge	167:e84263d55307	1159	/**
AnnaBridge	167:e84263d55307	1160	* @brief Set the data to be loaded in the data holding register
AnnaBridge	167:e84263d55307	1161	* in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge	167:e84263d55307	1162	* for the selected DAC channel.
AnnaBridge	167:e84263d55307	1163	* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
AnnaBridge	167:e84263d55307	1164	* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
AnnaBridge	167:e84263d55307	1165	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1166	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1167	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	1168	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	1169	*
AnnaBridge	167:e84263d55307	1170	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	1171	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	1172	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1173	* @retval None
AnnaBridge	167:e84263d55307	1174	*/
AnnaBridge	167:e84263d55307	1175	__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge	167:e84263d55307	1176	{
AnnaBridge	167:e84263d55307	1177	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
AnnaBridge	167:e84263d55307	1178
AnnaBridge	167:e84263d55307	1179	MODIFY_REG(*preg,
AnnaBridge	167:e84263d55307	1180	DAC_DHR8R1_DACC1DHR,
AnnaBridge	167:e84263d55307	1181	Data);
AnnaBridge	167:e84263d55307	1182	}
AnnaBridge	167:e84263d55307	1183
AnnaBridge	167:e84263d55307	1184	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	1185	/**
AnnaBridge	167:e84263d55307	1186	* @brief Set the data to be loaded in the data holding register
AnnaBridge	167:e84263d55307	1187	* in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge	167:e84263d55307	1188	* for both DAC channels.
AnnaBridge	167:e84263d55307	1189	* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
AnnaBridge	167:e84263d55307	1190	* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
AnnaBridge	167:e84263d55307	1191	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1192	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	167:e84263d55307	1193	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	167:e84263d55307	1194	* @retval None
AnnaBridge	167:e84263d55307	1195	*/
AnnaBridge	167:e84263d55307	1196	__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	167:e84263d55307	1197	{
AnnaBridge	167:e84263d55307	1198	MODIFY_REG(DACx->DHR12RD,
AnnaBridge	167:e84263d55307	1199	(DAC_DHR12RD_DACC2DHR \| DAC_DHR12RD_DACC1DHR),
AnnaBridge	167:e84263d55307	1200	((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
AnnaBridge	167:e84263d55307	1201	}
AnnaBridge	167:e84263d55307	1202
AnnaBridge	167:e84263d55307	1203	/**
AnnaBridge	167:e84263d55307	1204	* @brief Set the data to be loaded in the data holding register
AnnaBridge	167:e84263d55307	1205	* in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge	167:e84263d55307	1206	* for both DAC channels.
AnnaBridge	167:e84263d55307	1207	* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
AnnaBridge	167:e84263d55307	1208	* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
AnnaBridge	167:e84263d55307	1209	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1210	* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	167:e84263d55307	1211	* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	167:e84263d55307	1212	* @retval None
AnnaBridge	167:e84263d55307	1213	*/
AnnaBridge	167:e84263d55307	1214	__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	167:e84263d55307	1215	{
AnnaBridge	167:e84263d55307	1216	/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
AnnaBridge	167:e84263d55307	1217	/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
AnnaBridge	167:e84263d55307	1218	/* the 4 LSB must be taken into account for the shift value. */
AnnaBridge	167:e84263d55307	1219	MODIFY_REG(DACx->DHR12LD,
AnnaBridge	167:e84263d55307	1220	(DAC_DHR12LD_DACC2DHR \| DAC_DHR12LD_DACC1DHR),
AnnaBridge	167:e84263d55307	1221	((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) \| DataChannel1));
AnnaBridge	167:e84263d55307	1222	}
AnnaBridge	167:e84263d55307	1223
AnnaBridge	167:e84263d55307	1224	/**
AnnaBridge	167:e84263d55307	1225	* @brief Set the data to be loaded in the data holding register
AnnaBridge	167:e84263d55307	1226	* in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge	167:e84263d55307	1227	* for both DAC channels.
AnnaBridge	167:e84263d55307	1228	* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
AnnaBridge	167:e84263d55307	1229	* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
AnnaBridge	167:e84263d55307	1230	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1231	* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1232	* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1233	* @retval None
AnnaBridge	167:e84263d55307	1234	*/
AnnaBridge	167:e84263d55307	1235	__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge	167:e84263d55307	1236	{
AnnaBridge	167:e84263d55307	1237	MODIFY_REG(DACx->DHR8RD,
AnnaBridge	167:e84263d55307	1238	(DAC_DHR8RD_DACC2DHR \| DAC_DHR8RD_DACC1DHR),
AnnaBridge	167:e84263d55307	1239	((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) \| DataChannel1));
AnnaBridge	167:e84263d55307	1240	}
AnnaBridge	167:e84263d55307	1241
AnnaBridge	167:e84263d55307	1242	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	1243	/**
AnnaBridge	167:e84263d55307	1244	* @brief Retrieve output data currently generated for the selected DAC channel.
AnnaBridge	167:e84263d55307	1245	* @note Whatever alignment and resolution settings
AnnaBridge	167:e84263d55307	1246	* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge	167:e84263d55307	1247	* @ref LL_DAC_ConvertData12RightAligned(), ...),
AnnaBridge	167:e84263d55307	1248	* output data format is 12 bits right aligned (LSB aligned on bit 0).
AnnaBridge	167:e84263d55307	1249	* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
AnnaBridge	167:e84263d55307	1250	* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
AnnaBridge	167:e84263d55307	1251	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1252	* @param DAC_Channel This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1253	* @arg @ref LL_DAC_CHANNEL_1
AnnaBridge	167:e84263d55307	1254	* @arg @ref LL_DAC_CHANNEL_2 (1)
AnnaBridge	167:e84263d55307	1255	*
AnnaBridge	167:e84263d55307	1256	* (1) On this STM32 serie, parameter not available on all devices.
AnnaBridge	167:e84263d55307	1257	* Refer to device datasheet for channels availability.
AnnaBridge	167:e84263d55307	1258	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge	167:e84263d55307	1259	*/
AnnaBridge	167:e84263d55307	1260	__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge	167:e84263d55307	1261	{
AnnaBridge	167:e84263d55307	1262	register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
AnnaBridge	167:e84263d55307	1263
AnnaBridge	167:e84263d55307	1264	return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
AnnaBridge	167:e84263d55307	1265	}
AnnaBridge	167:e84263d55307	1266
AnnaBridge	167:e84263d55307	1267	/**
AnnaBridge	167:e84263d55307	1268	* @}
AnnaBridge	167:e84263d55307	1269	*/
AnnaBridge	167:e84263d55307	1270
AnnaBridge	167:e84263d55307	1271	/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	167:e84263d55307	1272	* @{
AnnaBridge	167:e84263d55307	1273	*/
AnnaBridge	167:e84263d55307	1274	/**
AnnaBridge	167:e84263d55307	1275	* @brief Get DAC underrun flag for DAC channel 1
AnnaBridge	167:e84263d55307	1276	* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
AnnaBridge	167:e84263d55307	1277	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1278	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1279	*/
AnnaBridge	167:e84263d55307	1280	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1281	{
AnnaBridge	167:e84263d55307	1282	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
AnnaBridge	167:e84263d55307	1283	}
AnnaBridge	167:e84263d55307	1284
AnnaBridge	167:e84263d55307	1285	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	1286	/**
AnnaBridge	167:e84263d55307	1287	* @brief Get DAC underrun flag for DAC channel 2
AnnaBridge	167:e84263d55307	1288	* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
AnnaBridge	167:e84263d55307	1289	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1290	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1291	*/
AnnaBridge	167:e84263d55307	1292	__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1293	{
AnnaBridge	167:e84263d55307	1294	return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
AnnaBridge	167:e84263d55307	1295	}
AnnaBridge	167:e84263d55307	1296	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	1297
AnnaBridge	167:e84263d55307	1298	/**
AnnaBridge	167:e84263d55307	1299	* @brief Clear DAC underrun flag for DAC channel 1
AnnaBridge	167:e84263d55307	1300	* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
AnnaBridge	167:e84263d55307	1301	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1302	* @retval None
AnnaBridge	167:e84263d55307	1303	*/
AnnaBridge	167:e84263d55307	1304	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1305	{
AnnaBridge	167:e84263d55307	1306	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
AnnaBridge	167:e84263d55307	1307	}
AnnaBridge	167:e84263d55307	1308
AnnaBridge	167:e84263d55307	1309	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	1310	/**
AnnaBridge	167:e84263d55307	1311	* @brief Clear DAC underrun flag for DAC channel 2
AnnaBridge	167:e84263d55307	1312	* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
AnnaBridge	167:e84263d55307	1313	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1314	* @retval None
AnnaBridge	167:e84263d55307	1315	*/
AnnaBridge	167:e84263d55307	1316	__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1317	{
AnnaBridge	167:e84263d55307	1318	WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
AnnaBridge	167:e84263d55307	1319	}
AnnaBridge	167:e84263d55307	1320	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	1321
AnnaBridge	167:e84263d55307	1322	/**
AnnaBridge	167:e84263d55307	1323	* @}
AnnaBridge	167:e84263d55307	1324	*/
AnnaBridge	167:e84263d55307	1325
AnnaBridge	167:e84263d55307	1326	/** @defgroup DAC_LL_EF_IT_Management IT management
AnnaBridge	167:e84263d55307	1327	* @{
AnnaBridge	167:e84263d55307	1328	*/
AnnaBridge	167:e84263d55307	1329
AnnaBridge	167:e84263d55307	1330	/**
AnnaBridge	167:e84263d55307	1331	* @brief Enable DMA underrun interrupt for DAC channel 1
AnnaBridge	167:e84263d55307	1332	* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
AnnaBridge	167:e84263d55307	1333	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1334	* @retval None
AnnaBridge	167:e84263d55307	1335	*/
AnnaBridge	167:e84263d55307	1336	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1337	{
AnnaBridge	167:e84263d55307	1338	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge	167:e84263d55307	1339	}
AnnaBridge	167:e84263d55307	1340
AnnaBridge	167:e84263d55307	1341	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	1342	/**
AnnaBridge	167:e84263d55307	1343	* @brief Enable DMA underrun interrupt for DAC channel 2
AnnaBridge	167:e84263d55307	1344	* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
AnnaBridge	167:e84263d55307	1345	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1346	* @retval None
AnnaBridge	167:e84263d55307	1347	*/
AnnaBridge	167:e84263d55307	1348	__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1349	{
AnnaBridge	167:e84263d55307	1350	SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge	167:e84263d55307	1351	}
AnnaBridge	167:e84263d55307	1352	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	1353
AnnaBridge	167:e84263d55307	1354	/**
AnnaBridge	167:e84263d55307	1355	* @brief Disable DMA underrun interrupt for DAC channel 1
AnnaBridge	167:e84263d55307	1356	* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
AnnaBridge	167:e84263d55307	1357	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1358	* @retval None
AnnaBridge	167:e84263d55307	1359	*/
AnnaBridge	167:e84263d55307	1360	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1361	{
AnnaBridge	167:e84263d55307	1362	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge	167:e84263d55307	1363	}
AnnaBridge	167:e84263d55307	1364
AnnaBridge	167:e84263d55307	1365	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	1366	/**
AnnaBridge	167:e84263d55307	1367	* @brief Disable DMA underrun interrupt for DAC channel 2
AnnaBridge	167:e84263d55307	1368	* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
AnnaBridge	167:e84263d55307	1369	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1370	* @retval None
AnnaBridge	167:e84263d55307	1371	*/
AnnaBridge	167:e84263d55307	1372	__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1373	{
AnnaBridge	167:e84263d55307	1374	CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge	167:e84263d55307	1375	}
AnnaBridge	167:e84263d55307	1376	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	1377
AnnaBridge	167:e84263d55307	1378	/**
AnnaBridge	167:e84263d55307	1379	* @brief Get DMA underrun interrupt for DAC channel 1
AnnaBridge	167:e84263d55307	1380	* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
AnnaBridge	167:e84263d55307	1381	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1382	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1383	*/
AnnaBridge	167:e84263d55307	1384	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1385	{
AnnaBridge	167:e84263d55307	1386	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
AnnaBridge	167:e84263d55307	1387	}
AnnaBridge	167:e84263d55307	1388
AnnaBridge	167:e84263d55307	1389	#if defined(DAC_CHANNEL2_SUPPORT)
AnnaBridge	167:e84263d55307	1390	/**
AnnaBridge	167:e84263d55307	1391	* @brief Get DMA underrun interrupt for DAC channel 2
AnnaBridge	167:e84263d55307	1392	* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
AnnaBridge	167:e84263d55307	1393	* @param DACx DAC instance
AnnaBridge	167:e84263d55307	1394	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1395	*/
AnnaBridge	167:e84263d55307	1396	__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge	167:e84263d55307	1397	{
AnnaBridge	167:e84263d55307	1398	return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
AnnaBridge	167:e84263d55307	1399	}
AnnaBridge	167:e84263d55307	1400	#endif /* DAC_CHANNEL2_SUPPORT */
AnnaBridge	167:e84263d55307	1401
AnnaBridge	167:e84263d55307	1402	/**
AnnaBridge	167:e84263d55307	1403	* @}
AnnaBridge	167:e84263d55307	1404	*/
AnnaBridge	167:e84263d55307	1405
AnnaBridge	167:e84263d55307	1406	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	1407	/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	167:e84263d55307	1408	* @{
AnnaBridge	167:e84263d55307	1409	*/
AnnaBridge	167:e84263d55307	1410
AnnaBridge	167:e84263d55307	1411	ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
AnnaBridge	167:e84263d55307	1412	ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge	167:e84263d55307	1413	void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge	167:e84263d55307	1414
AnnaBridge	167:e84263d55307	1415	/**
AnnaBridge	167:e84263d55307	1416	* @}
AnnaBridge	167:e84263d55307	1417	*/
AnnaBridge	167:e84263d55307	1418	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	1419
AnnaBridge	167:e84263d55307	1420	/**
AnnaBridge	167:e84263d55307	1421	* @}
AnnaBridge	167:e84263d55307	1422	*/
AnnaBridge	167:e84263d55307	1423
AnnaBridge	167:e84263d55307	1424	/**
AnnaBridge	167:e84263d55307	1425	* @}
AnnaBridge	167:e84263d55307	1426	*/
AnnaBridge	167:e84263d55307	1427
AnnaBridge	167:e84263d55307	1428	#endif /* DAC */
AnnaBridge	167:e84263d55307	1429
AnnaBridge	167:e84263d55307	1430	/**
AnnaBridge	167:e84263d55307	1431	* @}
AnnaBridge	167:e84263d55307	1432	*/
AnnaBridge	167:e84263d55307	1433
AnnaBridge	167:e84263d55307	1434	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	1435	}
AnnaBridge	167:e84263d55307	1436	#endif
AnnaBridge	167:e84263d55307	1437
AnnaBridge	167:e84263d55307	1438	#endif /* __STM32F4xx_LL_DAC_H */
AnnaBridge	167:e84263d55307	1439
AnnaBridge	167:e84263d55307	1440	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Repository details

Type:	Library
Created:	29 Jun 2017
Imports:	0
Forks:	0
Commits:	169
Dependents:	0
Dependencies:	0
Followers:	2

The code in this repository is Apache licensed.

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h@168:1dc8c8bdd03d, 2017-06-29 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h@168:1dc8c8bdd03d, 2017-06-29 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning