I-O DATA DEV2 / KANI-GS1_mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of UDNS1_mbed-dev by I-O DATA DEV2

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h@113:b3775bf36a83, 2016-04-19 (annotated)

Committer:
mbed_official
Date:
Tue Apr 19 11:15:15 2016 +0100
Revision:
113:b3775bf36a83
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision 896981126b34b6d9441e3eea77881c67a1ae3dbd



Full URL: https://github.com/mbedmicro/mbed/commit/896981126b34b6d9441e3eea77881c67a1ae3dbd/



Exporter tool addition for e2 studio

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32l0xx_hal_adc.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
mbed_official 113:b3775bf36a83 5 * @version V1.5.0
mbed_official 113:b3775bf36a83 6 * @date 8-January-2016
bogdanm 0:9b334a45a8ff 7 * @brief This file contains all the functions prototypes for the ADC firmware
bogdanm 0:9b334a45a8ff 8 * library.
bogdanm 0:9b334a45a8ff 9 ******************************************************************************
bogdanm 0:9b334a45a8ff 10 * @attention
bogdanm 0:9b334a45a8ff 11 *
mbed_official 113:b3775bf36a83 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 15 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 17 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 20 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 22 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 23 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 24 *
bogdanm 0:9b334a45a8ff 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 35 *
bogdanm 0:9b334a45a8ff 36 ******************************************************************************
bogdanm 0:9b334a45a8ff 37 */
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 40 #ifndef __STM32L0xx_ADC_H
bogdanm 0:9b334a45a8ff 41 #define __STM32L0xx_ADC_H
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 44 extern "C" {
bogdanm 0:9b334a45a8ff 45 #endif
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 48 #include "stm32l0xx_hal_def.h"
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 51 * @{
bogdanm 0:9b334a45a8ff 52 */
bogdanm 0:9b334a45a8ff 53
mbed_official 113:b3775bf36a83 54 /** @defgroup ADC ADC
bogdanm 0:9b334a45a8ff 55 * @{
bogdanm 0:9b334a45a8ff 56 */
bogdanm 0:9b334a45a8ff 57
mbed_official 113:b3775bf36a83 58 /** @defgroup ADC_Exported_Types ADC Exported Types
mbed_official 113:b3775bf36a83 59 * @{
mbed_official 113:b3775bf36a83 60 */
mbed_official 113:b3775bf36a83 61
bogdanm 0:9b334a45a8ff 62 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 63 /**
mbed_official 113:b3775bf36a83 64 * @brief HAL ADC state machine: ADC states definition (bitfields)
bogdanm 0:9b334a45a8ff 65 */
mbed_official 113:b3775bf36a83 66 /* States of ADC global scope */
mbed_official 113:b3775bf36a83 67 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
mbed_official 113:b3775bf36a83 68 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
mbed_official 113:b3775bf36a83 69 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
mbed_official 113:b3775bf36a83 70 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
mbed_official 113:b3775bf36a83 71
mbed_official 113:b3775bf36a83 72 /* States of ADC errors */
mbed_official 113:b3775bf36a83 73 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
mbed_official 113:b3775bf36a83 74 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
mbed_official 113:b3775bf36a83 75 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
mbed_official 113:b3775bf36a83 76
mbed_official 113:b3775bf36a83 77 /* States of ADC group regular */
mbed_official 113:b3775bf36a83 78 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
mbed_official 113:b3775bf36a83 79 external trigger, low power auto power-on, multimode ADC master control) */
mbed_official 113:b3775bf36a83 80 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
mbed_official 113:b3775bf36a83 81 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
mbed_official 113:b3775bf36a83 82 #define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
mbed_official 113:b3775bf36a83 83
mbed_official 113:b3775bf36a83 84 /* States of ADC group injected */
mbed_official 113:b3775bf36a83 85 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
mbed_official 113:b3775bf36a83 86 external trigger, low power auto power-on, multimode ADC master control) */
mbed_official 113:b3775bf36a83 87 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on STM32F0 device: Conversion data available on group injected */
mbed_official 113:b3775bf36a83 88 #define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
mbed_official 113:b3775bf36a83 89
mbed_official 113:b3775bf36a83 90 /* States of ADC analog watchdogs */
mbed_official 113:b3775bf36a83 91 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
mbed_official 113:b3775bf36a83 92 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
mbed_official 113:b3775bf36a83 93 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
mbed_official 113:b3775bf36a83 94
mbed_official 113:b3775bf36a83 95 /* States of ADC multi-mode */
mbed_official 113:b3775bf36a83 96 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 /**
bogdanm 0:9b334a45a8ff 100 * @brief ADC Oversampler structure definition
bogdanm 0:9b334a45a8ff 101 */
bogdanm 0:9b334a45a8ff 102 typedef struct
bogdanm 0:9b334a45a8ff 103 {
bogdanm 0:9b334a45a8ff 104 uint32_t Ratio; /*!< Configures the oversampling ratio.
bogdanm 0:9b334a45a8ff 105 This parameter can be a value of @ref ADC_Oversampling_Ratio */
bogdanm 0:9b334a45a8ff 106 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
bogdanm 0:9b334a45a8ff 107 This parameter can be a value of @ref ADC_Right_Bit_Shift */
bogdanm 0:9b334a45a8ff 108 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode
bogdanm 0:9b334a45a8ff 109 This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 }ADC_OversamplingTypeDef;
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /**
bogdanm 0:9b334a45a8ff 114 * @brief ADC Init structure definition
bogdanm 0:9b334a45a8ff 115 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state.
bogdanm 0:9b334a45a8ff 116 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
bogdanm 0:9b334a45a8ff 117 * without error reporting (as it can be the expected behaviour in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly).
bogdanm 0:9b334a45a8ff 118 */
bogdanm 0:9b334a45a8ff 119 typedef struct
bogdanm 0:9b334a45a8ff 120 {
bogdanm 0:9b334a45a8ff 121 uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled
bogdanm 0:9b334a45a8ff 122 This parameter can be set to ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 123 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 124 ADC_OversamplingTypeDef Oversample; /*!< Specifies the Oversampling parameters
bogdanm 0:9b334a45a8ff 125 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 126 uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency.
bogdanm 0:9b334a45a8ff 127 This parameter can be a value of @ref ADC_ClockPrescaler
mbed_official 113:b3775bf36a83 128 Note: This parameter can be modified only if ADC is disabled.
mbed_official 113:b3775bf36a83 129 Note: In case of Synchronous clock mode divided by 1, this configuration must be enabled only
mbed_official 113:b3775bf36a83 130 if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC
mbed_official 113:b3775bf36a83 131 must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual for details */
bogdanm 0:9b334a45a8ff 132 uint32_t Resolution; /*!< Configures the ADC resolution mode.
bogdanm 0:9b334a45a8ff 133 This parameter can be a value of @ref ADC_Resolution
bogdanm 0:9b334a45a8ff 134 Note: This parameter can be modified only if ADC is disabled. */
bogdanm 0:9b334a45a8ff 135 uint32_t SamplingTime; /*!< The sample time value to be set for all channels.
bogdanm 0:9b334a45a8ff 136 This parameter can be a value of @ref ADC_sampling_times
bogdanm 0:9b334a45a8ff 137 Note: This parameter can be modified only if there is no conversion ongoing. */
bogdanm 0:9b334a45a8ff 138 uint32_t ScanConvMode; /*!< The scan sequence direction.
mbed_official 113:b3775bf36a83 139 If several channels are set: Conversions are performed in sequence mode
mbed_official 113:b3775bf36a83 140 (ranks defined by each channel number: channel 0 fixed on rank 0,
mbed_official 113:b3775bf36a83 141 channel 1 fixed on rank1, ...).
bogdanm 0:9b334a45a8ff 142 This parameter can be a value of @ref ADC_Scan_mode
bogdanm 0:9b334a45a8ff 143 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 144 uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
bogdanm 0:9b334a45a8ff 145 This parameter can be a value of @ref ADC_data_align
bogdanm 0:9b334a45a8ff 146 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 147 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
bogdanm 0:9b334a45a8ff 148 This parameter can be set to ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 149 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 150 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed
bogdanm 0:9b334a45a8ff 151 in Complete-sequence/Discontinuous-sequence.
bogdanm 0:9b334a45a8ff 152 Discontinuous mode can be enabled only if continuous mode is disabled.
bogdanm 0:9b334a45a8ff 153 This parameter can be set to ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 154 Note: This parameter can be modified only if there is no conversion is ongoing. */
mbed_official 113:b3775bf36a83 155 uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
mbed_official 113:b3775bf36a83 156 If set to ADC_SOFTWARE_START, external triggers are disabled.
mbed_official 113:b3775bf36a83 157 This parameter can be a value of @ref ADC_External_trigger_Source
bogdanm 0:9b334a45a8ff 158 Note: This parameter can be modified only if there is no conversion is ongoing. */
mbed_official 113:b3775bf36a83 159 uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
mbed_official 113:b3775bf36a83 160 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
mbed_official 113:b3775bf36a83 161 This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
bogdanm 0:9b334a45a8ff 162 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 163 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
bogdanm 0:9b334a45a8ff 164 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
bogdanm 0:9b334a45a8ff 165 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer max pointer is reached.
bogdanm 0:9b334a45a8ff 166 This parameter can be set to ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 167 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 168 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion polling and interruption:
bogdanm 0:9b334a45a8ff 169 end of single channel conversion or end of channels conversions sequence.
bogdanm 0:9b334a45a8ff 170 This parameter can be a value of @ref ADC_EOCSelection */
bogdanm 0:9b334a45a8ff 171 uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
bogdanm 0:9b334a45a8ff 172 This parameter has an effect on regular channels only, including in DMA mode.
bogdanm 0:9b334a45a8ff 173 This parameter can be a value of @ref ADC_Overrun
bogdanm 0:9b334a45a8ff 174 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 175 uint32_t LowPowerAutoWait; /*!< Specifies the usage of dynamic low power Auto Delay: new conversion start only
bogdanm 0:9b334a45a8ff 176 when the previous conversion (for regular channel) is completed.
bogdanm 0:9b334a45a8ff 177 This avoids risk of overrun for low frequency application.
bogdanm 0:9b334a45a8ff 178 This parameter can be set to ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 179 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 180 uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
bogdanm 0:9b334a45a8ff 181 it is mandatory to first enable the Low Frequency Mode.
bogdanm 0:9b334a45a8ff 182 This parameter can be set to ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 183 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 184 uint32_t LowPowerAutoPowerOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically
bogdanm 0:9b334a45a8ff 185 wakes-up when a conversion is started (by software or hardware trigger).
bogdanm 0:9b334a45a8ff 186 This parameter can be set to ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 187 Note: This parameter can be modified only if there is no conversion is ongoing. */
bogdanm 0:9b334a45a8ff 188 }ADC_InitTypeDef;
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 /**
bogdanm 0:9b334a45a8ff 191 * @brief ADC handle Structure definition
bogdanm 0:9b334a45a8ff 192 */
mbed_official 113:b3775bf36a83 193 typedef struct
bogdanm 0:9b334a45a8ff 194 {
bogdanm 0:9b334a45a8ff 195 ADC_TypeDef *Instance; /*!< Register base address */
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 ADC_InitTypeDef Init; /*!< ADC required parameters */
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 HAL_LockTypeDef Lock; /*!< ADC locking object */
bogdanm 0:9b334a45a8ff 202
mbed_official 113:b3775bf36a83 203 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 __IO uint32_t ErrorCode; /*!< ADC Error code */
bogdanm 0:9b334a45a8ff 206 }ADC_HandleTypeDef;
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 /**
bogdanm 0:9b334a45a8ff 209 * @brief ADC Configuration regular Channel structure definition
bogdanm 0:9b334a45a8ff 210 */
bogdanm 0:9b334a45a8ff 211 typedef struct
bogdanm 0:9b334a45a8ff 212 {
bogdanm 0:9b334a45a8ff 213 uint32_t Channel; /*!< the ADC channel to configure
bogdanm 0:9b334a45a8ff 214 This parameter can be a value of @ref ADC_channels */
mbed_official 113:b3775bf36a83 215
mbed_official 113:b3775bf36a83 216 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
mbed_official 113:b3775bf36a83 217 On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
mbed_official 113:b3775bf36a83 218 (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
mbed_official 113:b3775bf36a83 219 Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
mbed_official 113:b3775bf36a83 220 This parameter can be a value of @ref ADC_rank */
bogdanm 0:9b334a45a8ff 221 }ADC_ChannelConfTypeDef;
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /**
bogdanm 0:9b334a45a8ff 225 * @brief ADC Configuration analog watchdog definition
bogdanm 0:9b334a45a8ff 226 */
bogdanm 0:9b334a45a8ff 227 typedef struct
bogdanm 0:9b334a45a8ff 228 {
bogdanm 0:9b334a45a8ff 229 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels.
bogdanm 0:9b334a45a8ff 230 This parameter can be a value of @ref ADC_analog_watchdog_mode */
bogdanm 0:9b334a45a8ff 231 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
bogdanm 0:9b334a45a8ff 232 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
bogdanm 0:9b334a45a8ff 233 This parameter can be a value of @ref ADC_channels */
bogdanm 0:9b334a45a8ff 234 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
bogdanm 0:9b334a45a8ff 235 This parameter can be set to ENABLE or DISABLE */
bogdanm 0:9b334a45a8ff 236 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 0:9b334a45a8ff 237 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
bogdanm 0:9b334a45a8ff 238 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
bogdanm 0:9b334a45a8ff 239 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
bogdanm 0:9b334a45a8ff 240 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
bogdanm 0:9b334a45a8ff 241 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
bogdanm 0:9b334a45a8ff 242 }ADC_AnalogWDGConfTypeDef;
bogdanm 0:9b334a45a8ff 243
mbed_official 113:b3775bf36a83 244 /**
mbed_official 113:b3775bf36a83 245 * @}
mbed_official 113:b3775bf36a83 246 */
mbed_official 113:b3775bf36a83 247
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 250
mbed_official 113:b3775bf36a83 251 /** @defgroup ADC_Exported_Constants ADC Exported Constants
bogdanm 0:9b334a45a8ff 252 * @{
bogdanm 0:9b334a45a8ff 253 */
bogdanm 0:9b334a45a8ff 254
mbed_official 113:b3775bf36a83 255 /** @defgroup ADC_Error_Code ADC Error Code
bogdanm 0:9b334a45a8ff 256 * @{
bogdanm 0:9b334a45a8ff 257 */
bogdanm 0:9b334a45a8ff 258 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
bogdanm 0:9b334a45a8ff 259 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
bogdanm 0:9b334a45a8ff 260 enable/disable, erroneous state */
bogdanm 0:9b334a45a8ff 261 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< OVR error */
mbed_official 113:b3775bf36a83 262 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
bogdanm 0:9b334a45a8ff 263 /**
bogdanm 0:9b334a45a8ff 264 * @}
bogdanm 0:9b334a45a8ff 265 */
bogdanm 0:9b334a45a8ff 266
mbed_official 113:b3775bf36a83 267 /** @defgroup ADC_TimeOut_Values ADC TimeOut Values
bogdanm 0:9b334a45a8ff 268 * @{
bogdanm 0:9b334a45a8ff 269 */
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /* Fixed timeout values for ADC calibration, enable settling time, disable */
bogdanm 0:9b334a45a8ff 272 /* settling time. */
bogdanm 0:9b334a45a8ff 273 /* Values defined to be higher than worst cases: low clocks freq, */
bogdanm 0:9b334a45a8ff 274 /* maximum prescalers. */
bogdanm 0:9b334a45a8ff 275 /* Unit: ms */
bogdanm 0:9b334a45a8ff 276 #define ADC_ENABLE_TIMEOUT 10
bogdanm 0:9b334a45a8ff 277 #define ADC_DISABLE_TIMEOUT 10
bogdanm 0:9b334a45a8ff 278 #define ADC_STOP_CONVERSION_TIMEOUT 10
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */
bogdanm 0:9b334a45a8ff 281 /* the minimum number of CPU cycles to fulfill this delay */
bogdanm 0:9b334a45a8ff 282 #define ADC_DELAY_10US_MIN_CPU_CYCLES 1800
bogdanm 0:9b334a45a8ff 283 /**
bogdanm 0:9b334a45a8ff 284 * @}
bogdanm 0:9b334a45a8ff 285 */
bogdanm 0:9b334a45a8ff 286
mbed_official 113:b3775bf36a83 287 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
bogdanm 0:9b334a45a8ff 288 * @{
bogdanm 0:9b334a45a8ff 289 */
bogdanm 0:9b334a45a8ff 290 #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode divided by 1 */
bogdanm 0:9b334a45a8ff 291 #define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 292 #define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 293 #define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 294 #define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 295 #define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 296 #define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 297 #define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 298 #define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 299 #define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 300 #define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 301 #define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */
bogdanm 0:9b334a45a8ff 302
mbed_official 113:b3775bf36a83 303 #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1
bogdanm 0:9b334a45a8ff 304 This configuration must be enabled only if PCLK has a 50%
bogdanm 0:9b334a45a8ff 305 duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
bogdanm 0:9b334a45a8ff 306 must by 50% duty cycle)*/
mbed_official 113:b3775bf36a83 307 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 2 */
mbed_official 113:b3775bf36a83 308 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 4 */
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 /**
bogdanm 0:9b334a45a8ff 311 * @}
bogdanm 0:9b334a45a8ff 312 */
bogdanm 0:9b334a45a8ff 313
mbed_official 113:b3775bf36a83 314 /** @defgroup ADC_Resolution ADC Resolution
bogdanm 0:9b334a45a8ff 315 * @{
bogdanm 0:9b334a45a8ff 316 */
bogdanm 0:9b334a45a8ff 317 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
bogdanm 0:9b334a45a8ff 318 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */
bogdanm 0:9b334a45a8ff 319 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */
bogdanm 0:9b334a45a8ff 320 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */
bogdanm 0:9b334a45a8ff 321 /**
bogdanm 0:9b334a45a8ff 322 * @}
bogdanm 0:9b334a45a8ff 323 */
bogdanm 0:9b334a45a8ff 324
mbed_official 113:b3775bf36a83 325 /** @defgroup ADC_data_align ADC Data Align
bogdanm 0:9b334a45a8ff 326 * @{
bogdanm 0:9b334a45a8ff 327 */
bogdanm 0:9b334a45a8ff 328 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 329 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /**
bogdanm 0:9b334a45a8ff 332 * @}
bogdanm 0:9b334a45a8ff 333 */
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 /** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
bogdanm 0:9b334a45a8ff 336 * @{
bogdanm 0:9b334a45a8ff 337 */
bogdanm 0:9b334a45a8ff 338 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 339 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
bogdanm 0:9b334a45a8ff 340 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
bogdanm 0:9b334a45a8ff 341 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
mbed_official 113:b3775bf36a83 342 /**
mbed_official 113:b3775bf36a83 343 * @}
mbed_official 113:b3775bf36a83 344 */
bogdanm 0:9b334a45a8ff 345
mbed_official 113:b3775bf36a83 346 /** @defgroup ADC_EOCSelection ADC EOC Selection
mbed_official 113:b3775bf36a83 347 * @{
mbed_official 113:b3775bf36a83 348 */
mbed_official 113:b3775bf36a83 349 #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
mbed_official 113:b3775bf36a83 350 #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
mbed_official 113:b3775bf36a83 351 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
bogdanm 0:9b334a45a8ff 352 /**
bogdanm 0:9b334a45a8ff 353 * @}
bogdanm 0:9b334a45a8ff 354 */
bogdanm 0:9b334a45a8ff 355
mbed_official 113:b3775bf36a83 356 /** @defgroup ADC_Overrun ADC Overrun
bogdanm 0:9b334a45a8ff 357 * @{
mbed_official 113:b3775bf36a83 358 */
mbed_official 113:b3775bf36a83 359 #define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
mbed_official 113:b3775bf36a83 360 #define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
bogdanm 0:9b334a45a8ff 361 /**
bogdanm 0:9b334a45a8ff 362 * @}
bogdanm 0:9b334a45a8ff 363 */
bogdanm 0:9b334a45a8ff 364
mbed_official 113:b3775bf36a83 365
mbed_official 113:b3775bf36a83 366 /** @defgroup ADC_rank ADC rank
bogdanm 0:9b334a45a8ff 367 * @{
bogdanm 0:9b334a45a8ff 368 */
mbed_official 113:b3775bf36a83 369 #define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
mbed_official 113:b3775bf36a83 370 #define ADC_RANK_NONE ((uint32_t)0x00001001) /*!< Disable the selected rank (selected channel) from sequencer */
bogdanm 0:9b334a45a8ff 371 /**
bogdanm 0:9b334a45a8ff 372 * @}
mbed_official 113:b3775bf36a83 373 */
bogdanm 0:9b334a45a8ff 374
bogdanm 0:9b334a45a8ff 375
mbed_official 113:b3775bf36a83 376 /** @defgroup ADC_channels ADC_Channels
bogdanm 0:9b334a45a8ff 377 * @{
bogdanm 0:9b334a45a8ff 378 */
bogdanm 0:9b334a45a8ff 379 #define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
bogdanm 0:9b334a45a8ff 380 #define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0)
bogdanm 0:9b334a45a8ff 381 #define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1)
bogdanm 0:9b334a45a8ff 382 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
bogdanm 0:9b334a45a8ff 383 #define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2)
bogdanm 0:9b334a45a8ff 384 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
bogdanm 0:9b334a45a8ff 385 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
bogdanm 0:9b334a45a8ff 386 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0)
bogdanm 0:9b334a45a8ff 387 #define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3)
bogdanm 0:9b334a45a8ff 388 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0)
bogdanm 0:9b334a45a8ff 389 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1)
bogdanm 0:9b334a45a8ff 390 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
bogdanm 0:9b334a45a8ff 391 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2)
bogdanm 0:9b334a45a8ff 392 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0)
bogdanm 0:9b334a45a8ff 393 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1)
bogdanm 0:9b334a45a8ff 394 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0)
mbed_official 113:b3775bf36a83 395 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
bogdanm 0:9b334a45a8ff 396 #define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4)
mbed_official 113:b3775bf36a83 397 #endif
bogdanm 0:9b334a45a8ff 398 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0)
bogdanm 0:9b334a45a8ff 399 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1)
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /* Internal channels */
mbed_official 113:b3775bf36a83 402 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
bogdanm 0:9b334a45a8ff 403 #define ADC_CHANNEL_VLCD ADC_CHANNEL_16
mbed_official 113:b3775bf36a83 404 #endif
bogdanm 0:9b334a45a8ff 405 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
bogdanm 0:9b334a45a8ff 406 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
bogdanm 0:9b334a45a8ff 407 /**
bogdanm 0:9b334a45a8ff 408 * @}
bogdanm 0:9b334a45a8ff 409 */
bogdanm 0:9b334a45a8ff 410
mbed_official 113:b3775bf36a83 411 /** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
bogdanm 0:9b334a45a8ff 412 * @{
bogdanm 0:9b334a45a8ff 413 */
bogdanm 0:9b334a45a8ff 414 #define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFF)
bogdanm 0:9b334a45a8ff 415 #define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000)
bogdanm 0:9b334a45a8ff 416 /**
bogdanm 0:9b334a45a8ff 417 * @}
bogdanm 0:9b334a45a8ff 418 */
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420
mbed_official 113:b3775bf36a83 421 /** @defgroup ADC_sampling_times ADC Sampling Cycles
bogdanm 0:9b334a45a8ff 422 * @{
bogdanm 0:9b334a45a8ff 423 */
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< ADC sampling time 1.5 cycle */
bogdanm 0:9b334a45a8ff 426 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 7.5 CYCLES */
bogdanm 0:9b334a45a8ff 427 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 13.5 CYCLES */
bogdanm 0:9b334a45a8ff 428 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 28.5 CYCLES */
bogdanm 0:9b334a45a8ff 429 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 41.5 CYCLES */
bogdanm 0:9b334a45a8ff 430 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 55.5 CYCLES */
bogdanm 0:9b334a45a8ff 431 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 71.5 CYCLES */
bogdanm 0:9b334a45a8ff 432 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 239.5 CYCLES */
bogdanm 0:9b334a45a8ff 433 /**
bogdanm 0:9b334a45a8ff 434 * @}
bogdanm 0:9b334a45a8ff 435 */
bogdanm 0:9b334a45a8ff 436
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /** @defgroup ADC_Scan_mode ADC Scan mode
bogdanm 0:9b334a45a8ff 439 * @{
bogdanm 0:9b334a45a8ff 440 */
bogdanm 0:9b334a45a8ff 441 /* Note: Scan mode values must be compatible with other STM32 devices having */
bogdanm 0:9b334a45a8ff 442 /* a configurable sequencer. */
bogdanm 0:9b334a45a8ff 443 /* Scan direction setting values are defined by taking in account */
bogdanm 0:9b334a45a8ff 444 /* already defined values for other STM32 devices: */
bogdanm 0:9b334a45a8ff 445 /* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */
bogdanm 0:9b334a45a8ff 446 /* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */
bogdanm 0:9b334a45a8ff 447 /* Scan direction forward is considered as default setting equivalent */
bogdanm 0:9b334a45a8ff 448 /* to scan enable. */
bogdanm 0:9b334a45a8ff 449 /* Scan direction backward is considered as additional setting. */
bogdanm 0:9b334a45a8ff 450 /* In case of migration from another STM32 device, the user will be */
bogdanm 0:9b334a45a8ff 451 /* warned of change of setting choices with assert check. */
bogdanm 0:9b334a45a8ff 452 #define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /*!< Scan direction forward: from channel 0 to channel 18 */
bogdanm 0:9b334a45a8ff 453 #define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455 #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
bogdanm 0:9b334a45a8ff 456 /**
bogdanm 0:9b334a45a8ff 457 * @}
bogdanm 0:9b334a45a8ff 458 */
bogdanm 0:9b334a45a8ff 459
mbed_official 113:b3775bf36a83 460 /** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
bogdanm 0:9b334a45a8ff 461 * @{
bogdanm 0:9b334a45a8ff 462 */
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 #define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */
bogdanm 0:9b334a45a8ff 465 #define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004) /*!< ADC Oversampling ratio 4x */
bogdanm 0:9b334a45a8ff 466 #define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008) /*!< ADC Oversampling ratio 8x */
bogdanm 0:9b334a45a8ff 467 #define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000C) /*!< ADC Oversampling ratio 16x */
bogdanm 0:9b334a45a8ff 468 #define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010) /*!< ADC Oversampling ratio 32x */
bogdanm 0:9b334a45a8ff 469 #define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014) /*!< ADC Oversampling ratio 64x */
bogdanm 0:9b334a45a8ff 470 #define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018) /*!< ADC Oversampling ratio 128x */
bogdanm 0:9b334a45a8ff 471 #define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001C) /*!< ADC Oversampling ratio 256x */
bogdanm 0:9b334a45a8ff 472 /**
bogdanm 0:9b334a45a8ff 473 * @}
bogdanm 0:9b334a45a8ff 474 */
bogdanm 0:9b334a45a8ff 475
mbed_official 113:b3775bf36a83 476 /** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
bogdanm 0:9b334a45a8ff 477 * @{
bogdanm 0:9b334a45a8ff 478 */
bogdanm 0:9b334a45a8ff 479 #define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
bogdanm 0:9b334a45a8ff 480 #define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020) /*!< ADC 1 bit shift for oversampling */
bogdanm 0:9b334a45a8ff 481 #define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040) /*!< ADC 2 bits shift for oversampling */
bogdanm 0:9b334a45a8ff 482 #define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060) /*!< ADC 3 bits shift for oversampling */
bogdanm 0:9b334a45a8ff 483 #define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080) /*!< ADC 4 bits shift for oversampling */
bogdanm 0:9b334a45a8ff 484 #define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0) /*!< ADC 5 bits shift for oversampling */
bogdanm 0:9b334a45a8ff 485 #define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0) /*!< ADC 6 bits shift for oversampling */
bogdanm 0:9b334a45a8ff 486 #define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0) /*!< ADC 7 bits shift for oversampling */
bogdanm 0:9b334a45a8ff 487 #define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100) /*!< ADC 8 bits shift for oversampling */
bogdanm 0:9b334a45a8ff 488 /**
bogdanm 0:9b334a45a8ff 489 * @}
bogdanm 0:9b334a45a8ff 490 */
bogdanm 0:9b334a45a8ff 491
mbed_official 113:b3775bf36a83 492 /** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
bogdanm 0:9b334a45a8ff 493 * @{
bogdanm 0:9b334a45a8ff 494 */
bogdanm 0:9b334a45a8ff 495 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */
bogdanm 0:9b334a45a8ff 496 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200) /*!< ADC No bit shift for oversampling */
bogdanm 0:9b334a45a8ff 497 /**
bogdanm 0:9b334a45a8ff 498 * @}
bogdanm 0:9b334a45a8ff 499 */
bogdanm 0:9b334a45a8ff 500
mbed_official 113:b3775bf36a83 501 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
bogdanm 0:9b334a45a8ff 502 * @{
bogdanm 0:9b334a45a8ff 503 */
bogdanm 0:9b334a45a8ff 504 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
bogdanm 0:9b334a45a8ff 505 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN))
bogdanm 0:9b334a45a8ff 506 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
bogdanm 0:9b334a45a8ff 507 /**
bogdanm 0:9b334a45a8ff 508 * @}
bogdanm 0:9b334a45a8ff 509 */
bogdanm 0:9b334a45a8ff 510
mbed_official 113:b3775bf36a83 511 /** @defgroup ADC_conversion_type ADC Conversion Group
bogdanm 0:9b334a45a8ff 512 * @{
bogdanm 0:9b334a45a8ff 513 */
bogdanm 0:9b334a45a8ff 514 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
bogdanm 0:9b334a45a8ff 515 /**
bogdanm 0:9b334a45a8ff 516 * @}
bogdanm 0:9b334a45a8ff 517 */
bogdanm 0:9b334a45a8ff 518
mbed_official 113:b3775bf36a83 519 /** @defgroup ADC_Event_type ADC Event
bogdanm 0:9b334a45a8ff 520 * @{
bogdanm 0:9b334a45a8ff 521 */
bogdanm 0:9b334a45a8ff 522 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
bogdanm 0:9b334a45a8ff 523 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
bogdanm 0:9b334a45a8ff 524 /**
bogdanm 0:9b334a45a8ff 525 * @}
bogdanm 0:9b334a45a8ff 526 */
bogdanm 0:9b334a45a8ff 527
mbed_official 113:b3775bf36a83 528 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
bogdanm 0:9b334a45a8ff 529 * @{
bogdanm 0:9b334a45a8ff 530 */
bogdanm 0:9b334a45a8ff 531 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready (ADRDY) interrupt source */
bogdanm 0:9b334a45a8ff 532 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */
bogdanm 0:9b334a45a8ff 533 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */
bogdanm 0:9b334a45a8ff 534 #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */
bogdanm 0:9b334a45a8ff 535 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
bogdanm 0:9b334a45a8ff 536 #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog 1 interrupt source */
bogdanm 0:9b334a45a8ff 537 #define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */
bogdanm 0:9b334a45a8ff 538 /**
bogdanm 0:9b334a45a8ff 539 * @}
bogdanm 0:9b334a45a8ff 540 */
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543
mbed_official 113:b3775bf36a83 544 /** @defgroup ADC_flags_definition ADC Flags Definition
bogdanm 0:9b334a45a8ff 545 * @{
bogdanm 0:9b334a45a8ff 546 */
bogdanm 0:9b334a45a8ff 547 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */
bogdanm 0:9b334a45a8ff 548 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
bogdanm 0:9b334a45a8ff 549 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
bogdanm 0:9b334a45a8ff 550 #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */
bogdanm 0:9b334a45a8ff 551 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
bogdanm 0:9b334a45a8ff 552 #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */
bogdanm 0:9b334a45a8ff 553 #define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC Enf Of Calibration flag */
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
bogdanm 0:9b334a45a8ff 557 ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL)
bogdanm 0:9b334a45a8ff 558 /**
bogdanm 0:9b334a45a8ff 559 * @}
bogdanm 0:9b334a45a8ff 560 */
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /**
bogdanm 0:9b334a45a8ff 563 * @}
bogdanm 0:9b334a45a8ff 564 */
bogdanm 0:9b334a45a8ff 565 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 566
mbed_official 113:b3775bf36a83 567 /** @defgroup ADC_Exported_Macro ADC Exported Macro
bogdanm 0:9b334a45a8ff 568 * @{
bogdanm 0:9b334a45a8ff 569 */
bogdanm 0:9b334a45a8ff 570 /** @brief Reset ADC handle state
bogdanm 0:9b334a45a8ff 571 * @param __HANDLE__: ADC handle
bogdanm 0:9b334a45a8ff 572 * @retval None
bogdanm 0:9b334a45a8ff 573 */
bogdanm 0:9b334a45a8ff 574 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /**
bogdanm 0:9b334a45a8ff 577 * @brief Enable the ADC peripheral
bogdanm 0:9b334a45a8ff 578 * @param __HANDLE__: ADC handle
bogdanm 0:9b334a45a8ff 579 * @retval None
bogdanm 0:9b334a45a8ff 580 */
bogdanm 0:9b334a45a8ff 581 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 /**
bogdanm 0:9b334a45a8ff 584 * @brief Verification of hardware constraints before ADC can be enabled
bogdanm 0:9b334a45a8ff 585 * @param __HANDLE__: ADC handle
bogdanm 0:9b334a45a8ff 586 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
bogdanm 0:9b334a45a8ff 587 */
bogdanm 0:9b334a45a8ff 588 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \
bogdanm 0:9b334a45a8ff 589 (( ( ((__HANDLE__)->Instance->CR) & \
bogdanm 0:9b334a45a8ff 590 (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \
bogdanm 0:9b334a45a8ff 591 ADC_CR_ADDIS | ADC_CR_ADEN ) \
bogdanm 0:9b334a45a8ff 592 ) == RESET \
bogdanm 0:9b334a45a8ff 593 ) ? SET : RESET)
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 /**
bogdanm 0:9b334a45a8ff 596 * @brief Disable the ADC peripheral
bogdanm 0:9b334a45a8ff 597 * @param __HANDLE__: ADC handle
bogdanm 0:9b334a45a8ff 598 * @retval None
bogdanm 0:9b334a45a8ff 599 */
bogdanm 0:9b334a45a8ff 600 #define __HAL_ADC_DISABLE(__HANDLE__) \
bogdanm 0:9b334a45a8ff 601 do{ \
bogdanm 0:9b334a45a8ff 602 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
bogdanm 0:9b334a45a8ff 603 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
bogdanm 0:9b334a45a8ff 604 } while(0)
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 /**
bogdanm 0:9b334a45a8ff 607 * @brief Verification of hardware constraints before ADC can be disabled
bogdanm 0:9b334a45a8ff 608 * @param __HANDLE__: ADC handle
bogdanm 0:9b334a45a8ff 609 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
bogdanm 0:9b334a45a8ff 610 */
bogdanm 0:9b334a45a8ff 611 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \
bogdanm 0:9b334a45a8ff 612 (( ( ((__HANDLE__)->Instance->CR) & \
bogdanm 0:9b334a45a8ff 613 (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
bogdanm 0:9b334a45a8ff 614 ) ? SET : RESET)
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 /**
bogdanm 0:9b334a45a8ff 617 * @brief Verification of ADC state: enabled or disabled
bogdanm 0:9b334a45a8ff 618 * @param __HANDLE__: ADC handle
bogdanm 0:9b334a45a8ff 619 * @retval SET (ADC enabled) or RESET (ADC disabled)
bogdanm 0:9b334a45a8ff 620 */
bogdanm 0:9b334a45a8ff 621 #define ADC_IS_ENABLE(__HANDLE__) \
bogdanm 0:9b334a45a8ff 622 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
bogdanm 0:9b334a45a8ff 623 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
bogdanm 0:9b334a45a8ff 624 ) ? SET : RESET)
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 /**
bogdanm 0:9b334a45a8ff 627 * @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
bogdanm 0:9b334a45a8ff 628 * @param __HANDLE__: ADC handle
bogdanm 0:9b334a45a8ff 629 * @retval None
bogdanm 0:9b334a45a8ff 630 */
bogdanm 0:9b334a45a8ff 631 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
mbed_official 113:b3775bf36a83 632 /**
mbed_official 113:b3775bf36a83 633 * @brief Test if conversion trigger of regular group is software start
mbed_official 113:b3775bf36a83 634 * or external trigger.
mbed_official 113:b3775bf36a83 635 * @param __HANDLE__: ADC handle
mbed_official 113:b3775bf36a83 636 * @retval SET (software start) or RESET (external trigger)
mbed_official 113:b3775bf36a83 637 */
mbed_official 113:b3775bf36a83 638 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
mbed_official 113:b3775bf36a83 639 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
mbed_official 113:b3775bf36a83 640
mbed_official 113:b3775bf36a83 641
bogdanm 0:9b334a45a8ff 642
bogdanm 0:9b334a45a8ff 643 /**
mbed_official 113:b3775bf36a83 644 * @brief Check if no conversion on going on regular group
bogdanm 0:9b334a45a8ff 645 * @param __HANDLE__: ADC handle
bogdanm 0:9b334a45a8ff 646 * @retval SET (conversion is on going) or RESET (no conversion is on going)
bogdanm 0:9b334a45a8ff 647 */
mbed_official 113:b3775bf36a83 648 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
mbed_official 113:b3775bf36a83 649 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
mbed_official 113:b3775bf36a83 650 ) ? RESET : SET)
bogdanm 0:9b334a45a8ff 651
bogdanm 0:9b334a45a8ff 652 /**
bogdanm 0:9b334a45a8ff 653 * @brief Enable ADC continuous conversion mode.
bogdanm 0:9b334a45a8ff 654 * @param _CONTINUOUS_MODE_: Continuous mode.
bogdanm 0:9b334a45a8ff 655 * @retval None
bogdanm 0:9b334a45a8ff 656 */
bogdanm 0:9b334a45a8ff 657 #define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 /**
bogdanm 0:9b334a45a8ff 660 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
bogdanm 0:9b334a45a8ff 661 * @param _SCAN_MODE_: Scan conversion mode.
bogdanm 0:9b334a45a8ff 662 * @retval None
bogdanm 0:9b334a45a8ff 663 */
bogdanm 0:9b334a45a8ff 664 #define ADC_SCANDIR(_SCAN_MODE_) \
bogdanm 0:9b334a45a8ff 665 ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
bogdanm 0:9b334a45a8ff 666 )? (ADC_CFGR1_SCANDIR) : (0x00000000) \
bogdanm 0:9b334a45a8ff 667 )
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669 /**
bogdanm 0:9b334a45a8ff 670 * @brief Configures the number of discontinuous conversions for the regular group channels.
bogdanm 0:9b334a45a8ff 671 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
bogdanm 0:9b334a45a8ff 672 * @retval None
bogdanm 0:9b334a45a8ff 673 */
bogdanm 0:9b334a45a8ff 674 #define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17)
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 /**
bogdanm 0:9b334a45a8ff 677 * @brief Enable the ADC DMA continuous request.
bogdanm 0:9b334a45a8ff 678 * @param _DMAContReq_MODE_: DMA continuous request mode.
bogdanm 0:9b334a45a8ff 679 * @retval None
bogdanm 0:9b334a45a8ff 680 */
bogdanm 0:9b334a45a8ff 681 #define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1)
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 /**
bogdanm 0:9b334a45a8ff 684 * @brief Enable the ADC Auto Delay.
bogdanm 0:9b334a45a8ff 685 * @param _AutoDelay_: Auto delay bit enable or disable.
bogdanm 0:9b334a45a8ff 686 * @retval None
bogdanm 0:9b334a45a8ff 687 */
bogdanm 0:9b334a45a8ff 688 #define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14)
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 /**
bogdanm 0:9b334a45a8ff 691 * @brief Enable the ADC LowPowerAutoPowerOff.
bogdanm 0:9b334a45a8ff 692 * @param _AUTOFF_: AutoOff bit enable or disable.
bogdanm 0:9b334a45a8ff 693 * @retval None
bogdanm 0:9b334a45a8ff 694 */
bogdanm 0:9b334a45a8ff 695 #define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15)
bogdanm 0:9b334a45a8ff 696
bogdanm 0:9b334a45a8ff 697 /**
bogdanm 0:9b334a45a8ff 698 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
bogdanm 0:9b334a45a8ff 699 * @param _Threshold_: Threshold value
bogdanm 0:9b334a45a8ff 700 * @retval None
bogdanm 0:9b334a45a8ff 701 */
bogdanm 0:9b334a45a8ff 702 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
bogdanm 0:9b334a45a8ff 703
mbed_official 113:b3775bf36a83 704 /**
bogdanm 0:9b334a45a8ff 705 * @brief Enable the ADC Low Frequency mode.
bogdanm 0:9b334a45a8ff 706 * @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
bogdanm 0:9b334a45a8ff 707 * @retval None
bogdanm 0:9b334a45a8ff 708 */
bogdanm 0:9b334a45a8ff 709 #define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25)
bogdanm 0:9b334a45a8ff 710
bogdanm 0:9b334a45a8ff 711 /**
bogdanm 0:9b334a45a8ff 712 * @brief Shift the offset in function of the selected ADC resolution.
bogdanm 0:9b334a45a8ff 713 * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
bogdanm 0:9b334a45a8ff 714 * If resolution 12 bits, no shift.
bogdanm 0:9b334a45a8ff 715 * If resolution 10 bits, shift of 2 ranks on the right.
bogdanm 0:9b334a45a8ff 716 * If resolution 8 bits, shift of 4 ranks on the right.
bogdanm 0:9b334a45a8ff 717 * If resolution 6 bits, shift of 6 ranks on the right.
bogdanm 0:9b334a45a8ff 718 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
bogdanm 0:9b334a45a8ff 719 * @param __HANDLE__: ADC handle.
bogdanm 0:9b334a45a8ff 720 * @param _Offset_: Value to be shifted
bogdanm 0:9b334a45a8ff 721 * @retval None
bogdanm 0:9b334a45a8ff 722 */
bogdanm 0:9b334a45a8ff 723 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
bogdanm 0:9b334a45a8ff 724 ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3)*2))
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726 /**
bogdanm 0:9b334a45a8ff 727 * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
bogdanm 0:9b334a45a8ff 728 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
bogdanm 0:9b334a45a8ff 729 * If resolution 12 bits, no shift.
bogdanm 0:9b334a45a8ff 730 * If resolution 10 bits, shift of 2 ranks on the right.
bogdanm 0:9b334a45a8ff 731 * If resolution 8 bits, shift of 4 ranks on the right.
bogdanm 0:9b334a45a8ff 732 * If resolution 6 bits, shift of 6 ranks on the right.
bogdanm 0:9b334a45a8ff 733 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
bogdanm 0:9b334a45a8ff 734 * @param __HANDLE__: ADC handle.
bogdanm 0:9b334a45a8ff 735 * @param _Threshold_: Value to be shifted
bogdanm 0:9b334a45a8ff 736 * @retval None
bogdanm 0:9b334a45a8ff 737 */
bogdanm 0:9b334a45a8ff 738 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
bogdanm 0:9b334a45a8ff 739 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2))
bogdanm 0:9b334a45a8ff 740
bogdanm 0:9b334a45a8ff 741 /**
bogdanm 0:9b334a45a8ff 742 * @brief Shift the value on the left, less significant are set to 0.
bogdanm 0:9b334a45a8ff 743 * @param _Value_: Value to be shifted
bogdanm 0:9b334a45a8ff 744 * @param _Shift_: Number of shift to be done
bogdanm 0:9b334a45a8ff 745 * @retval None
bogdanm 0:9b334a45a8ff 746 */
bogdanm 0:9b334a45a8ff 747 #define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
bogdanm 0:9b334a45a8ff 748
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 /**
bogdanm 0:9b334a45a8ff 751 * @brief Enable the ADC end of conversion interrupt.
bogdanm 0:9b334a45a8ff 752 * @param __HANDLE__: ADC handle.
bogdanm 0:9b334a45a8ff 753 * @param __INTERRUPT__: ADC Interrupt.
bogdanm 0:9b334a45a8ff 754 * @retval None
bogdanm 0:9b334a45a8ff 755 */
mbed_official 113:b3775bf36a83 756 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
mbed_official 113:b3775bf36a83 757 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 758
bogdanm 0:9b334a45a8ff 759 /**
bogdanm 0:9b334a45a8ff 760 * @brief Disable the ADC end of conversion interrupt.
bogdanm 0:9b334a45a8ff 761 * @param __HANDLE__: ADC handle.
bogdanm 0:9b334a45a8ff 762 * @param __INTERRUPT__: ADC interrupt.
bogdanm 0:9b334a45a8ff 763 * @retval None
bogdanm 0:9b334a45a8ff 764 */
mbed_official 113:b3775bf36a83 765 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
mbed_official 113:b3775bf36a83 766 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
bogdanm 0:9b334a45a8ff 767
bogdanm 0:9b334a45a8ff 768 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
mbed_official 113:b3775bf36a83 769 * @param __HANDLE__: ADC handle
mbed_official 113:b3775bf36a83 770 * @param __INTERRUPT__: ADC interrupt source to check
mbed_official 113:b3775bf36a83 771 * @arg ...
mbed_official 113:b3775bf36a83 772 * @arg ...
mbed_official 113:b3775bf36a83 773 * @retval State of interruption (TRUE or FALSE)
bogdanm 0:9b334a45a8ff 774 */
mbed_official 113:b3775bf36a83 775 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
mbed_official 113:b3775bf36a83 776 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 777
bogdanm 0:9b334a45a8ff 778 /**
bogdanm 0:9b334a45a8ff 779 * @brief Clear the ADC's pending flags
bogdanm 0:9b334a45a8ff 780 * @param __HANDLE__: ADC handle.
bogdanm 0:9b334a45a8ff 781 * @param __FLAG__: ADC flag.
bogdanm 0:9b334a45a8ff 782 * @retval None
bogdanm 0:9b334a45a8ff 783 */
bogdanm 0:9b334a45a8ff 784 /* Note: bit cleared bit by writing 1 */
mbed_official 113:b3775bf36a83 785 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
mbed_official 113:b3775bf36a83 786 (((__HANDLE__)->Instance->ISR) = (__FLAG__))
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 /**
bogdanm 0:9b334a45a8ff 789 * @brief Get the selected ADC's flag status.
bogdanm 0:9b334a45a8ff 790 * @param __HANDLE__: ADC handle.
bogdanm 0:9b334a45a8ff 791 * @param __FLAG__: ADC flag.
bogdanm 0:9b334a45a8ff 792 * @retval None
bogdanm 0:9b334a45a8ff 793 */
mbed_official 113:b3775bf36a83 794 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
mbed_official 113:b3775bf36a83 795 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
mbed_official 113:b3775bf36a83 796
mbed_official 113:b3775bf36a83 797
mbed_official 113:b3775bf36a83 798 /**
mbed_official 113:b3775bf36a83 799 * @brief Simultaneously clears and sets specific bits of the handle State
mbed_official 113:b3775bf36a83 800 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
mbed_official 113:b3775bf36a83 801 * the first parameter is the ADC handle State, the second parameter is the
mbed_official 113:b3775bf36a83 802 * bit field to clear, the third and last parameter is the bit field to set.
mbed_official 113:b3775bf36a83 803 * @retval None
mbed_official 113:b3775bf36a83 804 */
mbed_official 113:b3775bf36a83 805 #define ADC_STATE_CLR_SET MODIFY_REG
mbed_official 113:b3775bf36a83 806
mbed_official 113:b3775bf36a83 807 /**
mbed_official 113:b3775bf36a83 808 * @brief Clear ADC error code (set it to error code: "no error")
mbed_official 113:b3775bf36a83 809 * @param __HANDLE__: ADC handle
mbed_official 113:b3775bf36a83 810 * @retval None
mbed_official 113:b3775bf36a83 811 */
mbed_official 113:b3775bf36a83 812 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
mbed_official 113:b3775bf36a83 813 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
mbed_official 113:b3775bf36a83 814
bogdanm 0:9b334a45a8ff 815
bogdanm 0:9b334a45a8ff 816
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818 /**
bogdanm 0:9b334a45a8ff 819 * @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
bogdanm 0:9b334a45a8ff 820 * @param __HANDLE__: ADC handle
bogdanm 0:9b334a45a8ff 821 * @retval None
bogdanm 0:9b334a45a8ff 822 */
bogdanm 0:9b334a45a8ff 823
bogdanm 0:9b334a45a8ff 824 #define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \
bogdanm 0:9b334a45a8ff 825 do{ \
bogdanm 0:9b334a45a8ff 826 if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
bogdanm 0:9b334a45a8ff 827 (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
bogdanm 0:9b334a45a8ff 828 (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \
bogdanm 0:9b334a45a8ff 829 { \
bogdanm 0:9b334a45a8ff 830 (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
bogdanm 0:9b334a45a8ff 831 (__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; \
bogdanm 0:9b334a45a8ff 832 } \
bogdanm 0:9b334a45a8ff 833 else \
bogdanm 0:9b334a45a8ff 834 { \
bogdanm 0:9b334a45a8ff 835 /* CKMOD bits must be reset */ \
bogdanm 0:9b334a45a8ff 836 (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
bogdanm 0:9b334a45a8ff 837 ADC->CCR &= ~(ADC_CCR_PRESC); \
bogdanm 0:9b334a45a8ff 838 ADC->CCR |= (__HANDLE__)->Init.ClockPrescaler; \
bogdanm 0:9b334a45a8ff 839 } \
bogdanm 0:9b334a45a8ff 840 } while(0)
bogdanm 0:9b334a45a8ff 841
mbed_official 113:b3775bf36a83 842
mbed_official 113:b3775bf36a83 843 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\
mbed_official 113:b3775bf36a83 844 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
mbed_official 113:b3775bf36a83 845 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
mbed_official 113:b3775bf36a83 846 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
mbed_official 113:b3775bf36a83 847 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\
mbed_official 113:b3775bf36a83 848 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\
mbed_official 113:b3775bf36a83 849 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\
mbed_official 113:b3775bf36a83 850 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\
mbed_official 113:b3775bf36a83 851 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\
mbed_official 113:b3775bf36a83 852 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\
mbed_official 113:b3775bf36a83 853 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\
mbed_official 113:b3775bf36a83 854 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\
mbed_official 113:b3775bf36a83 855 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\
mbed_official 113:b3775bf36a83 856 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\
mbed_official 113:b3775bf36a83 857 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\
mbed_official 113:b3775bf36a83 858 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
mbed_official 113:b3775bf36a83 859
mbed_official 113:b3775bf36a83 860 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
mbed_official 113:b3775bf36a83 861 ((RESOLUTION) == ADC_RESOLUTION_10B) || \
mbed_official 113:b3775bf36a83 862 ((RESOLUTION) == ADC_RESOLUTION_8B) || \
mbed_official 113:b3775bf36a83 863 ((RESOLUTION) == ADC_RESOLUTION_6B))
mbed_official 113:b3775bf36a83 864
mbed_official 113:b3775bf36a83 865 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
mbed_official 113:b3775bf36a83 866 ((RESOLUTION) == ADC_RESOLUTION_6B))
mbed_official 113:b3775bf36a83 867
mbed_official 113:b3775bf36a83 868 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
mbed_official 113:b3775bf36a83 869 ((ALIGN) == ADC_DATAALIGN_LEFT))
mbed_official 113:b3775bf36a83 870
mbed_official 113:b3775bf36a83 871 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
mbed_official 113:b3775bf36a83 872 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
mbed_official 113:b3775bf36a83 873 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
mbed_official 113:b3775bf36a83 874 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
mbed_official 113:b3775bf36a83 875
mbed_official 113:b3775bf36a83 876 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
mbed_official 113:b3775bf36a83 877 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
mbed_official 113:b3775bf36a83 878 ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
mbed_official 113:b3775bf36a83 879
mbed_official 113:b3775bf36a83 880 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
mbed_official 113:b3775bf36a83 881 ((OVR) == ADC_OVR_DATA_OVERWRITTEN))
mbed_official 113:b3775bf36a83 882
mbed_official 113:b3775bf36a83 883 #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \
mbed_official 113:b3775bf36a83 884 ((WATCHDOG) == ADC_RANK_NONE))
mbed_official 113:b3775bf36a83 885
mbed_official 113:b3775bf36a83 886 #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx)
mbed_official 113:b3775bf36a83 887 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
mbed_official 113:b3775bf36a83 888 ((CHANNEL) == ADC_CHANNEL_1) || \
mbed_official 113:b3775bf36a83 889 ((CHANNEL) == ADC_CHANNEL_2) || \
mbed_official 113:b3775bf36a83 890 ((CHANNEL) == ADC_CHANNEL_3) || \
mbed_official 113:b3775bf36a83 891 ((CHANNEL) == ADC_CHANNEL_4) || \
mbed_official 113:b3775bf36a83 892 ((CHANNEL) == ADC_CHANNEL_5) || \
mbed_official 113:b3775bf36a83 893 ((CHANNEL) == ADC_CHANNEL_6) || \
mbed_official 113:b3775bf36a83 894 ((CHANNEL) == ADC_CHANNEL_7) || \
mbed_official 113:b3775bf36a83 895 ((CHANNEL) == ADC_CHANNEL_8) || \
mbed_official 113:b3775bf36a83 896 ((CHANNEL) == ADC_CHANNEL_9) || \
mbed_official 113:b3775bf36a83 897 ((CHANNEL) == ADC_CHANNEL_10) || \
mbed_official 113:b3775bf36a83 898 ((CHANNEL) == ADC_CHANNEL_11) || \
mbed_official 113:b3775bf36a83 899 ((CHANNEL) == ADC_CHANNEL_12) || \
mbed_official 113:b3775bf36a83 900 ((CHANNEL) == ADC_CHANNEL_13) || \
mbed_official 113:b3775bf36a83 901 ((CHANNEL) == ADC_CHANNEL_14) || \
mbed_official 113:b3775bf36a83 902 ((CHANNEL) == ADC_CHANNEL_15) || \
mbed_official 113:b3775bf36a83 903 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
mbed_official 113:b3775bf36a83 904 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
mbed_official 113:b3775bf36a83 905 ((CHANNEL) == ADC_CHANNEL_VLCD))
mbed_official 113:b3775bf36a83 906 #else
mbed_official 113:b3775bf36a83 907 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
mbed_official 113:b3775bf36a83 908 ((CHANNEL) == ADC_CHANNEL_1) || \
mbed_official 113:b3775bf36a83 909 ((CHANNEL) == ADC_CHANNEL_2) || \
mbed_official 113:b3775bf36a83 910 ((CHANNEL) == ADC_CHANNEL_3) || \
mbed_official 113:b3775bf36a83 911 ((CHANNEL) == ADC_CHANNEL_4) || \
mbed_official 113:b3775bf36a83 912 ((CHANNEL) == ADC_CHANNEL_5) || \
mbed_official 113:b3775bf36a83 913 ((CHANNEL) == ADC_CHANNEL_6) || \
mbed_official 113:b3775bf36a83 914 ((CHANNEL) == ADC_CHANNEL_7) || \
mbed_official 113:b3775bf36a83 915 ((CHANNEL) == ADC_CHANNEL_8) || \
mbed_official 113:b3775bf36a83 916 ((CHANNEL) == ADC_CHANNEL_9) || \
mbed_official 113:b3775bf36a83 917 ((CHANNEL) == ADC_CHANNEL_10) || \
mbed_official 113:b3775bf36a83 918 ((CHANNEL) == ADC_CHANNEL_11) || \
mbed_official 113:b3775bf36a83 919 ((CHANNEL) == ADC_CHANNEL_12) || \
mbed_official 113:b3775bf36a83 920 ((CHANNEL) == ADC_CHANNEL_13) || \
mbed_official 113:b3775bf36a83 921 ((CHANNEL) == ADC_CHANNEL_14) || \
mbed_official 113:b3775bf36a83 922 ((CHANNEL) == ADC_CHANNEL_15) || \
mbed_official 113:b3775bf36a83 923 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
mbed_official 113:b3775bf36a83 924 ((CHANNEL) == ADC_CHANNEL_VREFINT))
mbed_official 113:b3775bf36a83 925 #endif
mbed_official 113:b3775bf36a83 926
mbed_official 113:b3775bf36a83 927 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \
mbed_official 113:b3775bf36a83 928 ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \
mbed_official 113:b3775bf36a83 929 ((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) || \
mbed_official 113:b3775bf36a83 930 ((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) || \
mbed_official 113:b3775bf36a83 931 ((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) || \
mbed_official 113:b3775bf36a83 932 ((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) || \
mbed_official 113:b3775bf36a83 933 ((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) || \
mbed_official 113:b3775bf36a83 934 ((TIME) == ADC_SAMPLETIME_239CYCLES_5))
mbed_official 113:b3775bf36a83 935
mbed_official 113:b3775bf36a83 936 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
mbed_official 113:b3775bf36a83 937 ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
mbed_official 113:b3775bf36a83 938
mbed_official 113:b3775bf36a83 939 #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \
mbed_official 113:b3775bf36a83 940 ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \
mbed_official 113:b3775bf36a83 941 ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \
mbed_official 113:b3775bf36a83 942 ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \
mbed_official 113:b3775bf36a83 943 ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \
mbed_official 113:b3775bf36a83 944 ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \
mbed_official 113:b3775bf36a83 945 ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \
mbed_official 113:b3775bf36a83 946 ((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
mbed_official 113:b3775bf36a83 947
mbed_official 113:b3775bf36a83 948 #define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \
mbed_official 113:b3775bf36a83 949 ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \
mbed_official 113:b3775bf36a83 950 ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \
mbed_official 113:b3775bf36a83 951 ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \
mbed_official 113:b3775bf36a83 952 ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \
mbed_official 113:b3775bf36a83 953 ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \
mbed_official 113:b3775bf36a83 954 ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \
mbed_official 113:b3775bf36a83 955 ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \
mbed_official 113:b3775bf36a83 956 ((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
mbed_official 113:b3775bf36a83 957
mbed_official 113:b3775bf36a83 958 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
mbed_official 113:b3775bf36a83 959 ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
mbed_official 113:b3775bf36a83 960
mbed_official 113:b3775bf36a83 961 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \
mbed_official 113:b3775bf36a83 962 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
mbed_official 113:b3775bf36a83 963 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
mbed_official 113:b3775bf36a83 964
mbed_official 113:b3775bf36a83 965 #define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
mbed_official 113:b3775bf36a83 966
mbed_official 113:b3775bf36a83 967 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
mbed_official 113:b3775bf36a83 968 ((EVENT) == ADC_OVR_EVENT))
mbed_official 113:b3775bf36a83 969
mbed_official 113:b3775bf36a83 970
mbed_official 113:b3775bf36a83 971 /** @defgroup ADC_range_verification ADC Range Verification
mbed_official 113:b3775bf36a83 972 * in function of ADC resolution selected (12, 10, 8 or 6 bits)
mbed_official 113:b3775bf36a83 973 * @{
mbed_official 113:b3775bf36a83 974 */
mbed_official 113:b3775bf36a83 975 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
mbed_official 113:b3775bf36a83 976 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
mbed_official 113:b3775bf36a83 977 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
mbed_official 113:b3775bf36a83 978 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
mbed_official 113:b3775bf36a83 979 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
mbed_official 113:b3775bf36a83 980 /**
mbed_official 113:b3775bf36a83 981 * @}
mbed_official 113:b3775bf36a83 982 */
mbed_official 113:b3775bf36a83 983
mbed_official 113:b3775bf36a83 984 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
mbed_official 113:b3775bf36a83 985 * @{
mbed_official 113:b3775bf36a83 986 */
mbed_official 113:b3775bf36a83 987 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
mbed_official 113:b3775bf36a83 988 /**
mbed_official 113:b3775bf36a83 989 * @}
mbed_official 113:b3775bf36a83 990 */
mbed_official 113:b3775bf36a83 991
bogdanm 0:9b334a45a8ff 992 /**
bogdanm 0:9b334a45a8ff 993 * @}
bogdanm 0:9b334a45a8ff 994 */
bogdanm 0:9b334a45a8ff 995
bogdanm 0:9b334a45a8ff 996 /* Include ADC HAL Extension module */
bogdanm 0:9b334a45a8ff 997 #include "stm32l0xx_hal_adc_ex.h"
bogdanm 0:9b334a45a8ff 998
bogdanm 0:9b334a45a8ff 999 /* Exported functions --------------------------------------------------------*/
mbed_official 113:b3775bf36a83 1000 /** @defgroup ADC_Exported_Functions ADC Exported Functions
mbed_official 113:b3775bf36a83 1001 * @{
mbed_official 113:b3775bf36a83 1002 */
bogdanm 0:9b334a45a8ff 1003 /* Initialization and de-initialization functions **********************************/
mbed_official 113:b3775bf36a83 1004 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 113:b3775bf36a83 1005 * @brief Initialization and de-initialization functions
mbed_official 113:b3775bf36a83 1006 * @{
mbed_official 113:b3775bf36a83 1007 */
bogdanm 0:9b334a45a8ff 1008 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1009 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
bogdanm 0:9b334a45a8ff 1010 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1011 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
mbed_official 113:b3775bf36a83 1012 /**
mbed_official 113:b3775bf36a83 1013 * @}
mbed_official 113:b3775bf36a83 1014 */
bogdanm 0:9b334a45a8ff 1015
bogdanm 0:9b334a45a8ff 1016 /* IO operation functions *****************************************************/
mbed_official 113:b3775bf36a83 1017 /** @defgroup ADC_Exported_Functions_Group2 I/O operation functions
mbed_official 113:b3775bf36a83 1018 * @{
mbed_official 113:b3775bf36a83 1019 */
bogdanm 0:9b334a45a8ff 1020 /* Blocking mode: Polling */
bogdanm 0:9b334a45a8ff 1021 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1022 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1023 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 1024 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
bogdanm 0:9b334a45a8ff 1025
bogdanm 0:9b334a45a8ff 1026 /* Non-blocking mode: Interruption */
bogdanm 0:9b334a45a8ff 1027 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1028 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1029
bogdanm 0:9b334a45a8ff 1030 /* Non-blocking mode: DMA */
bogdanm 0:9b334a45a8ff 1031 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
bogdanm 0:9b334a45a8ff 1032 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1033
bogdanm 0:9b334a45a8ff 1034 /* ADC retrieve conversion value intended to be used with polling or interruption */
bogdanm 0:9b334a45a8ff 1035 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1036
bogdanm 0:9b334a45a8ff 1037 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
mbed_official 113:b3775bf36a83 1038 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1039 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1040 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1041 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1042 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
mbed_official 113:b3775bf36a83 1043 /**
mbed_official 113:b3775bf36a83 1044 * @}
mbed_official 113:b3775bf36a83 1045 */
bogdanm 0:9b334a45a8ff 1046
bogdanm 0:9b334a45a8ff 1047 /* Peripheral Control functions ***********************************************/
mbed_official 113:b3775bf36a83 1048 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
mbed_official 113:b3775bf36a83 1049 * @{
mbed_official 113:b3775bf36a83 1050 */
bogdanm 0:9b334a45a8ff 1051 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
bogdanm 0:9b334a45a8ff 1052 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
mbed_official 113:b3775bf36a83 1053 /**
mbed_official 113:b3775bf36a83 1054 * @}
mbed_official 113:b3775bf36a83 1055 */
bogdanm 0:9b334a45a8ff 1056
bogdanm 0:9b334a45a8ff 1057 /* Peripheral State functions *************************************************/
mbed_official 113:b3775bf36a83 1058 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
mbed_official 113:b3775bf36a83 1059 * @{
mbed_official 113:b3775bf36a83 1060 */
mbed_official 113:b3775bf36a83 1061 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
bogdanm 0:9b334a45a8ff 1062 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
mbed_official 113:b3775bf36a83 1063 /**
mbed_official 113:b3775bf36a83 1064 * @}
mbed_official 113:b3775bf36a83 1065 */
bogdanm 0:9b334a45a8ff 1066
bogdanm 0:9b334a45a8ff 1067
bogdanm 0:9b334a45a8ff 1068 /**
bogdanm 0:9b334a45a8ff 1069 * @}
bogdanm 0:9b334a45a8ff 1070 */
bogdanm 0:9b334a45a8ff 1071
mbed_official 113:b3775bf36a83 1072 /* Define the private group ***********************************/
mbed_official 113:b3775bf36a83 1073 /**************************************************************/
mbed_official 113:b3775bf36a83 1074 /** @defgroup ADC_Private ADC Private
mbed_official 113:b3775bf36a83 1075 * @{
mbed_official 113:b3775bf36a83 1076 */
mbed_official 113:b3775bf36a83 1077 /**
mbed_official 113:b3775bf36a83 1078 * @}
mbed_official 113:b3775bf36a83 1079 */
mbed_official 113:b3775bf36a83 1080 /**************************************************************/
mbed_official 113:b3775bf36a83 1081
mbed_official 113:b3775bf36a83 1082 /**
mbed_official 113:b3775bf36a83 1083 * @}
mbed_official 113:b3775bf36a83 1084 */
mbed_official 113:b3775bf36a83 1085
bogdanm 0:9b334a45a8ff 1086 /**
bogdanm 0:9b334a45a8ff 1087 * @}
bogdanm 0:9b334a45a8ff 1088 */
bogdanm 0:9b334a45a8ff 1089
bogdanm 0:9b334a45a8ff 1090 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 1091 }
bogdanm 0:9b334a45a8ff 1092 #endif
bogdanm 0:9b334a45a8ff 1093
bogdanm 0:9b334a45a8ff 1094 #endif /*__STM32L0xx_ADC_H */
bogdanm 0:9b334a45a8ff 1095
bogdanm 0:9b334a45a8ff 1096
bogdanm 0:9b334a45a8ff 1097 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/