Gymtrack / RFIDTestNFC

interrupt handling

Dependencies:  

main.cpp@5:93c612f43ec2, 2015-04-01 (annotated)

Committer:
soumi_ghsoh
Date:
Wed Apr 01 22:06:40 2015 +0000
Revision:
5:93c612f43ec2
Parent:
4:9ab0d84bbd07
Child:
6:3c510c297e2f
TAG read with multiple instances of RX complete IRQ; Imp changes: reduced RX wait time, Vin=3V/AGC ON, RX_IN2(main) , RX_IN1(aux)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rwclough 1:1eb96189824d 1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 2 Filename: main.cpp
rwclough 1:1eb96189824d 3 Description: Interface nRF51-DK eval board to TRF7970 eval board
rwclough 1:1eb96189824d 4 to test the suitability of the TRF7970 NFC chip
rwclough 1:1eb96189824d 5 for use in Gymtrack products.
rwclough 1:1eb96189824d 6 The nRF51-DK board has an nRF51422 MCU.
rwclough 1:1eb96189824d 7 Copyright (C) 2015 Gymtrack, Inc.
rwclough 1:1eb96189824d 8 Author: Ron Clough
rwclough 1:1eb96189824d 9 Date: 2015-02-26
rwclough 1:1eb96189824d 10
rwclough 1:1eb96189824d 11 Changes:
rwclough 1:1eb96189824d 12 Rev Date Who Details
rwclough 1:1eb96189824d 13 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
rwclough 1:1eb96189824d 14 0.0 2015-02-26 RWC Original version.
rwclough 1:1eb96189824d 15
rwclough 1:1eb96189824d 16 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
rwclough 0:5622c60e9d3a 17
rwclough 1:1eb96189824d 18 #include "mbed.h"
soumi_ghsoh 5:93c612f43ec2 19
soumi_ghsoh 5:93c612f43ec2 20 //#include "NFC_7970.h"
rwclough 1:1eb96189824d 21 #include "readerComm.h"
rwclough 2:bd5afc5aa139 22 #include "interruptStuff.h"
rwclough 0:5622c60e9d3a 23
rwclough 1:1eb96189824d 24 SPI spi(p25, p28, p29); // MOSI, MISO, SCLK
soumi_ghsoh 5:93c612f43ec2 25 // Slave Select (SS)
rwclough 1:1eb96189824d 26 Serial pc(USBTX, USBRX); // Serial communication over USB with PC
rwclough 3:eaae5433ab45 27 DigitalOut heartbeatLED(LED4); // "Heartbeat" LED
rwclough 3:eaae5433ab45 28 DigitalOut debug2LED(LED2); // "Debug2" LED
rwclough 3:eaae5433ab45 29 DigitalOut ISO15693LED(LED3); // "Detected ISO15693 tag" LED
rwclough 3:eaae5433ab45 30 DigitalOut debug1LED(LED1); // "Debug1" LED
rwclough 4:9ab0d84bbd07 31 DigitalInOut ook_ask(p6); // Control ASK/OOK pin on TRF7970
rwclough 1:1eb96189824d 32 DigitalOut mod(p5); // Control MOD pin on TRF7970
rwclough 0:5622c60e9d3a 33
rwclough 3:eaae5433ab45 34 DigitalOut testPin(p1);
rwclough 3:eaae5433ab45 35
rwclough 2:bd5afc5aa139 36 uint8_t buffer[2];
rwclough 2:bd5afc5aa139 37 int8_t rxtxState = 1; // Transmit/Receive byte count
rwclough 2:bd5afc5aa139 38 uint8_t buf[300];
rwclough 2:bd5afc5aa139 39 uint8_t irqRegister = 0x01; // Interrupt register
rwclough 3:eaae5433ab45 40 volatile uint8_t irqFlag = 0x00;
rwclough 2:bd5afc5aa139 41 uint8_t rxErrorFlag = 0x00;
rwclough 3:eaae5433ab45 42 uint8_t readerMode; // Determines how interrupts will be handled
rwclough 2:bd5afc5aa139 43 int16_t nfc_state;
rwclough 2:bd5afc5aa139 44 uint8_t nfc_protocol;
rwclough 2:bd5afc5aa139 45 uint8_t active;
rwclough 2:bd5afc5aa139 46 uint8_t tagFlag;
rwclough 3:eaae5433ab45 47 uint8_t irqCount = 0;
rwclough 0:5622c60e9d3a 48
rwclough 4:9ab0d84bbd07 49 uint8_t debugBuffer[1000]; // Capture data for analysis
rwclough 4:9ab0d84bbd07 50 uint8_t bufIdx=0;
soumi_ghsoh 5:93c612f43ec2 51 extern uint8_t turnRFOn[2];
rwclough 4:9ab0d84bbd07 52
soumi_ghsoh 5:93c612f43ec2 53 extern uint8_t testcommand[2];
rwclough 2:bd5afc5aa139 54 void blinkHeartbeatLED(void)
rwclough 1:1eb96189824d 55 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 1:1eb96189824d 56 // blinkHeartbeatLED()
rwclough 1:1eb96189824d 57 // Description: Toogle the heartbeat LED.
rwclough 1:1eb96189824d 58 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 59 {
rwclough 1:1eb96189824d 60 heartbeatLED = !heartbeatLED;
rwclough 1:1eb96189824d 61 } // End of blinkHeartbeatLED()
rwclough 0:5622c60e9d3a 62
rwclough 2:bd5afc5aa139 63 int main()
soumi_ghsoh 5:93c612f43ec2 64 {pc.baud(115200);
soumi_ghsoh 5:93c612f43ec2 65 PowerUpNFC();
rwclough 3:eaae5433ab45 66 // Power up sequence. See TRF7970A datasheet "SLOU43K August 2011 Revised April 20914" Figures 6-3 and 6-4.
soumi_ghsoh 5:93c612f43ec2 67 SpiInit1();
soumi_ghsoh 5:93c612f43ec2 68 NFCInit();
soumi_ghsoh 5:93c612f43ec2 69 SpiInit2();
soumi_ghsoh 5:93c612f43ec2 70 wait_ms(15);
soumi_ghsoh 5:93c612f43ec2 71
soumi_ghsoh 5:93c612f43ec2 72 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 73 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 74 //
soumi_ghsoh 5:93c612f43ec2 75 //trf797xReadSingle(&turnRFOn[1], 1);
soumi_ghsoh 5:93c612f43ec2 76 turnRFOn[1] &= 0x3F;
soumi_ghsoh 5:93c612f43ec2 77 turnRFOn[1] |= 0x2C;
soumi_ghsoh 5:93c612f43ec2 78 // Oroiginal code has 0x20 !!!
soumi_ghsoh 5:93c612f43ec2 79 trf797xReadSingle(turnRFOn, 1);
soumi_ghsoh 5:93c612f43ec2 80 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 81 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 82
soumi_ghsoh 5:93c612f43ec2 83 turnRFOn[1] &= 0x3F;
soumi_ghsoh 5:93c612f43ec2 84 turnRFOn[1] |= 0x2C;
soumi_ghsoh 5:93c612f43ec2 85 trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 5:93c612f43ec2 86 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 87
soumi_ghsoh 5:93c612f43ec2 88 testcommand[0] = ISO_CONTROL;
soumi_ghsoh 5:93c612f43ec2 89 testcommand[1] = 0x02; // 6.78 MHz, OOK 100%
soumi_ghsoh 5:93c612f43ec2 90 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 91 wait_ms(6);
soumi_ghsoh 5:93c612f43ec2 92 // mod = 0;
rwclough 3:eaae5433ab45 93 testPin = 0;
rwclough 1:1eb96189824d 94 // Setup serial communication
soumi_ghsoh 5:93c612f43ec2 95
rwclough 3:eaae5433ab45 96 // printf("\r\nInitialization: ");
rwclough 3:eaae5433ab45 97
rwclough 3:eaae5433ab45 98 /*
rwclough 3:eaae5433ab45 99 // After power up sequence, Chip Status = 0x81, Regulator Control = 0x80
rwclough 3:eaae5433ab45 100 *buffer = CHIP_STATUS_CONTROL;
rwclough 3:eaae5433ab45 101 spiReadContinuous(buffer, 2);
rwclough 3:eaae5433ab45 102 printf("\r\nChip Status: 0x%X\r\n", buffer[1]);
rwclough 3:eaae5433ab45 103 *buffer = REGULATOR_CONTROL;
rwclough 3:eaae5433ab45 104 spiReadContinuous(buffer, 2);
rwclough 3:eaae5433ab45 105 printf("Regulator Control: 0x%X\r\n", buffer[1]);
rwclough 3:eaae5433ab45 106 */
rwclough 3:eaae5433ab45 107
soumi_ghsoh 5:93c612f43ec2 108 heartbeatLED = LED_OFF;
rwclough 2:bd5afc5aa139 109 ISO15693LED = LED_OFF;
rwclough 3:eaae5433ab45 110 debug1LED = LED_OFF;
rwclough 3:eaae5433ab45 111 debug2LED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 112
soumi_ghsoh 5:93c612f43ec2 113 ook_ask.output(); // Set On-Off Keying modulation
soumi_ghsoh 5:93c612f43ec2 114 ook_ask = 1;
soumi_ghsoh 5:93c612f43ec2 115
soumi_ghsoh 5:93c612f43ec2 116 //******************************************
soumi_ghsoh 5:93c612f43ec2 117
soumi_ghsoh 5:93c612f43ec2 118 //testcommand[0] = ISO_CONTROL;
soumi_ghsoh 5:93c612f43ec2 119 //testcommand[1] = 0x21;
soumi_ghsoh 5:93c612f43ec2 120 //trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 121 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 5:93c612f43ec2 122 //trf797xReadContinuous(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 123 //turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 124 //turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 125 //turnRFOn[1] &= 0x3F;
soumi_ghsoh 5:93c612f43ec2 126 //turnRFOn[1] |= 0x21;
soumi_ghsoh 5:93c612f43ec2 127 //trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 5:93c612f43ec2 128 //testcommand[0] = ISO_CONTROL;
soumi_ghsoh 5:93c612f43ec2 129 //testcommand[1] = 0x00;
soumi_ghsoh 5:93c612f43ec2 130 //trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 131 //testcommand[0] = ISO_CONTROL;
soumi_ghsoh 5:93c612f43ec2 132 //testcommand[1] = 0x00;
soumi_ghsoh 5:93c612f43ec2 133 //trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 134 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 5:93c612f43ec2 135 //trf797xReadContinuous(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 136 //turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 137 //trf797xReadSingle(&turnRFOn[0], 1);
soumi_ghsoh 5:93c612f43ec2 138
soumi_ghsoh 5:93c612f43ec2 139 //
soumi_ghsoh 5:93c612f43ec2 140 //turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 141 //turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 142 //turnRFOn[1] &= 0x3F;
soumi_ghsoh 5:93c612f43ec2 143 //turnRFOn[1] |= 0x21;
soumi_ghsoh 5:93c612f43ec2 144 //trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 5:93c612f43ec2 145 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 5:93c612f43ec2 146 //trf797xReadContinuous(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 147 //turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 148 //trf797xReadSingle(&turnRFOn[0], 1);
soumi_ghsoh 5:93c612f43ec2 149 //
soumi_ghsoh 5:93c612f43ec2 150 //
soumi_ghsoh 5:93c612f43ec2 151 //turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 152 //turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 153 //turnRFOn[1] &= 0x3F;
soumi_ghsoh 5:93c612f43ec2 154 //turnRFOn[1] |= 0x21;
soumi_ghsoh 5:93c612f43ec2 155 //trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 5:93c612f43ec2 156 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 5:93c612f43ec2 157 //trf797xReadContinuous(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 158 //*********************************************
soumi_ghsoh 5:93c612f43ec2 159
soumi_ghsoh 5:93c612f43ec2 160 RegisterReInitNFC();
soumi_ghsoh 5:93c612f43ec2 161
soumi_ghsoh 5:93c612f43ec2 162
soumi_ghsoh 5:93c612f43ec2 163 testcommand[0] = TX_TIMER_EPC_HIGH;
soumi_ghsoh 5:93c612f43ec2 164 //testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 165 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 166 testcommand[0] = TX_TIMER_EPC_LOW ;
soumi_ghsoh 5:93c612f43ec2 167 //testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 168 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 169 testcommand[0] = TX_PULSE_LENGTH_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 170 //testcommand[1] = 0x00;
soumi_ghsoh 5:93c612f43ec2 171 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 172 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 5:93c612f43ec2 173 //testcommand[1] = 0x30;
soumi_ghsoh 5:93c612f43ec2 174 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 175 testcommand[0] = RX_WAIT_TIME ;
soumi_ghsoh 5:93c612f43ec2 176 //testcommand[1] = 0x1F;
soumi_ghsoh 5:93c612f43ec2 177 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 178 testcommand[0] = MODULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 179 //testcommand[1] = 0x21; //0x34 100%ook@13MHz
soumi_ghsoh 5:93c612f43ec2 180 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 181 testcommand[0] = RX_SPECIAL_SETTINGS ;
soumi_ghsoh 5:93c612f43ec2 182 //testcommand[1] = 0x40;
soumi_ghsoh 5:93c612f43ec2 183 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 184 testcommand[0] = REGULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 185 //testcommand[1] = 0x87;
soumi_ghsoh 5:93c612f43ec2 186 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 187
soumi_ghsoh 5:93c612f43ec2 188 //}
soumi_ghsoh 5:93c612f43ec2 189
soumi_ghsoh 5:93c612f43ec2 190
soumi_ghsoh 5:93c612f43ec2 191
soumi_ghsoh 5:93c612f43ec2 192 //RegisterReInitNFC();
soumi_ghsoh 5:93c612f43ec2 193 //
soumi_ghsoh 5:93c612f43ec2 194 /* ook_ask.input(); // Tri-state OOK pin
soumi_ghsoh 5:93c612f43ec2 195 ook_ask.mode(PullUp);*/
soumi_ghsoh 5:93c612f43ec2 196 //
soumi_ghsoh 5:93c612f43ec2 197 ////readerInt.enable_irq();
soumi_ghsoh 5:93c612f43ec2 198 ////========================================================================
soumi_ghsoh 5:93c612f43ec2 199 //
soumi_ghsoh 5:93c612f43ec2 200
soumi_ghsoh 5:93c612f43ec2 201 while(1)
soumi_ghsoh 5:93c612f43ec2 202 {
soumi_ghsoh 5:93c612f43ec2 203
soumi_ghsoh 5:93c612f43ec2 204 //send inventory command==================================================
soumi_ghsoh 5:93c612f43ec2 205 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 5:93c612f43ec2 206 buf[1]=0x91;
soumi_ghsoh 5:93c612f43ec2 207 buf[2]=0x3D;
soumi_ghsoh 5:93c612f43ec2 208 buf[3]=0x00;
soumi_ghsoh 5:93c612f43ec2 209 buf[4]=0x30;
soumi_ghsoh 5:93c612f43ec2 210 buf[5]=0x26;
soumi_ghsoh 5:93c612f43ec2 211 buf[6]=0x01;
soumi_ghsoh 5:93c612f43ec2 212 buf[7]=0x00;
soumi_ghsoh 5:93c612f43ec2 213
soumi_ghsoh 5:93c612f43ec2 214 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 5:93c612f43ec2 215
soumi_ghsoh 5:93c612f43ec2 216 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 217
soumi_ghsoh 5:93c612f43ec2 218 testcommand[0] = IRQ_STATUS; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 219 trf797xReadSingle(testcommand,1);
soumi_ghsoh 5:93c612f43ec2 220 testcommand[0] = IRQ_STATUS; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 221 trf797xReadSingle(testcommand,1);
soumi_ghsoh 5:93c612f43ec2 222 //wait_us(240); //Wait 2ms
soumi_ghsoh 5:93c612f43ec2 223 //testcommand[0] = IRQ_STATUS; //Read/Clear IRQ Status(0x0C=>0x6C)+dummy read
soumi_ghsoh 5:93c612f43ec2 224 //trf797xReadContinuous(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 225 //testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 226 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 227
soumi_ghsoh 5:93c612f43ec2 228 // Read second register as dummy read
soumi_ghsoh 5:93c612f43ec2 229 //
soumi_ghsoh 5:93c612f43ec2 230 wait_ms(5);
soumi_ghsoh 5:93c612f43ec2 231 testcommand[0] = IRQ_STATUS; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 232 trf797xReadSingle(testcommand,1);
soumi_ghsoh 5:93c612f43ec2 233 testcommand[0] = IRQ_STATUS; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 234 trf797xReadSingle(testcommand,1);
soumi_ghsoh 5:93c612f43ec2 235
soumi_ghsoh 5:93c612f43ec2 236 testcommand[0] = IRQ_STATUS; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 237 trf797xReadSingle(testcommand,1);
soumi_ghsoh 5:93c612f43ec2 238 testcommand[0] = RSSI_LEVELS; //Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 5:93c612f43ec2 239 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 240 testcommand[0] = FIFO_CONTROL; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 5:93c612f43ec2 241 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 242 // // Determine the number of bytes left in FIFO
soumi_ghsoh 5:93c612f43ec2 243 testcommand[0] = 0x7F & testcommand[0];
soumi_ghsoh 5:93c612f43ec2 244 //
soumi_ghsoh 5:93c612f43ec2 245 ////buf[rxtxState] = FIFO;
soumi_ghsoh 5:93c612f43ec2 246 buf[100] = FIFO;
soumi_ghsoh 5:93c612f43ec2 247 //////testPin=1; // Write the received bytes to the correct place in the buffer
soumi_ghsoh 5:93c612f43ec2 248 trf797xReadContinuous(&buf[100], testcommand[0]);
soumi_ghsoh 5:93c612f43ec2 249
soumi_ghsoh 5:93c612f43ec2 250
soumi_ghsoh 5:93c612f43ec2 251 ////testPin=0;
soumi_ghsoh 5:93c612f43ec2 252 //testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 253 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 254
soumi_ghsoh 5:93c612f43ec2 255 //testcommand[0] = 0x96; //DISABLE REVEIVER
soumi_ghsoh 5:93c612f43ec2 256 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 257 ////====================================================================8 clk cycles
soumi_ghsoh 5:93c612f43ec2 258 ////testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 259 ////trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 260 //
soumi_ghsoh 5:93c612f43ec2 261 //
soumi_ghsoh 5:93c612f43ec2 262 ////====================================================================
soumi_ghsoh 5:93c612f43ec2 263 //testcommand[0] = 0x97; //ENABLE RECEIVER
soumi_ghsoh 5:93c612f43ec2 264 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 265 ////testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 266 ////trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 267
soumi_ghsoh 5:93c612f43ec2 268 //====================================================================8 clk cycles
soumi_ghsoh 5:93c612f43ec2 269
soumi_ghsoh 5:93c612f43ec2 270 //====================================================================8 clk cycles
soumi_ghsoh 5:93c612f43ec2 271 //testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 272 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 273
soumi_ghsoh 5:93c612f43ec2 274
soumi_ghsoh 5:93c612f43ec2 275 //====================================================================
soumi_ghsoh 5:93c612f43ec2 276
soumi_ghsoh 5:93c612f43ec2 277 //
soumi_ghsoh 5:93c612f43ec2 278 ////
soumi_ghsoh 5:93c612f43ec2 279 ////
soumi_ghsoh 5:93c612f43ec2 280 ////
soumi_ghsoh 5:93c612f43ec2 281 //buf[8] = FIFO; // Write the received bytes to the correct place in the buffer
soumi_ghsoh 5:93c612f43ec2 282 ////
soumi_ghsoh 5:93c612f43ec2 283 //trf797xReadContinuous(&buf[8], 10);//Read Continuous FIFO from 0x1F to 0x1F+0x0A(0x1F/0x7F)
soumi_ghsoh 5:93c612f43ec2 284 ////
soumi_ghsoh 5:93c612f43ec2 285 //// //Wait 10 ms
soumi_ghsoh 5:93c612f43ec2 286 //testcommand[0] = IRQ_STATUS; //Read/Clear IRQ Status(0x0C=>0x6C)+dummy read
soumi_ghsoh 5:93c612f43ec2 287 //trf797xReadContinuous(testcommand, 2); // Read second register as dummy read
soumi_ghsoh 5:93c612f43ec2 288 //testcommand[0] = FIFO_CONTROL; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 5:93c612f43ec2 289 //trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 290 //testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 291 //trf797xDirectCommand(testcommand); // FIFO must be reset before receiving the next response
soumi_ghsoh 5:93c612f43ec2 292 testcommand[0] = RSSI_LEVELS; //Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 5:93c612f43ec2 293 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 294 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 295 trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 296 //trf797xStopDecoders();
soumi_ghsoh 5:93c612f43ec2 297 //trf797xRunDecoders();
soumi_ghsoh 5:93c612f43ec2 298 //testcommand[0] = 0x94; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 299 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 300
soumi_ghsoh 5:93c612f43ec2 301 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 5:93c612f43ec2 302 //trf797xReadContinuous(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 303
soumi_ghsoh 5:93c612f43ec2 304
soumi_ghsoh 5:93c612f43ec2 305 }} // Read RSSI levels
soumi_ghsoh 5:93c612f43ec2 306 //testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 5:93c612f43ec2 307 //trf797xDirectCommand(testcommand); //RESET
soumi_ghsoh 5:93c612f43ec2 308
soumi_ghsoh 5:93c612f43ec2 309 //=========================================================================
soumi_ghsoh 5:93c612f43ec2 310
soumi_ghsoh 5:93c612f43ec2 311
soumi_ghsoh 5:93c612f43ec2 312 //}// end of while
soumi_ghsoh 5:93c612f43ec2 313 //}// end of main
soumi_ghsoh 5:93c612f43ec2 314 /*==========================================================================
soumi_ghsoh 5:93c612f43ec2 315 Initialize the chipset ISO15693 and read UID:
soumi_ghsoh 5:93c612f43ec2 316 1) Reset
soumi_ghsoh 5:93c612f43ec2 317 [0x83]
soumi_ghsoh 5:93c612f43ec2 318 2) Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz))
soumi_ghsoh 5:93c612f43ec2 319 [0x09 0x31]
soumi_ghsoh 5:93c612f43ec2 320 3) Configure Mode ISO Control Register (0x01) to 0x02 (ISO15693 high bit rate, one subcarrier, 1 out of 4)
soumi_ghsoh 5:93c612f43ec2 321 [0x01 0x02]
soumi_ghsoh 5:93c612f43ec2 322 4) Turn RF ON (Chip Status Control Register (0x00))
soumi_ghsoh 5:93c612f43ec2 323 [0x40 r] [0x00 0x20] [0x40 r]
soumi_ghsoh 5:93c612f43ec2 324 5) Inventory Command (see Figure 5-20. Inventory Command Sent From MCU to TRF7970A)
soumi_ghsoh 5:93c612f43ec2 325 5-1) Send Inventory(8B), Wait 2ms, Read/Clear IRQ Status(0x0C=>0x6C)+dummy read, Read FIFO Status Register(0x1C/0x5C), Read Continuous FIFO from 0x1F to 0x1F+0x0A(0x1F/0x7F), Read/Clear IRQ Status(0x0C=>0x6C)+dummy read, Read FIFO Status Register(0x1C/0x5C), Reset FIFO(0x0F/0x8F), Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 5:93c612f43ec2 326 [0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00] %:2 [0x6C r:2] [0x5C r] [0x7F r:10] %:10 [0x6C r:2] [0x5C r] [0x8F] [0x4F r]
soumi_ghsoh 5:93c612f43ec2 327 ==============================================================================*/
soumi_ghsoh 5:93c612f43ec2 328
soumi_ghsoh 5:93c612f43ec2 329
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soumi_ghsoh 5:93c612f43ec2 345
soumi_ghsoh 5:93c612f43ec2 346
soumi_ghsoh 5:93c612f43ec2 347 //// Setup LEDs
soumi_ghsoh 5:93c612f43ec2 348 // heartbeatLED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 349 // ISO15693LED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 350 // debug1LED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 351 // debug2LED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 352
soumi_ghsoh 5:93c612f43ec2 353 //for (uint8_t i=0; i<4; i++) {
soumi_ghsoh 5:93c612f43ec2 354 // heartbeatLED = LED_ON;
soumi_ghsoh 5:93c612f43ec2 355 // ISO15693LED = LED_ON;
soumi_ghsoh 5:93c612f43ec2 356 // debug1LED = LED_ON;
soumi_ghsoh 5:93c612f43ec2 357 // wait_ms(100);
soumi_ghsoh 5:93c612f43ec2 358 // heartbeatLED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 359 // ISO15693LED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 360 // debug1LED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 361 // wait_ms(100);
soumi_ghsoh 5:93c612f43ec2 362 // }
soumi_ghsoh 5:93c612f43ec2 363 //
rwclough 3:eaae5433ab45 364 // Ticker heartbeat;
rwclough 3:eaae5433ab45 365 // heartbeat.attach(blinkHeartbeatLED, 1);
rwclough 3:eaae5433ab45 366 // printf("LEDs, ");
soumi_ghsoh 5:93c612f43ec2 367 //===============================================================
rwclough 1:1eb96189824d 368 // Setup the SPI interface
soumi_ghsoh 5:93c612f43ec2 369 // spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 370 // spi.frequency(1000000); // SCLK = 1 MHz
soumi_ghsoh 5:93c612f43ec2 371 //// printf("SPI, ");
soumi_ghsoh 5:93c612f43ec2 372 //
soumi_ghsoh 5:93c612f43ec2 373 // // Set On-Off Keying modulation
soumi_ghsoh 5:93c612f43ec2 374 // ook_ask.output();
soumi_ghsoh 5:93c612f43ec2 375 // ook_ask = 1;
soumi_ghsoh 5:93c612f43ec2 376 //// printf("OOK, ");
soumi_ghsoh 5:93c612f43ec2 377 //
soumi_ghsoh 5:93c612f43ec2 378 // // Apply initial settings to the TRF7970
soumi_ghsoh 5:93c612f43ec2 379 // testPin=1;
soumi_ghsoh 5:93c612f43ec2 380 // trf797xInitialSettings();
soumi_ghsoh 5:93c612f43ec2 381 //// printf("Initialized, ");
soumi_ghsoh 5:93c612f43ec2 382 // testPin=0;
soumi_ghsoh 5:93c612f43ec2 383 // // Tri-state OOK pin
soumi_ghsoh 5:93c612f43ec2 384 // ook_ask.input();
soumi_ghsoh 5:93c612f43ec2 385 // ook_ask.mode(PullUp);
soumi_ghsoh 5:93c612f43ec2 386 //
soumi_ghsoh 5:93c612f43ec2 387 // readerMode = 0x00;
soumi_ghsoh 5:93c612f43ec2 388 //=============================================================
rwclough 3:eaae5433ab45 389 /*
rwclough 3:eaae5433ab45 390 // Test: Write 0xAA to MODULATOR_CONTROL, then verify by reading MODULATOR_CONTROL.
rwclough 3:eaae5433ab45 391 // printf("\r\n");
rwclough 3:eaae5433ab45 392 buffer[0] = MODULATOR_CONTROL;
rwclough 3:eaae5433ab45 393 buffer[1] = 0xAA;
rwclough 3:eaae5433ab45 394 // printf("BEFORE WR: buffer[0]: %X buffer[1]: %X\r\n", buffer[0], buffer[1]);
rwclough 3:eaae5433ab45 395 spiWriteSingle(buffer, 2);
rwclough 3:eaae5433ab45 396 // printf("AFTER WR: buffer[0]: %X buffer[1]: %X\r\n", buffer[0], buffer[1]);
rwclough 3:eaae5433ab45 397 spiReadSingle(buffer, 1);
rwclough 3:eaae5433ab45 398 // printf("AFTER RD: buffer[0]: %X buffer[1]: %X\r\n", buffer[0], buffer[1]);
rwclough 3:eaae5433ab45 399 // printf("\r\n");
rwclough 3:eaae5433ab45 400 */
rwclough 1:1eb96189824d 401
soumi_ghsoh 5:93c612f43ec2 402 // printf("\r\nFinished Init\r\n");
rwclough 4:9ab0d84bbd07 403
rwclough 1:1eb96189824d 404 // Setup interrupt from TRF7970
soumi_ghsoh 5:93c612f43ec2 405 // testPin=1;
soumi_ghsoh 5:93c612f43ec2 406 //========================
soumi_ghsoh 5:93c612f43ec2 407 // trf797xSetupIrq();
soumi_ghsoh 5:93c612f43ec2 408 //======================
soumi_ghsoh 5:93c612f43ec2 409 // testPin=0;
rwclough 3:eaae5433ab45 410 // printf("IRQ setup, ");
rwclough 1:1eb96189824d 411
rwclough 3:eaae5433ab45 412 // printf("finished init.\r\n\r\n");
rwclough 3:eaae5433ab45 413
soumi_ghsoh 5:93c612f43ec2 414 // while(1) { // changed TRUE to 1 $SG
soumi_ghsoh 5:93c612f43ec2 415 // iso15693FindTag();
soumi_ghsoh 5:93c612f43ec2 416 // }
soumi_ghsoh 5:93c612f43ec2 417 //
soumi_ghsoh 5:93c612f43ec2 418 //} // End of main()