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mbed official
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_msc.h@525:c320967f86b9, 2015-04-28 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Apr 28 11:45:12 2015 +0100
- Revision:
- 525:c320967f86b9
Synchronized with git revision 299385b8331142b9dc524da7a986536f60b14553
Full URL: https://github.com/mbedmicro/mbed/commit/299385b8331142b9dc524da7a986536f60b14553/
Add in Silicon Labs targets with asynchronous API support
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 525:c320967f86b9 | 1 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 2 | * @file efm32lg_msc.h |
| mbed_official | 525:c320967f86b9 | 3 | * @brief EFM32LG_MSC register and bit field definitions |
| mbed_official | 525:c320967f86b9 | 4 | * @version 3.20.6 |
| mbed_official | 525:c320967f86b9 | 5 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 6 | * @section License |
| mbed_official | 525:c320967f86b9 | 7 | * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| mbed_official | 525:c320967f86b9 | 8 | ****************************************************************************** |
| mbed_official | 525:c320967f86b9 | 9 | * |
| mbed_official | 525:c320967f86b9 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| mbed_official | 525:c320967f86b9 | 11 | * including commercial applications, and to alter it and redistribute it |
| mbed_official | 525:c320967f86b9 | 12 | * freely, subject to the following restrictions: |
| mbed_official | 525:c320967f86b9 | 13 | * |
| mbed_official | 525:c320967f86b9 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| mbed_official | 525:c320967f86b9 | 15 | * claim that you wrote the original software.@n |
| mbed_official | 525:c320967f86b9 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| mbed_official | 525:c320967f86b9 | 17 | * misrepresented as being the original software.@n |
| mbed_official | 525:c320967f86b9 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| mbed_official | 525:c320967f86b9 | 19 | * |
| mbed_official | 525:c320967f86b9 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| mbed_official | 525:c320967f86b9 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| mbed_official | 525:c320967f86b9 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| mbed_official | 525:c320967f86b9 | 23 | * kind, including, but not limited to, any implied warranties of |
| mbed_official | 525:c320967f86b9 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| mbed_official | 525:c320967f86b9 | 25 | * infringement of any proprietary rights of a third party. |
| mbed_official | 525:c320967f86b9 | 26 | * |
| mbed_official | 525:c320967f86b9 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| mbed_official | 525:c320967f86b9 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| mbed_official | 525:c320967f86b9 | 29 | * any third party, arising from your use of this Software. |
| mbed_official | 525:c320967f86b9 | 30 | * |
| mbed_official | 525:c320967f86b9 | 31 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 32 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 33 | * @defgroup EFM32LG_MSC |
| mbed_official | 525:c320967f86b9 | 34 | * @{ |
| mbed_official | 525:c320967f86b9 | 35 | * @brief EFM32LG_MSC Register Declaration |
| mbed_official | 525:c320967f86b9 | 36 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 37 | typedef struct |
| mbed_official | 525:c320967f86b9 | 38 | { |
| mbed_official | 525:c320967f86b9 | 39 | __IO uint32_t CTRL; /**< Memory System Control Register */ |
| mbed_official | 525:c320967f86b9 | 40 | __IO uint32_t READCTRL; /**< Read Control Register */ |
| mbed_official | 525:c320967f86b9 | 41 | __IO uint32_t WRITECTRL; /**< Write Control Register */ |
| mbed_official | 525:c320967f86b9 | 42 | __IO uint32_t WRITECMD; /**< Write Command Register */ |
| mbed_official | 525:c320967f86b9 | 43 | __IO uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ |
| mbed_official | 525:c320967f86b9 | 44 | |
| mbed_official | 525:c320967f86b9 | 45 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| mbed_official | 525:c320967f86b9 | 46 | __IO uint32_t WDATA; /**< Write Data Register */ |
| mbed_official | 525:c320967f86b9 | 47 | __I uint32_t STATUS; /**< Status Register */ |
| mbed_official | 525:c320967f86b9 | 48 | |
| mbed_official | 525:c320967f86b9 | 49 | uint32_t RESERVED1[3]; /**< Reserved for future use **/ |
| mbed_official | 525:c320967f86b9 | 50 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| mbed_official | 525:c320967f86b9 | 51 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| mbed_official | 525:c320967f86b9 | 52 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| mbed_official | 525:c320967f86b9 | 53 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| mbed_official | 525:c320967f86b9 | 54 | __IO uint32_t LOCK; /**< Configuration Lock Register */ |
| mbed_official | 525:c320967f86b9 | 55 | __IO uint32_t CMD; /**< Command Register */ |
| mbed_official | 525:c320967f86b9 | 56 | __I uint32_t CACHEHITS; /**< Cache Hits Performance Counter */ |
| mbed_official | 525:c320967f86b9 | 57 | __I uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */ |
| mbed_official | 525:c320967f86b9 | 58 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
| mbed_official | 525:c320967f86b9 | 59 | __IO uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */ |
| mbed_official | 525:c320967f86b9 | 60 | __IO uint32_t MASSLOCK; /**< Mass Erase Lock Register */ |
| mbed_official | 525:c320967f86b9 | 61 | } MSC_TypeDef; /** @} */ |
| mbed_official | 525:c320967f86b9 | 62 | |
| mbed_official | 525:c320967f86b9 | 63 | /**************************************************************************//** |
| mbed_official | 525:c320967f86b9 | 64 | * @defgroup EFM32LG_MSC_BitFields |
| mbed_official | 525:c320967f86b9 | 65 | * @{ |
| mbed_official | 525:c320967f86b9 | 66 | *****************************************************************************/ |
| mbed_official | 525:c320967f86b9 | 67 | |
| mbed_official | 525:c320967f86b9 | 68 | /* Bit fields for MSC CTRL */ |
| mbed_official | 525:c320967f86b9 | 69 | #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 70 | #define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 71 | #define MSC_CTRL_BUSFAULT (0x1UL << 0) /**< Bus Fault Response Enable */ |
| mbed_official | 525:c320967f86b9 | 72 | #define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */ |
| mbed_official | 525:c320967f86b9 | 73 | #define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */ |
| mbed_official | 525:c320967f86b9 | 74 | #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 75 | #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 76 | #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 77 | #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 78 | #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 79 | #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) /**< Shifted mode IGNORE for MSC_CTRL */ |
| mbed_official | 525:c320967f86b9 | 80 | |
| mbed_official | 525:c320967f86b9 | 81 | /* Bit fields for MSC READCTRL */ |
| mbed_official | 525:c320967f86b9 | 82 | #define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 83 | #define _MSC_READCTRL_MASK 0x000300FFUL /**< Mask for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 84 | #define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */ |
| mbed_official | 525:c320967f86b9 | 85 | #define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */ |
| mbed_official | 525:c320967f86b9 | 86 | #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 87 | #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 88 | #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 89 | #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 90 | #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 91 | #define _MSC_READCTRL_MODE_WS2 0x00000004UL /**< Mode WS2 for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 92 | #define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL /**< Mode WS2SCBTP for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 93 | #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) /**< Shifted mode WS0 for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 94 | #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 95 | #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) /**< Shifted mode WS1 for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 96 | #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 97 | #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 98 | #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0) /**< Shifted mode WS2 for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 99 | #define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0) /**< Shifted mode WS2SCBTP for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 100 | #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */ |
| mbed_official | 525:c320967f86b9 | 101 | #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */ |
| mbed_official | 525:c320967f86b9 | 102 | #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */ |
| mbed_official | 525:c320967f86b9 | 103 | #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 104 | #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 105 | #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */ |
| mbed_official | 525:c320967f86b9 | 106 | #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */ |
| mbed_official | 525:c320967f86b9 | 107 | #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */ |
| mbed_official | 525:c320967f86b9 | 108 | #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 109 | #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 110 | #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */ |
| mbed_official | 525:c320967f86b9 | 111 | #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */ |
| mbed_official | 525:c320967f86b9 | 112 | #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */ |
| mbed_official | 525:c320967f86b9 | 113 | #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 114 | #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 115 | #define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */ |
| mbed_official | 525:c320967f86b9 | 116 | #define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */ |
| mbed_official | 525:c320967f86b9 | 117 | #define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */ |
| mbed_official | 525:c320967f86b9 | 118 | #define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 119 | #define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 120 | #define MSC_READCTRL_RAMCEN (0x1UL << 7) /**< RAM Cache Enable */ |
| mbed_official | 525:c320967f86b9 | 121 | #define _MSC_READCTRL_RAMCEN_SHIFT 7 /**< Shift value for MSC_RAMCEN */ |
| mbed_official | 525:c320967f86b9 | 122 | #define _MSC_READCTRL_RAMCEN_MASK 0x80UL /**< Bit mask for MSC_RAMCEN */ |
| mbed_official | 525:c320967f86b9 | 123 | #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 124 | #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 125 | #define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16 /**< Shift value for MSC_BUSSTRATEGY */ |
| mbed_official | 525:c320967f86b9 | 126 | #define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL /**< Bit mask for MSC_BUSSTRATEGY */ |
| mbed_official | 525:c320967f86b9 | 127 | #define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 128 | #define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL /**< Mode CPU for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 129 | #define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL /**< Mode DMA for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 130 | #define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL /**< Mode DMAEM1 for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 131 | #define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL /**< Mode NONE for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 132 | #define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 133 | #define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16) /**< Shifted mode CPU for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 134 | #define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16) /**< Shifted mode DMA for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 135 | #define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16) /**< Shifted mode DMAEM1 for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 136 | #define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16) /**< Shifted mode NONE for MSC_READCTRL */ |
| mbed_official | 525:c320967f86b9 | 137 | |
| mbed_official | 525:c320967f86b9 | 138 | /* Bit fields for MSC WRITECTRL */ |
| mbed_official | 525:c320967f86b9 | 139 | #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ |
| mbed_official | 525:c320967f86b9 | 140 | #define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */ |
| mbed_official | 525:c320967f86b9 | 141 | #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ |
| mbed_official | 525:c320967f86b9 | 142 | #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ |
| mbed_official | 525:c320967f86b9 | 143 | #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ |
| mbed_official | 525:c320967f86b9 | 144 | #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ |
| mbed_official | 525:c320967f86b9 | 145 | #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ |
| mbed_official | 525:c320967f86b9 | 146 | #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ |
| mbed_official | 525:c320967f86b9 | 147 | #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ |
| mbed_official | 525:c320967f86b9 | 148 | #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ |
| mbed_official | 525:c320967f86b9 | 149 | #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ |
| mbed_official | 525:c320967f86b9 | 150 | #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ |
| mbed_official | 525:c320967f86b9 | 151 | |
| mbed_official | 525:c320967f86b9 | 152 | /* Bit fields for MSC WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 153 | #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 154 | #define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 155 | #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */ |
| mbed_official | 525:c320967f86b9 | 156 | #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */ |
| mbed_official | 525:c320967f86b9 | 157 | #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */ |
| mbed_official | 525:c320967f86b9 | 158 | #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 159 | #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 160 | #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ |
| mbed_official | 525:c320967f86b9 | 161 | #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ |
| mbed_official | 525:c320967f86b9 | 162 | #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ |
| mbed_official | 525:c320967f86b9 | 163 | #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 164 | #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 165 | #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ |
| mbed_official | 525:c320967f86b9 | 166 | #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ |
| mbed_official | 525:c320967f86b9 | 167 | #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ |
| mbed_official | 525:c320967f86b9 | 168 | #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 169 | #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 170 | #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */ |
| mbed_official | 525:c320967f86b9 | 171 | #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */ |
| mbed_official | 525:c320967f86b9 | 172 | #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */ |
| mbed_official | 525:c320967f86b9 | 173 | #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 174 | #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 175 | #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */ |
| mbed_official | 525:c320967f86b9 | 176 | #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */ |
| mbed_official | 525:c320967f86b9 | 177 | #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */ |
| mbed_official | 525:c320967f86b9 | 178 | #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 179 | #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 180 | #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ |
| mbed_official | 525:c320967f86b9 | 181 | #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ |
| mbed_official | 525:c320967f86b9 | 182 | #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ |
| mbed_official | 525:c320967f86b9 | 183 | #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 184 | #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 185 | #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ |
| mbed_official | 525:c320967f86b9 | 186 | #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ |
| mbed_official | 525:c320967f86b9 | 187 | #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ |
| mbed_official | 525:c320967f86b9 | 188 | #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 189 | #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 190 | #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ |
| mbed_official | 525:c320967f86b9 | 191 | #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ |
| mbed_official | 525:c320967f86b9 | 192 | #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ |
| mbed_official | 525:c320967f86b9 | 193 | #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 194 | #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ |
| mbed_official | 525:c320967f86b9 | 195 | |
| mbed_official | 525:c320967f86b9 | 196 | /* Bit fields for MSC ADDRB */ |
| mbed_official | 525:c320967f86b9 | 197 | #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ |
| mbed_official | 525:c320967f86b9 | 198 | #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ |
| mbed_official | 525:c320967f86b9 | 199 | #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ |
| mbed_official | 525:c320967f86b9 | 200 | #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ |
| mbed_official | 525:c320967f86b9 | 201 | #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ |
| mbed_official | 525:c320967f86b9 | 202 | #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ |
| mbed_official | 525:c320967f86b9 | 203 | |
| mbed_official | 525:c320967f86b9 | 204 | /* Bit fields for MSC WDATA */ |
| mbed_official | 525:c320967f86b9 | 205 | #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ |
| mbed_official | 525:c320967f86b9 | 206 | #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ |
| mbed_official | 525:c320967f86b9 | 207 | #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */ |
| mbed_official | 525:c320967f86b9 | 208 | #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */ |
| mbed_official | 525:c320967f86b9 | 209 | #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ |
| mbed_official | 525:c320967f86b9 | 210 | #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ |
| mbed_official | 525:c320967f86b9 | 211 | |
| mbed_official | 525:c320967f86b9 | 212 | /* Bit fields for MSC STATUS */ |
| mbed_official | 525:c320967f86b9 | 213 | #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 214 | #define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 215 | #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ |
| mbed_official | 525:c320967f86b9 | 216 | #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ |
| mbed_official | 525:c320967f86b9 | 217 | #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ |
| mbed_official | 525:c320967f86b9 | 218 | #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 219 | #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 220 | #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ |
| mbed_official | 525:c320967f86b9 | 221 | #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ |
| mbed_official | 525:c320967f86b9 | 222 | #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ |
| mbed_official | 525:c320967f86b9 | 223 | #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 224 | #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 225 | #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ |
| mbed_official | 525:c320967f86b9 | 226 | #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ |
| mbed_official | 525:c320967f86b9 | 227 | #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ |
| mbed_official | 525:c320967f86b9 | 228 | #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 229 | #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 230 | #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ |
| mbed_official | 525:c320967f86b9 | 231 | #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ |
| mbed_official | 525:c320967f86b9 | 232 | #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ |
| mbed_official | 525:c320967f86b9 | 233 | #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 234 | #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 235 | #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */ |
| mbed_official | 525:c320967f86b9 | 236 | #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */ |
| mbed_official | 525:c320967f86b9 | 237 | #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */ |
| mbed_official | 525:c320967f86b9 | 238 | #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 239 | #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 240 | #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */ |
| mbed_official | 525:c320967f86b9 | 241 | #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */ |
| mbed_official | 525:c320967f86b9 | 242 | #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */ |
| mbed_official | 525:c320967f86b9 | 243 | #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 244 | #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 245 | #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */ |
| mbed_official | 525:c320967f86b9 | 246 | #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */ |
| mbed_official | 525:c320967f86b9 | 247 | #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */ |
| mbed_official | 525:c320967f86b9 | 248 | #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 249 | #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ |
| mbed_official | 525:c320967f86b9 | 250 | |
| mbed_official | 525:c320967f86b9 | 251 | /* Bit fields for MSC IF */ |
| mbed_official | 525:c320967f86b9 | 252 | #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 253 | #define _MSC_IF_MASK 0x0000000FUL /**< Mask for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 254 | #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */ |
| mbed_official | 525:c320967f86b9 | 255 | #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ |
| mbed_official | 525:c320967f86b9 | 256 | #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ |
| mbed_official | 525:c320967f86b9 | 257 | #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 258 | #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 259 | #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */ |
| mbed_official | 525:c320967f86b9 | 260 | #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ |
| mbed_official | 525:c320967f86b9 | 261 | #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ |
| mbed_official | 525:c320967f86b9 | 262 | #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 263 | #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 264 | #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 265 | #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ |
| mbed_official | 525:c320967f86b9 | 266 | #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ |
| mbed_official | 525:c320967f86b9 | 267 | #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 268 | #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 269 | #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */ |
| mbed_official | 525:c320967f86b9 | 270 | #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ |
| mbed_official | 525:c320967f86b9 | 271 | #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ |
| mbed_official | 525:c320967f86b9 | 272 | #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 273 | #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */ |
| mbed_official | 525:c320967f86b9 | 274 | |
| mbed_official | 525:c320967f86b9 | 275 | /* Bit fields for MSC IFS */ |
| mbed_official | 525:c320967f86b9 | 276 | #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 277 | #define _MSC_IFS_MASK 0x0000000FUL /**< Mask for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 278 | #define MSC_IFS_ERASE (0x1UL << 0) /**< Erase Done Interrupt Set */ |
| mbed_official | 525:c320967f86b9 | 279 | #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ |
| mbed_official | 525:c320967f86b9 | 280 | #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ |
| mbed_official | 525:c320967f86b9 | 281 | #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 282 | #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 283 | #define MSC_IFS_WRITE (0x1UL << 1) /**< Write Done Interrupt Set */ |
| mbed_official | 525:c320967f86b9 | 284 | #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ |
| mbed_official | 525:c320967f86b9 | 285 | #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ |
| mbed_official | 525:c320967f86b9 | 286 | #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 287 | #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 288 | #define MSC_IFS_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Set */ |
| mbed_official | 525:c320967f86b9 | 289 | #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ |
| mbed_official | 525:c320967f86b9 | 290 | #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ |
| mbed_official | 525:c320967f86b9 | 291 | #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 292 | #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 293 | #define MSC_IFS_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Set */ |
| mbed_official | 525:c320967f86b9 | 294 | #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ |
| mbed_official | 525:c320967f86b9 | 295 | #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ |
| mbed_official | 525:c320967f86b9 | 296 | #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 297 | #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */ |
| mbed_official | 525:c320967f86b9 | 298 | |
| mbed_official | 525:c320967f86b9 | 299 | /* Bit fields for MSC IFC */ |
| mbed_official | 525:c320967f86b9 | 300 | #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 301 | #define _MSC_IFC_MASK 0x0000000FUL /**< Mask for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 302 | #define MSC_IFC_ERASE (0x1UL << 0) /**< Erase Done Interrupt Clear */ |
| mbed_official | 525:c320967f86b9 | 303 | #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ |
| mbed_official | 525:c320967f86b9 | 304 | #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ |
| mbed_official | 525:c320967f86b9 | 305 | #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 306 | #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 307 | #define MSC_IFC_WRITE (0x1UL << 1) /**< Write Done Interrupt Clear */ |
| mbed_official | 525:c320967f86b9 | 308 | #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ |
| mbed_official | 525:c320967f86b9 | 309 | #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ |
| mbed_official | 525:c320967f86b9 | 310 | #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 311 | #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 312 | #define MSC_IFC_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Clear */ |
| mbed_official | 525:c320967f86b9 | 313 | #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ |
| mbed_official | 525:c320967f86b9 | 314 | #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ |
| mbed_official | 525:c320967f86b9 | 315 | #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 316 | #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 317 | #define MSC_IFC_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Clear */ |
| mbed_official | 525:c320967f86b9 | 318 | #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ |
| mbed_official | 525:c320967f86b9 | 319 | #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ |
| mbed_official | 525:c320967f86b9 | 320 | #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 321 | #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */ |
| mbed_official | 525:c320967f86b9 | 322 | |
| mbed_official | 525:c320967f86b9 | 323 | /* Bit fields for MSC IEN */ |
| mbed_official | 525:c320967f86b9 | 324 | #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 325 | #define _MSC_IEN_MASK 0x0000000FUL /**< Mask for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 326 | #define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 327 | #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ |
| mbed_official | 525:c320967f86b9 | 328 | #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ |
| mbed_official | 525:c320967f86b9 | 329 | #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 330 | #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 331 | #define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 332 | #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ |
| mbed_official | 525:c320967f86b9 | 333 | #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ |
| mbed_official | 525:c320967f86b9 | 334 | #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 335 | #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 336 | #define MSC_IEN_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 337 | #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */ |
| mbed_official | 525:c320967f86b9 | 338 | #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */ |
| mbed_official | 525:c320967f86b9 | 339 | #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 340 | #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 341 | #define MSC_IEN_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Enable */ |
| mbed_official | 525:c320967f86b9 | 342 | #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */ |
| mbed_official | 525:c320967f86b9 | 343 | #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */ |
| mbed_official | 525:c320967f86b9 | 344 | #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 345 | #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */ |
| mbed_official | 525:c320967f86b9 | 346 | |
| mbed_official | 525:c320967f86b9 | 347 | /* Bit fields for MSC LOCK */ |
| mbed_official | 525:c320967f86b9 | 348 | #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 349 | #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 350 | #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ |
| mbed_official | 525:c320967f86b9 | 351 | #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ |
| mbed_official | 525:c320967f86b9 | 352 | #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 353 | #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 354 | #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 355 | #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 356 | #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 357 | #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 358 | #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 359 | #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 360 | #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 361 | #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ |
| mbed_official | 525:c320967f86b9 | 362 | |
| mbed_official | 525:c320967f86b9 | 363 | /* Bit fields for MSC CMD */ |
| mbed_official | 525:c320967f86b9 | 364 | #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ |
| mbed_official | 525:c320967f86b9 | 365 | #define _MSC_CMD_MASK 0x00000007UL /**< Mask for MSC_CMD */ |
| mbed_official | 525:c320967f86b9 | 366 | #define MSC_CMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */ |
| mbed_official | 525:c320967f86b9 | 367 | #define _MSC_CMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */ |
| mbed_official | 525:c320967f86b9 | 368 | #define _MSC_CMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */ |
| mbed_official | 525:c320967f86b9 | 369 | #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ |
| mbed_official | 525:c320967f86b9 | 370 | #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ |
| mbed_official | 525:c320967f86b9 | 371 | #define MSC_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ |
| mbed_official | 525:c320967f86b9 | 372 | #define _MSC_CMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */ |
| mbed_official | 525:c320967f86b9 | 373 | #define _MSC_CMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */ |
| mbed_official | 525:c320967f86b9 | 374 | #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ |
| mbed_official | 525:c320967f86b9 | 375 | #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */ |
| mbed_official | 525:c320967f86b9 | 376 | #define MSC_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ |
| mbed_official | 525:c320967f86b9 | 377 | #define _MSC_CMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */ |
| mbed_official | 525:c320967f86b9 | 378 | #define _MSC_CMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */ |
| mbed_official | 525:c320967f86b9 | 379 | #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ |
| mbed_official | 525:c320967f86b9 | 380 | #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CMD */ |
| mbed_official | 525:c320967f86b9 | 381 | |
| mbed_official | 525:c320967f86b9 | 382 | /* Bit fields for MSC CACHEHITS */ |
| mbed_official | 525:c320967f86b9 | 383 | #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */ |
| mbed_official | 525:c320967f86b9 | 384 | #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */ |
| mbed_official | 525:c320967f86b9 | 385 | #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */ |
| mbed_official | 525:c320967f86b9 | 386 | #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */ |
| mbed_official | 525:c320967f86b9 | 387 | #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */ |
| mbed_official | 525:c320967f86b9 | 388 | #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */ |
| mbed_official | 525:c320967f86b9 | 389 | |
| mbed_official | 525:c320967f86b9 | 390 | /* Bit fields for MSC CACHEMISSES */ |
| mbed_official | 525:c320967f86b9 | 391 | #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */ |
| mbed_official | 525:c320967f86b9 | 392 | #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */ |
| mbed_official | 525:c320967f86b9 | 393 | #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */ |
| mbed_official | 525:c320967f86b9 | 394 | #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */ |
| mbed_official | 525:c320967f86b9 | 395 | #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */ |
| mbed_official | 525:c320967f86b9 | 396 | #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */ |
| mbed_official | 525:c320967f86b9 | 397 | |
| mbed_official | 525:c320967f86b9 | 398 | /* Bit fields for MSC TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 399 | #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL /**< Default value for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 400 | #define _MSC_TIMEBASE_MASK 0x0001003FUL /**< Mask for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 401 | #define _MSC_TIMEBASE_BASE_SHIFT 0 /**< Shift value for MSC_BASE */ |
| mbed_official | 525:c320967f86b9 | 402 | #define _MSC_TIMEBASE_BASE_MASK 0x3FUL /**< Bit mask for MSC_BASE */ |
| mbed_official | 525:c320967f86b9 | 403 | #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 404 | #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 405 | #define MSC_TIMEBASE_PERIOD (0x1UL << 16) /**< Sets the timebase period */ |
| mbed_official | 525:c320967f86b9 | 406 | #define _MSC_TIMEBASE_PERIOD_SHIFT 16 /**< Shift value for MSC_PERIOD */ |
| mbed_official | 525:c320967f86b9 | 407 | #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL /**< Bit mask for MSC_PERIOD */ |
| mbed_official | 525:c320967f86b9 | 408 | #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 409 | #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL /**< Mode 1US for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 410 | #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL /**< Mode 5US for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 411 | #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 412 | #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16) /**< Shifted mode 1US for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 413 | #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16) /**< Shifted mode 5US for MSC_TIMEBASE */ |
| mbed_official | 525:c320967f86b9 | 414 | |
| mbed_official | 525:c320967f86b9 | 415 | /* Bit fields for MSC MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 416 | #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 417 | #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 418 | #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ |
| mbed_official | 525:c320967f86b9 | 419 | #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ |
| mbed_official | 525:c320967f86b9 | 420 | #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 421 | #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 422 | #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 423 | #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 424 | #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 425 | #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 426 | #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 427 | #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 428 | #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 429 | #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */ |
| mbed_official | 525:c320967f86b9 | 430 | |
| mbed_official | 525:c320967f86b9 | 431 | /** @} End of group EFM32LG_MSC */ |
| mbed_official | 525:c320967f86b9 | 432 | |
| mbed_official | 525:c320967f86b9 | 433 |