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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_cmu.h@603:f00c7e78e8b4, 2015-08-09 (annotated)

Committer:
HiAlgoBoost
Date:
Sun Aug 09 05:18:54 2015 +0000
Revision:
603:f00c7e78e8b4
Parent:
525:c320967f86b9 
Evening of August 8th version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 525:c320967f86b9 1 /**************************************************************************//**
mbed_official 525:c320967f86b9 2 * @file efm32hg_cmu.h
mbed_official 525:c320967f86b9 3 * @brief EFM32HG_CMU register and bit field definitions
mbed_official 525:c320967f86b9 4 * @version 3.20.12
mbed_official 525:c320967f86b9 5 ******************************************************************************
mbed_official 525:c320967f86b9 6 * @section License
mbed_official 525:c320967f86b9 7 * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
mbed_official 525:c320967f86b9 8 ******************************************************************************
mbed_official 525:c320967f86b9 9 *
mbed_official 525:c320967f86b9 10 * Permission is granted to anyone to use this software for any purpose,
mbed_official 525:c320967f86b9 11 * including commercial applications, and to alter it and redistribute it
mbed_official 525:c320967f86b9 12 * freely, subject to the following restrictions:
mbed_official 525:c320967f86b9 13 *
mbed_official 525:c320967f86b9 14 * 1. The origin of this software must not be misrepresented; you must not
mbed_official 525:c320967f86b9 15 * claim that you wrote the original software.@n
mbed_official 525:c320967f86b9 16 * 2. Altered source versions must be plainly marked as such, and must not be
mbed_official 525:c320967f86b9 17 * misrepresented as being the original software.@n
mbed_official 525:c320967f86b9 18 * 3. This notice may not be removed or altered from any source distribution.
mbed_official 525:c320967f86b9 19 *
mbed_official 525:c320967f86b9 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
mbed_official 525:c320967f86b9 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
mbed_official 525:c320967f86b9 22 * providing the Software "AS IS", with no express or implied warranties of any
mbed_official 525:c320967f86b9 23 * kind, including, but not limited to, any implied warranties of
mbed_official 525:c320967f86b9 24 * merchantability or fitness for any particular purpose or warranties against
mbed_official 525:c320967f86b9 25 * infringement of any proprietary rights of a third party.
mbed_official 525:c320967f86b9 26 *
mbed_official 525:c320967f86b9 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
mbed_official 525:c320967f86b9 28 * incidental, or special damages, or any other relief, or for any claim by
mbed_official 525:c320967f86b9 29 * any third party, arising from your use of this Software.
mbed_official 525:c320967f86b9 30 *
mbed_official 525:c320967f86b9 31 *****************************************************************************/
mbed_official 525:c320967f86b9 32 /**************************************************************************//**
mbed_official 525:c320967f86b9 33 * @defgroup EFM32HG_CMU
mbed_official 525:c320967f86b9 34 * @{
mbed_official 525:c320967f86b9 35 * @brief EFM32HG_CMU Register Declaration
mbed_official 525:c320967f86b9 36 *****************************************************************************/
mbed_official 525:c320967f86b9 37 typedef struct
mbed_official 525:c320967f86b9 38 {
mbed_official 525:c320967f86b9 39 __IO uint32_t CTRL; /**< CMU Control Register */
mbed_official 525:c320967f86b9 40 __IO uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
mbed_official 525:c320967f86b9 41 __IO uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
mbed_official 525:c320967f86b9 42 __IO uint32_t HFRCOCTRL; /**< HFRCO Control Register */
mbed_official 525:c320967f86b9 43 __IO uint32_t LFRCOCTRL; /**< LFRCO Control Register */
mbed_official 525:c320967f86b9 44 __IO uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
mbed_official 525:c320967f86b9 45 __IO uint32_t CALCTRL; /**< Calibration Control Register */
mbed_official 525:c320967f86b9 46 __IO uint32_t CALCNT; /**< Calibration Counter Register */
mbed_official 525:c320967f86b9 47 __IO uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
mbed_official 525:c320967f86b9 48 __IO uint32_t CMD; /**< Command Register */
mbed_official 525:c320967f86b9 49 __IO uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
mbed_official 525:c320967f86b9 50 __I uint32_t STATUS; /**< Status Register */
mbed_official 525:c320967f86b9 51 __I uint32_t IF; /**< Interrupt Flag Register */
mbed_official 525:c320967f86b9 52 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
mbed_official 525:c320967f86b9 53 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
mbed_official 525:c320967f86b9 54 __IO uint32_t IEN; /**< Interrupt Enable Register */
mbed_official 525:c320967f86b9 55 __IO uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
mbed_official 525:c320967f86b9 56 __IO uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
mbed_official 525:c320967f86b9 57 uint32_t RESERVED0[2]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 58 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
mbed_official 525:c320967f86b9 59 __IO uint32_t FREEZE; /**< Freeze Register */
mbed_official 525:c320967f86b9 60 __IO uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
mbed_official 525:c320967f86b9 61 uint32_t RESERVED1[1]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 62 __IO uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
mbed_official 525:c320967f86b9 63 __IO uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */
mbed_official 525:c320967f86b9 64 __IO uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
mbed_official 525:c320967f86b9 65 uint32_t RESERVED2[1]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 66 __IO uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
mbed_official 525:c320967f86b9 67 uint32_t RESERVED3[1]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 68 __IO uint32_t PCNTCTRL; /**< PCNT Control Register */
mbed_official 525:c320967f86b9 69
mbed_official 525:c320967f86b9 70 uint32_t RESERVED4[1]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 71 __IO uint32_t ROUTE; /**< I/O Routing Register */
mbed_official 525:c320967f86b9 72 __IO uint32_t LOCK; /**< Configuration Lock Register */
mbed_official 525:c320967f86b9 73
mbed_official 525:c320967f86b9 74 uint32_t RESERVED5[18]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 75 __IO uint32_t USBCRCTRL; /**< USB Clock Recovery Control */
mbed_official 525:c320967f86b9 76 __IO uint32_t USHFRCOCTRL; /**< USHFRCO Control */
mbed_official 525:c320967f86b9 77 __IO uint32_t USHFRCOTUNE; /**< USHFRCO Frequency Tune */
mbed_official 525:c320967f86b9 78 __IO uint32_t USHFRCOCONF; /**< USHFRCO Configuration */
mbed_official 525:c320967f86b9 79 } CMU_TypeDef; /** @} */
mbed_official 525:c320967f86b9 80
mbed_official 525:c320967f86b9 81 /**************************************************************************//**
mbed_official 525:c320967f86b9 82 * @defgroup EFM32HG_CMU_BitFields
mbed_official 525:c320967f86b9 83 * @{
mbed_official 525:c320967f86b9 84 *****************************************************************************/
mbed_official 525:c320967f86b9 85
mbed_official 525:c320967f86b9 86 /* Bit fields for CMU CTRL */
mbed_official 525:c320967f86b9 87 #define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */
mbed_official 525:c320967f86b9 88 #define _CMU_CTRL_MASK 0x07FFFEEFUL /**< Mask for CMU_CTRL */
mbed_official 525:c320967f86b9 89 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
mbed_official 525:c320967f86b9 90 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
mbed_official 525:c320967f86b9 91 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 92 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
mbed_official 525:c320967f86b9 93 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 94 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 95 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 96 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
mbed_official 525:c320967f86b9 97 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 98 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 99 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
mbed_official 525:c320967f86b9 100 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
mbed_official 525:c320967f86b9 101 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 102 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 103 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 104 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 105 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 106 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 107 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 108 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 109 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 110 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 111 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
mbed_official 525:c320967f86b9 112 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
mbed_official 525:c320967f86b9 113 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 114 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 115 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
mbed_official 525:c320967f86b9 116 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
mbed_official 525:c320967f86b9 117 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
mbed_official 525:c320967f86b9 118 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 119 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 120 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
mbed_official 525:c320967f86b9 121 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
mbed_official 525:c320967f86b9 122 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 123 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 124 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 125 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 126 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 127 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 128 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 129 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 130 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 131 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 132 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
mbed_official 525:c320967f86b9 133 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
mbed_official 525:c320967f86b9 134 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 135 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
mbed_official 525:c320967f86b9 136 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 137 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 138 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 139 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
mbed_official 525:c320967f86b9 140 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 141 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 142 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
mbed_official 525:c320967f86b9 143 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
mbed_official 525:c320967f86b9 144 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
mbed_official 525:c320967f86b9 145 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 146 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 147 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 148 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 149 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 150 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
mbed_official 525:c320967f86b9 151 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */
mbed_official 525:c320967f86b9 152 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */
mbed_official 525:c320967f86b9 153 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 154 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 155 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
mbed_official 525:c320967f86b9 156 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
mbed_official 525:c320967f86b9 157 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
mbed_official 525:c320967f86b9 158 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 159 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 160 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
mbed_official 525:c320967f86b9 161 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
mbed_official 525:c320967f86b9 162 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 163 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 164 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 165 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 166 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 167 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 168 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 169 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 170 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 171 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
mbed_official 525:c320967f86b9 172 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
mbed_official 525:c320967f86b9 173 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
mbed_official 525:c320967f86b9 174 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 175 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 176 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
mbed_official 525:c320967f86b9 177 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
mbed_official 525:c320967f86b9 178 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
mbed_official 525:c320967f86b9 179 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
mbed_official 525:c320967f86b9 180 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
mbed_official 525:c320967f86b9 181 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 182 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 183 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 184 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 185 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
mbed_official 525:c320967f86b9 186 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
mbed_official 525:c320967f86b9 187 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
mbed_official 525:c320967f86b9 188 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
mbed_official 525:c320967f86b9 189 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
mbed_official 525:c320967f86b9 190 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 191 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 192 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
mbed_official 525:c320967f86b9 193 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
mbed_official 525:c320967f86b9 194 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 195 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 196 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
mbed_official 525:c320967f86b9 197 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 198 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 199 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 200 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 201 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 202 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 203 #define _CMU_CTRL_CLKOUTSEL1_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 204 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
mbed_official 525:c320967f86b9 205 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 206 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
mbed_official 525:c320967f86b9 207 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
mbed_official 525:c320967f86b9 208 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 209 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 210 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 211 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 212 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
mbed_official 525:c320967f86b9 213 #define CMU_CTRL_CLKOUTSEL1_USHFRCO (_CMU_CTRL_CLKOUTSEL1_USHFRCO << 23) /**< Shifted mode USHFRCO for CMU_CTRL */
mbed_official 525:c320967f86b9 214
mbed_official 525:c320967f86b9 215 /* Bit fields for CMU HFCORECLKDIV */
mbed_official 525:c320967f86b9 216 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 217 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 218 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 219 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 220 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 221 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 222 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 223 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 224 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 225 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 226 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 227 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 228 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 229 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 230 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 231 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 232 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 233 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 234 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 235 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 236 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 237 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 238 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 239 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 240 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 241 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 242 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
mbed_official 525:c320967f86b9 243 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
mbed_official 525:c320967f86b9 244 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
mbed_official 525:c320967f86b9 245 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 246 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 247 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 248 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 249 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 250 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
mbed_official 525:c320967f86b9 251
mbed_official 525:c320967f86b9 252 /* Bit fields for CMU HFPERCLKDIV */
mbed_official 525:c320967f86b9 253 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 254 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 255 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 256 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 257 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 258 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 259 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 260 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 261 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 262 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 263 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 264 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 265 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 266 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 267 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 268 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 269 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 270 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 271 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 272 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 273 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 274 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 275 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 276 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 277 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 278 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 279 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
mbed_official 525:c320967f86b9 280 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
mbed_official 525:c320967f86b9 281 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
mbed_official 525:c320967f86b9 282 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 283 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
mbed_official 525:c320967f86b9 284
mbed_official 525:c320967f86b9 285 /* Bit fields for CMU HFRCOCTRL */
mbed_official 525:c320967f86b9 286 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 287 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 288 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
mbed_official 525:c320967f86b9 289 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
mbed_official 525:c320967f86b9 290 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 291 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 292 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
mbed_official 525:c320967f86b9 293 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
mbed_official 525:c320967f86b9 294 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 295 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 296 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 297 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 298 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 299 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 300 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 301 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 302 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 303 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 304 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 305 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 306 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
mbed_official 525:c320967f86b9 307 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
mbed_official 525:c320967f86b9 308 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 309 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
mbed_official 525:c320967f86b9 310
mbed_official 525:c320967f86b9 311 /* Bit fields for CMU LFRCOCTRL */
mbed_official 525:c320967f86b9 312 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
mbed_official 525:c320967f86b9 313 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
mbed_official 525:c320967f86b9 314 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
mbed_official 525:c320967f86b9 315 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
mbed_official 525:c320967f86b9 316 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
mbed_official 525:c320967f86b9 317 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
mbed_official 525:c320967f86b9 318
mbed_official 525:c320967f86b9 319 /* Bit fields for CMU AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 320 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 321 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 322 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
mbed_official 525:c320967f86b9 323 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
mbed_official 525:c320967f86b9 324 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 325 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 326 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
mbed_official 525:c320967f86b9 327 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
mbed_official 525:c320967f86b9 328 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 329 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 330 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 331 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 332 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 333 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 334 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 335 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 336 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 337 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 338 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 339 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
mbed_official 525:c320967f86b9 340
mbed_official 525:c320967f86b9 341 /* Bit fields for CMU CALCTRL */
mbed_official 525:c320967f86b9 342 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
mbed_official 525:c320967f86b9 343 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
mbed_official 525:c320967f86b9 344 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
mbed_official 525:c320967f86b9 345 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
mbed_official 525:c320967f86b9 346 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
mbed_official 525:c320967f86b9 347 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 348 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 349 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 350 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 351 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 352 #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000005UL /**< Mode USHFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 353 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
mbed_official 525:c320967f86b9 354 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 355 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 356 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 357 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 358 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 359 #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 360 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
mbed_official 525:c320967f86b9 361 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
mbed_official 525:c320967f86b9 362 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
mbed_official 525:c320967f86b9 363 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
mbed_official 525:c320967f86b9 364 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 365 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 366 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 367 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 368 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 369 #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 370 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
mbed_official 525:c320967f86b9 371 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
mbed_official 525:c320967f86b9 372 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 373 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 374 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 375 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 376 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 377 #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_CALCTRL */
mbed_official 525:c320967f86b9 378 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
mbed_official 525:c320967f86b9 379 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
mbed_official 525:c320967f86b9 380 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
mbed_official 525:c320967f86b9 381 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
mbed_official 525:c320967f86b9 382 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
mbed_official 525:c320967f86b9 383
mbed_official 525:c320967f86b9 384 /* Bit fields for CMU CALCNT */
mbed_official 525:c320967f86b9 385 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
mbed_official 525:c320967f86b9 386 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
mbed_official 525:c320967f86b9 387 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
mbed_official 525:c320967f86b9 388 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
mbed_official 525:c320967f86b9 389 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
mbed_official 525:c320967f86b9 390 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
mbed_official 525:c320967f86b9 391
mbed_official 525:c320967f86b9 392 /* Bit fields for CMU OSCENCMD */
mbed_official 525:c320967f86b9 393 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 394 #define _CMU_OSCENCMD_MASK 0x00000FFFUL /**< Mask for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 395 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
mbed_official 525:c320967f86b9 396 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
mbed_official 525:c320967f86b9 397 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
mbed_official 525:c320967f86b9 398 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 399 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 400 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
mbed_official 525:c320967f86b9 401 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
mbed_official 525:c320967f86b9 402 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
mbed_official 525:c320967f86b9 403 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 404 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 405 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
mbed_official 525:c320967f86b9 406 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
mbed_official 525:c320967f86b9 407 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
mbed_official 525:c320967f86b9 408 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 409 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 410 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
mbed_official 525:c320967f86b9 411 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
mbed_official 525:c320967f86b9 412 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
mbed_official 525:c320967f86b9 413 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 414 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 415 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
mbed_official 525:c320967f86b9 416 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
mbed_official 525:c320967f86b9 417 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
mbed_official 525:c320967f86b9 418 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 419 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 420 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
mbed_official 525:c320967f86b9 421 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
mbed_official 525:c320967f86b9 422 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
mbed_official 525:c320967f86b9 423 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 424 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 425 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
mbed_official 525:c320967f86b9 426 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
mbed_official 525:c320967f86b9 427 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
mbed_official 525:c320967f86b9 428 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 429 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 430 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
mbed_official 525:c320967f86b9 431 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
mbed_official 525:c320967f86b9 432 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
mbed_official 525:c320967f86b9 433 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 434 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 435 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
mbed_official 525:c320967f86b9 436 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
mbed_official 525:c320967f86b9 437 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
mbed_official 525:c320967f86b9 438 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 439 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 440 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
mbed_official 525:c320967f86b9 441 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
mbed_official 525:c320967f86b9 442 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
mbed_official 525:c320967f86b9 443 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 444 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 445 #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */
mbed_official 525:c320967f86b9 446 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */
mbed_official 525:c320967f86b9 447 #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */
mbed_official 525:c320967f86b9 448 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 449 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 450 #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */
mbed_official 525:c320967f86b9 451 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */
mbed_official 525:c320967f86b9 452 #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */
mbed_official 525:c320967f86b9 453 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 454 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
mbed_official 525:c320967f86b9 455
mbed_official 525:c320967f86b9 456 /* Bit fields for CMU CMD */
mbed_official 525:c320967f86b9 457 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
mbed_official 525:c320967f86b9 458 #define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */
mbed_official 525:c320967f86b9 459 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
mbed_official 525:c320967f86b9 460 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
mbed_official 525:c320967f86b9 461 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
mbed_official 525:c320967f86b9 462 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
mbed_official 525:c320967f86b9 463 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
mbed_official 525:c320967f86b9 464 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
mbed_official 525:c320967f86b9 465 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
mbed_official 525:c320967f86b9 466 #define _CMU_CMD_HFCLKSEL_USHFRCODIV2 0x00000005UL /**< Mode USHFRCODIV2 for CMU_CMD */
mbed_official 525:c320967f86b9 467 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
mbed_official 525:c320967f86b9 468 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
mbed_official 525:c320967f86b9 469 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
mbed_official 525:c320967f86b9 470 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
mbed_official 525:c320967f86b9 471 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
mbed_official 525:c320967f86b9 472 #define CMU_CMD_HFCLKSEL_USHFRCODIV2 (_CMU_CMD_HFCLKSEL_USHFRCODIV2 << 0) /**< Shifted mode USHFRCODIV2 for CMU_CMD */
mbed_official 525:c320967f86b9 473 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
mbed_official 525:c320967f86b9 474 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
mbed_official 525:c320967f86b9 475 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
mbed_official 525:c320967f86b9 476 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
mbed_official 525:c320967f86b9 477 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
mbed_official 525:c320967f86b9 478 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
mbed_official 525:c320967f86b9 479 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
mbed_official 525:c320967f86b9 480 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
mbed_official 525:c320967f86b9 481 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
mbed_official 525:c320967f86b9 482 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
mbed_official 525:c320967f86b9 483 #define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */
mbed_official 525:c320967f86b9 484 #define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */
mbed_official 525:c320967f86b9 485 #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
mbed_official 525:c320967f86b9 486 #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */
mbed_official 525:c320967f86b9 487 #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
mbed_official 525:c320967f86b9 488 #define _CMU_CMD_USBCCLKSEL_USHFRCO 0x00000004UL /**< Mode USHFRCO for CMU_CMD */
mbed_official 525:c320967f86b9 489 #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
mbed_official 525:c320967f86b9 490 #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */
mbed_official 525:c320967f86b9 491 #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */
mbed_official 525:c320967f86b9 492 #define CMU_CMD_USBCCLKSEL_USHFRCO (_CMU_CMD_USBCCLKSEL_USHFRCO << 5) /**< Shifted mode USHFRCO for CMU_CMD */
mbed_official 525:c320967f86b9 493
mbed_official 525:c320967f86b9 494 /* Bit fields for CMU LFCLKSEL */
mbed_official 525:c320967f86b9 495 #define _CMU_LFCLKSEL_RESETVALUE 0x00000015UL /**< Default value for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 496 #define _CMU_LFCLKSEL_MASK 0x0011003FUL /**< Mask for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 497 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
mbed_official 525:c320967f86b9 498 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
mbed_official 525:c320967f86b9 499 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 500 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 501 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 502 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 503 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 504 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 505 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 506 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 507 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 508 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 509 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
mbed_official 525:c320967f86b9 510 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
mbed_official 525:c320967f86b9 511 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 512 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 513 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 514 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 515 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 516 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 517 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 518 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 519 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 520 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 521 #define _CMU_LFCLKSEL_LFC_SHIFT 4 /**< Shift value for CMU_LFC */
mbed_official 525:c320967f86b9 522 #define _CMU_LFCLKSEL_LFC_MASK 0x30UL /**< Bit mask for CMU_LFC */
mbed_official 525:c320967f86b9 523 #define _CMU_LFCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 524 #define _CMU_LFCLKSEL_LFC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 525 #define _CMU_LFCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 526 #define _CMU_LFCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 527 #define CMU_LFCLKSEL_LFC_DISABLED (_CMU_LFCLKSEL_LFC_DISABLED << 4) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 528 #define CMU_LFCLKSEL_LFC_DEFAULT (_CMU_LFCLKSEL_LFC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 529 #define CMU_LFCLKSEL_LFC_LFRCO (_CMU_LFCLKSEL_LFC_LFRCO << 4) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 530 #define CMU_LFCLKSEL_LFC_LFXO (_CMU_LFCLKSEL_LFC_LFXO << 4) /**< Shifted mode LFXO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 531 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
mbed_official 525:c320967f86b9 532 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
mbed_official 525:c320967f86b9 533 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
mbed_official 525:c320967f86b9 534 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 535 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 536 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 537 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 538 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 539 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 540 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
mbed_official 525:c320967f86b9 541 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
mbed_official 525:c320967f86b9 542 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
mbed_official 525:c320967f86b9 543 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 544 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 545 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 546 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 547 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 548 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
mbed_official 525:c320967f86b9 549
mbed_official 525:c320967f86b9 550 /* Bit fields for CMU STATUS */
mbed_official 525:c320967f86b9 551 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
mbed_official 525:c320967f86b9 552 #define _CMU_STATUS_MASK 0x04F77FFFUL /**< Mask for CMU_STATUS */
mbed_official 525:c320967f86b9 553 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
mbed_official 525:c320967f86b9 554 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
mbed_official 525:c320967f86b9 555 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
mbed_official 525:c320967f86b9 556 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 557 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 558 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
mbed_official 525:c320967f86b9 559 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 560 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 561 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 562 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 563 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
mbed_official 525:c320967f86b9 564 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
mbed_official 525:c320967f86b9 565 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
mbed_official 525:c320967f86b9 566 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 567 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 568 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
mbed_official 525:c320967f86b9 569 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
mbed_official 525:c320967f86b9 570 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
mbed_official 525:c320967f86b9 571 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 572 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 573 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
mbed_official 525:c320967f86b9 574 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
mbed_official 525:c320967f86b9 575 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
mbed_official 525:c320967f86b9 576 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 577 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 578 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
mbed_official 525:c320967f86b9 579 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 580 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 581 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 582 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 583 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
mbed_official 525:c320967f86b9 584 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
mbed_official 525:c320967f86b9 585 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
mbed_official 525:c320967f86b9 586 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 587 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 588 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
mbed_official 525:c320967f86b9 589 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 590 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 591 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 592 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 593 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
mbed_official 525:c320967f86b9 594 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
mbed_official 525:c320967f86b9 595 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
mbed_official 525:c320967f86b9 596 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 597 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 598 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
mbed_official 525:c320967f86b9 599 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
mbed_official 525:c320967f86b9 600 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
mbed_official 525:c320967f86b9 601 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 602 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 603 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
mbed_official 525:c320967f86b9 604 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
mbed_official 525:c320967f86b9 605 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
mbed_official 525:c320967f86b9 606 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 607 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 608 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
mbed_official 525:c320967f86b9 609 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
mbed_official 525:c320967f86b9 610 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
mbed_official 525:c320967f86b9 611 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 612 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 613 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
mbed_official 525:c320967f86b9 614 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
mbed_official 525:c320967f86b9 615 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
mbed_official 525:c320967f86b9 616 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 617 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 618 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
mbed_official 525:c320967f86b9 619 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
mbed_official 525:c320967f86b9 620 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
mbed_official 525:c320967f86b9 621 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 622 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 623 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
mbed_official 525:c320967f86b9 624 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
mbed_official 525:c320967f86b9 625 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
mbed_official 525:c320967f86b9 626 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 627 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 628 #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */
mbed_official 525:c320967f86b9 629 #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */
mbed_official 525:c320967f86b9 630 #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */
mbed_official 525:c320967f86b9 631 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 632 #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 633 #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */
mbed_official 525:c320967f86b9 634 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */
mbed_official 525:c320967f86b9 635 #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */
mbed_official 525:c320967f86b9 636 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 637 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 638 #define CMU_STATUS_USBCUSHFRCOSEL (0x1UL << 18) /**< USBC USHFRCO Selected */
mbed_official 525:c320967f86b9 639 #define _CMU_STATUS_USBCUSHFRCOSEL_SHIFT 18 /**< Shift value for CMU_USBCUSHFRCOSEL */
mbed_official 525:c320967f86b9 640 #define _CMU_STATUS_USBCUSHFRCOSEL_MASK 0x40000UL /**< Bit mask for CMU_USBCUSHFRCOSEL */
mbed_official 525:c320967f86b9 641 #define _CMU_STATUS_USBCUSHFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 642 #define CMU_STATUS_USBCUSHFRCOSEL_DEFAULT (_CMU_STATUS_USBCUSHFRCOSEL_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 643 #define CMU_STATUS_USBCHFCLKSYNC (0x1UL << 20) /**< USBC is synchronous to HFCLK */
mbed_official 525:c320967f86b9 644 #define _CMU_STATUS_USBCHFCLKSYNC_SHIFT 20 /**< Shift value for CMU_USBCHFCLKSYNC */
mbed_official 525:c320967f86b9 645 #define _CMU_STATUS_USBCHFCLKSYNC_MASK 0x100000UL /**< Bit mask for CMU_USBCHFCLKSYNC */
mbed_official 525:c320967f86b9 646 #define _CMU_STATUS_USBCHFCLKSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 647 #define CMU_STATUS_USBCHFCLKSYNC_DEFAULT (_CMU_STATUS_USBCHFCLKSYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 648 #define CMU_STATUS_USHFRCOENS (0x1UL << 21) /**< USHFRCO Enable Status */
mbed_official 525:c320967f86b9 649 #define _CMU_STATUS_USHFRCOENS_SHIFT 21 /**< Shift value for CMU_USHFRCOENS */
mbed_official 525:c320967f86b9 650 #define _CMU_STATUS_USHFRCOENS_MASK 0x200000UL /**< Bit mask for CMU_USHFRCOENS */
mbed_official 525:c320967f86b9 651 #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 652 #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 653 #define CMU_STATUS_USHFRCORDY (0x1UL << 22) /**< USHFRCO Ready */
mbed_official 525:c320967f86b9 654 #define _CMU_STATUS_USHFRCORDY_SHIFT 22 /**< Shift value for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 655 #define _CMU_STATUS_USHFRCORDY_MASK 0x400000UL /**< Bit mask for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 656 #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 657 #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 658 #define CMU_STATUS_USHFRCOSUSPEND (0x1UL << 23) /**< USHFRCO is suspended */
mbed_official 525:c320967f86b9 659 #define _CMU_STATUS_USHFRCOSUSPEND_SHIFT 23 /**< Shift value for CMU_USHFRCOSUSPEND */
mbed_official 525:c320967f86b9 660 #define _CMU_STATUS_USHFRCOSUSPEND_MASK 0x800000UL /**< Bit mask for CMU_USHFRCOSUSPEND */
mbed_official 525:c320967f86b9 661 #define _CMU_STATUS_USHFRCOSUSPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 662 #define CMU_STATUS_USHFRCOSUSPEND_DEFAULT (_CMU_STATUS_USHFRCOSUSPEND_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 663 #define CMU_STATUS_USHFRCODIV2SEL (0x1UL << 26) /**< USHFRCODIV2 Selected */
mbed_official 525:c320967f86b9 664 #define _CMU_STATUS_USHFRCODIV2SEL_SHIFT 26 /**< Shift value for CMU_USHFRCODIV2SEL */
mbed_official 525:c320967f86b9 665 #define _CMU_STATUS_USHFRCODIV2SEL_MASK 0x4000000UL /**< Bit mask for CMU_USHFRCODIV2SEL */
mbed_official 525:c320967f86b9 666 #define _CMU_STATUS_USHFRCODIV2SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 667 #define CMU_STATUS_USHFRCODIV2SEL_DEFAULT (_CMU_STATUS_USHFRCODIV2SEL_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */
mbed_official 525:c320967f86b9 668
mbed_official 525:c320967f86b9 669 /* Bit fields for CMU IF */
mbed_official 525:c320967f86b9 670 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
mbed_official 525:c320967f86b9 671 #define _CMU_IF_MASK 0x0000037FUL /**< Mask for CMU_IF */
mbed_official 525:c320967f86b9 672 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
mbed_official 525:c320967f86b9 673 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 674 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 675 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 676 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 677 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
mbed_official 525:c320967f86b9 678 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
mbed_official 525:c320967f86b9 679 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
mbed_official 525:c320967f86b9 680 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 681 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 682 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
mbed_official 525:c320967f86b9 683 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 684 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 685 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 686 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 687 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
mbed_official 525:c320967f86b9 688 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
mbed_official 525:c320967f86b9 689 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
mbed_official 525:c320967f86b9 690 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 691 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 692 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
mbed_official 525:c320967f86b9 693 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 694 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 695 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 696 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 697 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
mbed_official 525:c320967f86b9 698 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
mbed_official 525:c320967f86b9 699 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
mbed_official 525:c320967f86b9 700 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 701 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 702 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
mbed_official 525:c320967f86b9 703 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
mbed_official 525:c320967f86b9 704 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
mbed_official 525:c320967f86b9 705 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 706 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 707 #define CMU_IF_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag */
mbed_official 525:c320967f86b9 708 #define _CMU_IF_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 709 #define _CMU_IF_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 710 #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 711 #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 712 #define CMU_IF_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag */
mbed_official 525:c320967f86b9 713 #define _CMU_IF_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */
mbed_official 525:c320967f86b9 714 #define _CMU_IF_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */
mbed_official 525:c320967f86b9 715 #define _CMU_IF_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 716 #define CMU_IF_USBCHFOSCSEL_DEFAULT (_CMU_IF_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */
mbed_official 525:c320967f86b9 717
mbed_official 525:c320967f86b9 718 /* Bit fields for CMU IFS */
mbed_official 525:c320967f86b9 719 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
mbed_official 525:c320967f86b9 720 #define _CMU_IFS_MASK 0x0000037FUL /**< Mask for CMU_IFS */
mbed_official 525:c320967f86b9 721 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
mbed_official 525:c320967f86b9 722 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 723 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 724 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 725 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 726 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
mbed_official 525:c320967f86b9 727 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
mbed_official 525:c320967f86b9 728 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
mbed_official 525:c320967f86b9 729 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 730 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 731 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
mbed_official 525:c320967f86b9 732 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 733 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 734 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 735 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 736 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
mbed_official 525:c320967f86b9 737 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
mbed_official 525:c320967f86b9 738 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
mbed_official 525:c320967f86b9 739 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 740 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 741 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
mbed_official 525:c320967f86b9 742 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 743 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 744 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 745 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 746 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
mbed_official 525:c320967f86b9 747 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
mbed_official 525:c320967f86b9 748 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
mbed_official 525:c320967f86b9 749 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 750 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 751 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
mbed_official 525:c320967f86b9 752 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
mbed_official 525:c320967f86b9 753 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
mbed_official 525:c320967f86b9 754 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 755 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 756 #define CMU_IFS_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag Set */
mbed_official 525:c320967f86b9 757 #define _CMU_IFS_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 758 #define _CMU_IFS_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 759 #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 760 #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 761 #define CMU_IFS_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag Set */
mbed_official 525:c320967f86b9 762 #define _CMU_IFS_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */
mbed_official 525:c320967f86b9 763 #define _CMU_IFS_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */
mbed_official 525:c320967f86b9 764 #define _CMU_IFS_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 765 #define CMU_IFS_USBCHFOSCSEL_DEFAULT (_CMU_IFS_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */
mbed_official 525:c320967f86b9 766
mbed_official 525:c320967f86b9 767 /* Bit fields for CMU IFC */
mbed_official 525:c320967f86b9 768 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
mbed_official 525:c320967f86b9 769 #define _CMU_IFC_MASK 0x0000037FUL /**< Mask for CMU_IFC */
mbed_official 525:c320967f86b9 770 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
mbed_official 525:c320967f86b9 771 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 772 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 773 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 774 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 775 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
mbed_official 525:c320967f86b9 776 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
mbed_official 525:c320967f86b9 777 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
mbed_official 525:c320967f86b9 778 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 779 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 780 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
mbed_official 525:c320967f86b9 781 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 782 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 783 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 784 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 785 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
mbed_official 525:c320967f86b9 786 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
mbed_official 525:c320967f86b9 787 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
mbed_official 525:c320967f86b9 788 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 789 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 790 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
mbed_official 525:c320967f86b9 791 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 792 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 793 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 794 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 795 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
mbed_official 525:c320967f86b9 796 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
mbed_official 525:c320967f86b9 797 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
mbed_official 525:c320967f86b9 798 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 799 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 800 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
mbed_official 525:c320967f86b9 801 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
mbed_official 525:c320967f86b9 802 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
mbed_official 525:c320967f86b9 803 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 804 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 805 #define CMU_IFC_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag Clear */
mbed_official 525:c320967f86b9 806 #define _CMU_IFC_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 807 #define _CMU_IFC_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 808 #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 809 #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 810 #define CMU_IFC_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag Clear */
mbed_official 525:c320967f86b9 811 #define _CMU_IFC_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */
mbed_official 525:c320967f86b9 812 #define _CMU_IFC_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */
mbed_official 525:c320967f86b9 813 #define _CMU_IFC_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 814 #define CMU_IFC_USBCHFOSCSEL_DEFAULT (_CMU_IFC_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */
mbed_official 525:c320967f86b9 815
mbed_official 525:c320967f86b9 816 /* Bit fields for CMU IEN */
mbed_official 525:c320967f86b9 817 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
mbed_official 525:c320967f86b9 818 #define _CMU_IEN_MASK 0x0000037FUL /**< Mask for CMU_IEN */
mbed_official 525:c320967f86b9 819 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
mbed_official 525:c320967f86b9 820 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 821 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
mbed_official 525:c320967f86b9 822 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 823 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 824 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
mbed_official 525:c320967f86b9 825 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
mbed_official 525:c320967f86b9 826 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
mbed_official 525:c320967f86b9 827 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 828 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 829 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
mbed_official 525:c320967f86b9 830 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 831 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
mbed_official 525:c320967f86b9 832 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 833 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 834 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
mbed_official 525:c320967f86b9 835 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
mbed_official 525:c320967f86b9 836 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
mbed_official 525:c320967f86b9 837 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 838 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 839 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
mbed_official 525:c320967f86b9 840 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 841 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
mbed_official 525:c320967f86b9 842 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 843 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 844 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
mbed_official 525:c320967f86b9 845 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
mbed_official 525:c320967f86b9 846 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
mbed_official 525:c320967f86b9 847 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 848 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 849 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
mbed_official 525:c320967f86b9 850 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
mbed_official 525:c320967f86b9 851 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
mbed_official 525:c320967f86b9 852 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 853 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 854 #define CMU_IEN_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Enable */
mbed_official 525:c320967f86b9 855 #define _CMU_IEN_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 856 #define _CMU_IEN_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */
mbed_official 525:c320967f86b9 857 #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 858 #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 859 #define CMU_IEN_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag Clear */
mbed_official 525:c320967f86b9 860 #define _CMU_IEN_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */
mbed_official 525:c320967f86b9 861 #define _CMU_IEN_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */
mbed_official 525:c320967f86b9 862 #define _CMU_IEN_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 863 #define CMU_IEN_USBCHFOSCSEL_DEFAULT (_CMU_IEN_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */
mbed_official 525:c320967f86b9 864
mbed_official 525:c320967f86b9 865 /* Bit fields for CMU HFCORECLKEN0 */
mbed_official 525:c320967f86b9 866 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 867 #define _CMU_HFCORECLKEN0_MASK 0x0000001FUL /**< Mask for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 868 #define CMU_HFCORECLKEN0_AES (0x1UL << 0) /**< Advanced Encryption Standard Accelerator Clock Enable */
mbed_official 525:c320967f86b9 869 #define _CMU_HFCORECLKEN0_AES_SHIFT 0 /**< Shift value for CMU_AES */
mbed_official 525:c320967f86b9 870 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL /**< Bit mask for CMU_AES */
mbed_official 525:c320967f86b9 871 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 872 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 873 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1) /**< Direct Memory Access Controller Clock Enable */
mbed_official 525:c320967f86b9 874 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1 /**< Shift value for CMU_DMA */
mbed_official 525:c320967f86b9 875 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL /**< Bit mask for CMU_DMA */
mbed_official 525:c320967f86b9 876 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 877 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 878 #define CMU_HFCORECLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */
mbed_official 525:c320967f86b9 879 #define _CMU_HFCORECLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */
mbed_official 525:c320967f86b9 880 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */
mbed_official 525:c320967f86b9 881 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 882 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 883 #define CMU_HFCORECLKEN0_USBC (0x1UL << 3) /**< Universal Serial Bus Interface Core Clock Enable */
mbed_official 525:c320967f86b9 884 #define _CMU_HFCORECLKEN0_USBC_SHIFT 3 /**< Shift value for CMU_USBC */
mbed_official 525:c320967f86b9 885 #define _CMU_HFCORECLKEN0_USBC_MASK 0x8UL /**< Bit mask for CMU_USBC */
mbed_official 525:c320967f86b9 886 #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 887 #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 888 #define CMU_HFCORECLKEN0_USB (0x1UL << 4) /**< Universal Serial Bus Interface Clock Enable */
mbed_official 525:c320967f86b9 889 #define _CMU_HFCORECLKEN0_USB_SHIFT 4 /**< Shift value for CMU_USB */
mbed_official 525:c320967f86b9 890 #define _CMU_HFCORECLKEN0_USB_MASK 0x10UL /**< Bit mask for CMU_USB */
mbed_official 525:c320967f86b9 891 #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 892 #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
mbed_official 525:c320967f86b9 893
mbed_official 525:c320967f86b9 894 /* Bit fields for CMU HFPERCLKEN0 */
mbed_official 525:c320967f86b9 895 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 896 #define _CMU_HFPERCLKEN0_MASK 0x00000FFFUL /**< Mask for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 897 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */
mbed_official 525:c320967f86b9 898 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */
mbed_official 525:c320967f86b9 899 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */
mbed_official 525:c320967f86b9 900 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 901 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 902 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */
mbed_official 525:c320967f86b9 903 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */
mbed_official 525:c320967f86b9 904 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */
mbed_official 525:c320967f86b9 905 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 906 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 907 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */
mbed_official 525:c320967f86b9 908 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */
mbed_official 525:c320967f86b9 909 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */
mbed_official 525:c320967f86b9 910 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 911 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 912 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
mbed_official 525:c320967f86b9 913 #define _CMU_HFPERCLKEN0_USART0_SHIFT 3 /**< Shift value for CMU_USART0 */
mbed_official 525:c320967f86b9 914 #define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL /**< Bit mask for CMU_USART0 */
mbed_official 525:c320967f86b9 915 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 916 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 917 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
mbed_official 525:c320967f86b9 918 #define _CMU_HFPERCLKEN0_USART1_SHIFT 4 /**< Shift value for CMU_USART1 */
mbed_official 525:c320967f86b9 919 #define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL /**< Bit mask for CMU_USART1 */
mbed_official 525:c320967f86b9 920 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 921 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 922 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 5) /**< Analog Comparator 0 Clock Enable */
mbed_official 525:c320967f86b9 923 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 5 /**< Shift value for CMU_ACMP0 */
mbed_official 525:c320967f86b9 924 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x20UL /**< Bit mask for CMU_ACMP0 */
mbed_official 525:c320967f86b9 925 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 926 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 927 #define CMU_HFPERCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */
mbed_official 525:c320967f86b9 928 #define _CMU_HFPERCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */
mbed_official 525:c320967f86b9 929 #define _CMU_HFPERCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */
mbed_official 525:c320967f86b9 930 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 931 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 932 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 7) /**< Current Digital to Analog Converter 0 Clock Enable */
mbed_official 525:c320967f86b9 933 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 7 /**< Shift value for CMU_IDAC0 */
mbed_official 525:c320967f86b9 934 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x80UL /**< Bit mask for CMU_IDAC0 */
mbed_official 525:c320967f86b9 935 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 936 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 937 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 8) /**< General purpose Input/Output Clock Enable */
mbed_official 525:c320967f86b9 938 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 8 /**< Shift value for CMU_GPIO */
mbed_official 525:c320967f86b9 939 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x100UL /**< Bit mask for CMU_GPIO */
mbed_official 525:c320967f86b9 940 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 941 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 942 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 9) /**< Voltage Comparator Clock Enable */
mbed_official 525:c320967f86b9 943 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 9 /**< Shift value for CMU_VCMP */
mbed_official 525:c320967f86b9 944 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x200UL /**< Bit mask for CMU_VCMP */
mbed_official 525:c320967f86b9 945 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 946 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 947 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 10) /**< Analog to Digital Converter 0 Clock Enable */
mbed_official 525:c320967f86b9 948 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 10 /**< Shift value for CMU_ADC0 */
mbed_official 525:c320967f86b9 949 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x400UL /**< Bit mask for CMU_ADC0 */
mbed_official 525:c320967f86b9 950 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 951 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 952 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
mbed_official 525:c320967f86b9 953 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
mbed_official 525:c320967f86b9 954 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
mbed_official 525:c320967f86b9 955 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 956 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
mbed_official 525:c320967f86b9 957
mbed_official 525:c320967f86b9 958 /* Bit fields for CMU SYNCBUSY */
mbed_official 525:c320967f86b9 959 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 960 #define _CMU_SYNCBUSY_MASK 0x00000155UL /**< Mask for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 961 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
mbed_official 525:c320967f86b9 962 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
mbed_official 525:c320967f86b9 963 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
mbed_official 525:c320967f86b9 964 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 965 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 966 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
mbed_official 525:c320967f86b9 967 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 968 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 969 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 970 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 971 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
mbed_official 525:c320967f86b9 972 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
mbed_official 525:c320967f86b9 973 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
mbed_official 525:c320967f86b9 974 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 975 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 976 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
mbed_official 525:c320967f86b9 977 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 978 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 979 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 980 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 981 #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */
mbed_official 525:c320967f86b9 982 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */
mbed_official 525:c320967f86b9 983 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */
mbed_official 525:c320967f86b9 984 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 985 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
mbed_official 525:c320967f86b9 986
mbed_official 525:c320967f86b9 987 /* Bit fields for CMU FREEZE */
mbed_official 525:c320967f86b9 988 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
mbed_official 525:c320967f86b9 989 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
mbed_official 525:c320967f86b9 990 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
mbed_official 525:c320967f86b9 991 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
mbed_official 525:c320967f86b9 992 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
mbed_official 525:c320967f86b9 993 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
mbed_official 525:c320967f86b9 994 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
mbed_official 525:c320967f86b9 995 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
mbed_official 525:c320967f86b9 996 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
mbed_official 525:c320967f86b9 997 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
mbed_official 525:c320967f86b9 998 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
mbed_official 525:c320967f86b9 999
mbed_official 525:c320967f86b9 1000 /* Bit fields for CMU LFACLKEN0 */
mbed_official 525:c320967f86b9 1001 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
mbed_official 525:c320967f86b9 1002 #define _CMU_LFACLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFACLKEN0 */
mbed_official 525:c320967f86b9 1003 #define CMU_LFACLKEN0_RTC (0x1UL << 0) /**< Real-Time Counter Clock Enable */
mbed_official 525:c320967f86b9 1004 #define _CMU_LFACLKEN0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */
mbed_official 525:c320967f86b9 1005 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL /**< Bit mask for CMU_RTC */
mbed_official 525:c320967f86b9 1006 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
mbed_official 525:c320967f86b9 1007 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
mbed_official 525:c320967f86b9 1008
mbed_official 525:c320967f86b9 1009 /* Bit fields for CMU LFBCLKEN0 */
mbed_official 525:c320967f86b9 1010 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
mbed_official 525:c320967f86b9 1011 #define _CMU_LFBCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFBCLKEN0 */
mbed_official 525:c320967f86b9 1012 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
mbed_official 525:c320967f86b9 1013 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
mbed_official 525:c320967f86b9 1014 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
mbed_official 525:c320967f86b9 1015 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
mbed_official 525:c320967f86b9 1016 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
mbed_official 525:c320967f86b9 1017
mbed_official 525:c320967f86b9 1018 /* Bit fields for CMU LFCCLKEN0 */
mbed_official 525:c320967f86b9 1019 #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */
mbed_official 525:c320967f86b9 1020 #define _CMU_LFCCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFCCLKEN0 */
mbed_official 525:c320967f86b9 1021 #define CMU_LFCCLKEN0_USBLE (0x1UL << 0) /**< Universal Serial Bus Low Energy Clock Clock Enable */
mbed_official 525:c320967f86b9 1022 #define _CMU_LFCCLKEN0_USBLE_SHIFT 0 /**< Shift value for CMU_USBLE */
mbed_official 525:c320967f86b9 1023 #define _CMU_LFCCLKEN0_USBLE_MASK 0x1UL /**< Bit mask for CMU_USBLE */
mbed_official 525:c320967f86b9 1024 #define _CMU_LFCCLKEN0_USBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKEN0 */
mbed_official 525:c320967f86b9 1025 #define CMU_LFCCLKEN0_USBLE_DEFAULT (_CMU_LFCCLKEN0_USBLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKEN0 */
mbed_official 525:c320967f86b9 1026
mbed_official 525:c320967f86b9 1027 /* Bit fields for CMU LFAPRESC0 */
mbed_official 525:c320967f86b9 1028 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1029 #define _CMU_LFAPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1030 #define _CMU_LFAPRESC0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */
mbed_official 525:c320967f86b9 1031 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL /**< Bit mask for CMU_RTC */
mbed_official 525:c320967f86b9 1032 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1033 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1034 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1035 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1036 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1037 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1038 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1039 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1040 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1041 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1042 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1043 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1044 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1045 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1046 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1047 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1048 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1049 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1050 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1051 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1052 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1053 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1054 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1055 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1056 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1057 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1058 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1059 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1060 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1061 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1062 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1063 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
mbed_official 525:c320967f86b9 1064
mbed_official 525:c320967f86b9 1065 /* Bit fields for CMU LFBPRESC0 */
mbed_official 525:c320967f86b9 1066 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1067 #define _CMU_LFBPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1068 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
mbed_official 525:c320967f86b9 1069 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
mbed_official 525:c320967f86b9 1070 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1071 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1072 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1073 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1074 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1075 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1076 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1077 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
mbed_official 525:c320967f86b9 1078
mbed_official 525:c320967f86b9 1079 /* Bit fields for CMU PCNTCTRL */
mbed_official 525:c320967f86b9 1080 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1081 #define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1082 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
mbed_official 525:c320967f86b9 1083 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
mbed_official 525:c320967f86b9 1084 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
mbed_official 525:c320967f86b9 1085 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1086 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1087 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
mbed_official 525:c320967f86b9 1088 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
mbed_official 525:c320967f86b9 1089 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
mbed_official 525:c320967f86b9 1090 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1091 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1092 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1093 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1094 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1095 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
mbed_official 525:c320967f86b9 1096
mbed_official 525:c320967f86b9 1097 /* Bit fields for CMU ROUTE */
mbed_official 525:c320967f86b9 1098 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
mbed_official 525:c320967f86b9 1099 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
mbed_official 525:c320967f86b9 1100 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
mbed_official 525:c320967f86b9 1101 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
mbed_official 525:c320967f86b9 1102 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
mbed_official 525:c320967f86b9 1103 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
mbed_official 525:c320967f86b9 1104 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
mbed_official 525:c320967f86b9 1105 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
mbed_official 525:c320967f86b9 1106 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
mbed_official 525:c320967f86b9 1107 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
mbed_official 525:c320967f86b9 1108 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
mbed_official 525:c320967f86b9 1109 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
mbed_official 525:c320967f86b9 1110 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
mbed_official 525:c320967f86b9 1111 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
mbed_official 525:c320967f86b9 1112 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
mbed_official 525:c320967f86b9 1113 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
mbed_official 525:c320967f86b9 1114 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
mbed_official 525:c320967f86b9 1115 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
mbed_official 525:c320967f86b9 1116 #define _CMU_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTE */
mbed_official 525:c320967f86b9 1117 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
mbed_official 525:c320967f86b9 1118 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
mbed_official 525:c320967f86b9 1119 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
mbed_official 525:c320967f86b9 1120 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
mbed_official 525:c320967f86b9 1121 #define CMU_ROUTE_LOCATION_LOC3 (_CMU_ROUTE_LOCATION_LOC3 << 2) /**< Shifted mode LOC3 for CMU_ROUTE */
mbed_official 525:c320967f86b9 1122
mbed_official 525:c320967f86b9 1123 /* Bit fields for CMU LOCK */
mbed_official 525:c320967f86b9 1124 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
mbed_official 525:c320967f86b9 1125 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
mbed_official 525:c320967f86b9 1126 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
mbed_official 525:c320967f86b9 1127 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
mbed_official 525:c320967f86b9 1128 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
mbed_official 525:c320967f86b9 1129 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
mbed_official 525:c320967f86b9 1130 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
mbed_official 525:c320967f86b9 1131 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
mbed_official 525:c320967f86b9 1132 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
mbed_official 525:c320967f86b9 1133 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
mbed_official 525:c320967f86b9 1134 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
mbed_official 525:c320967f86b9 1135 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
mbed_official 525:c320967f86b9 1136 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
mbed_official 525:c320967f86b9 1137 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
mbed_official 525:c320967f86b9 1138
mbed_official 525:c320967f86b9 1139 /* Bit fields for CMU USBCRCTRL */
mbed_official 525:c320967f86b9 1140 #define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCRCTRL */
mbed_official 525:c320967f86b9 1141 #define _CMU_USBCRCTRL_MASK 0x00000003UL /**< Mask for CMU_USBCRCTRL */
mbed_official 525:c320967f86b9 1142 #define CMU_USBCRCTRL_EN (0x1UL << 0) /**< Clock Recovery Enable */
mbed_official 525:c320967f86b9 1143 #define _CMU_USBCRCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */
mbed_official 525:c320967f86b9 1144 #define _CMU_USBCRCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */
mbed_official 525:c320967f86b9 1145 #define _CMU_USBCRCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */
mbed_official 525:c320967f86b9 1146 #define CMU_USBCRCTRL_EN_DEFAULT (_CMU_USBCRCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */
mbed_official 525:c320967f86b9 1147 #define CMU_USBCRCTRL_LSMODE (0x1UL << 1) /**< Low Speed Clock Recovery Mode */
mbed_official 525:c320967f86b9 1148 #define _CMU_USBCRCTRL_LSMODE_SHIFT 1 /**< Shift value for CMU_LSMODE */
mbed_official 525:c320967f86b9 1149 #define _CMU_USBCRCTRL_LSMODE_MASK 0x2UL /**< Bit mask for CMU_LSMODE */
mbed_official 525:c320967f86b9 1150 #define _CMU_USBCRCTRL_LSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */
mbed_official 525:c320967f86b9 1151 #define CMU_USBCRCTRL_LSMODE_DEFAULT (_CMU_USBCRCTRL_LSMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */
mbed_official 525:c320967f86b9 1152
mbed_official 525:c320967f86b9 1153 /* Bit fields for CMU USHFRCOCTRL */
mbed_official 525:c320967f86b9 1154 #define _CMU_USHFRCOCTRL_RESETVALUE 0x000FF040UL /**< Default value for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1155 #define _CMU_USHFRCOCTRL_MASK 0x000FF37FUL /**< Mask for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1156 #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
mbed_official 525:c320967f86b9 1157 #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
mbed_official 525:c320967f86b9 1158 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1159 #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1160 #define CMU_USHFRCOCTRL_DITHEN (0x1UL << 8) /**< USHFRCO dither enable */
mbed_official 525:c320967f86b9 1161 #define _CMU_USHFRCOCTRL_DITHEN_SHIFT 8 /**< Shift value for CMU_DITHEN */
mbed_official 525:c320967f86b9 1162 #define _CMU_USHFRCOCTRL_DITHEN_MASK 0x100UL /**< Bit mask for CMU_DITHEN */
mbed_official 525:c320967f86b9 1163 #define _CMU_USHFRCOCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1164 #define CMU_USHFRCOCTRL_DITHEN_DEFAULT (_CMU_USHFRCOCTRL_DITHEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1165 #define CMU_USHFRCOCTRL_SUSPEND (0x1UL << 9) /**< USHFRCO suspend */
mbed_official 525:c320967f86b9 1166 #define _CMU_USHFRCOCTRL_SUSPEND_SHIFT 9 /**< Shift value for CMU_SUSPEND */
mbed_official 525:c320967f86b9 1167 #define _CMU_USHFRCOCTRL_SUSPEND_MASK 0x200UL /**< Bit mask for CMU_SUSPEND */
mbed_official 525:c320967f86b9 1168 #define _CMU_USHFRCOCTRL_SUSPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1169 #define CMU_USHFRCOCTRL_SUSPEND_DEFAULT (_CMU_USHFRCOCTRL_SUSPEND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1170 #define _CMU_USHFRCOCTRL_TIMEOUT_SHIFT 12 /**< Shift value for CMU_TIMEOUT */
mbed_official 525:c320967f86b9 1171 #define _CMU_USHFRCOCTRL_TIMEOUT_MASK 0xFF000UL /**< Bit mask for CMU_TIMEOUT */
mbed_official 525:c320967f86b9 1172 #define _CMU_USHFRCOCTRL_TIMEOUT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1173 #define CMU_USHFRCOCTRL_TIMEOUT_DEFAULT (_CMU_USHFRCOCTRL_TIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
mbed_official 525:c320967f86b9 1174
mbed_official 525:c320967f86b9 1175 /* Bit fields for CMU USHFRCOTUNE */
mbed_official 525:c320967f86b9 1176 #define _CMU_USHFRCOTUNE_RESETVALUE 0x00000020UL /**< Default value for CMU_USHFRCOTUNE */
mbed_official 525:c320967f86b9 1177 #define _CMU_USHFRCOTUNE_MASK 0x0000003FUL /**< Mask for CMU_USHFRCOTUNE */
mbed_official 525:c320967f86b9 1178 #define _CMU_USHFRCOTUNE_FINETUNING_SHIFT 0 /**< Shift value for CMU_FINETUNING */
mbed_official 525:c320967f86b9 1179 #define _CMU_USHFRCOTUNE_FINETUNING_MASK 0x3FUL /**< Bit mask for CMU_FINETUNING */
mbed_official 525:c320967f86b9 1180 #define _CMU_USHFRCOTUNE_FINETUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_USHFRCOTUNE */
mbed_official 525:c320967f86b9 1181 #define CMU_USHFRCOTUNE_FINETUNING_DEFAULT (_CMU_USHFRCOTUNE_FINETUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOTUNE */
mbed_official 525:c320967f86b9 1182
mbed_official 525:c320967f86b9 1183 /* Bit fields for CMU USHFRCOCONF */
mbed_official 525:c320967f86b9 1184 #define _CMU_USHFRCOCONF_RESETVALUE 0x00000001UL /**< Default value for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1185 #define _CMU_USHFRCOCONF_MASK 0x00000017UL /**< Mask for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1186 #define _CMU_USHFRCOCONF_BAND_SHIFT 0 /**< Shift value for CMU_BAND */
mbed_official 525:c320967f86b9 1187 #define _CMU_USHFRCOCONF_BAND_MASK 0x7UL /**< Bit mask for CMU_BAND */
mbed_official 525:c320967f86b9 1188 #define _CMU_USHFRCOCONF_BAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1189 #define _CMU_USHFRCOCONF_BAND_48MHZ 0x00000001UL /**< Mode 48MHZ for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1190 #define _CMU_USHFRCOCONF_BAND_24MHZ 0x00000003UL /**< Mode 24MHZ for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1191 #define CMU_USHFRCOCONF_BAND_DEFAULT (_CMU_USHFRCOCONF_BAND_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1192 #define CMU_USHFRCOCONF_BAND_48MHZ (_CMU_USHFRCOCONF_BAND_48MHZ << 0) /**< Shifted mode 48MHZ for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1193 #define CMU_USHFRCOCONF_BAND_24MHZ (_CMU_USHFRCOCONF_BAND_24MHZ << 0) /**< Shifted mode 24MHZ for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1194 #define CMU_USHFRCOCONF_USHFRCODIV2DIS (0x1UL << 4) /**< USHFRCO divider for HFCLK disable */
mbed_official 525:c320967f86b9 1195 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT 4 /**< Shift value for CMU_USHFRCODIV2DIS */
mbed_official 525:c320967f86b9 1196 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_MASK 0x10UL /**< Bit mask for CMU_USHFRCODIV2DIS */
mbed_official 525:c320967f86b9 1197 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1198 #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */
mbed_official 525:c320967f86b9 1199
mbed_official 525:c320967f86b9 1200 /** @} End of group EFM32HG_CMU */
mbed_official 525:c320967f86b9 1201
mbed_official 525:c320967f86b9 1202