GameOpener / mbed-src

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@363:12a245e5c745, 2014-10-23 (annotated)

Committer:
mbed_official
Date:
Thu Oct 23 09:45:08 2014 +0100
Revision:
363:12a245e5c745
Parent:
82:0b31dbcd4769
Child:
441:d2c15dda23c1
Synchronized with git revision 6ff7dfe464a15417f666938479c7860707707331



Full URL: https://github.com/mbedmicro/mbed/commit/6ff7dfe464a15417f666938479c7860707707331/



Target: Freescale FRDM-KL43Z addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 82:0b31dbcd4769 1 /* mbed Microcontroller Library
mbed_official 82:0b31dbcd4769 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 82:0b31dbcd4769 3 *
mbed_official 82:0b31dbcd4769 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 82:0b31dbcd4769 5 * you may not use this file except in compliance with the License.
mbed_official 82:0b31dbcd4769 6 * You may obtain a copy of the License at
mbed_official 82:0b31dbcd4769 7 *
mbed_official 82:0b31dbcd4769 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 82:0b31dbcd4769 9 *
mbed_official 82:0b31dbcd4769 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 82:0b31dbcd4769 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 82:0b31dbcd4769 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 82:0b31dbcd4769 13 * See the License for the specific language governing permissions and
mbed_official 82:0b31dbcd4769 14 * limitations under the License.
mbed_official 82:0b31dbcd4769 15 */
mbed_official 82:0b31dbcd4769 16 #ifndef MBED_CLK_FREQS_H
mbed_official 82:0b31dbcd4769 17 #define MBED_CLK_FREQS_H
mbed_official 82:0b31dbcd4769 18
mbed_official 82:0b31dbcd4769 19 #ifdef __cplusplus
mbed_official 82:0b31dbcd4769 20 extern "C" {
mbed_official 82:0b31dbcd4769 21 #endif
mbed_official 82:0b31dbcd4769 22
mbed_official 82:0b31dbcd4769 23 #include "PeripheralPins.h"
mbed_official 82:0b31dbcd4769 24
mbed_official 82:0b31dbcd4769 25 //Get the peripheral bus clock frequency
mbed_official 82:0b31dbcd4769 26 static inline uint32_t bus_frequency(void) {
mbed_official 363:12a245e5c745 27 return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
mbed_official 363:12a245e5c745 28 }
mbed_official 363:12a245e5c745 29
mbed_official 363:12a245e5c745 30 #if defined(TARGET_KL43Z)
mbed_official 363:12a245e5c745 31
mbed_official 363:12a245e5c745 32 static inline uint32_t extosc_frequency(void) {
mbed_official 363:12a245e5c745 33 return CPU_XTAL_CLK_HZ;
mbed_official 82:0b31dbcd4769 34 }
mbed_official 82:0b31dbcd4769 35
mbed_official 363:12a245e5c745 36 static inline uint32_t mcgirc_frequency(void) {
mbed_official 363:12a245e5c745 37 uint32_t mcgirc_clock = 0;
mbed_official 363:12a245e5c745 38
mbed_official 363:12a245e5c745 39 if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
mbed_official 363:12a245e5c745 40 mcgirc_clock = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
mbed_official 363:12a245e5c745 41 mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
mbed_official 363:12a245e5c745 42 mcgirc_clock /= 1u + (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
mbed_official 363:12a245e5c745 43 }
mbed_official 363:12a245e5c745 44
mbed_official 363:12a245e5c745 45 return mcgirc_clock;
mbed_official 363:12a245e5c745 46 }
mbed_official 363:12a245e5c745 47
mbed_official 363:12a245e5c745 48 #else
mbed_official 363:12a245e5c745 49
mbed_official 82:0b31dbcd4769 50 //Get external oscillator (crystal) frequency
mbed_official 82:0b31dbcd4769 51 static uint32_t extosc_frequency(void) {
mbed_official 82:0b31dbcd4769 52 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
mbed_official 82:0b31dbcd4769 53
mbed_official 82:0b31dbcd4769 54 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
mbed_official 82:0b31dbcd4769 55 return MCGClock;
mbed_official 82:0b31dbcd4769 56
mbed_official 82:0b31dbcd4769 57 uint32_t divider, multiplier;
mbed_official 363:12a245e5c745 58 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
mbed_official 82:0b31dbcd4769 59 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
mbed_official 82:0b31dbcd4769 60 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
mbed_official 82:0b31dbcd4769 61 #endif
mbed_official 82:0b31dbcd4769 62 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
mbed_official 82:0b31dbcd4769 63 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 82:0b31dbcd4769 64 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
mbed_official 82:0b31dbcd4769 65 divider <<= 5u;
mbed_official 82:0b31dbcd4769 66 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 82:0b31dbcd4769 67 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 82:0b31dbcd4769 68 case 0x0u:
mbed_official 82:0b31dbcd4769 69 multiplier = 640u;
mbed_official 82:0b31dbcd4769 70 break;
mbed_official 82:0b31dbcd4769 71 case 0x20u:
mbed_official 82:0b31dbcd4769 72 multiplier = 1280u;
mbed_official 82:0b31dbcd4769 73 break;
mbed_official 82:0b31dbcd4769 74 case 0x40u:
mbed_official 82:0b31dbcd4769 75 multiplier = 1920u;
mbed_official 82:0b31dbcd4769 76 break;
mbed_official 82:0b31dbcd4769 77 case 0x60u:
mbed_official 82:0b31dbcd4769 78 multiplier = 2560u;
mbed_official 82:0b31dbcd4769 79 break;
mbed_official 82:0b31dbcd4769 80 case 0x80u:
mbed_official 82:0b31dbcd4769 81 multiplier = 732u;
mbed_official 82:0b31dbcd4769 82 break;
mbed_official 82:0b31dbcd4769 83 case 0xA0u:
mbed_official 82:0b31dbcd4769 84 multiplier = 1464u;
mbed_official 82:0b31dbcd4769 85 break;
mbed_official 82:0b31dbcd4769 86 case 0xC0u:
mbed_official 82:0b31dbcd4769 87 multiplier = 2197u;
mbed_official 82:0b31dbcd4769 88 break;
mbed_official 82:0b31dbcd4769 89 case 0xE0u:
mbed_official 82:0b31dbcd4769 90 default:
mbed_official 82:0b31dbcd4769 91 multiplier = 2929u;
mbed_official 82:0b31dbcd4769 92 break;
mbed_official 82:0b31dbcd4769 93 }
mbed_official 82:0b31dbcd4769 94
mbed_official 82:0b31dbcd4769 95 return MCGClock * divider / multiplier;
mbed_official 82:0b31dbcd4769 96 }
mbed_official 82:0b31dbcd4769 97 #ifdef MCG_C5_PLLCLKEN0_MASK
mbed_official 82:0b31dbcd4769 98 } else { //PLL is selected
mbed_official 82:0b31dbcd4769 99 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
mbed_official 82:0b31dbcd4769 100 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
mbed_official 82:0b31dbcd4769 101 return MCGClock * divider / multiplier;
mbed_official 82:0b31dbcd4769 102 }
mbed_official 82:0b31dbcd4769 103 }
mbed_official 82:0b31dbcd4769 104 #endif
mbed_official 82:0b31dbcd4769 105
mbed_official 82:0b31dbcd4769 106 //In all other cases either there is no crystal or we cannot determine it
mbed_official 82:0b31dbcd4769 107 //For example when the FLL is running on the internal reference, and there is also an
mbed_official 82:0b31dbcd4769 108 //external crystal. However these are unlikely situations
mbed_official 82:0b31dbcd4769 109 return 0;
mbed_official 82:0b31dbcd4769 110 }
mbed_official 82:0b31dbcd4769 111
mbed_official 82:0b31dbcd4769 112 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
mbed_official 82:0b31dbcd4769 113 static uint32_t mcgpllfll_frequency(void) {
mbed_official 82:0b31dbcd4769 114 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
mbed_official 82:0b31dbcd4769 115 return 0;
mbed_official 82:0b31dbcd4769 116
mbed_official 82:0b31dbcd4769 117 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
mbed_official 82:0b31dbcd4769 118 #ifdef MCG_C5_PLLCLKEN0_MASK
mbed_official 82:0b31dbcd4769 119 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
mbed_official 82:0b31dbcd4769 120 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
mbed_official 82:0b31dbcd4769 121 #endif
mbed_official 82:0b31dbcd4769 122 return MCGClock;
mbed_official 82:0b31dbcd4769 123 #ifdef MCG_C5_PLLCLKEN0_MASK
mbed_official 82:0b31dbcd4769 124 } else { //PLL is selected
mbed_official 82:0b31dbcd4769 125 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
mbed_official 82:0b31dbcd4769 126 return (MCGClock >> 1);
mbed_official 82:0b31dbcd4769 127 }
mbed_official 82:0b31dbcd4769 128 #endif
mbed_official 82:0b31dbcd4769 129
mbed_official 82:0b31dbcd4769 130 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
mbed_official 82:0b31dbcd4769 131 //for the peripherals, this is however an unlikely setup
mbed_official 82:0b31dbcd4769 132 }
mbed_official 82:0b31dbcd4769 133
mbed_official 363:12a245e5c745 134 #endif
mbed_official 363:12a245e5c745 135
mbed_official 82:0b31dbcd4769 136 #ifdef __cplusplus
mbed_official 82:0b31dbcd4769 137 }
mbed_official 82:0b31dbcd4769 138 #endif
mbed_official 82:0b31dbcd4769 139
mbed_official 82:0b31dbcd4769 140 #endif