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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c@603:f00c7e78e8b4, 2015-08-09 (annotated)
- Committer:
- HiAlgoBoost
- Date:
- Sun Aug 09 05:18:54 2015 +0000
- Revision:
- 603:f00c7e78e8b4
- Parent:
- 573:ad23fe03a082
Evening of August 8th version
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 573:ad23fe03a082 | 1 | /** |
mbed_official | 573:ad23fe03a082 | 2 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 3 | * @file stm32f7xx_hal_dma2d.c |
mbed_official | 573:ad23fe03a082 | 4 | * @author MCD Application Team |
mbed_official | 573:ad23fe03a082 | 5 | * @version V1.0.0 |
mbed_official | 573:ad23fe03a082 | 6 | * @date 12-May-2015 |
mbed_official | 573:ad23fe03a082 | 7 | * @brief DMA2D HAL module driver. |
mbed_official | 573:ad23fe03a082 | 8 | * This file provides firmware functions to manage the following |
mbed_official | 573:ad23fe03a082 | 9 | * functionalities of the DMA2D peripheral: |
mbed_official | 573:ad23fe03a082 | 10 | * + Initialization and de-initialization functions |
mbed_official | 573:ad23fe03a082 | 11 | * + IO operation functions |
mbed_official | 573:ad23fe03a082 | 12 | * + Peripheral Control functions |
mbed_official | 573:ad23fe03a082 | 13 | * + Peripheral State and Errors functions |
mbed_official | 573:ad23fe03a082 | 14 | * |
mbed_official | 573:ad23fe03a082 | 15 | @verbatim |
mbed_official | 573:ad23fe03a082 | 16 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 17 | ##### How to use this driver ##### |
mbed_official | 573:ad23fe03a082 | 18 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 19 | [..] |
mbed_official | 573:ad23fe03a082 | 20 | (#) Program the required configuration through following parameters: |
mbed_official | 573:ad23fe03a082 | 21 | the Transfer Mode, the output color mode and the output offset using |
mbed_official | 573:ad23fe03a082 | 22 | HAL_DMA2D_Init() function. |
mbed_official | 573:ad23fe03a082 | 23 | |
mbed_official | 573:ad23fe03a082 | 24 | (#) Program the required configuration through following parameters: |
mbed_official | 573:ad23fe03a082 | 25 | the input color mode, the input color, input alpha value, alpha mode |
mbed_official | 573:ad23fe03a082 | 26 | and the input offset using HAL_DMA2D_ConfigLayer() function for foreground |
mbed_official | 573:ad23fe03a082 | 27 | or/and background layer. |
mbed_official | 573:ad23fe03a082 | 28 | |
mbed_official | 573:ad23fe03a082 | 29 | *** Polling mode IO operation *** |
mbed_official | 573:ad23fe03a082 | 30 | ================================= |
mbed_official | 573:ad23fe03a082 | 31 | [..] |
mbed_official | 573:ad23fe03a082 | 32 | (+) Configure the pdata, Destination and data length and Enable |
mbed_official | 573:ad23fe03a082 | 33 | the transfer using HAL_DMA2D_Start() |
mbed_official | 573:ad23fe03a082 | 34 | (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage |
mbed_official | 573:ad23fe03a082 | 35 | user can specify the value of timeout according to his end application. |
mbed_official | 573:ad23fe03a082 | 36 | |
mbed_official | 573:ad23fe03a082 | 37 | *** Interrupt mode IO operation *** |
mbed_official | 573:ad23fe03a082 | 38 | =================================== |
mbed_official | 573:ad23fe03a082 | 39 | [..] |
mbed_official | 573:ad23fe03a082 | 40 | (#) Configure the pdata, Destination and data length and Enable |
mbed_official | 573:ad23fe03a082 | 41 | the transfer using HAL_DMA2D_Start_IT() |
mbed_official | 573:ad23fe03a082 | 42 | (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine |
mbed_official | 573:ad23fe03a082 | 43 | (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can |
mbed_official | 573:ad23fe03a082 | 44 | add his own function by customization of function pointer XferCpltCallback and |
mbed_official | 573:ad23fe03a082 | 45 | XferErrorCallback (i.e a member of DMA2D handle structure). |
mbed_official | 573:ad23fe03a082 | 46 | |
mbed_official | 573:ad23fe03a082 | 47 | -@- In Register-to-Memory transfer mode, the pdata parameter is the register |
mbed_official | 573:ad23fe03a082 | 48 | color, in Memory-to-memory or memory-to-memory with pixel format |
mbed_official | 573:ad23fe03a082 | 49 | conversion the pdata is the source address. |
mbed_official | 573:ad23fe03a082 | 50 | |
mbed_official | 573:ad23fe03a082 | 51 | -@- Configure the foreground source address, the background source address, |
mbed_official | 573:ad23fe03a082 | 52 | the Destination and data length and Enable the transfer using |
mbed_official | 573:ad23fe03a082 | 53 | HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() |
mbed_official | 573:ad23fe03a082 | 54 | in interrupt mode. |
mbed_official | 573:ad23fe03a082 | 55 | |
mbed_official | 573:ad23fe03a082 | 56 | -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions |
mbed_official | 573:ad23fe03a082 | 57 | are used if the memory to memory with blending transfer mode is selected. |
mbed_official | 573:ad23fe03a082 | 58 | |
mbed_official | 573:ad23fe03a082 | 59 | (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT() |
mbed_official | 573:ad23fe03a082 | 60 | HAL_DMA2D_EnableCLUT() functions. |
mbed_official | 573:ad23fe03a082 | 61 | |
mbed_official | 573:ad23fe03a082 | 62 | (#) Optionally, configure and enable LineInterrupt using the following function: |
mbed_official | 573:ad23fe03a082 | 63 | HAL_DMA2D_ProgramLineEvent(). |
mbed_official | 573:ad23fe03a082 | 64 | |
mbed_official | 573:ad23fe03a082 | 65 | (#) The transfer can be suspended, continued and aborted using the following |
mbed_official | 573:ad23fe03a082 | 66 | functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). |
mbed_official | 573:ad23fe03a082 | 67 | |
mbed_official | 573:ad23fe03a082 | 68 | (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState() |
mbed_official | 573:ad23fe03a082 | 69 | |
mbed_official | 573:ad23fe03a082 | 70 | *** DMA2D HAL driver macros list *** |
mbed_official | 573:ad23fe03a082 | 71 | ============================================= |
mbed_official | 573:ad23fe03a082 | 72 | [..] |
mbed_official | 573:ad23fe03a082 | 73 | Below the list of most used macros in DMA2D HAL driver : |
mbed_official | 573:ad23fe03a082 | 74 | |
mbed_official | 573:ad23fe03a082 | 75 | (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. |
mbed_official | 573:ad23fe03a082 | 76 | (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral. |
mbed_official | 573:ad23fe03a082 | 77 | (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. |
mbed_official | 573:ad23fe03a082 | 78 | (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. |
mbed_official | 573:ad23fe03a082 | 79 | (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. |
mbed_official | 573:ad23fe03a082 | 80 | (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. |
mbed_official | 573:ad23fe03a082 | 81 | (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not. |
mbed_official | 573:ad23fe03a082 | 82 | |
mbed_official | 573:ad23fe03a082 | 83 | [..] |
mbed_official | 573:ad23fe03a082 | 84 | (@) You can refer to the DMA2D HAL driver header file for more useful macros |
mbed_official | 573:ad23fe03a082 | 85 | |
mbed_official | 573:ad23fe03a082 | 86 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 87 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 88 | * @attention |
mbed_official | 573:ad23fe03a082 | 89 | * |
mbed_official | 573:ad23fe03a082 | 90 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
mbed_official | 573:ad23fe03a082 | 91 | * |
mbed_official | 573:ad23fe03a082 | 92 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 573:ad23fe03a082 | 93 | * are permitted provided that the following conditions are met: |
mbed_official | 573:ad23fe03a082 | 94 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 573:ad23fe03a082 | 95 | * this list of conditions and the following disclaimer. |
mbed_official | 573:ad23fe03a082 | 96 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 573:ad23fe03a082 | 97 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 573:ad23fe03a082 | 98 | * and/or other materials provided with the distribution. |
mbed_official | 573:ad23fe03a082 | 99 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 573:ad23fe03a082 | 100 | * may be used to endorse or promote products derived from this software |
mbed_official | 573:ad23fe03a082 | 101 | * without specific prior written permission. |
mbed_official | 573:ad23fe03a082 | 102 | * |
mbed_official | 573:ad23fe03a082 | 103 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 573:ad23fe03a082 | 104 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 573:ad23fe03a082 | 105 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 573:ad23fe03a082 | 106 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 573:ad23fe03a082 | 107 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 573:ad23fe03a082 | 108 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 573:ad23fe03a082 | 109 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 573:ad23fe03a082 | 110 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 573:ad23fe03a082 | 111 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 573:ad23fe03a082 | 112 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 573:ad23fe03a082 | 113 | * |
mbed_official | 573:ad23fe03a082 | 114 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 115 | */ |
mbed_official | 573:ad23fe03a082 | 116 | |
mbed_official | 573:ad23fe03a082 | 117 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 118 | #include "stm32f7xx_hal.h" |
mbed_official | 573:ad23fe03a082 | 119 | |
mbed_official | 573:ad23fe03a082 | 120 | /** @addtogroup STM32F7xx_HAL_Driver |
mbed_official | 573:ad23fe03a082 | 121 | * @{ |
mbed_official | 573:ad23fe03a082 | 122 | */ |
mbed_official | 573:ad23fe03a082 | 123 | /** @addtogroup DMA2D |
mbed_official | 573:ad23fe03a082 | 124 | * @brief DMA2D HAL module driver |
mbed_official | 573:ad23fe03a082 | 125 | * @{ |
mbed_official | 573:ad23fe03a082 | 126 | */ |
mbed_official | 573:ad23fe03a082 | 127 | |
mbed_official | 573:ad23fe03a082 | 128 | #ifdef HAL_DMA2D_MODULE_ENABLED |
mbed_official | 573:ad23fe03a082 | 129 | |
mbed_official | 573:ad23fe03a082 | 130 | /* Private types -------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 131 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 132 | /** @addtogroup DMA2D_Private_Defines |
mbed_official | 573:ad23fe03a082 | 133 | * @{ |
mbed_official | 573:ad23fe03a082 | 134 | */ |
mbed_official | 573:ad23fe03a082 | 135 | #define HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */ |
mbed_official | 573:ad23fe03a082 | 136 | #define HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */ |
mbed_official | 573:ad23fe03a082 | 137 | /** |
mbed_official | 573:ad23fe03a082 | 138 | * @} |
mbed_official | 573:ad23fe03a082 | 139 | */ |
mbed_official | 573:ad23fe03a082 | 140 | |
mbed_official | 573:ad23fe03a082 | 141 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 142 | /* Private constants ---------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 143 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 144 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 145 | /** @addtogroup DMA2D_Private_Functions_Prototypes |
mbed_official | 573:ad23fe03a082 | 146 | * @{ |
mbed_official | 573:ad23fe03a082 | 147 | */ |
mbed_official | 573:ad23fe03a082 | 148 | static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); |
mbed_official | 573:ad23fe03a082 | 149 | /** |
mbed_official | 573:ad23fe03a082 | 150 | * @} |
mbed_official | 573:ad23fe03a082 | 151 | */ |
mbed_official | 573:ad23fe03a082 | 152 | |
mbed_official | 573:ad23fe03a082 | 153 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 154 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 155 | /** @addtogroup DMA2D_Exported_Functions |
mbed_official | 573:ad23fe03a082 | 156 | * @{ |
mbed_official | 573:ad23fe03a082 | 157 | */ |
mbed_official | 573:ad23fe03a082 | 158 | |
mbed_official | 573:ad23fe03a082 | 159 | /** @defgroup DMA2D_Group1 Initialization and Configuration functions |
mbed_official | 573:ad23fe03a082 | 160 | * @brief Initialization and Configuration functions |
mbed_official | 573:ad23fe03a082 | 161 | * |
mbed_official | 573:ad23fe03a082 | 162 | @verbatim |
mbed_official | 573:ad23fe03a082 | 163 | =============================================================================== |
mbed_official | 573:ad23fe03a082 | 164 | ##### Initialization and Configuration functions ##### |
mbed_official | 573:ad23fe03a082 | 165 | =============================================================================== |
mbed_official | 573:ad23fe03a082 | 166 | [..] This section provides functions allowing to: |
mbed_official | 573:ad23fe03a082 | 167 | (+) Initialize and configure the DMA2D |
mbed_official | 573:ad23fe03a082 | 168 | (+) De-initialize the DMA2D |
mbed_official | 573:ad23fe03a082 | 169 | |
mbed_official | 573:ad23fe03a082 | 170 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 171 | * @{ |
mbed_official | 573:ad23fe03a082 | 172 | */ |
mbed_official | 573:ad23fe03a082 | 173 | |
mbed_official | 573:ad23fe03a082 | 174 | /** |
mbed_official | 573:ad23fe03a082 | 175 | * @brief Initializes the DMA2D according to the specified |
mbed_official | 573:ad23fe03a082 | 176 | * parameters in the DMA2D_InitTypeDef and create the associated handle. |
mbed_official | 573:ad23fe03a082 | 177 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 178 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 179 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 180 | */ |
mbed_official | 573:ad23fe03a082 | 181 | HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 573:ad23fe03a082 | 182 | { |
mbed_official | 573:ad23fe03a082 | 183 | uint32_t tmp = 0; |
mbed_official | 573:ad23fe03a082 | 184 | |
mbed_official | 573:ad23fe03a082 | 185 | /* Check the DMA2D peripheral state */ |
mbed_official | 573:ad23fe03a082 | 186 | if(hdma2d == NULL) |
mbed_official | 573:ad23fe03a082 | 187 | { |
mbed_official | 573:ad23fe03a082 | 188 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 189 | } |
mbed_official | 573:ad23fe03a082 | 190 | |
mbed_official | 573:ad23fe03a082 | 191 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 192 | assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); |
mbed_official | 573:ad23fe03a082 | 193 | assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); |
mbed_official | 573:ad23fe03a082 | 194 | assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); |
mbed_official | 573:ad23fe03a082 | 195 | assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); |
mbed_official | 573:ad23fe03a082 | 196 | |
mbed_official | 573:ad23fe03a082 | 197 | if(hdma2d->State == HAL_DMA2D_STATE_RESET) |
mbed_official | 573:ad23fe03a082 | 198 | { |
mbed_official | 573:ad23fe03a082 | 199 | /* Allocate lock resource and initialize it */ |
mbed_official | 573:ad23fe03a082 | 200 | hdma2d->Lock = HAL_UNLOCKED; |
mbed_official | 573:ad23fe03a082 | 201 | /* Init the low level hardware */ |
mbed_official | 573:ad23fe03a082 | 202 | HAL_DMA2D_MspInit(hdma2d); |
mbed_official | 573:ad23fe03a082 | 203 | } |
mbed_official | 573:ad23fe03a082 | 204 | |
mbed_official | 573:ad23fe03a082 | 205 | /* Change DMA2D peripheral state */ |
mbed_official | 573:ad23fe03a082 | 206 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 207 | |
mbed_official | 573:ad23fe03a082 | 208 | /* DMA2D CR register configuration -------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 209 | /* Get the CR register value */ |
mbed_official | 573:ad23fe03a082 | 210 | tmp = hdma2d->Instance->CR; |
mbed_official | 573:ad23fe03a082 | 211 | |
mbed_official | 573:ad23fe03a082 | 212 | /* Clear Mode bits */ |
mbed_official | 573:ad23fe03a082 | 213 | tmp &= (uint32_t)~DMA2D_CR_MODE; |
mbed_official | 573:ad23fe03a082 | 214 | |
mbed_official | 573:ad23fe03a082 | 215 | /* Prepare the value to be wrote to the CR register */ |
mbed_official | 573:ad23fe03a082 | 216 | tmp |= hdma2d->Init.Mode; |
mbed_official | 573:ad23fe03a082 | 217 | |
mbed_official | 573:ad23fe03a082 | 218 | /* Write to DMA2D CR register */ |
mbed_official | 573:ad23fe03a082 | 219 | hdma2d->Instance->CR = tmp; |
mbed_official | 573:ad23fe03a082 | 220 | |
mbed_official | 573:ad23fe03a082 | 221 | /* DMA2D OPFCCR register configuration ---------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 222 | /* Get the OPFCCR register value */ |
mbed_official | 573:ad23fe03a082 | 223 | tmp = hdma2d->Instance->OPFCCR; |
mbed_official | 573:ad23fe03a082 | 224 | |
mbed_official | 573:ad23fe03a082 | 225 | /* Clear Color Mode bits */ |
mbed_official | 573:ad23fe03a082 | 226 | tmp &= (uint32_t)~DMA2D_OPFCCR_CM; |
mbed_official | 573:ad23fe03a082 | 227 | |
mbed_official | 573:ad23fe03a082 | 228 | /* Prepare the value to be wrote to the OPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 229 | tmp |= hdma2d->Init.ColorMode; |
mbed_official | 573:ad23fe03a082 | 230 | |
mbed_official | 573:ad23fe03a082 | 231 | /* Write to DMA2D OPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 232 | hdma2d->Instance->OPFCCR = tmp; |
mbed_official | 573:ad23fe03a082 | 233 | |
mbed_official | 573:ad23fe03a082 | 234 | /* DMA2D OOR register configuration ------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 235 | /* Get the OOR register value */ |
mbed_official | 573:ad23fe03a082 | 236 | tmp = hdma2d->Instance->OOR; |
mbed_official | 573:ad23fe03a082 | 237 | |
mbed_official | 573:ad23fe03a082 | 238 | /* Clear Offset bits */ |
mbed_official | 573:ad23fe03a082 | 239 | tmp &= (uint32_t)~DMA2D_OOR_LO; |
mbed_official | 573:ad23fe03a082 | 240 | |
mbed_official | 573:ad23fe03a082 | 241 | /* Prepare the value to be wrote to the OOR register */ |
mbed_official | 573:ad23fe03a082 | 242 | tmp |= hdma2d->Init.OutputOffset; |
mbed_official | 573:ad23fe03a082 | 243 | |
mbed_official | 573:ad23fe03a082 | 244 | /* Write to DMA2D OOR register */ |
mbed_official | 573:ad23fe03a082 | 245 | hdma2d->Instance->OOR = tmp; |
mbed_official | 573:ad23fe03a082 | 246 | |
mbed_official | 573:ad23fe03a082 | 247 | /* Update error code */ |
mbed_official | 573:ad23fe03a082 | 248 | hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; |
mbed_official | 573:ad23fe03a082 | 249 | |
mbed_official | 573:ad23fe03a082 | 250 | /* Initialize the DMA2D state*/ |
mbed_official | 573:ad23fe03a082 | 251 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 252 | |
mbed_official | 573:ad23fe03a082 | 253 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 254 | } |
mbed_official | 573:ad23fe03a082 | 255 | |
mbed_official | 573:ad23fe03a082 | 256 | /** |
mbed_official | 573:ad23fe03a082 | 257 | * @brief Deinitializes the DMA2D peripheral registers to their default reset |
mbed_official | 573:ad23fe03a082 | 258 | * values. |
mbed_official | 573:ad23fe03a082 | 259 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 260 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 261 | * @retval None |
mbed_official | 573:ad23fe03a082 | 262 | */ |
mbed_official | 573:ad23fe03a082 | 263 | |
mbed_official | 573:ad23fe03a082 | 264 | HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 573:ad23fe03a082 | 265 | { |
mbed_official | 573:ad23fe03a082 | 266 | /* Check the DMA2D peripheral state */ |
mbed_official | 573:ad23fe03a082 | 267 | if(hdma2d == NULL) |
mbed_official | 573:ad23fe03a082 | 268 | { |
mbed_official | 573:ad23fe03a082 | 269 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 270 | } |
mbed_official | 573:ad23fe03a082 | 271 | |
mbed_official | 573:ad23fe03a082 | 272 | /* DeInit the low level hardware */ |
mbed_official | 573:ad23fe03a082 | 273 | HAL_DMA2D_MspDeInit(hdma2d); |
mbed_official | 573:ad23fe03a082 | 274 | |
mbed_official | 573:ad23fe03a082 | 275 | /* Update error code */ |
mbed_official | 573:ad23fe03a082 | 276 | hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; |
mbed_official | 573:ad23fe03a082 | 277 | |
mbed_official | 573:ad23fe03a082 | 278 | /* Initialize the DMA2D state*/ |
mbed_official | 573:ad23fe03a082 | 279 | hdma2d->State = HAL_DMA2D_STATE_RESET; |
mbed_official | 573:ad23fe03a082 | 280 | |
mbed_official | 573:ad23fe03a082 | 281 | /* Release Lock */ |
mbed_official | 573:ad23fe03a082 | 282 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 283 | |
mbed_official | 573:ad23fe03a082 | 284 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 285 | } |
mbed_official | 573:ad23fe03a082 | 286 | |
mbed_official | 573:ad23fe03a082 | 287 | /** |
mbed_official | 573:ad23fe03a082 | 288 | * @brief Initializes the DMA2D MSP. |
mbed_official | 573:ad23fe03a082 | 289 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 290 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 291 | * @retval None |
mbed_official | 573:ad23fe03a082 | 292 | */ |
mbed_official | 573:ad23fe03a082 | 293 | __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) |
mbed_official | 573:ad23fe03a082 | 294 | { |
mbed_official | 573:ad23fe03a082 | 295 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 573:ad23fe03a082 | 296 | the HAL_DMA2D_MspInit could be implemented in the user file |
mbed_official | 573:ad23fe03a082 | 297 | */ |
mbed_official | 573:ad23fe03a082 | 298 | } |
mbed_official | 573:ad23fe03a082 | 299 | |
mbed_official | 573:ad23fe03a082 | 300 | /** |
mbed_official | 573:ad23fe03a082 | 301 | * @brief DeInitializes the DMA2D MSP. |
mbed_official | 573:ad23fe03a082 | 302 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 303 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 304 | * @retval None |
mbed_official | 573:ad23fe03a082 | 305 | */ |
mbed_official | 573:ad23fe03a082 | 306 | __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) |
mbed_official | 573:ad23fe03a082 | 307 | { |
mbed_official | 573:ad23fe03a082 | 308 | /* NOTE : This function Should not be modified, when the callback is needed, |
mbed_official | 573:ad23fe03a082 | 309 | the HAL_DMA2D_MspDeInit could be implemented in the user file |
mbed_official | 573:ad23fe03a082 | 310 | */ |
mbed_official | 573:ad23fe03a082 | 311 | } |
mbed_official | 573:ad23fe03a082 | 312 | |
mbed_official | 573:ad23fe03a082 | 313 | /** |
mbed_official | 573:ad23fe03a082 | 314 | * @} |
mbed_official | 573:ad23fe03a082 | 315 | */ |
mbed_official | 573:ad23fe03a082 | 316 | |
mbed_official | 573:ad23fe03a082 | 317 | /** @defgroup DMA2D_Group2 IO operation functions |
mbed_official | 573:ad23fe03a082 | 318 | * @brief IO operation functions |
mbed_official | 573:ad23fe03a082 | 319 | * |
mbed_official | 573:ad23fe03a082 | 320 | @verbatim |
mbed_official | 573:ad23fe03a082 | 321 | =============================================================================== |
mbed_official | 573:ad23fe03a082 | 322 | ##### IO operation functions ##### |
mbed_official | 573:ad23fe03a082 | 323 | =============================================================================== |
mbed_official | 573:ad23fe03a082 | 324 | [..] This section provides functions allowing to: |
mbed_official | 573:ad23fe03a082 | 325 | (+) Configure the pdata, destination address and data size and |
mbed_official | 573:ad23fe03a082 | 326 | Start DMA2D transfer. |
mbed_official | 573:ad23fe03a082 | 327 | (+) Configure the source for foreground and background, destination address |
mbed_official | 573:ad23fe03a082 | 328 | and data size and Start MultiBuffer DMA2D transfer. |
mbed_official | 573:ad23fe03a082 | 329 | (+) Configure the pdata, destination address and data size and |
mbed_official | 573:ad23fe03a082 | 330 | Start DMA2D transfer with interrupt. |
mbed_official | 573:ad23fe03a082 | 331 | (+) Configure the source for foreground and background, destination address |
mbed_official | 573:ad23fe03a082 | 332 | and data size and Start MultiBuffer DMA2D transfer with interrupt. |
mbed_official | 573:ad23fe03a082 | 333 | (+) Abort DMA2D transfer. |
mbed_official | 573:ad23fe03a082 | 334 | (+) Suspend DMA2D transfer. |
mbed_official | 573:ad23fe03a082 | 335 | (+) Continue DMA2D transfer. |
mbed_official | 573:ad23fe03a082 | 336 | (+) Poll for transfer complete. |
mbed_official | 573:ad23fe03a082 | 337 | (+) handle DMA2D interrupt request. |
mbed_official | 573:ad23fe03a082 | 338 | |
mbed_official | 573:ad23fe03a082 | 339 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 340 | * @{ |
mbed_official | 573:ad23fe03a082 | 341 | */ |
mbed_official | 573:ad23fe03a082 | 342 | |
mbed_official | 573:ad23fe03a082 | 343 | /** |
mbed_official | 573:ad23fe03a082 | 344 | * @brief Start the DMA2D Transfer. |
mbed_official | 573:ad23fe03a082 | 345 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 346 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 347 | * @param pdata: Configure the source memory Buffer address if |
mbed_official | 573:ad23fe03a082 | 348 | * the memory to memory or memory to memory with pixel format |
mbed_official | 573:ad23fe03a082 | 349 | * conversion DMA2D mode is selected, and configure |
mbed_official | 573:ad23fe03a082 | 350 | * the color value if register to memory DMA2D mode is selected. |
mbed_official | 573:ad23fe03a082 | 351 | * @param DstAddress: The destination memory Buffer address. |
mbed_official | 573:ad23fe03a082 | 352 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 353 | * @param Height: The height of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 354 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 355 | */ |
mbed_official | 573:ad23fe03a082 | 356 | HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) |
mbed_official | 573:ad23fe03a082 | 357 | { |
mbed_official | 573:ad23fe03a082 | 358 | /* Process locked */ |
mbed_official | 573:ad23fe03a082 | 359 | __HAL_LOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 360 | |
mbed_official | 573:ad23fe03a082 | 361 | /* Change DMA2D peripheral state */ |
mbed_official | 573:ad23fe03a082 | 362 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 363 | |
mbed_official | 573:ad23fe03a082 | 364 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 365 | assert_param(IS_DMA2D_LINE(Height)); |
mbed_official | 573:ad23fe03a082 | 366 | assert_param(IS_DMA2D_PIXEL(Width)); |
mbed_official | 573:ad23fe03a082 | 367 | |
mbed_official | 573:ad23fe03a082 | 368 | /* Disable the Peripheral */ |
mbed_official | 573:ad23fe03a082 | 369 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 573:ad23fe03a082 | 370 | |
mbed_official | 573:ad23fe03a082 | 371 | /* Configure the source, destination address and the data size */ |
mbed_official | 573:ad23fe03a082 | 372 | DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); |
mbed_official | 573:ad23fe03a082 | 373 | |
mbed_official | 573:ad23fe03a082 | 374 | /* Enable the Peripheral */ |
mbed_official | 573:ad23fe03a082 | 375 | __HAL_DMA2D_ENABLE(hdma2d); |
mbed_official | 573:ad23fe03a082 | 376 | |
mbed_official | 573:ad23fe03a082 | 377 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 378 | } |
mbed_official | 573:ad23fe03a082 | 379 | |
mbed_official | 573:ad23fe03a082 | 380 | /** |
mbed_official | 573:ad23fe03a082 | 381 | * @brief Start the DMA2D Transfer with interrupt enabled. |
mbed_official | 573:ad23fe03a082 | 382 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 383 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 384 | * @param pdata: Configure the source memory Buffer address if |
mbed_official | 573:ad23fe03a082 | 385 | * the memory to memory or memory to memory with pixel format |
mbed_official | 573:ad23fe03a082 | 386 | * conversion DMA2D mode is selected, and configure |
mbed_official | 573:ad23fe03a082 | 387 | * the color value if register to memory DMA2D mode is selected. |
mbed_official | 573:ad23fe03a082 | 388 | * @param DstAddress: The destination memory Buffer address. |
mbed_official | 573:ad23fe03a082 | 389 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 390 | * @param Height: The height of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 391 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 392 | */ |
mbed_official | 573:ad23fe03a082 | 393 | HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) |
mbed_official | 573:ad23fe03a082 | 394 | { |
mbed_official | 573:ad23fe03a082 | 395 | /* Process locked */ |
mbed_official | 573:ad23fe03a082 | 396 | __HAL_LOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 397 | |
mbed_official | 573:ad23fe03a082 | 398 | /* Change DMA2D peripheral state */ |
mbed_official | 573:ad23fe03a082 | 399 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 400 | |
mbed_official | 573:ad23fe03a082 | 401 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 402 | assert_param(IS_DMA2D_LINE(Height)); |
mbed_official | 573:ad23fe03a082 | 403 | assert_param(IS_DMA2D_PIXEL(Width)); |
mbed_official | 573:ad23fe03a082 | 404 | |
mbed_official | 573:ad23fe03a082 | 405 | /* Disable the Peripheral */ |
mbed_official | 573:ad23fe03a082 | 406 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 573:ad23fe03a082 | 407 | |
mbed_official | 573:ad23fe03a082 | 408 | /* Configure the source, destination address and the data size */ |
mbed_official | 573:ad23fe03a082 | 409 | DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); |
mbed_official | 573:ad23fe03a082 | 410 | |
mbed_official | 573:ad23fe03a082 | 411 | /* Enable the transfer complete interrupt */ |
mbed_official | 573:ad23fe03a082 | 412 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC); |
mbed_official | 573:ad23fe03a082 | 413 | |
mbed_official | 573:ad23fe03a082 | 414 | /* Enable the transfer Error interrupt */ |
mbed_official | 573:ad23fe03a082 | 415 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE); |
mbed_official | 573:ad23fe03a082 | 416 | |
mbed_official | 573:ad23fe03a082 | 417 | /* Enable the Peripheral */ |
mbed_official | 573:ad23fe03a082 | 418 | __HAL_DMA2D_ENABLE(hdma2d); |
mbed_official | 573:ad23fe03a082 | 419 | |
mbed_official | 573:ad23fe03a082 | 420 | /* Enable the configuration error interrupt */ |
mbed_official | 573:ad23fe03a082 | 421 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE); |
mbed_official | 573:ad23fe03a082 | 422 | |
mbed_official | 573:ad23fe03a082 | 423 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 424 | } |
mbed_official | 573:ad23fe03a082 | 425 | |
mbed_official | 573:ad23fe03a082 | 426 | /** |
mbed_official | 573:ad23fe03a082 | 427 | * @brief Start the multi-source DMA2D Transfer. |
mbed_official | 573:ad23fe03a082 | 428 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 429 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 430 | * @param SrcAddress1: The source memory Buffer address of the foreground layer. |
mbed_official | 573:ad23fe03a082 | 431 | * @param SrcAddress2: The source memory Buffer address of the background layer. |
mbed_official | 573:ad23fe03a082 | 432 | * @param DstAddress: The destination memory Buffer address |
mbed_official | 573:ad23fe03a082 | 433 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 434 | * @param Height: The height of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 435 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 436 | */ |
mbed_official | 573:ad23fe03a082 | 437 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) |
mbed_official | 573:ad23fe03a082 | 438 | { |
mbed_official | 573:ad23fe03a082 | 439 | /* Process locked */ |
mbed_official | 573:ad23fe03a082 | 440 | __HAL_LOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 441 | |
mbed_official | 573:ad23fe03a082 | 442 | /* Change DMA2D peripheral state */ |
mbed_official | 573:ad23fe03a082 | 443 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 444 | |
mbed_official | 573:ad23fe03a082 | 445 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 446 | assert_param(IS_DMA2D_LINE(Height)); |
mbed_official | 573:ad23fe03a082 | 447 | assert_param(IS_DMA2D_PIXEL(Width)); |
mbed_official | 573:ad23fe03a082 | 448 | |
mbed_official | 573:ad23fe03a082 | 449 | /* Disable the Peripheral */ |
mbed_official | 573:ad23fe03a082 | 450 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 573:ad23fe03a082 | 451 | |
mbed_official | 573:ad23fe03a082 | 452 | /* Configure DMA2D Stream source2 address */ |
mbed_official | 573:ad23fe03a082 | 453 | hdma2d->Instance->BGMAR = SrcAddress2; |
mbed_official | 573:ad23fe03a082 | 454 | |
mbed_official | 573:ad23fe03a082 | 455 | /* Configure the source, destination address and the data size */ |
mbed_official | 573:ad23fe03a082 | 456 | DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); |
mbed_official | 573:ad23fe03a082 | 457 | |
mbed_official | 573:ad23fe03a082 | 458 | /* Enable the Peripheral */ |
mbed_official | 573:ad23fe03a082 | 459 | __HAL_DMA2D_ENABLE(hdma2d); |
mbed_official | 573:ad23fe03a082 | 460 | |
mbed_official | 573:ad23fe03a082 | 461 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 462 | } |
mbed_official | 573:ad23fe03a082 | 463 | |
mbed_official | 573:ad23fe03a082 | 464 | /** |
mbed_official | 573:ad23fe03a082 | 465 | * @brief Start the multi-source DMA2D Transfer with interrupt enabled. |
mbed_official | 573:ad23fe03a082 | 466 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 467 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 468 | * @param SrcAddress1: The source memory Buffer address of the foreground layer. |
mbed_official | 573:ad23fe03a082 | 469 | * @param SrcAddress2: The source memory Buffer address of the background layer. |
mbed_official | 573:ad23fe03a082 | 470 | * @param DstAddress: The destination memory Buffer address. |
mbed_official | 573:ad23fe03a082 | 471 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 472 | * @param Height: The height of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 473 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 474 | */ |
mbed_official | 573:ad23fe03a082 | 475 | HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) |
mbed_official | 573:ad23fe03a082 | 476 | { |
mbed_official | 573:ad23fe03a082 | 477 | /* Process locked */ |
mbed_official | 573:ad23fe03a082 | 478 | __HAL_LOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 479 | |
mbed_official | 573:ad23fe03a082 | 480 | /* Change DMA2D peripheral state */ |
mbed_official | 573:ad23fe03a082 | 481 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 482 | |
mbed_official | 573:ad23fe03a082 | 483 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 484 | assert_param(IS_DMA2D_LINE(Height)); |
mbed_official | 573:ad23fe03a082 | 485 | assert_param(IS_DMA2D_PIXEL(Width)); |
mbed_official | 573:ad23fe03a082 | 486 | |
mbed_official | 573:ad23fe03a082 | 487 | /* Disable the Peripheral */ |
mbed_official | 573:ad23fe03a082 | 488 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 573:ad23fe03a082 | 489 | |
mbed_official | 573:ad23fe03a082 | 490 | /* Configure DMA2D Stream source2 address */ |
mbed_official | 573:ad23fe03a082 | 491 | hdma2d->Instance->BGMAR = SrcAddress2; |
mbed_official | 573:ad23fe03a082 | 492 | |
mbed_official | 573:ad23fe03a082 | 493 | /* Configure the source, destination address and the data size */ |
mbed_official | 573:ad23fe03a082 | 494 | DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); |
mbed_official | 573:ad23fe03a082 | 495 | |
mbed_official | 573:ad23fe03a082 | 496 | /* Enable the configuration error interrupt */ |
mbed_official | 573:ad23fe03a082 | 497 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE); |
mbed_official | 573:ad23fe03a082 | 498 | |
mbed_official | 573:ad23fe03a082 | 499 | /* Enable the transfer complete interrupt */ |
mbed_official | 573:ad23fe03a082 | 500 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC); |
mbed_official | 573:ad23fe03a082 | 501 | |
mbed_official | 573:ad23fe03a082 | 502 | /* Enable the transfer Error interrupt */ |
mbed_official | 573:ad23fe03a082 | 503 | __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE); |
mbed_official | 573:ad23fe03a082 | 504 | |
mbed_official | 573:ad23fe03a082 | 505 | /* Enable the Peripheral */ |
mbed_official | 573:ad23fe03a082 | 506 | __HAL_DMA2D_ENABLE(hdma2d); |
mbed_official | 573:ad23fe03a082 | 507 | |
mbed_official | 573:ad23fe03a082 | 508 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 509 | } |
mbed_official | 573:ad23fe03a082 | 510 | |
mbed_official | 573:ad23fe03a082 | 511 | /** |
mbed_official | 573:ad23fe03a082 | 512 | * @brief Abort the DMA2D Transfer. |
mbed_official | 573:ad23fe03a082 | 513 | * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 514 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 515 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 516 | */ |
mbed_official | 573:ad23fe03a082 | 517 | HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 573:ad23fe03a082 | 518 | { |
mbed_official | 573:ad23fe03a082 | 519 | uint32_t tickstart = 0; |
mbed_official | 573:ad23fe03a082 | 520 | |
mbed_official | 573:ad23fe03a082 | 521 | /* Disable the DMA2D */ |
mbed_official | 573:ad23fe03a082 | 522 | __HAL_DMA2D_DISABLE(hdma2d); |
mbed_official | 573:ad23fe03a082 | 523 | |
mbed_official | 573:ad23fe03a082 | 524 | /* Get tick */ |
mbed_official | 573:ad23fe03a082 | 525 | tickstart = HAL_GetTick(); |
mbed_official | 573:ad23fe03a082 | 526 | |
mbed_official | 573:ad23fe03a082 | 527 | /* Check if the DMA2D is effectively disabled */ |
mbed_official | 573:ad23fe03a082 | 528 | while((hdma2d->Instance->CR & DMA2D_CR_START) != 0) |
mbed_official | 573:ad23fe03a082 | 529 | { |
mbed_official | 573:ad23fe03a082 | 530 | if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_ABORT) |
mbed_official | 573:ad23fe03a082 | 531 | { |
mbed_official | 573:ad23fe03a082 | 532 | /* Update error code */ |
mbed_official | 573:ad23fe03a082 | 533 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 534 | |
mbed_official | 573:ad23fe03a082 | 535 | /* Change the DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 536 | hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 537 | |
mbed_official | 573:ad23fe03a082 | 538 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 539 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 540 | |
mbed_official | 573:ad23fe03a082 | 541 | return HAL_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 542 | } |
mbed_official | 573:ad23fe03a082 | 543 | } |
mbed_official | 573:ad23fe03a082 | 544 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 545 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 546 | |
mbed_official | 573:ad23fe03a082 | 547 | /* Change the DMA2D state*/ |
mbed_official | 573:ad23fe03a082 | 548 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 549 | |
mbed_official | 573:ad23fe03a082 | 550 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 551 | } |
mbed_official | 573:ad23fe03a082 | 552 | |
mbed_official | 573:ad23fe03a082 | 553 | /** |
mbed_official | 573:ad23fe03a082 | 554 | * @brief Suspend the DMA2D Transfer. |
mbed_official | 573:ad23fe03a082 | 555 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 556 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 557 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 558 | */ |
mbed_official | 573:ad23fe03a082 | 559 | HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 573:ad23fe03a082 | 560 | { |
mbed_official | 573:ad23fe03a082 | 561 | uint32_t tickstart = 0; |
mbed_official | 573:ad23fe03a082 | 562 | |
mbed_official | 573:ad23fe03a082 | 563 | /* Suspend the DMA2D transfer */ |
mbed_official | 573:ad23fe03a082 | 564 | hdma2d->Instance->CR |= DMA2D_CR_SUSP; |
mbed_official | 573:ad23fe03a082 | 565 | |
mbed_official | 573:ad23fe03a082 | 566 | /* Get tick */ |
mbed_official | 573:ad23fe03a082 | 567 | tickstart = HAL_GetTick(); |
mbed_official | 573:ad23fe03a082 | 568 | |
mbed_official | 573:ad23fe03a082 | 569 | /* Check if the DMA2D is effectively suspended */ |
mbed_official | 573:ad23fe03a082 | 570 | while((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) |
mbed_official | 573:ad23fe03a082 | 571 | { |
mbed_official | 573:ad23fe03a082 | 572 | if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_SUSPEND) |
mbed_official | 573:ad23fe03a082 | 573 | { |
mbed_official | 573:ad23fe03a082 | 574 | /* Update error code */ |
mbed_official | 573:ad23fe03a082 | 575 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 576 | |
mbed_official | 573:ad23fe03a082 | 577 | /* Change the DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 578 | hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 579 | |
mbed_official | 573:ad23fe03a082 | 580 | return HAL_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 581 | } |
mbed_official | 573:ad23fe03a082 | 582 | } |
mbed_official | 573:ad23fe03a082 | 583 | /* Change the DMA2D state*/ |
mbed_official | 573:ad23fe03a082 | 584 | hdma2d->State = HAL_DMA2D_STATE_SUSPEND; |
mbed_official | 573:ad23fe03a082 | 585 | |
mbed_official | 573:ad23fe03a082 | 586 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 587 | } |
mbed_official | 573:ad23fe03a082 | 588 | |
mbed_official | 573:ad23fe03a082 | 589 | /** |
mbed_official | 573:ad23fe03a082 | 590 | * @brief Resume the DMA2D Transfer. |
mbed_official | 573:ad23fe03a082 | 591 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 592 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 593 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 594 | */ |
mbed_official | 573:ad23fe03a082 | 595 | HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 573:ad23fe03a082 | 596 | { |
mbed_official | 573:ad23fe03a082 | 597 | /* Resume the DMA2D transfer */ |
mbed_official | 573:ad23fe03a082 | 598 | hdma2d->Instance->CR &= ~DMA2D_CR_SUSP; |
mbed_official | 573:ad23fe03a082 | 599 | |
mbed_official | 573:ad23fe03a082 | 600 | /* Change the DMA2D state*/ |
mbed_official | 573:ad23fe03a082 | 601 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 602 | |
mbed_official | 573:ad23fe03a082 | 603 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 604 | } |
mbed_official | 573:ad23fe03a082 | 605 | |
mbed_official | 573:ad23fe03a082 | 606 | /** |
mbed_official | 573:ad23fe03a082 | 607 | * @brief Polling for transfer complete or CLUT loading. |
mbed_official | 573:ad23fe03a082 | 608 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 609 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 610 | * @param Timeout: Timeout duration |
mbed_official | 573:ad23fe03a082 | 611 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 612 | */ |
mbed_official | 573:ad23fe03a082 | 613 | HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) |
mbed_official | 573:ad23fe03a082 | 614 | { |
mbed_official | 573:ad23fe03a082 | 615 | uint32_t tmp, tmp1; |
mbed_official | 573:ad23fe03a082 | 616 | uint32_t tickstart = 0; |
mbed_official | 573:ad23fe03a082 | 617 | |
mbed_official | 573:ad23fe03a082 | 618 | /* Polling for DMA2D transfer */ |
mbed_official | 573:ad23fe03a082 | 619 | if((hdma2d->Instance->CR & DMA2D_CR_START) != 0) |
mbed_official | 573:ad23fe03a082 | 620 | { |
mbed_official | 573:ad23fe03a082 | 621 | /* Get tick */ |
mbed_official | 573:ad23fe03a082 | 622 | tickstart = HAL_GetTick(); |
mbed_official | 573:ad23fe03a082 | 623 | |
mbed_official | 573:ad23fe03a082 | 624 | while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) |
mbed_official | 573:ad23fe03a082 | 625 | { |
mbed_official | 573:ad23fe03a082 | 626 | tmp = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE); |
mbed_official | 573:ad23fe03a082 | 627 | tmp1 = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE); |
mbed_official | 573:ad23fe03a082 | 628 | |
mbed_official | 573:ad23fe03a082 | 629 | if((tmp != RESET) || (tmp1 != RESET)) |
mbed_official | 573:ad23fe03a082 | 630 | { |
mbed_official | 573:ad23fe03a082 | 631 | /* Clear the transfer and configuration error flags */ |
mbed_official | 573:ad23fe03a082 | 632 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); |
mbed_official | 573:ad23fe03a082 | 633 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); |
mbed_official | 573:ad23fe03a082 | 634 | |
mbed_official | 573:ad23fe03a082 | 635 | /* Change DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 636 | hdma2d->State= HAL_DMA2D_STATE_ERROR; |
mbed_official | 573:ad23fe03a082 | 637 | |
mbed_official | 573:ad23fe03a082 | 638 | /* Process unlocked */ |
mbed_official | 573:ad23fe03a082 | 639 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 640 | |
mbed_official | 573:ad23fe03a082 | 641 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 642 | } |
mbed_official | 573:ad23fe03a082 | 643 | /* Check for the Timeout */ |
mbed_official | 573:ad23fe03a082 | 644 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 573:ad23fe03a082 | 645 | { |
mbed_official | 573:ad23fe03a082 | 646 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
mbed_official | 573:ad23fe03a082 | 647 | { |
mbed_official | 573:ad23fe03a082 | 648 | /* Process unlocked */ |
mbed_official | 573:ad23fe03a082 | 649 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 650 | |
mbed_official | 573:ad23fe03a082 | 651 | /* Update error code */ |
mbed_official | 573:ad23fe03a082 | 652 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 653 | |
mbed_official | 573:ad23fe03a082 | 654 | /* Change the DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 655 | hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 656 | |
mbed_official | 573:ad23fe03a082 | 657 | return HAL_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 658 | } |
mbed_official | 573:ad23fe03a082 | 659 | } |
mbed_official | 573:ad23fe03a082 | 660 | } |
mbed_official | 573:ad23fe03a082 | 661 | } |
mbed_official | 573:ad23fe03a082 | 662 | /* Polling for CLUT loading */ |
mbed_official | 573:ad23fe03a082 | 663 | if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0) |
mbed_official | 573:ad23fe03a082 | 664 | { |
mbed_official | 573:ad23fe03a082 | 665 | /* Get tick */ |
mbed_official | 573:ad23fe03a082 | 666 | tickstart = HAL_GetTick(); |
mbed_official | 573:ad23fe03a082 | 667 | |
mbed_official | 573:ad23fe03a082 | 668 | while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) |
mbed_official | 573:ad23fe03a082 | 669 | { |
mbed_official | 573:ad23fe03a082 | 670 | if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET)) |
mbed_official | 573:ad23fe03a082 | 671 | { |
mbed_official | 573:ad23fe03a082 | 672 | /* Clear the transfer and configuration error flags */ |
mbed_official | 573:ad23fe03a082 | 673 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); |
mbed_official | 573:ad23fe03a082 | 674 | |
mbed_official | 573:ad23fe03a082 | 675 | /* Change DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 676 | hdma2d->State= HAL_DMA2D_STATE_ERROR; |
mbed_official | 573:ad23fe03a082 | 677 | |
mbed_official | 573:ad23fe03a082 | 678 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 679 | } |
mbed_official | 573:ad23fe03a082 | 680 | /* Check for the Timeout */ |
mbed_official | 573:ad23fe03a082 | 681 | if(Timeout != HAL_MAX_DELAY) |
mbed_official | 573:ad23fe03a082 | 682 | { |
mbed_official | 573:ad23fe03a082 | 683 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
mbed_official | 573:ad23fe03a082 | 684 | { |
mbed_official | 573:ad23fe03a082 | 685 | /* Update error code */ |
mbed_official | 573:ad23fe03a082 | 686 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 687 | |
mbed_official | 573:ad23fe03a082 | 688 | /* Change the DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 689 | hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 690 | |
mbed_official | 573:ad23fe03a082 | 691 | return HAL_TIMEOUT; |
mbed_official | 573:ad23fe03a082 | 692 | } |
mbed_official | 573:ad23fe03a082 | 693 | } |
mbed_official | 573:ad23fe03a082 | 694 | } |
mbed_official | 573:ad23fe03a082 | 695 | } |
mbed_official | 573:ad23fe03a082 | 696 | /* Clear the transfer complete flag */ |
mbed_official | 573:ad23fe03a082 | 697 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); |
mbed_official | 573:ad23fe03a082 | 698 | |
mbed_official | 573:ad23fe03a082 | 699 | /* Clear the CLUT loading flag */ |
mbed_official | 573:ad23fe03a082 | 700 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); |
mbed_official | 573:ad23fe03a082 | 701 | |
mbed_official | 573:ad23fe03a082 | 702 | /* Change DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 703 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 704 | |
mbed_official | 573:ad23fe03a082 | 705 | /* Process unlocked */ |
mbed_official | 573:ad23fe03a082 | 706 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 707 | |
mbed_official | 573:ad23fe03a082 | 708 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 709 | } |
mbed_official | 573:ad23fe03a082 | 710 | /** |
mbed_official | 573:ad23fe03a082 | 711 | * @brief Handles DMA2D interrupt request. |
mbed_official | 573:ad23fe03a082 | 712 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 713 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 714 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 715 | */ |
mbed_official | 573:ad23fe03a082 | 716 | void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 573:ad23fe03a082 | 717 | { |
mbed_official | 573:ad23fe03a082 | 718 | /* Transfer Error Interrupt management ***************************************/ |
mbed_official | 573:ad23fe03a082 | 719 | if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET) |
mbed_official | 573:ad23fe03a082 | 720 | { |
mbed_official | 573:ad23fe03a082 | 721 | if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET) |
mbed_official | 573:ad23fe03a082 | 722 | { |
mbed_official | 573:ad23fe03a082 | 723 | /* Disable the transfer Error interrupt */ |
mbed_official | 573:ad23fe03a082 | 724 | __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); |
mbed_official | 573:ad23fe03a082 | 725 | |
mbed_official | 573:ad23fe03a082 | 726 | /* Update error code */ |
mbed_official | 573:ad23fe03a082 | 727 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; |
mbed_official | 573:ad23fe03a082 | 728 | |
mbed_official | 573:ad23fe03a082 | 729 | /* Clear the transfer error flag */ |
mbed_official | 573:ad23fe03a082 | 730 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); |
mbed_official | 573:ad23fe03a082 | 731 | |
mbed_official | 573:ad23fe03a082 | 732 | /* Change DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 733 | hdma2d->State = HAL_DMA2D_STATE_ERROR; |
mbed_official | 573:ad23fe03a082 | 734 | |
mbed_official | 573:ad23fe03a082 | 735 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 736 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 737 | |
mbed_official | 573:ad23fe03a082 | 738 | if(hdma2d->XferErrorCallback != NULL) |
mbed_official | 573:ad23fe03a082 | 739 | { |
mbed_official | 573:ad23fe03a082 | 740 | /* Transfer error Callback */ |
mbed_official | 573:ad23fe03a082 | 741 | hdma2d->XferErrorCallback(hdma2d); |
mbed_official | 573:ad23fe03a082 | 742 | } |
mbed_official | 573:ad23fe03a082 | 743 | } |
mbed_official | 573:ad23fe03a082 | 744 | } |
mbed_official | 573:ad23fe03a082 | 745 | /* Configuration Error Interrupt management **********************************/ |
mbed_official | 573:ad23fe03a082 | 746 | if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET) |
mbed_official | 573:ad23fe03a082 | 747 | { |
mbed_official | 573:ad23fe03a082 | 748 | if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET) |
mbed_official | 573:ad23fe03a082 | 749 | { |
mbed_official | 573:ad23fe03a082 | 750 | /* Disable the Configuration Error interrupt */ |
mbed_official | 573:ad23fe03a082 | 751 | __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); |
mbed_official | 573:ad23fe03a082 | 752 | |
mbed_official | 573:ad23fe03a082 | 753 | /* Clear the Configuration error flag */ |
mbed_official | 573:ad23fe03a082 | 754 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); |
mbed_official | 573:ad23fe03a082 | 755 | |
mbed_official | 573:ad23fe03a082 | 756 | /* Update error code */ |
mbed_official | 573:ad23fe03a082 | 757 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; |
mbed_official | 573:ad23fe03a082 | 758 | |
mbed_official | 573:ad23fe03a082 | 759 | /* Change DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 760 | hdma2d->State = HAL_DMA2D_STATE_ERROR; |
mbed_official | 573:ad23fe03a082 | 761 | |
mbed_official | 573:ad23fe03a082 | 762 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 763 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 764 | |
mbed_official | 573:ad23fe03a082 | 765 | if(hdma2d->XferErrorCallback != NULL) |
mbed_official | 573:ad23fe03a082 | 766 | { |
mbed_official | 573:ad23fe03a082 | 767 | /* Transfer error Callback */ |
mbed_official | 573:ad23fe03a082 | 768 | hdma2d->XferErrorCallback(hdma2d); |
mbed_official | 573:ad23fe03a082 | 769 | } |
mbed_official | 573:ad23fe03a082 | 770 | } |
mbed_official | 573:ad23fe03a082 | 771 | } |
mbed_official | 573:ad23fe03a082 | 772 | /* Transfer Complete Interrupt management ************************************/ |
mbed_official | 573:ad23fe03a082 | 773 | if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET) |
mbed_official | 573:ad23fe03a082 | 774 | { |
mbed_official | 573:ad23fe03a082 | 775 | if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET) |
mbed_official | 573:ad23fe03a082 | 776 | { |
mbed_official | 573:ad23fe03a082 | 777 | /* Disable the transfer complete interrupt */ |
mbed_official | 573:ad23fe03a082 | 778 | __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); |
mbed_official | 573:ad23fe03a082 | 779 | |
mbed_official | 573:ad23fe03a082 | 780 | /* Clear the transfer complete flag */ |
mbed_official | 573:ad23fe03a082 | 781 | __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); |
mbed_official | 573:ad23fe03a082 | 782 | |
mbed_official | 573:ad23fe03a082 | 783 | /* Update error code */ |
mbed_official | 573:ad23fe03a082 | 784 | hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; |
mbed_official | 573:ad23fe03a082 | 785 | |
mbed_official | 573:ad23fe03a082 | 786 | /* Change DMA2D state */ |
mbed_official | 573:ad23fe03a082 | 787 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 788 | |
mbed_official | 573:ad23fe03a082 | 789 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 790 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 791 | |
mbed_official | 573:ad23fe03a082 | 792 | if(hdma2d->XferCpltCallback != NULL) |
mbed_official | 573:ad23fe03a082 | 793 | { |
mbed_official | 573:ad23fe03a082 | 794 | /* Transfer complete Callback */ |
mbed_official | 573:ad23fe03a082 | 795 | hdma2d->XferCpltCallback(hdma2d); |
mbed_official | 573:ad23fe03a082 | 796 | } |
mbed_official | 573:ad23fe03a082 | 797 | } |
mbed_official | 573:ad23fe03a082 | 798 | } |
mbed_official | 573:ad23fe03a082 | 799 | } |
mbed_official | 573:ad23fe03a082 | 800 | |
mbed_official | 573:ad23fe03a082 | 801 | /** |
mbed_official | 573:ad23fe03a082 | 802 | * @} |
mbed_official | 573:ad23fe03a082 | 803 | */ |
mbed_official | 573:ad23fe03a082 | 804 | |
mbed_official | 573:ad23fe03a082 | 805 | /** @defgroup DMA2D_Group3 Peripheral Control functions |
mbed_official | 573:ad23fe03a082 | 806 | * @brief Peripheral Control functions |
mbed_official | 573:ad23fe03a082 | 807 | * |
mbed_official | 573:ad23fe03a082 | 808 | @verbatim |
mbed_official | 573:ad23fe03a082 | 809 | =============================================================================== |
mbed_official | 573:ad23fe03a082 | 810 | ##### Peripheral Control functions ##### |
mbed_official | 573:ad23fe03a082 | 811 | =============================================================================== |
mbed_official | 573:ad23fe03a082 | 812 | [..] This section provides functions allowing to: |
mbed_official | 573:ad23fe03a082 | 813 | (+) Configure the DMA2D foreground or/and background parameters. |
mbed_official | 573:ad23fe03a082 | 814 | (+) Configure the DMA2D CLUT transfer. |
mbed_official | 573:ad23fe03a082 | 815 | (+) Enable DMA2D CLUT. |
mbed_official | 573:ad23fe03a082 | 816 | (+) Disable DMA2D CLUT. |
mbed_official | 573:ad23fe03a082 | 817 | (+) Configure the line watermark |
mbed_official | 573:ad23fe03a082 | 818 | |
mbed_official | 573:ad23fe03a082 | 819 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 820 | * @{ |
mbed_official | 573:ad23fe03a082 | 821 | */ |
mbed_official | 573:ad23fe03a082 | 822 | /** |
mbed_official | 573:ad23fe03a082 | 823 | * @brief Configure the DMA2D Layer according to the specified |
mbed_official | 573:ad23fe03a082 | 824 | * parameters in the DMA2D_InitTypeDef and create the associated handle. |
mbed_official | 573:ad23fe03a082 | 825 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 826 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 827 | * @param LayerIdx: DMA2D Layer index. |
mbed_official | 573:ad23fe03a082 | 828 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 829 | * 0(background) / 1(foreground) |
mbed_official | 573:ad23fe03a082 | 830 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 831 | */ |
mbed_official | 573:ad23fe03a082 | 832 | HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) |
mbed_official | 573:ad23fe03a082 | 833 | { |
mbed_official | 573:ad23fe03a082 | 834 | DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; |
mbed_official | 573:ad23fe03a082 | 835 | |
mbed_official | 573:ad23fe03a082 | 836 | uint32_t tmp = 0; |
mbed_official | 573:ad23fe03a082 | 837 | |
mbed_official | 573:ad23fe03a082 | 838 | /* Process locked */ |
mbed_official | 573:ad23fe03a082 | 839 | __HAL_LOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 840 | |
mbed_official | 573:ad23fe03a082 | 841 | /* Change DMA2D peripheral state */ |
mbed_official | 573:ad23fe03a082 | 842 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 843 | |
mbed_official | 573:ad23fe03a082 | 844 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 845 | assert_param(IS_DMA2D_LAYER(LayerIdx)); |
mbed_official | 573:ad23fe03a082 | 846 | assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset)); |
mbed_official | 573:ad23fe03a082 | 847 | if(hdma2d->Init.Mode != DMA2D_R2M) |
mbed_official | 573:ad23fe03a082 | 848 | { |
mbed_official | 573:ad23fe03a082 | 849 | assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode)); |
mbed_official | 573:ad23fe03a082 | 850 | if(hdma2d->Init.Mode != DMA2D_M2M) |
mbed_official | 573:ad23fe03a082 | 851 | { |
mbed_official | 573:ad23fe03a082 | 852 | assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode)); |
mbed_official | 573:ad23fe03a082 | 853 | } |
mbed_official | 573:ad23fe03a082 | 854 | } |
mbed_official | 573:ad23fe03a082 | 855 | |
mbed_official | 573:ad23fe03a082 | 856 | /* Configure the background DMA2D layer */ |
mbed_official | 573:ad23fe03a082 | 857 | if(LayerIdx == 0) |
mbed_official | 573:ad23fe03a082 | 858 | { |
mbed_official | 573:ad23fe03a082 | 859 | /* DMA2D BGPFCR register configuration -----------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 860 | /* Get the BGPFCCR register value */ |
mbed_official | 573:ad23fe03a082 | 861 | tmp = hdma2d->Instance->BGPFCCR; |
mbed_official | 573:ad23fe03a082 | 862 | |
mbed_official | 573:ad23fe03a082 | 863 | /* Clear Input color mode, alpha value and alpha mode bits */ |
mbed_official | 573:ad23fe03a082 | 864 | tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA); |
mbed_official | 573:ad23fe03a082 | 865 | |
mbed_official | 573:ad23fe03a082 | 866 | if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) |
mbed_official | 573:ad23fe03a082 | 867 | { |
mbed_official | 573:ad23fe03a082 | 868 | /* Prepare the value to be wrote to the BGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 869 | tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000)); |
mbed_official | 573:ad23fe03a082 | 870 | } |
mbed_official | 573:ad23fe03a082 | 871 | else |
mbed_official | 573:ad23fe03a082 | 872 | { |
mbed_official | 573:ad23fe03a082 | 873 | /* Prepare the value to be wrote to the BGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 874 | tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); |
mbed_official | 573:ad23fe03a082 | 875 | } |
mbed_official | 573:ad23fe03a082 | 876 | |
mbed_official | 573:ad23fe03a082 | 877 | /* Write to DMA2D BGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 878 | hdma2d->Instance->BGPFCCR = tmp; |
mbed_official | 573:ad23fe03a082 | 879 | |
mbed_official | 573:ad23fe03a082 | 880 | /* DMA2D BGOR register configuration -------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 881 | /* Get the BGOR register value */ |
mbed_official | 573:ad23fe03a082 | 882 | tmp = hdma2d->Instance->BGOR; |
mbed_official | 573:ad23fe03a082 | 883 | |
mbed_official | 573:ad23fe03a082 | 884 | /* Clear colors bits */ |
mbed_official | 573:ad23fe03a082 | 885 | tmp &= (uint32_t)~DMA2D_BGOR_LO; |
mbed_official | 573:ad23fe03a082 | 886 | |
mbed_official | 573:ad23fe03a082 | 887 | /* Prepare the value to be wrote to the BGOR register */ |
mbed_official | 573:ad23fe03a082 | 888 | tmp |= pLayerCfg->InputOffset; |
mbed_official | 573:ad23fe03a082 | 889 | |
mbed_official | 573:ad23fe03a082 | 890 | /* Write to DMA2D BGOR register */ |
mbed_official | 573:ad23fe03a082 | 891 | hdma2d->Instance->BGOR = tmp; |
mbed_official | 573:ad23fe03a082 | 892 | |
mbed_official | 573:ad23fe03a082 | 893 | if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) |
mbed_official | 573:ad23fe03a082 | 894 | { |
mbed_official | 573:ad23fe03a082 | 895 | /* Prepare the value to be wrote to the BGCOLR register */ |
mbed_official | 573:ad23fe03a082 | 896 | tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF); |
mbed_official | 573:ad23fe03a082 | 897 | |
mbed_official | 573:ad23fe03a082 | 898 | /* Write to DMA2D BGCOLR register */ |
mbed_official | 573:ad23fe03a082 | 899 | hdma2d->Instance->BGCOLR = tmp; |
mbed_official | 573:ad23fe03a082 | 900 | } |
mbed_official | 573:ad23fe03a082 | 901 | } |
mbed_official | 573:ad23fe03a082 | 902 | /* Configure the foreground DMA2D layer */ |
mbed_official | 573:ad23fe03a082 | 903 | else |
mbed_official | 573:ad23fe03a082 | 904 | { |
mbed_official | 573:ad23fe03a082 | 905 | /* DMA2D FGPFCR register configuration -----------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 906 | /* Get the FGPFCCR register value */ |
mbed_official | 573:ad23fe03a082 | 907 | tmp = hdma2d->Instance->FGPFCCR; |
mbed_official | 573:ad23fe03a082 | 908 | |
mbed_official | 573:ad23fe03a082 | 909 | /* Clear Input color mode, alpha value and alpha mode bits */ |
mbed_official | 573:ad23fe03a082 | 910 | tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA); |
mbed_official | 573:ad23fe03a082 | 911 | |
mbed_official | 573:ad23fe03a082 | 912 | if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) |
mbed_official | 573:ad23fe03a082 | 913 | { |
mbed_official | 573:ad23fe03a082 | 914 | /* Prepare the value to be wrote to the FGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 915 | tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000)); |
mbed_official | 573:ad23fe03a082 | 916 | } |
mbed_official | 573:ad23fe03a082 | 917 | else |
mbed_official | 573:ad23fe03a082 | 918 | { |
mbed_official | 573:ad23fe03a082 | 919 | /* Prepare the value to be wrote to the FGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 920 | tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24)); |
mbed_official | 573:ad23fe03a082 | 921 | } |
mbed_official | 573:ad23fe03a082 | 922 | |
mbed_official | 573:ad23fe03a082 | 923 | /* Write to DMA2D FGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 924 | hdma2d->Instance->FGPFCCR = tmp; |
mbed_official | 573:ad23fe03a082 | 925 | |
mbed_official | 573:ad23fe03a082 | 926 | /* DMA2D FGOR register configuration -------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 927 | /* Get the FGOR register value */ |
mbed_official | 573:ad23fe03a082 | 928 | tmp = hdma2d->Instance->FGOR; |
mbed_official | 573:ad23fe03a082 | 929 | |
mbed_official | 573:ad23fe03a082 | 930 | /* Clear colors bits */ |
mbed_official | 573:ad23fe03a082 | 931 | tmp &= (uint32_t)~DMA2D_FGOR_LO; |
mbed_official | 573:ad23fe03a082 | 932 | |
mbed_official | 573:ad23fe03a082 | 933 | /* Prepare the value to be wrote to the FGOR register */ |
mbed_official | 573:ad23fe03a082 | 934 | tmp |= pLayerCfg->InputOffset; |
mbed_official | 573:ad23fe03a082 | 935 | |
mbed_official | 573:ad23fe03a082 | 936 | /* Write to DMA2D FGOR register */ |
mbed_official | 573:ad23fe03a082 | 937 | hdma2d->Instance->FGOR = tmp; |
mbed_official | 573:ad23fe03a082 | 938 | |
mbed_official | 573:ad23fe03a082 | 939 | if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) |
mbed_official | 573:ad23fe03a082 | 940 | { |
mbed_official | 573:ad23fe03a082 | 941 | /* Prepare the value to be wrote to the FGCOLR register */ |
mbed_official | 573:ad23fe03a082 | 942 | tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF); |
mbed_official | 573:ad23fe03a082 | 943 | |
mbed_official | 573:ad23fe03a082 | 944 | /* Write to DMA2D FGCOLR register */ |
mbed_official | 573:ad23fe03a082 | 945 | hdma2d->Instance->FGCOLR = tmp; |
mbed_official | 573:ad23fe03a082 | 946 | } |
mbed_official | 573:ad23fe03a082 | 947 | } |
mbed_official | 573:ad23fe03a082 | 948 | /* Initialize the DMA2D state*/ |
mbed_official | 573:ad23fe03a082 | 949 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 950 | |
mbed_official | 573:ad23fe03a082 | 951 | /* Process unlocked */ |
mbed_official | 573:ad23fe03a082 | 952 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 953 | |
mbed_official | 573:ad23fe03a082 | 954 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 955 | } |
mbed_official | 573:ad23fe03a082 | 956 | |
mbed_official | 573:ad23fe03a082 | 957 | /** |
mbed_official | 573:ad23fe03a082 | 958 | * @brief Configure the DMA2D CLUT Transfer. |
mbed_official | 573:ad23fe03a082 | 959 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 960 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 961 | * @param CLUTCfg: pointer to a DMA2D_CLUTCfgTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 962 | * the configuration information for the color look up table. |
mbed_official | 573:ad23fe03a082 | 963 | * @param LayerIdx: DMA2D Layer index. |
mbed_official | 573:ad23fe03a082 | 964 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 965 | * 0(background) / 1(foreground) |
mbed_official | 573:ad23fe03a082 | 966 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 967 | */ |
mbed_official | 573:ad23fe03a082 | 968 | HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) |
mbed_official | 573:ad23fe03a082 | 969 | { |
mbed_official | 573:ad23fe03a082 | 970 | uint32_t tmp = 0, tmp1 = 0; |
mbed_official | 573:ad23fe03a082 | 971 | |
mbed_official | 573:ad23fe03a082 | 972 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 973 | assert_param(IS_DMA2D_LAYER(LayerIdx)); |
mbed_official | 573:ad23fe03a082 | 974 | assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); |
mbed_official | 573:ad23fe03a082 | 975 | assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); |
mbed_official | 573:ad23fe03a082 | 976 | |
mbed_official | 573:ad23fe03a082 | 977 | /* Configure the CLUT of the background DMA2D layer */ |
mbed_official | 573:ad23fe03a082 | 978 | if(LayerIdx == 0) |
mbed_official | 573:ad23fe03a082 | 979 | { |
mbed_official | 573:ad23fe03a082 | 980 | /* Get the BGCMAR register value */ |
mbed_official | 573:ad23fe03a082 | 981 | tmp = hdma2d->Instance->BGCMAR; |
mbed_official | 573:ad23fe03a082 | 982 | |
mbed_official | 573:ad23fe03a082 | 983 | /* Clear CLUT address bits */ |
mbed_official | 573:ad23fe03a082 | 984 | tmp &= (uint32_t)~DMA2D_BGCMAR_MA; |
mbed_official | 573:ad23fe03a082 | 985 | |
mbed_official | 573:ad23fe03a082 | 986 | /* Prepare the value to be wrote to the BGCMAR register */ |
mbed_official | 573:ad23fe03a082 | 987 | tmp |= (uint32_t)CLUTCfg.pCLUT; |
mbed_official | 573:ad23fe03a082 | 988 | |
mbed_official | 573:ad23fe03a082 | 989 | /* Write to DMA2D BGCMAR register */ |
mbed_official | 573:ad23fe03a082 | 990 | hdma2d->Instance->BGCMAR = tmp; |
mbed_official | 573:ad23fe03a082 | 991 | |
mbed_official | 573:ad23fe03a082 | 992 | /* Get the BGPFCCR register value */ |
mbed_official | 573:ad23fe03a082 | 993 | tmp = hdma2d->Instance->BGPFCCR; |
mbed_official | 573:ad23fe03a082 | 994 | |
mbed_official | 573:ad23fe03a082 | 995 | /* Clear CLUT size and CLUT address bits */ |
mbed_official | 573:ad23fe03a082 | 996 | tmp &= (uint32_t)~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM); |
mbed_official | 573:ad23fe03a082 | 997 | |
mbed_official | 573:ad23fe03a082 | 998 | /* Get the CLUT size */ |
mbed_official | 573:ad23fe03a082 | 999 | tmp1 = CLUTCfg.Size << 16; |
mbed_official | 573:ad23fe03a082 | 1000 | |
mbed_official | 573:ad23fe03a082 | 1001 | /* Prepare the value to be wrote to the BGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 1002 | tmp |= (CLUTCfg.CLUTColorMode | tmp1); |
mbed_official | 573:ad23fe03a082 | 1003 | |
mbed_official | 573:ad23fe03a082 | 1004 | /* Write to DMA2D BGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 1005 | hdma2d->Instance->BGPFCCR = tmp; |
mbed_official | 573:ad23fe03a082 | 1006 | } |
mbed_official | 573:ad23fe03a082 | 1007 | /* Configure the CLUT of the foreground DMA2D layer */ |
mbed_official | 573:ad23fe03a082 | 1008 | else |
mbed_official | 573:ad23fe03a082 | 1009 | { |
mbed_official | 573:ad23fe03a082 | 1010 | /* Get the FGCMAR register value */ |
mbed_official | 573:ad23fe03a082 | 1011 | tmp = hdma2d->Instance->FGCMAR; |
mbed_official | 573:ad23fe03a082 | 1012 | |
mbed_official | 573:ad23fe03a082 | 1013 | /* Clear CLUT address bits */ |
mbed_official | 573:ad23fe03a082 | 1014 | tmp &= (uint32_t)~DMA2D_FGCMAR_MA; |
mbed_official | 573:ad23fe03a082 | 1015 | |
mbed_official | 573:ad23fe03a082 | 1016 | /* Prepare the value to be wrote to the FGCMAR register */ |
mbed_official | 573:ad23fe03a082 | 1017 | tmp |= (uint32_t)CLUTCfg.pCLUT; |
mbed_official | 573:ad23fe03a082 | 1018 | |
mbed_official | 573:ad23fe03a082 | 1019 | /* Write to DMA2D FGCMAR register */ |
mbed_official | 573:ad23fe03a082 | 1020 | hdma2d->Instance->FGCMAR = tmp; |
mbed_official | 573:ad23fe03a082 | 1021 | |
mbed_official | 573:ad23fe03a082 | 1022 | /* Get the FGPFCCR register value */ |
mbed_official | 573:ad23fe03a082 | 1023 | tmp = hdma2d->Instance->FGPFCCR; |
mbed_official | 573:ad23fe03a082 | 1024 | |
mbed_official | 573:ad23fe03a082 | 1025 | /* Clear CLUT size and CLUT address bits */ |
mbed_official | 573:ad23fe03a082 | 1026 | tmp &= (uint32_t)~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM); |
mbed_official | 573:ad23fe03a082 | 1027 | |
mbed_official | 573:ad23fe03a082 | 1028 | /* Get the CLUT size */ |
mbed_official | 573:ad23fe03a082 | 1029 | tmp1 = CLUTCfg.Size << 8; |
mbed_official | 573:ad23fe03a082 | 1030 | |
mbed_official | 573:ad23fe03a082 | 1031 | /* Prepare the value to be wrote to the FGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 1032 | tmp |= (CLUTCfg.CLUTColorMode | tmp1); |
mbed_official | 573:ad23fe03a082 | 1033 | |
mbed_official | 573:ad23fe03a082 | 1034 | /* Write to DMA2D FGPFCCR register */ |
mbed_official | 573:ad23fe03a082 | 1035 | hdma2d->Instance->FGPFCCR = tmp; |
mbed_official | 573:ad23fe03a082 | 1036 | } |
mbed_official | 573:ad23fe03a082 | 1037 | |
mbed_official | 573:ad23fe03a082 | 1038 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 1039 | } |
mbed_official | 573:ad23fe03a082 | 1040 | |
mbed_official | 573:ad23fe03a082 | 1041 | /** |
mbed_official | 573:ad23fe03a082 | 1042 | * @brief Enable the DMA2D CLUT Transfer. |
mbed_official | 573:ad23fe03a082 | 1043 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 1044 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 1045 | * @param LayerIdx: DMA2D Layer index. |
mbed_official | 573:ad23fe03a082 | 1046 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 1047 | * 0(background) / 1(foreground) |
mbed_official | 573:ad23fe03a082 | 1048 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 1049 | */ |
mbed_official | 573:ad23fe03a082 | 1050 | HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) |
mbed_official | 573:ad23fe03a082 | 1051 | { |
mbed_official | 573:ad23fe03a082 | 1052 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 1053 | assert_param(IS_DMA2D_LAYER(LayerIdx)); |
mbed_official | 573:ad23fe03a082 | 1054 | |
mbed_official | 573:ad23fe03a082 | 1055 | if(LayerIdx == 0) |
mbed_official | 573:ad23fe03a082 | 1056 | { |
mbed_official | 573:ad23fe03a082 | 1057 | /* Enable the CLUT loading for the background */ |
mbed_official | 573:ad23fe03a082 | 1058 | hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START; |
mbed_official | 573:ad23fe03a082 | 1059 | } |
mbed_official | 573:ad23fe03a082 | 1060 | else |
mbed_official | 573:ad23fe03a082 | 1061 | { |
mbed_official | 573:ad23fe03a082 | 1062 | /* Enable the CLUT loading for the foreground */ |
mbed_official | 573:ad23fe03a082 | 1063 | hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START; |
mbed_official | 573:ad23fe03a082 | 1064 | } |
mbed_official | 573:ad23fe03a082 | 1065 | |
mbed_official | 573:ad23fe03a082 | 1066 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 1067 | } |
mbed_official | 573:ad23fe03a082 | 1068 | |
mbed_official | 573:ad23fe03a082 | 1069 | /** |
mbed_official | 573:ad23fe03a082 | 1070 | * @brief Disable the DMA2D CLUT Transfer. |
mbed_official | 573:ad23fe03a082 | 1071 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 1072 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 1073 | * @param LayerIdx: DMA2D Layer index. |
mbed_official | 573:ad23fe03a082 | 1074 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 1075 | * 0(background) / 1(foreground) |
mbed_official | 573:ad23fe03a082 | 1076 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 1077 | */ |
mbed_official | 573:ad23fe03a082 | 1078 | HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) |
mbed_official | 573:ad23fe03a082 | 1079 | { |
mbed_official | 573:ad23fe03a082 | 1080 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 1081 | assert_param(IS_DMA2D_LAYER(LayerIdx)); |
mbed_official | 573:ad23fe03a082 | 1082 | |
mbed_official | 573:ad23fe03a082 | 1083 | if(LayerIdx == 0) |
mbed_official | 573:ad23fe03a082 | 1084 | { |
mbed_official | 573:ad23fe03a082 | 1085 | /* Disable the CLUT loading for the background */ |
mbed_official | 573:ad23fe03a082 | 1086 | hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START; |
mbed_official | 573:ad23fe03a082 | 1087 | } |
mbed_official | 573:ad23fe03a082 | 1088 | else |
mbed_official | 573:ad23fe03a082 | 1089 | { |
mbed_official | 573:ad23fe03a082 | 1090 | /* Disable the CLUT loading for the foreground */ |
mbed_official | 573:ad23fe03a082 | 1091 | hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START; |
mbed_official | 573:ad23fe03a082 | 1092 | } |
mbed_official | 573:ad23fe03a082 | 1093 | |
mbed_official | 573:ad23fe03a082 | 1094 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 1095 | } |
mbed_official | 573:ad23fe03a082 | 1096 | |
mbed_official | 573:ad23fe03a082 | 1097 | /** |
mbed_official | 573:ad23fe03a082 | 1098 | * @brief Define the configuration of the line watermark . |
mbed_official | 573:ad23fe03a082 | 1099 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 1100 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 1101 | * @param Line: Line Watermark configuration. |
mbed_official | 573:ad23fe03a082 | 1102 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 1103 | */ |
mbed_official | 573:ad23fe03a082 | 1104 | |
mbed_official | 573:ad23fe03a082 | 1105 | HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) |
mbed_official | 573:ad23fe03a082 | 1106 | { |
mbed_official | 573:ad23fe03a082 | 1107 | /* Process locked */ |
mbed_official | 573:ad23fe03a082 | 1108 | __HAL_LOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 1109 | |
mbed_official | 573:ad23fe03a082 | 1110 | /* Change DMA2D peripheral state */ |
mbed_official | 573:ad23fe03a082 | 1111 | hdma2d->State = HAL_DMA2D_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 1112 | |
mbed_official | 573:ad23fe03a082 | 1113 | /* Check the parameters */ |
mbed_official | 573:ad23fe03a082 | 1114 | assert_param(IS_DMA2D_LineWatermark(Line)); |
mbed_official | 573:ad23fe03a082 | 1115 | |
mbed_official | 573:ad23fe03a082 | 1116 | /* Sets the Line watermark configuration */ |
mbed_official | 573:ad23fe03a082 | 1117 | DMA2D->LWR = (uint32_t)Line; |
mbed_official | 573:ad23fe03a082 | 1118 | |
mbed_official | 573:ad23fe03a082 | 1119 | /* Initialize the DMA2D state*/ |
mbed_official | 573:ad23fe03a082 | 1120 | hdma2d->State = HAL_DMA2D_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 1121 | |
mbed_official | 573:ad23fe03a082 | 1122 | /* Process unlocked */ |
mbed_official | 573:ad23fe03a082 | 1123 | __HAL_UNLOCK(hdma2d); |
mbed_official | 573:ad23fe03a082 | 1124 | |
mbed_official | 573:ad23fe03a082 | 1125 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 1126 | } |
mbed_official | 573:ad23fe03a082 | 1127 | |
mbed_official | 573:ad23fe03a082 | 1128 | /** |
mbed_official | 573:ad23fe03a082 | 1129 | * @} |
mbed_official | 573:ad23fe03a082 | 1130 | */ |
mbed_official | 573:ad23fe03a082 | 1131 | |
mbed_official | 573:ad23fe03a082 | 1132 | /** @defgroup DMA2D_Group4 Peripheral State functions |
mbed_official | 573:ad23fe03a082 | 1133 | * @brief Peripheral State functions |
mbed_official | 573:ad23fe03a082 | 1134 | * |
mbed_official | 573:ad23fe03a082 | 1135 | @verbatim |
mbed_official | 573:ad23fe03a082 | 1136 | =============================================================================== |
mbed_official | 573:ad23fe03a082 | 1137 | ##### Peripheral State and Errors functions ##### |
mbed_official | 573:ad23fe03a082 | 1138 | =============================================================================== |
mbed_official | 573:ad23fe03a082 | 1139 | [..] |
mbed_official | 573:ad23fe03a082 | 1140 | This subsection provides functions allowing to : |
mbed_official | 573:ad23fe03a082 | 1141 | (+) Check the DMA2D state |
mbed_official | 573:ad23fe03a082 | 1142 | (+) Get error code |
mbed_official | 573:ad23fe03a082 | 1143 | |
mbed_official | 573:ad23fe03a082 | 1144 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 1145 | * @{ |
mbed_official | 573:ad23fe03a082 | 1146 | */ |
mbed_official | 573:ad23fe03a082 | 1147 | |
mbed_official | 573:ad23fe03a082 | 1148 | /** |
mbed_official | 573:ad23fe03a082 | 1149 | * @brief Return the DMA2D state |
mbed_official | 573:ad23fe03a082 | 1150 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 1151 | * the configuration information for the DMA2D. |
mbed_official | 573:ad23fe03a082 | 1152 | * @retval HAL state |
mbed_official | 573:ad23fe03a082 | 1153 | */ |
mbed_official | 573:ad23fe03a082 | 1154 | HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 573:ad23fe03a082 | 1155 | { |
mbed_official | 573:ad23fe03a082 | 1156 | return hdma2d->State; |
mbed_official | 573:ad23fe03a082 | 1157 | } |
mbed_official | 573:ad23fe03a082 | 1158 | |
mbed_official | 573:ad23fe03a082 | 1159 | /** |
mbed_official | 573:ad23fe03a082 | 1160 | * @brief Return the DMA2D error code |
mbed_official | 573:ad23fe03a082 | 1161 | * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 1162 | * the configuration information for DMA2D. |
mbed_official | 573:ad23fe03a082 | 1163 | * @retval DMA2D Error Code |
mbed_official | 573:ad23fe03a082 | 1164 | */ |
mbed_official | 573:ad23fe03a082 | 1165 | uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) |
mbed_official | 573:ad23fe03a082 | 1166 | { |
mbed_official | 573:ad23fe03a082 | 1167 | return hdma2d->ErrorCode; |
mbed_official | 573:ad23fe03a082 | 1168 | } |
mbed_official | 573:ad23fe03a082 | 1169 | |
mbed_official | 573:ad23fe03a082 | 1170 | /** |
mbed_official | 573:ad23fe03a082 | 1171 | * @} |
mbed_official | 573:ad23fe03a082 | 1172 | */ |
mbed_official | 573:ad23fe03a082 | 1173 | |
mbed_official | 573:ad23fe03a082 | 1174 | |
mbed_official | 573:ad23fe03a082 | 1175 | /** |
mbed_official | 573:ad23fe03a082 | 1176 | * @brief Set the DMA2D Transfer parameter. |
mbed_official | 573:ad23fe03a082 | 1177 | * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 1178 | * the configuration information for the specified DMA2D. |
mbed_official | 573:ad23fe03a082 | 1179 | * @param pdata: The source memory Buffer address |
mbed_official | 573:ad23fe03a082 | 1180 | * @param DstAddress: The destination memory Buffer address |
mbed_official | 573:ad23fe03a082 | 1181 | * @param Width: The width of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 1182 | * @param Height: The height of data to be transferred from source to destination. |
mbed_official | 573:ad23fe03a082 | 1183 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 1184 | */ |
mbed_official | 573:ad23fe03a082 | 1185 | static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) |
mbed_official | 573:ad23fe03a082 | 1186 | { |
mbed_official | 573:ad23fe03a082 | 1187 | uint32_t tmp = 0; |
mbed_official | 573:ad23fe03a082 | 1188 | uint32_t tmp1 = 0; |
mbed_official | 573:ad23fe03a082 | 1189 | uint32_t tmp2 = 0; |
mbed_official | 573:ad23fe03a082 | 1190 | uint32_t tmp3 = 0; |
mbed_official | 573:ad23fe03a082 | 1191 | uint32_t tmp4 = 0; |
mbed_official | 573:ad23fe03a082 | 1192 | |
mbed_official | 573:ad23fe03a082 | 1193 | tmp = Width << 16; |
mbed_official | 573:ad23fe03a082 | 1194 | |
mbed_official | 573:ad23fe03a082 | 1195 | /* Configure DMA2D data size */ |
mbed_official | 573:ad23fe03a082 | 1196 | hdma2d->Instance->NLR = (Height | tmp); |
mbed_official | 573:ad23fe03a082 | 1197 | |
mbed_official | 573:ad23fe03a082 | 1198 | /* Configure DMA2D destination address */ |
mbed_official | 573:ad23fe03a082 | 1199 | hdma2d->Instance->OMAR = DstAddress; |
mbed_official | 573:ad23fe03a082 | 1200 | |
mbed_official | 573:ad23fe03a082 | 1201 | /* Register to memory DMA2D mode selected */ |
mbed_official | 573:ad23fe03a082 | 1202 | if (hdma2d->Init.Mode == DMA2D_R2M) |
mbed_official | 573:ad23fe03a082 | 1203 | { |
mbed_official | 573:ad23fe03a082 | 1204 | tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; |
mbed_official | 573:ad23fe03a082 | 1205 | tmp2 = pdata & DMA2D_OCOLR_RED_1; |
mbed_official | 573:ad23fe03a082 | 1206 | tmp3 = pdata & DMA2D_OCOLR_GREEN_1; |
mbed_official | 573:ad23fe03a082 | 1207 | tmp4 = pdata & DMA2D_OCOLR_BLUE_1; |
mbed_official | 573:ad23fe03a082 | 1208 | |
mbed_official | 573:ad23fe03a082 | 1209 | /* Prepare the value to be wrote to the OCOLR register according to the color mode */ |
mbed_official | 573:ad23fe03a082 | 1210 | if (hdma2d->Init.ColorMode == DMA2D_ARGB8888) |
mbed_official | 573:ad23fe03a082 | 1211 | { |
mbed_official | 573:ad23fe03a082 | 1212 | tmp = (tmp3 | tmp2 | tmp1| tmp4); |
mbed_official | 573:ad23fe03a082 | 1213 | } |
mbed_official | 573:ad23fe03a082 | 1214 | else if (hdma2d->Init.ColorMode == DMA2D_RGB888) |
mbed_official | 573:ad23fe03a082 | 1215 | { |
mbed_official | 573:ad23fe03a082 | 1216 | tmp = (tmp3 | tmp2 | tmp4); |
mbed_official | 573:ad23fe03a082 | 1217 | } |
mbed_official | 573:ad23fe03a082 | 1218 | else if (hdma2d->Init.ColorMode == DMA2D_RGB565) |
mbed_official | 573:ad23fe03a082 | 1219 | { |
mbed_official | 573:ad23fe03a082 | 1220 | tmp2 = (tmp2 >> 19); |
mbed_official | 573:ad23fe03a082 | 1221 | tmp3 = (tmp3 >> 10); |
mbed_official | 573:ad23fe03a082 | 1222 | tmp4 = (tmp4 >> 3 ); |
mbed_official | 573:ad23fe03a082 | 1223 | tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4); |
mbed_official | 573:ad23fe03a082 | 1224 | } |
mbed_official | 573:ad23fe03a082 | 1225 | else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555) |
mbed_official | 573:ad23fe03a082 | 1226 | { |
mbed_official | 573:ad23fe03a082 | 1227 | tmp1 = (tmp1 >> 31); |
mbed_official | 573:ad23fe03a082 | 1228 | tmp2 = (tmp2 >> 19); |
mbed_official | 573:ad23fe03a082 | 1229 | tmp3 = (tmp3 >> 11); |
mbed_official | 573:ad23fe03a082 | 1230 | tmp4 = (tmp4 >> 3 ); |
mbed_official | 573:ad23fe03a082 | 1231 | tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4); |
mbed_official | 573:ad23fe03a082 | 1232 | } |
mbed_official | 573:ad23fe03a082 | 1233 | else /* DMA2D_CMode = DMA2D_ARGB4444 */ |
mbed_official | 573:ad23fe03a082 | 1234 | { |
mbed_official | 573:ad23fe03a082 | 1235 | tmp1 = (tmp1 >> 28); |
mbed_official | 573:ad23fe03a082 | 1236 | tmp2 = (tmp2 >> 20); |
mbed_official | 573:ad23fe03a082 | 1237 | tmp3 = (tmp3 >> 12); |
mbed_official | 573:ad23fe03a082 | 1238 | tmp4 = (tmp4 >> 4 ); |
mbed_official | 573:ad23fe03a082 | 1239 | tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4); |
mbed_official | 573:ad23fe03a082 | 1240 | } |
mbed_official | 573:ad23fe03a082 | 1241 | /* Write to DMA2D OCOLR register */ |
mbed_official | 573:ad23fe03a082 | 1242 | hdma2d->Instance->OCOLR = tmp; |
mbed_official | 573:ad23fe03a082 | 1243 | } |
mbed_official | 573:ad23fe03a082 | 1244 | else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ |
mbed_official | 573:ad23fe03a082 | 1245 | { |
mbed_official | 573:ad23fe03a082 | 1246 | /* Configure DMA2D source address */ |
mbed_official | 573:ad23fe03a082 | 1247 | hdma2d->Instance->FGMAR = pdata; |
mbed_official | 573:ad23fe03a082 | 1248 | } |
mbed_official | 573:ad23fe03a082 | 1249 | } |
mbed_official | 573:ad23fe03a082 | 1250 | |
mbed_official | 573:ad23fe03a082 | 1251 | /** |
mbed_official | 573:ad23fe03a082 | 1252 | * @} |
mbed_official | 573:ad23fe03a082 | 1253 | */ |
mbed_official | 573:ad23fe03a082 | 1254 | #endif /* HAL_DMA2D_MODULE_ENABLED */ |
mbed_official | 573:ad23fe03a082 | 1255 | /** |
mbed_official | 573:ad23fe03a082 | 1256 | * @} |
mbed_official | 573:ad23fe03a082 | 1257 | */ |
mbed_official | 573:ad23fe03a082 | 1258 | |
mbed_official | 573:ad23fe03a082 | 1259 | /** |
mbed_official | 573:ad23fe03a082 | 1260 | * @} |
mbed_official | 573:ad23fe03a082 | 1261 | */ |
mbed_official | 573:ad23fe03a082 | 1262 | |
mbed_official | 573:ad23fe03a082 | 1263 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |