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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c@573:ad23fe03a082, 2015-06-19 (annotated)

Committer:
mbed_official
Date:
Fri Jun 19 09:15:11 2015 +0100
Revision:
573:ad23fe03a082
Synchronized with git revision d47834cd4d729e5b36b4c1ad4650f8b8f6a9ab86



Full URL: https://github.com/mbedmicro/mbed/commit/d47834cd4d729e5b36b4c1ad4650f8b8f6a9ab86/



DISCO_F746NG - Add new target

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UserRevisionLine numberNew contents of line
mbed_official 573:ad23fe03a082 1 /**
mbed_official 573:ad23fe03a082 2 ******************************************************************************
mbed_official 573:ad23fe03a082 3 * @file stm32f7xx_hal_eth.c
mbed_official 573:ad23fe03a082 4 * @author MCD Application Team
mbed_official 573:ad23fe03a082 5 * @version V1.0.0
mbed_official 573:ad23fe03a082 6 * @date 12-May-2015
mbed_official 573:ad23fe03a082 7 * @brief ETH HAL module driver.
mbed_official 573:ad23fe03a082 8 * This file provides firmware functions to manage the following
mbed_official 573:ad23fe03a082 9 * functionalities of the Ethernet (ETH) peripheral:
mbed_official 573:ad23fe03a082 10 * + Initialization and de-initialization functions
mbed_official 573:ad23fe03a082 11 * + IO operation functions
mbed_official 573:ad23fe03a082 12 * + Peripheral Control functions
mbed_official 573:ad23fe03a082 13 * + Peripheral State and Errors functions
mbed_official 573:ad23fe03a082 14 *
mbed_official 573:ad23fe03a082 15 @verbatim
mbed_official 573:ad23fe03a082 16 ==============================================================================
mbed_official 573:ad23fe03a082 17 ##### How to use this driver #####
mbed_official 573:ad23fe03a082 18 ==============================================================================
mbed_official 573:ad23fe03a082 19 [..]
mbed_official 573:ad23fe03a082 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
mbed_official 573:ad23fe03a082 21 ETH_HandleTypeDef heth;
mbed_official 573:ad23fe03a082 22
mbed_official 573:ad23fe03a082 23 (#)Fill parameters of Init structure in heth handle
mbed_official 573:ad23fe03a082 24
mbed_official 573:ad23fe03a082 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
mbed_official 573:ad23fe03a082 26
mbed_official 573:ad23fe03a082 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
mbed_official 573:ad23fe03a082 28 (##) Enable the Ethernet interface clock using
mbed_official 573:ad23fe03a082 29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
mbed_official 573:ad23fe03a082 30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
mbed_official 573:ad23fe03a082 31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
mbed_official 573:ad23fe03a082 32
mbed_official 573:ad23fe03a082 33 (##) Initialize the related GPIO clocks
mbed_official 573:ad23fe03a082 34 (##) Configure Ethernet pin-out
mbed_official 573:ad23fe03a082 35 (##) Configure Ethernet NVIC interrupt (IT mode)
mbed_official 573:ad23fe03a082 36
mbed_official 573:ad23fe03a082 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
mbed_official 573:ad23fe03a082 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
mbed_official 573:ad23fe03a082 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
mbed_official 573:ad23fe03a082 40
mbed_official 573:ad23fe03a082 41 (#)Enable MAC and DMA transmission and reception:
mbed_official 573:ad23fe03a082 42 (##) HAL_ETH_Start();
mbed_official 573:ad23fe03a082 43
mbed_official 573:ad23fe03a082 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
mbed_official 573:ad23fe03a082 45 the frame to MAC TX FIFO:
mbed_official 573:ad23fe03a082 46 (##) HAL_ETH_TransmitFrame();
mbed_official 573:ad23fe03a082 47
mbed_official 573:ad23fe03a082 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
mbed_official 573:ad23fe03a082 49 frame parameters
mbed_official 573:ad23fe03a082 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
mbed_official 573:ad23fe03a082 51
mbed_official 573:ad23fe03a082 52 (#) Get a received frame when an ETH RX interrupt occurs:
mbed_official 573:ad23fe03a082 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
mbed_official 573:ad23fe03a082 54
mbed_official 573:ad23fe03a082 55 (#) Communicate with external PHY device:
mbed_official 573:ad23fe03a082 56 (##) Read a specific register from the PHY
mbed_official 573:ad23fe03a082 57 HAL_ETH_ReadPHYRegister();
mbed_official 573:ad23fe03a082 58 (##) Write data to a specific RHY register:
mbed_official 573:ad23fe03a082 59 HAL_ETH_WritePHYRegister();
mbed_official 573:ad23fe03a082 60
mbed_official 573:ad23fe03a082 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
mbed_official 573:ad23fe03a082 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
mbed_official 573:ad23fe03a082 63
mbed_official 573:ad23fe03a082 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
mbed_official 573:ad23fe03a082 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
mbed_official 573:ad23fe03a082 66
mbed_official 573:ad23fe03a082 67 @endverbatim
mbed_official 573:ad23fe03a082 68 ******************************************************************************
mbed_official 573:ad23fe03a082 69 * @attention
mbed_official 573:ad23fe03a082 70 *
mbed_official 573:ad23fe03a082 71 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 573:ad23fe03a082 72 *
mbed_official 573:ad23fe03a082 73 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 573:ad23fe03a082 74 * are permitted provided that the following conditions are met:
mbed_official 573:ad23fe03a082 75 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 573:ad23fe03a082 76 * this list of conditions and the following disclaimer.
mbed_official 573:ad23fe03a082 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 573:ad23fe03a082 78 * this list of conditions and the following disclaimer in the documentation
mbed_official 573:ad23fe03a082 79 * and/or other materials provided with the distribution.
mbed_official 573:ad23fe03a082 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 573:ad23fe03a082 81 * may be used to endorse or promote products derived from this software
mbed_official 573:ad23fe03a082 82 * without specific prior written permission.
mbed_official 573:ad23fe03a082 83 *
mbed_official 573:ad23fe03a082 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 573:ad23fe03a082 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 573:ad23fe03a082 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 573:ad23fe03a082 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 573:ad23fe03a082 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 573:ad23fe03a082 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 573:ad23fe03a082 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 573:ad23fe03a082 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 573:ad23fe03a082 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 573:ad23fe03a082 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 573:ad23fe03a082 94 *
mbed_official 573:ad23fe03a082 95 ******************************************************************************
mbed_official 573:ad23fe03a082 96 */
mbed_official 573:ad23fe03a082 97
mbed_official 573:ad23fe03a082 98 /* Includes ------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 99 #include "stm32f7xx_hal.h"
mbed_official 573:ad23fe03a082 100
mbed_official 573:ad23fe03a082 101 /** @addtogroup STM32F7xx_HAL_Driver
mbed_official 573:ad23fe03a082 102 * @{
mbed_official 573:ad23fe03a082 103 */
mbed_official 573:ad23fe03a082 104
mbed_official 573:ad23fe03a082 105 /** @defgroup ETH ETH
mbed_official 573:ad23fe03a082 106 * @brief ETH HAL module driver
mbed_official 573:ad23fe03a082 107 * @{
mbed_official 573:ad23fe03a082 108 */
mbed_official 573:ad23fe03a082 109
mbed_official 573:ad23fe03a082 110 #ifdef HAL_ETH_MODULE_ENABLED
mbed_official 573:ad23fe03a082 111
mbed_official 573:ad23fe03a082 112 /* Private typedef -----------------------------------------------------------*/
mbed_official 573:ad23fe03a082 113 /* Private define ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 114 /** @defgroup ETH_Private_Constants ETH Private Constants
mbed_official 573:ad23fe03a082 115 * @{
mbed_official 573:ad23fe03a082 116 */
mbed_official 573:ad23fe03a082 117 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
mbed_official 573:ad23fe03a082 118 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
mbed_official 573:ad23fe03a082 119
mbed_official 573:ad23fe03a082 120 /**
mbed_official 573:ad23fe03a082 121 * @}
mbed_official 573:ad23fe03a082 122 */
mbed_official 573:ad23fe03a082 123 /* Private macro -------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 124 /* Private variables ---------------------------------------------------------*/
mbed_official 573:ad23fe03a082 125 /* Private function prototypes -----------------------------------------------*/
mbed_official 573:ad23fe03a082 126 /** @defgroup ETH_Private_Functions ETH Private Functions
mbed_official 573:ad23fe03a082 127 * @{
mbed_official 573:ad23fe03a082 128 */
mbed_official 573:ad23fe03a082 129 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
mbed_official 573:ad23fe03a082 130 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
mbed_official 573:ad23fe03a082 131 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 132 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 133 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 134 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 135 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 136 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 137 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 138 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 139 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 140
mbed_official 573:ad23fe03a082 141 /**
mbed_official 573:ad23fe03a082 142 * @}
mbed_official 573:ad23fe03a082 143 */
mbed_official 573:ad23fe03a082 144 /* Private functions ---------------------------------------------------------*/
mbed_official 573:ad23fe03a082 145
mbed_official 573:ad23fe03a082 146 /** @defgroup ETH_Exported_Functions ETH Exported Functions
mbed_official 573:ad23fe03a082 147 * @{
mbed_official 573:ad23fe03a082 148 */
mbed_official 573:ad23fe03a082 149
mbed_official 573:ad23fe03a082 150 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 573:ad23fe03a082 151 * @brief Initialization and Configuration functions
mbed_official 573:ad23fe03a082 152 *
mbed_official 573:ad23fe03a082 153 @verbatim
mbed_official 573:ad23fe03a082 154 ===============================================================================
mbed_official 573:ad23fe03a082 155 ##### Initialization and de-initialization functions #####
mbed_official 573:ad23fe03a082 156 ===============================================================================
mbed_official 573:ad23fe03a082 157 [..] This section provides functions allowing to:
mbed_official 573:ad23fe03a082 158 (+) Initialize and configure the Ethernet peripheral
mbed_official 573:ad23fe03a082 159 (+) De-initialize the Ethernet peripheral
mbed_official 573:ad23fe03a082 160
mbed_official 573:ad23fe03a082 161 @endverbatim
mbed_official 573:ad23fe03a082 162 * @{
mbed_official 573:ad23fe03a082 163 */
mbed_official 573:ad23fe03a082 164
mbed_official 573:ad23fe03a082 165 /**
mbed_official 573:ad23fe03a082 166 * @brief Initializes the Ethernet MAC and DMA according to default
mbed_official 573:ad23fe03a082 167 * parameters.
mbed_official 573:ad23fe03a082 168 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 169 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 170 * @retval HAL status
mbed_official 573:ad23fe03a082 171 */
mbed_official 573:ad23fe03a082 172 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 173 {
mbed_official 573:ad23fe03a082 174 uint32_t tempreg = 0, phyreg = 0;
mbed_official 573:ad23fe03a082 175 uint32_t hclk = 60000000;
mbed_official 573:ad23fe03a082 176 uint32_t tickstart = 0;
mbed_official 573:ad23fe03a082 177 uint32_t err = ETH_SUCCESS;
mbed_official 573:ad23fe03a082 178
mbed_official 573:ad23fe03a082 179 /* Check the ETH peripheral state */
mbed_official 573:ad23fe03a082 180 if(heth == NULL)
mbed_official 573:ad23fe03a082 181 {
mbed_official 573:ad23fe03a082 182 return HAL_ERROR;
mbed_official 573:ad23fe03a082 183 }
mbed_official 573:ad23fe03a082 184
mbed_official 573:ad23fe03a082 185 /* Check parameters */
mbed_official 573:ad23fe03a082 186 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
mbed_official 573:ad23fe03a082 187 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
mbed_official 573:ad23fe03a082 188 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
mbed_official 573:ad23fe03a082 189 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
mbed_official 573:ad23fe03a082 190
mbed_official 573:ad23fe03a082 191 if(heth->State == HAL_ETH_STATE_RESET)
mbed_official 573:ad23fe03a082 192 {
mbed_official 573:ad23fe03a082 193 /* Allocate lock resource and initialize it */
mbed_official 573:ad23fe03a082 194 heth->Lock = HAL_UNLOCKED;
mbed_official 573:ad23fe03a082 195 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 573:ad23fe03a082 196 HAL_ETH_MspInit(heth);
mbed_official 573:ad23fe03a082 197 }
mbed_official 573:ad23fe03a082 198
mbed_official 573:ad23fe03a082 199 /* Enable SYSCFG Clock */
mbed_official 573:ad23fe03a082 200 __HAL_RCC_SYSCFG_CLK_ENABLE();
mbed_official 573:ad23fe03a082 201
mbed_official 573:ad23fe03a082 202 /* Select MII or RMII Mode*/
mbed_official 573:ad23fe03a082 203 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
mbed_official 573:ad23fe03a082 204 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
mbed_official 573:ad23fe03a082 205
mbed_official 573:ad23fe03a082 206 /* Ethernet Software reset */
mbed_official 573:ad23fe03a082 207 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
mbed_official 573:ad23fe03a082 208 /* After reset all the registers holds their respective reset values */
mbed_official 573:ad23fe03a082 209 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
mbed_official 573:ad23fe03a082 210
mbed_official 573:ad23fe03a082 211 /* Wait for software reset */
mbed_official 573:ad23fe03a082 212 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
mbed_official 573:ad23fe03a082 213 {
mbed_official 573:ad23fe03a082 214 }
mbed_official 573:ad23fe03a082 215
mbed_official 573:ad23fe03a082 216 /*-------------------------------- MAC Initialization ----------------------*/
mbed_official 573:ad23fe03a082 217 /* Get the ETHERNET MACMIIAR value */
mbed_official 573:ad23fe03a082 218 tempreg = (heth->Instance)->MACMIIAR;
mbed_official 573:ad23fe03a082 219 /* Clear CSR Clock Range CR[2:0] bits */
mbed_official 573:ad23fe03a082 220 tempreg &= ETH_MACMIIAR_CR_MASK;
mbed_official 573:ad23fe03a082 221
mbed_official 573:ad23fe03a082 222 /* Get hclk frequency value */
mbed_official 573:ad23fe03a082 223 hclk = HAL_RCC_GetHCLKFreq();
mbed_official 573:ad23fe03a082 224
mbed_official 573:ad23fe03a082 225 /* Set CR bits depending on hclk value */
mbed_official 573:ad23fe03a082 226 if((hclk >= 20000000)&&(hclk < 35000000))
mbed_official 573:ad23fe03a082 227 {
mbed_official 573:ad23fe03a082 228 /* CSR Clock Range between 20-35 MHz */
mbed_official 573:ad23fe03a082 229 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
mbed_official 573:ad23fe03a082 230 }
mbed_official 573:ad23fe03a082 231 else if((hclk >= 35000000)&&(hclk < 60000000))
mbed_official 573:ad23fe03a082 232 {
mbed_official 573:ad23fe03a082 233 /* CSR Clock Range between 35-60 MHz */
mbed_official 573:ad23fe03a082 234 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
mbed_official 573:ad23fe03a082 235 }
mbed_official 573:ad23fe03a082 236 else if((hclk >= 60000000)&&(hclk < 100000000))
mbed_official 573:ad23fe03a082 237 {
mbed_official 573:ad23fe03a082 238 /* CSR Clock Range between 60-100 MHz */
mbed_official 573:ad23fe03a082 239 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
mbed_official 573:ad23fe03a082 240 }
mbed_official 573:ad23fe03a082 241 else if((hclk >= 100000000)&&(hclk < 150000000))
mbed_official 573:ad23fe03a082 242 {
mbed_official 573:ad23fe03a082 243 /* CSR Clock Range between 100-150 MHz */
mbed_official 573:ad23fe03a082 244 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
mbed_official 573:ad23fe03a082 245 }
mbed_official 573:ad23fe03a082 246 else /* ((hclk >= 150000000)&&(hclk <= 200000000)) */
mbed_official 573:ad23fe03a082 247 {
mbed_official 573:ad23fe03a082 248 /* CSR Clock Range between 150-216 MHz */
mbed_official 573:ad23fe03a082 249 tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
mbed_official 573:ad23fe03a082 250 }
mbed_official 573:ad23fe03a082 251
mbed_official 573:ad23fe03a082 252 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
mbed_official 573:ad23fe03a082 253 (heth->Instance)->MACMIIAR = (uint32_t)tempreg;
mbed_official 573:ad23fe03a082 254
mbed_official 573:ad23fe03a082 255 /*-------------------- PHY initialization and configuration ----------------*/
mbed_official 573:ad23fe03a082 256 /* Put the PHY in reset mode */
mbed_official 573:ad23fe03a082 257 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
mbed_official 573:ad23fe03a082 258 {
mbed_official 573:ad23fe03a082 259 /* In case of write timeout */
mbed_official 573:ad23fe03a082 260 err = ETH_ERROR;
mbed_official 573:ad23fe03a082 261
mbed_official 573:ad23fe03a082 262 /* Config MAC and DMA */
mbed_official 573:ad23fe03a082 263 ETH_MACDMAConfig(heth, err);
mbed_official 573:ad23fe03a082 264
mbed_official 573:ad23fe03a082 265 /* Set the ETH peripheral state to READY */
mbed_official 573:ad23fe03a082 266 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 267
mbed_official 573:ad23fe03a082 268 /* Return HAL_ERROR */
mbed_official 573:ad23fe03a082 269 return HAL_ERROR;
mbed_official 573:ad23fe03a082 270 }
mbed_official 573:ad23fe03a082 271
mbed_official 573:ad23fe03a082 272 /* Delay to assure PHY reset */
mbed_official 573:ad23fe03a082 273 HAL_Delay(PHY_RESET_DELAY);
mbed_official 573:ad23fe03a082 274
mbed_official 573:ad23fe03a082 275 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
mbed_official 573:ad23fe03a082 276 {
mbed_official 573:ad23fe03a082 277 /* Get tick */
mbed_official 573:ad23fe03a082 278 tickstart = HAL_GetTick();
mbed_official 573:ad23fe03a082 279
mbed_official 573:ad23fe03a082 280 /* We wait for linked status */
mbed_official 573:ad23fe03a082 281 do
mbed_official 573:ad23fe03a082 282 {
mbed_official 573:ad23fe03a082 283 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 573:ad23fe03a082 284
mbed_official 573:ad23fe03a082 285 /* Check for the Timeout */
mbed_official 573:ad23fe03a082 286 if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
mbed_official 573:ad23fe03a082 287 {
mbed_official 573:ad23fe03a082 288 /* In case of write timeout */
mbed_official 573:ad23fe03a082 289 err = ETH_ERROR;
mbed_official 573:ad23fe03a082 290
mbed_official 573:ad23fe03a082 291 /* Config MAC and DMA */
mbed_official 573:ad23fe03a082 292 ETH_MACDMAConfig(heth, err);
mbed_official 573:ad23fe03a082 293
mbed_official 573:ad23fe03a082 294 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 295
mbed_official 573:ad23fe03a082 296 /* Process Unlocked */
mbed_official 573:ad23fe03a082 297 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 298
mbed_official 573:ad23fe03a082 299 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 300 }
mbed_official 573:ad23fe03a082 301 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
mbed_official 573:ad23fe03a082 302
mbed_official 573:ad23fe03a082 303
mbed_official 573:ad23fe03a082 304 /* Enable Auto-Negotiation */
mbed_official 573:ad23fe03a082 305 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
mbed_official 573:ad23fe03a082 306 {
mbed_official 573:ad23fe03a082 307 /* In case of write timeout */
mbed_official 573:ad23fe03a082 308 err = ETH_ERROR;
mbed_official 573:ad23fe03a082 309
mbed_official 573:ad23fe03a082 310 /* Config MAC and DMA */
mbed_official 573:ad23fe03a082 311 ETH_MACDMAConfig(heth, err);
mbed_official 573:ad23fe03a082 312
mbed_official 573:ad23fe03a082 313 /* Set the ETH peripheral state to READY */
mbed_official 573:ad23fe03a082 314 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 315
mbed_official 573:ad23fe03a082 316 /* Return HAL_ERROR */
mbed_official 573:ad23fe03a082 317 return HAL_ERROR;
mbed_official 573:ad23fe03a082 318 }
mbed_official 573:ad23fe03a082 319
mbed_official 573:ad23fe03a082 320 /* Get tick */
mbed_official 573:ad23fe03a082 321 tickstart = HAL_GetTick();
mbed_official 573:ad23fe03a082 322
mbed_official 573:ad23fe03a082 323 /* Wait until the auto-negotiation will be completed */
mbed_official 573:ad23fe03a082 324 do
mbed_official 573:ad23fe03a082 325 {
mbed_official 573:ad23fe03a082 326 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 573:ad23fe03a082 327
mbed_official 573:ad23fe03a082 328 /* Check for the Timeout */
mbed_official 573:ad23fe03a082 329 if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
mbed_official 573:ad23fe03a082 330 {
mbed_official 573:ad23fe03a082 331 /* In case of write timeout */
mbed_official 573:ad23fe03a082 332 err = ETH_ERROR;
mbed_official 573:ad23fe03a082 333
mbed_official 573:ad23fe03a082 334 /* Config MAC and DMA */
mbed_official 573:ad23fe03a082 335 ETH_MACDMAConfig(heth, err);
mbed_official 573:ad23fe03a082 336
mbed_official 573:ad23fe03a082 337 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 338
mbed_official 573:ad23fe03a082 339 /* Process Unlocked */
mbed_official 573:ad23fe03a082 340 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 341
mbed_official 573:ad23fe03a082 342 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 343 }
mbed_official 573:ad23fe03a082 344
mbed_official 573:ad23fe03a082 345 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
mbed_official 573:ad23fe03a082 346
mbed_official 573:ad23fe03a082 347 /* Read the result of the auto-negotiation */
mbed_official 573:ad23fe03a082 348 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
mbed_official 573:ad23fe03a082 349 {
mbed_official 573:ad23fe03a082 350 /* In case of write timeout */
mbed_official 573:ad23fe03a082 351 err = ETH_ERROR;
mbed_official 573:ad23fe03a082 352
mbed_official 573:ad23fe03a082 353 /* Config MAC and DMA */
mbed_official 573:ad23fe03a082 354 ETH_MACDMAConfig(heth, err);
mbed_official 573:ad23fe03a082 355
mbed_official 573:ad23fe03a082 356 /* Set the ETH peripheral state to READY */
mbed_official 573:ad23fe03a082 357 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 358
mbed_official 573:ad23fe03a082 359 /* Return HAL_ERROR */
mbed_official 573:ad23fe03a082 360 return HAL_ERROR;
mbed_official 573:ad23fe03a082 361 }
mbed_official 573:ad23fe03a082 362
mbed_official 573:ad23fe03a082 363 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
mbed_official 573:ad23fe03a082 364 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
mbed_official 573:ad23fe03a082 365 {
mbed_official 573:ad23fe03a082 366 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
mbed_official 573:ad23fe03a082 367 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 573:ad23fe03a082 368 }
mbed_official 573:ad23fe03a082 369 else
mbed_official 573:ad23fe03a082 370 {
mbed_official 573:ad23fe03a082 371 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
mbed_official 573:ad23fe03a082 372 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
mbed_official 573:ad23fe03a082 373 }
mbed_official 573:ad23fe03a082 374 /* Configure the MAC with the speed fixed by the auto-negotiation process */
mbed_official 573:ad23fe03a082 375 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
mbed_official 573:ad23fe03a082 376 {
mbed_official 573:ad23fe03a082 377 /* Set Ethernet speed to 10M following the auto-negotiation */
mbed_official 573:ad23fe03a082 378 (heth->Init).Speed = ETH_SPEED_10M;
mbed_official 573:ad23fe03a082 379 }
mbed_official 573:ad23fe03a082 380 else
mbed_official 573:ad23fe03a082 381 {
mbed_official 573:ad23fe03a082 382 /* Set Ethernet speed to 100M following the auto-negotiation */
mbed_official 573:ad23fe03a082 383 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 573:ad23fe03a082 384 }
mbed_official 573:ad23fe03a082 385 }
mbed_official 573:ad23fe03a082 386 else /* AutoNegotiation Disable */
mbed_official 573:ad23fe03a082 387 {
mbed_official 573:ad23fe03a082 388 /* Check parameters */
mbed_official 573:ad23fe03a082 389 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 573:ad23fe03a082 390 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 573:ad23fe03a082 391
mbed_official 573:ad23fe03a082 392 /* Set MAC Speed and Duplex Mode */
mbed_official 573:ad23fe03a082 393 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
mbed_official 573:ad23fe03a082 394 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
mbed_official 573:ad23fe03a082 395 {
mbed_official 573:ad23fe03a082 396 /* In case of write timeout */
mbed_official 573:ad23fe03a082 397 err = ETH_ERROR;
mbed_official 573:ad23fe03a082 398
mbed_official 573:ad23fe03a082 399 /* Config MAC and DMA */
mbed_official 573:ad23fe03a082 400 ETH_MACDMAConfig(heth, err);
mbed_official 573:ad23fe03a082 401
mbed_official 573:ad23fe03a082 402 /* Set the ETH peripheral state to READY */
mbed_official 573:ad23fe03a082 403 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 404
mbed_official 573:ad23fe03a082 405 /* Return HAL_ERROR */
mbed_official 573:ad23fe03a082 406 return HAL_ERROR;
mbed_official 573:ad23fe03a082 407 }
mbed_official 573:ad23fe03a082 408
mbed_official 573:ad23fe03a082 409 /* Delay to assure PHY configuration */
mbed_official 573:ad23fe03a082 410 HAL_Delay(PHY_CONFIG_DELAY);
mbed_official 573:ad23fe03a082 411 }
mbed_official 573:ad23fe03a082 412
mbed_official 573:ad23fe03a082 413 /* Config MAC and DMA */
mbed_official 573:ad23fe03a082 414 ETH_MACDMAConfig(heth, err);
mbed_official 573:ad23fe03a082 415
mbed_official 573:ad23fe03a082 416 /* Set ETH HAL State to Ready */
mbed_official 573:ad23fe03a082 417 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 418
mbed_official 573:ad23fe03a082 419 /* Return function status */
mbed_official 573:ad23fe03a082 420 return HAL_OK;
mbed_official 573:ad23fe03a082 421 }
mbed_official 573:ad23fe03a082 422
mbed_official 573:ad23fe03a082 423 /**
mbed_official 573:ad23fe03a082 424 * @brief De-Initializes the ETH peripheral.
mbed_official 573:ad23fe03a082 425 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 426 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 427 * @retval HAL status
mbed_official 573:ad23fe03a082 428 */
mbed_official 573:ad23fe03a082 429 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 430 {
mbed_official 573:ad23fe03a082 431 /* Set the ETH peripheral state to BUSY */
mbed_official 573:ad23fe03a082 432 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 433
mbed_official 573:ad23fe03a082 434 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 573:ad23fe03a082 435 HAL_ETH_MspDeInit(heth);
mbed_official 573:ad23fe03a082 436
mbed_official 573:ad23fe03a082 437 /* Set ETH HAL state to Disabled */
mbed_official 573:ad23fe03a082 438 heth->State= HAL_ETH_STATE_RESET;
mbed_official 573:ad23fe03a082 439
mbed_official 573:ad23fe03a082 440 /* Release Lock */
mbed_official 573:ad23fe03a082 441 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 442
mbed_official 573:ad23fe03a082 443 /* Return function status */
mbed_official 573:ad23fe03a082 444 return HAL_OK;
mbed_official 573:ad23fe03a082 445 }
mbed_official 573:ad23fe03a082 446
mbed_official 573:ad23fe03a082 447 /**
mbed_official 573:ad23fe03a082 448 * @brief Initializes the DMA Tx descriptors in chain mode.
mbed_official 573:ad23fe03a082 449 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 450 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 451 * @param DMATxDescTab: Pointer to the first Tx desc list
mbed_official 573:ad23fe03a082 452 * @param TxBuff: Pointer to the first TxBuffer list
mbed_official 573:ad23fe03a082 453 * @param TxBuffCount: Number of the used Tx desc in the list
mbed_official 573:ad23fe03a082 454 * @retval HAL status
mbed_official 573:ad23fe03a082 455 */
mbed_official 573:ad23fe03a082 456 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
mbed_official 573:ad23fe03a082 457 {
mbed_official 573:ad23fe03a082 458 uint32_t i = 0;
mbed_official 573:ad23fe03a082 459 ETH_DMADescTypeDef *dmatxdesc;
mbed_official 573:ad23fe03a082 460
mbed_official 573:ad23fe03a082 461 /* Process Locked */
mbed_official 573:ad23fe03a082 462 __HAL_LOCK(heth);
mbed_official 573:ad23fe03a082 463
mbed_official 573:ad23fe03a082 464 /* Set the ETH peripheral state to BUSY */
mbed_official 573:ad23fe03a082 465 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 466
mbed_official 573:ad23fe03a082 467 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
mbed_official 573:ad23fe03a082 468 heth->TxDesc = DMATxDescTab;
mbed_official 573:ad23fe03a082 469
mbed_official 573:ad23fe03a082 470 /* Fill each DMATxDesc descriptor with the right values */
mbed_official 573:ad23fe03a082 471 for(i=0; i < TxBuffCount; i++)
mbed_official 573:ad23fe03a082 472 {
mbed_official 573:ad23fe03a082 473 /* Get the pointer on the ith member of the Tx Desc list */
mbed_official 573:ad23fe03a082 474 dmatxdesc = DMATxDescTab + i;
mbed_official 573:ad23fe03a082 475
mbed_official 573:ad23fe03a082 476 /* Set Second Address Chained bit */
mbed_official 573:ad23fe03a082 477 dmatxdesc->Status = ETH_DMATXDESC_TCH;
mbed_official 573:ad23fe03a082 478
mbed_official 573:ad23fe03a082 479 /* Set Buffer1 address pointer */
mbed_official 573:ad23fe03a082 480 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
mbed_official 573:ad23fe03a082 481
mbed_official 573:ad23fe03a082 482 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 573:ad23fe03a082 483 {
mbed_official 573:ad23fe03a082 484 /* Set the DMA Tx descriptors checksum insertion */
mbed_official 573:ad23fe03a082 485 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
mbed_official 573:ad23fe03a082 486 }
mbed_official 573:ad23fe03a082 487
mbed_official 573:ad23fe03a082 488 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 573:ad23fe03a082 489 if(i < (TxBuffCount-1))
mbed_official 573:ad23fe03a082 490 {
mbed_official 573:ad23fe03a082 491 /* Set next descriptor address register with next descriptor base address */
mbed_official 573:ad23fe03a082 492 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
mbed_official 573:ad23fe03a082 493 }
mbed_official 573:ad23fe03a082 494 else
mbed_official 573:ad23fe03a082 495 {
mbed_official 573:ad23fe03a082 496 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 573:ad23fe03a082 497 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
mbed_official 573:ad23fe03a082 498 }
mbed_official 573:ad23fe03a082 499 }
mbed_official 573:ad23fe03a082 500
mbed_official 573:ad23fe03a082 501 /* Set Transmit Descriptor List Address Register */
mbed_official 573:ad23fe03a082 502 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
mbed_official 573:ad23fe03a082 503
mbed_official 573:ad23fe03a082 504 /* Set ETH HAL State to Ready */
mbed_official 573:ad23fe03a082 505 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 506
mbed_official 573:ad23fe03a082 507 /* Process Unlocked */
mbed_official 573:ad23fe03a082 508 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 509
mbed_official 573:ad23fe03a082 510 /* Return function status */
mbed_official 573:ad23fe03a082 511 return HAL_OK;
mbed_official 573:ad23fe03a082 512 }
mbed_official 573:ad23fe03a082 513
mbed_official 573:ad23fe03a082 514 /**
mbed_official 573:ad23fe03a082 515 * @brief Initializes the DMA Rx descriptors in chain mode.
mbed_official 573:ad23fe03a082 516 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 517 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 518 * @param DMARxDescTab: Pointer to the first Rx desc list
mbed_official 573:ad23fe03a082 519 * @param RxBuff: Pointer to the first RxBuffer list
mbed_official 573:ad23fe03a082 520 * @param RxBuffCount: Number of the used Rx desc in the list
mbed_official 573:ad23fe03a082 521 * @retval HAL status
mbed_official 573:ad23fe03a082 522 */
mbed_official 573:ad23fe03a082 523 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
mbed_official 573:ad23fe03a082 524 {
mbed_official 573:ad23fe03a082 525 uint32_t i = 0;
mbed_official 573:ad23fe03a082 526 ETH_DMADescTypeDef *DMARxDesc;
mbed_official 573:ad23fe03a082 527
mbed_official 573:ad23fe03a082 528 /* Process Locked */
mbed_official 573:ad23fe03a082 529 __HAL_LOCK(heth);
mbed_official 573:ad23fe03a082 530
mbed_official 573:ad23fe03a082 531 /* Set the ETH peripheral state to BUSY */
mbed_official 573:ad23fe03a082 532 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 533
mbed_official 573:ad23fe03a082 534 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
mbed_official 573:ad23fe03a082 535 heth->RxDesc = DMARxDescTab;
mbed_official 573:ad23fe03a082 536
mbed_official 573:ad23fe03a082 537 /* Fill each DMARxDesc descriptor with the right values */
mbed_official 573:ad23fe03a082 538 for(i=0; i < RxBuffCount; i++)
mbed_official 573:ad23fe03a082 539 {
mbed_official 573:ad23fe03a082 540 /* Get the pointer on the ith member of the Rx Desc list */
mbed_official 573:ad23fe03a082 541 DMARxDesc = DMARxDescTab+i;
mbed_official 573:ad23fe03a082 542
mbed_official 573:ad23fe03a082 543 /* Set Own bit of the Rx descriptor Status */
mbed_official 573:ad23fe03a082 544 DMARxDesc->Status = ETH_DMARXDESC_OWN;
mbed_official 573:ad23fe03a082 545
mbed_official 573:ad23fe03a082 546 /* Set Buffer1 size and Second Address Chained bit */
mbed_official 573:ad23fe03a082 547 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
mbed_official 573:ad23fe03a082 548
mbed_official 573:ad23fe03a082 549 /* Set Buffer1 address pointer */
mbed_official 573:ad23fe03a082 550 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
mbed_official 573:ad23fe03a082 551
mbed_official 573:ad23fe03a082 552 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 573:ad23fe03a082 553 {
mbed_official 573:ad23fe03a082 554 /* Enable Ethernet DMA Rx Descriptor interrupt */
mbed_official 573:ad23fe03a082 555 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
mbed_official 573:ad23fe03a082 556 }
mbed_official 573:ad23fe03a082 557
mbed_official 573:ad23fe03a082 558 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 573:ad23fe03a082 559 if(i < (RxBuffCount-1))
mbed_official 573:ad23fe03a082 560 {
mbed_official 573:ad23fe03a082 561 /* Set next descriptor address register with next descriptor base address */
mbed_official 573:ad23fe03a082 562 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
mbed_official 573:ad23fe03a082 563 }
mbed_official 573:ad23fe03a082 564 else
mbed_official 573:ad23fe03a082 565 {
mbed_official 573:ad23fe03a082 566 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 573:ad23fe03a082 567 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
mbed_official 573:ad23fe03a082 568 }
mbed_official 573:ad23fe03a082 569 }
mbed_official 573:ad23fe03a082 570
mbed_official 573:ad23fe03a082 571 /* Set Receive Descriptor List Address Register */
mbed_official 573:ad23fe03a082 572 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
mbed_official 573:ad23fe03a082 573
mbed_official 573:ad23fe03a082 574 /* Set ETH HAL State to Ready */
mbed_official 573:ad23fe03a082 575 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 576
mbed_official 573:ad23fe03a082 577 /* Process Unlocked */
mbed_official 573:ad23fe03a082 578 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 579
mbed_official 573:ad23fe03a082 580 /* Return function status */
mbed_official 573:ad23fe03a082 581 return HAL_OK;
mbed_official 573:ad23fe03a082 582 }
mbed_official 573:ad23fe03a082 583
mbed_official 573:ad23fe03a082 584 /**
mbed_official 573:ad23fe03a082 585 * @brief Initializes the ETH MSP.
mbed_official 573:ad23fe03a082 586 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 587 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 588 * @retval None
mbed_official 573:ad23fe03a082 589 */
mbed_official 573:ad23fe03a082 590 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 591 {
mbed_official 573:ad23fe03a082 592 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 593 the HAL_ETH_MspInit could be implemented in the user file
mbed_official 573:ad23fe03a082 594 */
mbed_official 573:ad23fe03a082 595 }
mbed_official 573:ad23fe03a082 596
mbed_official 573:ad23fe03a082 597 /**
mbed_official 573:ad23fe03a082 598 * @brief DeInitializes ETH MSP.
mbed_official 573:ad23fe03a082 599 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 600 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 601 * @retval None
mbed_official 573:ad23fe03a082 602 */
mbed_official 573:ad23fe03a082 603 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 604 {
mbed_official 573:ad23fe03a082 605 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 606 the HAL_ETH_MspDeInit could be implemented in the user file
mbed_official 573:ad23fe03a082 607 */
mbed_official 573:ad23fe03a082 608 }
mbed_official 573:ad23fe03a082 609
mbed_official 573:ad23fe03a082 610 /**
mbed_official 573:ad23fe03a082 611 * @}
mbed_official 573:ad23fe03a082 612 */
mbed_official 573:ad23fe03a082 613
mbed_official 573:ad23fe03a082 614 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
mbed_official 573:ad23fe03a082 615 * @brief Data transfers functions
mbed_official 573:ad23fe03a082 616 *
mbed_official 573:ad23fe03a082 617 @verbatim
mbed_official 573:ad23fe03a082 618 ==============================================================================
mbed_official 573:ad23fe03a082 619 ##### IO operation functions #####
mbed_official 573:ad23fe03a082 620 ==============================================================================
mbed_official 573:ad23fe03a082 621 [..] This section provides functions allowing to:
mbed_official 573:ad23fe03a082 622 (+) Transmit a frame
mbed_official 573:ad23fe03a082 623 HAL_ETH_TransmitFrame();
mbed_official 573:ad23fe03a082 624 (+) Receive a frame
mbed_official 573:ad23fe03a082 625 HAL_ETH_GetReceivedFrame();
mbed_official 573:ad23fe03a082 626 HAL_ETH_GetReceivedFrame_IT();
mbed_official 573:ad23fe03a082 627 (+) Read from an External PHY register
mbed_official 573:ad23fe03a082 628 HAL_ETH_ReadPHYRegister();
mbed_official 573:ad23fe03a082 629 (+) Write to an External PHY register
mbed_official 573:ad23fe03a082 630 HAL_ETH_WritePHYRegister();
mbed_official 573:ad23fe03a082 631
mbed_official 573:ad23fe03a082 632 @endverbatim
mbed_official 573:ad23fe03a082 633
mbed_official 573:ad23fe03a082 634 * @{
mbed_official 573:ad23fe03a082 635 */
mbed_official 573:ad23fe03a082 636
mbed_official 573:ad23fe03a082 637 /**
mbed_official 573:ad23fe03a082 638 * @brief Sends an Ethernet frame.
mbed_official 573:ad23fe03a082 639 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 640 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 641 * @param FrameLength: Amount of data to be sent
mbed_official 573:ad23fe03a082 642 * @retval HAL status
mbed_official 573:ad23fe03a082 643 */
mbed_official 573:ad23fe03a082 644 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
mbed_official 573:ad23fe03a082 645 {
mbed_official 573:ad23fe03a082 646 uint32_t bufcount = 0, size = 0, i = 0;
mbed_official 573:ad23fe03a082 647
mbed_official 573:ad23fe03a082 648 /* Process Locked */
mbed_official 573:ad23fe03a082 649 __HAL_LOCK(heth);
mbed_official 573:ad23fe03a082 650
mbed_official 573:ad23fe03a082 651 /* Set the ETH peripheral state to BUSY */
mbed_official 573:ad23fe03a082 652 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 653
mbed_official 573:ad23fe03a082 654 if (FrameLength == 0)
mbed_official 573:ad23fe03a082 655 {
mbed_official 573:ad23fe03a082 656 /* Set ETH HAL state to READY */
mbed_official 573:ad23fe03a082 657 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 658
mbed_official 573:ad23fe03a082 659 /* Process Unlocked */
mbed_official 573:ad23fe03a082 660 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 661
mbed_official 573:ad23fe03a082 662 return HAL_ERROR;
mbed_official 573:ad23fe03a082 663 }
mbed_official 573:ad23fe03a082 664
mbed_official 573:ad23fe03a082 665 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
mbed_official 573:ad23fe03a082 666 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
mbed_official 573:ad23fe03a082 667 {
mbed_official 573:ad23fe03a082 668 /* OWN bit set */
mbed_official 573:ad23fe03a082 669 heth->State = HAL_ETH_STATE_BUSY_TX;
mbed_official 573:ad23fe03a082 670
mbed_official 573:ad23fe03a082 671 /* Process Unlocked */
mbed_official 573:ad23fe03a082 672 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 673
mbed_official 573:ad23fe03a082 674 return HAL_ERROR;
mbed_official 573:ad23fe03a082 675 }
mbed_official 573:ad23fe03a082 676
mbed_official 573:ad23fe03a082 677 /* Get the number of needed Tx buffers for the current frame */
mbed_official 573:ad23fe03a082 678 if (FrameLength > ETH_TX_BUF_SIZE)
mbed_official 573:ad23fe03a082 679 {
mbed_official 573:ad23fe03a082 680 bufcount = FrameLength/ETH_TX_BUF_SIZE;
mbed_official 573:ad23fe03a082 681 if (FrameLength % ETH_TX_BUF_SIZE)
mbed_official 573:ad23fe03a082 682 {
mbed_official 573:ad23fe03a082 683 bufcount++;
mbed_official 573:ad23fe03a082 684 }
mbed_official 573:ad23fe03a082 685 }
mbed_official 573:ad23fe03a082 686 else
mbed_official 573:ad23fe03a082 687 {
mbed_official 573:ad23fe03a082 688 bufcount = 1;
mbed_official 573:ad23fe03a082 689 }
mbed_official 573:ad23fe03a082 690 if (bufcount == 1)
mbed_official 573:ad23fe03a082 691 {
mbed_official 573:ad23fe03a082 692 /* Set LAST and FIRST segment */
mbed_official 573:ad23fe03a082 693 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
mbed_official 573:ad23fe03a082 694 /* Set frame size */
mbed_official 573:ad23fe03a082 695 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
mbed_official 573:ad23fe03a082 696 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 573:ad23fe03a082 697 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 573:ad23fe03a082 698 /* Point to next descriptor */
mbed_official 573:ad23fe03a082 699 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 573:ad23fe03a082 700 }
mbed_official 573:ad23fe03a082 701 else
mbed_official 573:ad23fe03a082 702 {
mbed_official 573:ad23fe03a082 703 for (i=0; i< bufcount; i++)
mbed_official 573:ad23fe03a082 704 {
mbed_official 573:ad23fe03a082 705 /* Clear FIRST and LAST segment bits */
mbed_official 573:ad23fe03a082 706 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
mbed_official 573:ad23fe03a082 707
mbed_official 573:ad23fe03a082 708 if (i == 0)
mbed_official 573:ad23fe03a082 709 {
mbed_official 573:ad23fe03a082 710 /* Setting the first segment bit */
mbed_official 573:ad23fe03a082 711 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
mbed_official 573:ad23fe03a082 712 }
mbed_official 573:ad23fe03a082 713
mbed_official 573:ad23fe03a082 714 /* Program size */
mbed_official 573:ad23fe03a082 715 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
mbed_official 573:ad23fe03a082 716
mbed_official 573:ad23fe03a082 717 if (i == (bufcount-1))
mbed_official 573:ad23fe03a082 718 {
mbed_official 573:ad23fe03a082 719 /* Setting the last segment bit */
mbed_official 573:ad23fe03a082 720 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
mbed_official 573:ad23fe03a082 721 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
mbed_official 573:ad23fe03a082 722 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
mbed_official 573:ad23fe03a082 723 }
mbed_official 573:ad23fe03a082 724
mbed_official 573:ad23fe03a082 725 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 573:ad23fe03a082 726 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 573:ad23fe03a082 727 /* point to next descriptor */
mbed_official 573:ad23fe03a082 728 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 573:ad23fe03a082 729 }
mbed_official 573:ad23fe03a082 730 }
mbed_official 573:ad23fe03a082 731
mbed_official 573:ad23fe03a082 732 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
mbed_official 573:ad23fe03a082 733 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
mbed_official 573:ad23fe03a082 734 {
mbed_official 573:ad23fe03a082 735 /* Clear TBUS ETHERNET DMA flag */
mbed_official 573:ad23fe03a082 736 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
mbed_official 573:ad23fe03a082 737 /* Resume DMA transmission*/
mbed_official 573:ad23fe03a082 738 (heth->Instance)->DMATPDR = 0;
mbed_official 573:ad23fe03a082 739 }
mbed_official 573:ad23fe03a082 740
mbed_official 573:ad23fe03a082 741 /* Set ETH HAL State to Ready */
mbed_official 573:ad23fe03a082 742 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 743
mbed_official 573:ad23fe03a082 744 /* Process Unlocked */
mbed_official 573:ad23fe03a082 745 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 746
mbed_official 573:ad23fe03a082 747 /* Return function status */
mbed_official 573:ad23fe03a082 748 return HAL_OK;
mbed_official 573:ad23fe03a082 749 }
mbed_official 573:ad23fe03a082 750
mbed_official 573:ad23fe03a082 751 /**
mbed_official 573:ad23fe03a082 752 * @brief Checks for received frames.
mbed_official 573:ad23fe03a082 753 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 754 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 755 * @retval HAL status
mbed_official 573:ad23fe03a082 756 */
mbed_official 573:ad23fe03a082 757 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 758 {
mbed_official 573:ad23fe03a082 759 uint32_t framelength = 0;
mbed_official 573:ad23fe03a082 760
mbed_official 573:ad23fe03a082 761 /* Process Locked */
mbed_official 573:ad23fe03a082 762 __HAL_LOCK(heth);
mbed_official 573:ad23fe03a082 763
mbed_official 573:ad23fe03a082 764 /* Check the ETH state to BUSY */
mbed_official 573:ad23fe03a082 765 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 766
mbed_official 573:ad23fe03a082 767 /* Check if segment is not owned by DMA */
mbed_official 573:ad23fe03a082 768 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
mbed_official 573:ad23fe03a082 769 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
mbed_official 573:ad23fe03a082 770 {
mbed_official 573:ad23fe03a082 771 /* Check if last segment */
mbed_official 573:ad23fe03a082 772 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
mbed_official 573:ad23fe03a082 773 {
mbed_official 573:ad23fe03a082 774 /* increment segment count */
mbed_official 573:ad23fe03a082 775 (heth->RxFrameInfos).SegCount++;
mbed_official 573:ad23fe03a082 776
mbed_official 573:ad23fe03a082 777 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 573:ad23fe03a082 778 if ((heth->RxFrameInfos).SegCount == 1)
mbed_official 573:ad23fe03a082 779 {
mbed_official 573:ad23fe03a082 780 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
mbed_official 573:ad23fe03a082 781 }
mbed_official 573:ad23fe03a082 782
mbed_official 573:ad23fe03a082 783 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 573:ad23fe03a082 784
mbed_official 573:ad23fe03a082 785 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 573:ad23fe03a082 786 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 573:ad23fe03a082 787 heth->RxFrameInfos.length = framelength;
mbed_official 573:ad23fe03a082 788
mbed_official 573:ad23fe03a082 789 /* Get the address of the buffer start address */
mbed_official 573:ad23fe03a082 790 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 573:ad23fe03a082 791 /* point to next descriptor */
mbed_official 573:ad23fe03a082 792 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
mbed_official 573:ad23fe03a082 793
mbed_official 573:ad23fe03a082 794 /* Set HAL State to Ready */
mbed_official 573:ad23fe03a082 795 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 796
mbed_official 573:ad23fe03a082 797 /* Process Unlocked */
mbed_official 573:ad23fe03a082 798 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 799
mbed_official 573:ad23fe03a082 800 /* Return function status */
mbed_official 573:ad23fe03a082 801 return HAL_OK;
mbed_official 573:ad23fe03a082 802 }
mbed_official 573:ad23fe03a082 803 /* Check if first segment */
mbed_official 573:ad23fe03a082 804 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
mbed_official 573:ad23fe03a082 805 {
mbed_official 573:ad23fe03a082 806 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
mbed_official 573:ad23fe03a082 807 (heth->RxFrameInfos).LSRxDesc = NULL;
mbed_official 573:ad23fe03a082 808 (heth->RxFrameInfos).SegCount = 1;
mbed_official 573:ad23fe03a082 809 /* Point to next descriptor */
mbed_official 573:ad23fe03a082 810 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 573:ad23fe03a082 811 }
mbed_official 573:ad23fe03a082 812 /* Check if intermediate segment */
mbed_official 573:ad23fe03a082 813 else
mbed_official 573:ad23fe03a082 814 {
mbed_official 573:ad23fe03a082 815 (heth->RxFrameInfos).SegCount++;
mbed_official 573:ad23fe03a082 816 /* Point to next descriptor */
mbed_official 573:ad23fe03a082 817 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 573:ad23fe03a082 818 }
mbed_official 573:ad23fe03a082 819 }
mbed_official 573:ad23fe03a082 820
mbed_official 573:ad23fe03a082 821 /* Set ETH HAL State to Ready */
mbed_official 573:ad23fe03a082 822 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 823
mbed_official 573:ad23fe03a082 824 /* Process Unlocked */
mbed_official 573:ad23fe03a082 825 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 826
mbed_official 573:ad23fe03a082 827 /* Return function status */
mbed_official 573:ad23fe03a082 828 return HAL_ERROR;
mbed_official 573:ad23fe03a082 829 }
mbed_official 573:ad23fe03a082 830
mbed_official 573:ad23fe03a082 831 /**
mbed_official 573:ad23fe03a082 832 * @brief Gets the Received frame in interrupt mode.
mbed_official 573:ad23fe03a082 833 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 834 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 835 * @retval HAL status
mbed_official 573:ad23fe03a082 836 */
mbed_official 573:ad23fe03a082 837 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 838 {
mbed_official 573:ad23fe03a082 839 uint32_t descriptorscancounter = 0;
mbed_official 573:ad23fe03a082 840
mbed_official 573:ad23fe03a082 841 /* Process Locked */
mbed_official 573:ad23fe03a082 842 __HAL_LOCK(heth);
mbed_official 573:ad23fe03a082 843
mbed_official 573:ad23fe03a082 844 /* Set ETH HAL State to BUSY */
mbed_official 573:ad23fe03a082 845 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 846
mbed_official 573:ad23fe03a082 847 /* Scan descriptors owned by CPU */
mbed_official 573:ad23fe03a082 848 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
mbed_official 573:ad23fe03a082 849 {
mbed_official 573:ad23fe03a082 850 /* Just for security */
mbed_official 573:ad23fe03a082 851 descriptorscancounter++;
mbed_official 573:ad23fe03a082 852
mbed_official 573:ad23fe03a082 853 /* Check if first segment in frame */
mbed_official 573:ad23fe03a082 854 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
mbed_official 573:ad23fe03a082 855 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
mbed_official 573:ad23fe03a082 856 {
mbed_official 573:ad23fe03a082 857 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 573:ad23fe03a082 858 heth->RxFrameInfos.SegCount = 1;
mbed_official 573:ad23fe03a082 859 /* Point to next descriptor */
mbed_official 573:ad23fe03a082 860 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 573:ad23fe03a082 861 }
mbed_official 573:ad23fe03a082 862 /* Check if intermediate segment */
mbed_official 573:ad23fe03a082 863 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
mbed_official 573:ad23fe03a082 864 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
mbed_official 573:ad23fe03a082 865 {
mbed_official 573:ad23fe03a082 866 /* Increment segment count */
mbed_official 573:ad23fe03a082 867 (heth->RxFrameInfos.SegCount)++;
mbed_official 573:ad23fe03a082 868 /* Point to next descriptor */
mbed_official 573:ad23fe03a082 869 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
mbed_official 573:ad23fe03a082 870 }
mbed_official 573:ad23fe03a082 871 /* Should be last segment */
mbed_official 573:ad23fe03a082 872 else
mbed_official 573:ad23fe03a082 873 {
mbed_official 573:ad23fe03a082 874 /* Last segment */
mbed_official 573:ad23fe03a082 875 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 573:ad23fe03a082 876
mbed_official 573:ad23fe03a082 877 /* Increment segment count */
mbed_official 573:ad23fe03a082 878 (heth->RxFrameInfos.SegCount)++;
mbed_official 573:ad23fe03a082 879
mbed_official 573:ad23fe03a082 880 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 573:ad23fe03a082 881 if ((heth->RxFrameInfos.SegCount) == 1)
mbed_official 573:ad23fe03a082 882 {
mbed_official 573:ad23fe03a082 883 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 573:ad23fe03a082 884 }
mbed_official 573:ad23fe03a082 885
mbed_official 573:ad23fe03a082 886 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 573:ad23fe03a082 887 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 573:ad23fe03a082 888
mbed_official 573:ad23fe03a082 889 /* Get the address of the buffer start address */
mbed_official 573:ad23fe03a082 890 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 573:ad23fe03a082 891
mbed_official 573:ad23fe03a082 892 /* Point to next descriptor */
mbed_official 573:ad23fe03a082 893 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 573:ad23fe03a082 894
mbed_official 573:ad23fe03a082 895 /* Set HAL State to Ready */
mbed_official 573:ad23fe03a082 896 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 897
mbed_official 573:ad23fe03a082 898 /* Process Unlocked */
mbed_official 573:ad23fe03a082 899 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 900
mbed_official 573:ad23fe03a082 901 /* Return function status */
mbed_official 573:ad23fe03a082 902 return HAL_OK;
mbed_official 573:ad23fe03a082 903 }
mbed_official 573:ad23fe03a082 904 }
mbed_official 573:ad23fe03a082 905
mbed_official 573:ad23fe03a082 906 /* Set HAL State to Ready */
mbed_official 573:ad23fe03a082 907 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 908
mbed_official 573:ad23fe03a082 909 /* Process Unlocked */
mbed_official 573:ad23fe03a082 910 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 911
mbed_official 573:ad23fe03a082 912 /* Return function status */
mbed_official 573:ad23fe03a082 913 return HAL_ERROR;
mbed_official 573:ad23fe03a082 914 }
mbed_official 573:ad23fe03a082 915
mbed_official 573:ad23fe03a082 916 /**
mbed_official 573:ad23fe03a082 917 * @brief This function handles ETH interrupt request.
mbed_official 573:ad23fe03a082 918 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 919 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 920 * @retval HAL status
mbed_official 573:ad23fe03a082 921 */
mbed_official 573:ad23fe03a082 922 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 923 {
mbed_official 573:ad23fe03a082 924 /* Frame received */
mbed_official 573:ad23fe03a082 925 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
mbed_official 573:ad23fe03a082 926 {
mbed_official 573:ad23fe03a082 927 /* Receive complete callback */
mbed_official 573:ad23fe03a082 928 HAL_ETH_RxCpltCallback(heth);
mbed_official 573:ad23fe03a082 929
mbed_official 573:ad23fe03a082 930 /* Clear the Eth DMA Rx IT pending bits */
mbed_official 573:ad23fe03a082 931 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
mbed_official 573:ad23fe03a082 932
mbed_official 573:ad23fe03a082 933 /* Set HAL State to Ready */
mbed_official 573:ad23fe03a082 934 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 935
mbed_official 573:ad23fe03a082 936 /* Process Unlocked */
mbed_official 573:ad23fe03a082 937 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 938
mbed_official 573:ad23fe03a082 939 }
mbed_official 573:ad23fe03a082 940 /* Frame transmitted */
mbed_official 573:ad23fe03a082 941 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
mbed_official 573:ad23fe03a082 942 {
mbed_official 573:ad23fe03a082 943 /* Transfer complete callback */
mbed_official 573:ad23fe03a082 944 HAL_ETH_TxCpltCallback(heth);
mbed_official 573:ad23fe03a082 945
mbed_official 573:ad23fe03a082 946 /* Clear the Eth DMA Tx IT pending bits */
mbed_official 573:ad23fe03a082 947 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
mbed_official 573:ad23fe03a082 948
mbed_official 573:ad23fe03a082 949 /* Set HAL State to Ready */
mbed_official 573:ad23fe03a082 950 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 951
mbed_official 573:ad23fe03a082 952 /* Process Unlocked */
mbed_official 573:ad23fe03a082 953 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 954 }
mbed_official 573:ad23fe03a082 955
mbed_official 573:ad23fe03a082 956 /* Clear the interrupt flags */
mbed_official 573:ad23fe03a082 957 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
mbed_official 573:ad23fe03a082 958
mbed_official 573:ad23fe03a082 959 /* ETH DMA Error */
mbed_official 573:ad23fe03a082 960 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
mbed_official 573:ad23fe03a082 961 {
mbed_official 573:ad23fe03a082 962 /* Ethernet Error callback */
mbed_official 573:ad23fe03a082 963 HAL_ETH_ErrorCallback(heth);
mbed_official 573:ad23fe03a082 964
mbed_official 573:ad23fe03a082 965 /* Clear the interrupt flags */
mbed_official 573:ad23fe03a082 966 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
mbed_official 573:ad23fe03a082 967
mbed_official 573:ad23fe03a082 968 /* Set HAL State to Ready */
mbed_official 573:ad23fe03a082 969 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 970
mbed_official 573:ad23fe03a082 971 /* Process Unlocked */
mbed_official 573:ad23fe03a082 972 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 973 }
mbed_official 573:ad23fe03a082 974 }
mbed_official 573:ad23fe03a082 975
mbed_official 573:ad23fe03a082 976 /**
mbed_official 573:ad23fe03a082 977 * @brief Tx Transfer completed callbacks.
mbed_official 573:ad23fe03a082 978 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 979 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 980 * @retval None
mbed_official 573:ad23fe03a082 981 */
mbed_official 573:ad23fe03a082 982 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 983 {
mbed_official 573:ad23fe03a082 984 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 985 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 573:ad23fe03a082 986 */
mbed_official 573:ad23fe03a082 987 }
mbed_official 573:ad23fe03a082 988
mbed_official 573:ad23fe03a082 989 /**
mbed_official 573:ad23fe03a082 990 * @brief Rx Transfer completed callbacks.
mbed_official 573:ad23fe03a082 991 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 992 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 993 * @retval None
mbed_official 573:ad23fe03a082 994 */
mbed_official 573:ad23fe03a082 995 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 996 {
mbed_official 573:ad23fe03a082 997 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 998 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 573:ad23fe03a082 999 */
mbed_official 573:ad23fe03a082 1000 }
mbed_official 573:ad23fe03a082 1001
mbed_official 573:ad23fe03a082 1002 /**
mbed_official 573:ad23fe03a082 1003 * @brief Ethernet transfer error callbacks
mbed_official 573:ad23fe03a082 1004 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1005 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1006 * @retval None
mbed_official 573:ad23fe03a082 1007 */
mbed_official 573:ad23fe03a082 1008 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1009 {
mbed_official 573:ad23fe03a082 1010 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 1011 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 573:ad23fe03a082 1012 */
mbed_official 573:ad23fe03a082 1013 }
mbed_official 573:ad23fe03a082 1014
mbed_official 573:ad23fe03a082 1015 /**
mbed_official 573:ad23fe03a082 1016 * @brief Reads a PHY register
mbed_official 573:ad23fe03a082 1017 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1018 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1019 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 573:ad23fe03a082 1020 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 1021 * PHY_BCR: Transceiver Basic Control Register,
mbed_official 573:ad23fe03a082 1022 * PHY_BSR: Transceiver Basic Status Register.
mbed_official 573:ad23fe03a082 1023 * More PHY register could be read depending on the used PHY
mbed_official 573:ad23fe03a082 1024 * @param RegValue: PHY register value
mbed_official 573:ad23fe03a082 1025 * @retval HAL status
mbed_official 573:ad23fe03a082 1026 */
mbed_official 573:ad23fe03a082 1027 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
mbed_official 573:ad23fe03a082 1028 {
mbed_official 573:ad23fe03a082 1029 uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1030 uint32_t tickstart = 0;
mbed_official 573:ad23fe03a082 1031
mbed_official 573:ad23fe03a082 1032 /* Check parameters */
mbed_official 573:ad23fe03a082 1033 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 573:ad23fe03a082 1034
mbed_official 573:ad23fe03a082 1035 /* Check the ETH peripheral state */
mbed_official 573:ad23fe03a082 1036 if(heth->State == HAL_ETH_STATE_BUSY_RD)
mbed_official 573:ad23fe03a082 1037 {
mbed_official 573:ad23fe03a082 1038 return HAL_BUSY;
mbed_official 573:ad23fe03a082 1039 }
mbed_official 573:ad23fe03a082 1040 /* Set ETH HAL State to BUSY_RD */
mbed_official 573:ad23fe03a082 1041 heth->State = HAL_ETH_STATE_BUSY_RD;
mbed_official 573:ad23fe03a082 1042
mbed_official 573:ad23fe03a082 1043 /* Get the ETHERNET MACMIIAR value */
mbed_official 573:ad23fe03a082 1044 tmpreg = heth->Instance->MACMIIAR;
mbed_official 573:ad23fe03a082 1045
mbed_official 573:ad23fe03a082 1046 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 573:ad23fe03a082 1047 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
mbed_official 573:ad23fe03a082 1048
mbed_official 573:ad23fe03a082 1049 /* Prepare the MII address register value */
mbed_official 573:ad23fe03a082 1050 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 573:ad23fe03a082 1051 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 573:ad23fe03a082 1052 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
mbed_official 573:ad23fe03a082 1053 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 573:ad23fe03a082 1054
mbed_official 573:ad23fe03a082 1055 /* Write the result value into the MII Address register */
mbed_official 573:ad23fe03a082 1056 heth->Instance->MACMIIAR = tmpreg;
mbed_official 573:ad23fe03a082 1057
mbed_official 573:ad23fe03a082 1058 /* Get tick */
mbed_official 573:ad23fe03a082 1059 tickstart = HAL_GetTick();
mbed_official 573:ad23fe03a082 1060
mbed_official 573:ad23fe03a082 1061 /* Check for the Busy flag */
mbed_official 573:ad23fe03a082 1062 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 573:ad23fe03a082 1063 {
mbed_official 573:ad23fe03a082 1064 /* Check for the Timeout */
mbed_official 573:ad23fe03a082 1065 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
mbed_official 573:ad23fe03a082 1066 {
mbed_official 573:ad23fe03a082 1067 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 1068
mbed_official 573:ad23fe03a082 1069 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1070 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 1071
mbed_official 573:ad23fe03a082 1072 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 1073 }
mbed_official 573:ad23fe03a082 1074
mbed_official 573:ad23fe03a082 1075 tmpreg = heth->Instance->MACMIIAR;
mbed_official 573:ad23fe03a082 1076 }
mbed_official 573:ad23fe03a082 1077
mbed_official 573:ad23fe03a082 1078 /* Get MACMIIDR value */
mbed_official 573:ad23fe03a082 1079 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
mbed_official 573:ad23fe03a082 1080
mbed_official 573:ad23fe03a082 1081 /* Set ETH HAL State to READY */
mbed_official 573:ad23fe03a082 1082 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 1083
mbed_official 573:ad23fe03a082 1084 /* Return function status */
mbed_official 573:ad23fe03a082 1085 return HAL_OK;
mbed_official 573:ad23fe03a082 1086 }
mbed_official 573:ad23fe03a082 1087
mbed_official 573:ad23fe03a082 1088 /**
mbed_official 573:ad23fe03a082 1089 * @brief Writes to a PHY register.
mbed_official 573:ad23fe03a082 1090 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1091 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1092 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 573:ad23fe03a082 1093 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 1094 * PHY_BCR: Transceiver Control Register.
mbed_official 573:ad23fe03a082 1095 * More PHY register could be written depending on the used PHY
mbed_official 573:ad23fe03a082 1096 * @param RegValue: the value to write
mbed_official 573:ad23fe03a082 1097 * @retval HAL status
mbed_official 573:ad23fe03a082 1098 */
mbed_official 573:ad23fe03a082 1099 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official 573:ad23fe03a082 1100 {
mbed_official 573:ad23fe03a082 1101 uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1102 uint32_t tickstart = 0;
mbed_official 573:ad23fe03a082 1103
mbed_official 573:ad23fe03a082 1104 /* Check parameters */
mbed_official 573:ad23fe03a082 1105 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 573:ad23fe03a082 1106
mbed_official 573:ad23fe03a082 1107 /* Check the ETH peripheral state */
mbed_official 573:ad23fe03a082 1108 if(heth->State == HAL_ETH_STATE_BUSY_WR)
mbed_official 573:ad23fe03a082 1109 {
mbed_official 573:ad23fe03a082 1110 return HAL_BUSY;
mbed_official 573:ad23fe03a082 1111 }
mbed_official 573:ad23fe03a082 1112 /* Set ETH HAL State to BUSY_WR */
mbed_official 573:ad23fe03a082 1113 heth->State = HAL_ETH_STATE_BUSY_WR;
mbed_official 573:ad23fe03a082 1114
mbed_official 573:ad23fe03a082 1115 /* Get the ETHERNET MACMIIAR value */
mbed_official 573:ad23fe03a082 1116 tmpreg = heth->Instance->MACMIIAR;
mbed_official 573:ad23fe03a082 1117
mbed_official 573:ad23fe03a082 1118 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 573:ad23fe03a082 1119 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
mbed_official 573:ad23fe03a082 1120
mbed_official 573:ad23fe03a082 1121 /* Prepare the MII register address value */
mbed_official 573:ad23fe03a082 1122 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 573:ad23fe03a082 1123 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 573:ad23fe03a082 1124 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
mbed_official 573:ad23fe03a082 1125 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 573:ad23fe03a082 1126
mbed_official 573:ad23fe03a082 1127 /* Give the value to the MII data register */
mbed_official 573:ad23fe03a082 1128 heth->Instance->MACMIIDR = (uint16_t)RegValue;
mbed_official 573:ad23fe03a082 1129
mbed_official 573:ad23fe03a082 1130 /* Write the result value into the MII Address register */
mbed_official 573:ad23fe03a082 1131 heth->Instance->MACMIIAR = tmpreg;
mbed_official 573:ad23fe03a082 1132
mbed_official 573:ad23fe03a082 1133 /* Get tick */
mbed_official 573:ad23fe03a082 1134 tickstart = HAL_GetTick();
mbed_official 573:ad23fe03a082 1135
mbed_official 573:ad23fe03a082 1136 /* Check for the Busy flag */
mbed_official 573:ad23fe03a082 1137 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 573:ad23fe03a082 1138 {
mbed_official 573:ad23fe03a082 1139 /* Check for the Timeout */
mbed_official 573:ad23fe03a082 1140 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
mbed_official 573:ad23fe03a082 1141 {
mbed_official 573:ad23fe03a082 1142 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 1143
mbed_official 573:ad23fe03a082 1144 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1145 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 1146
mbed_official 573:ad23fe03a082 1147 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 1148 }
mbed_official 573:ad23fe03a082 1149
mbed_official 573:ad23fe03a082 1150 tmpreg = heth->Instance->MACMIIAR;
mbed_official 573:ad23fe03a082 1151 }
mbed_official 573:ad23fe03a082 1152
mbed_official 573:ad23fe03a082 1153 /* Set ETH HAL State to READY */
mbed_official 573:ad23fe03a082 1154 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 1155
mbed_official 573:ad23fe03a082 1156 /* Return function status */
mbed_official 573:ad23fe03a082 1157 return HAL_OK;
mbed_official 573:ad23fe03a082 1158 }
mbed_official 573:ad23fe03a082 1159
mbed_official 573:ad23fe03a082 1160 /**
mbed_official 573:ad23fe03a082 1161 * @}
mbed_official 573:ad23fe03a082 1162 */
mbed_official 573:ad23fe03a082 1163
mbed_official 573:ad23fe03a082 1164 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
mbed_official 573:ad23fe03a082 1165 * @brief Peripheral Control functions
mbed_official 573:ad23fe03a082 1166 *
mbed_official 573:ad23fe03a082 1167 @verbatim
mbed_official 573:ad23fe03a082 1168 ===============================================================================
mbed_official 573:ad23fe03a082 1169 ##### Peripheral Control functions #####
mbed_official 573:ad23fe03a082 1170 ===============================================================================
mbed_official 573:ad23fe03a082 1171 [..] This section provides functions allowing to:
mbed_official 573:ad23fe03a082 1172 (+) Enable MAC and DMA transmission and reception.
mbed_official 573:ad23fe03a082 1173 HAL_ETH_Start();
mbed_official 573:ad23fe03a082 1174 (+) Disable MAC and DMA transmission and reception.
mbed_official 573:ad23fe03a082 1175 HAL_ETH_Stop();
mbed_official 573:ad23fe03a082 1176 (+) Set the MAC configuration in runtime mode
mbed_official 573:ad23fe03a082 1177 HAL_ETH_ConfigMAC();
mbed_official 573:ad23fe03a082 1178 (+) Set the DMA configuration in runtime mode
mbed_official 573:ad23fe03a082 1179 HAL_ETH_ConfigDMA();
mbed_official 573:ad23fe03a082 1180
mbed_official 573:ad23fe03a082 1181 @endverbatim
mbed_official 573:ad23fe03a082 1182 * @{
mbed_official 573:ad23fe03a082 1183 */
mbed_official 573:ad23fe03a082 1184
mbed_official 573:ad23fe03a082 1185 /**
mbed_official 573:ad23fe03a082 1186 * @brief Enables Ethernet MAC and DMA reception/transmission
mbed_official 573:ad23fe03a082 1187 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1188 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1189 * @retval HAL status
mbed_official 573:ad23fe03a082 1190 */
mbed_official 573:ad23fe03a082 1191 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1192 {
mbed_official 573:ad23fe03a082 1193 /* Process Locked */
mbed_official 573:ad23fe03a082 1194 __HAL_LOCK(heth);
mbed_official 573:ad23fe03a082 1195
mbed_official 573:ad23fe03a082 1196 /* Set the ETH peripheral state to BUSY */
mbed_official 573:ad23fe03a082 1197 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 1198
mbed_official 573:ad23fe03a082 1199 /* Enable transmit state machine of the MAC for transmission on the MII */
mbed_official 573:ad23fe03a082 1200 ETH_MACTransmissionEnable(heth);
mbed_official 573:ad23fe03a082 1201
mbed_official 573:ad23fe03a082 1202 /* Enable receive state machine of the MAC for reception from the MII */
mbed_official 573:ad23fe03a082 1203 ETH_MACReceptionEnable(heth);
mbed_official 573:ad23fe03a082 1204
mbed_official 573:ad23fe03a082 1205 /* Flush Transmit FIFO */
mbed_official 573:ad23fe03a082 1206 ETH_FlushTransmitFIFO(heth);
mbed_official 573:ad23fe03a082 1207
mbed_official 573:ad23fe03a082 1208 /* Start DMA transmission */
mbed_official 573:ad23fe03a082 1209 ETH_DMATransmissionEnable(heth);
mbed_official 573:ad23fe03a082 1210
mbed_official 573:ad23fe03a082 1211 /* Start DMA reception */
mbed_official 573:ad23fe03a082 1212 ETH_DMAReceptionEnable(heth);
mbed_official 573:ad23fe03a082 1213
mbed_official 573:ad23fe03a082 1214 /* Set the ETH state to READY*/
mbed_official 573:ad23fe03a082 1215 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 1216
mbed_official 573:ad23fe03a082 1217 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1218 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 1219
mbed_official 573:ad23fe03a082 1220 /* Return function status */
mbed_official 573:ad23fe03a082 1221 return HAL_OK;
mbed_official 573:ad23fe03a082 1222 }
mbed_official 573:ad23fe03a082 1223
mbed_official 573:ad23fe03a082 1224 /**
mbed_official 573:ad23fe03a082 1225 * @brief Stop Ethernet MAC and DMA reception/transmission
mbed_official 573:ad23fe03a082 1226 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1227 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1228 * @retval HAL status
mbed_official 573:ad23fe03a082 1229 */
mbed_official 573:ad23fe03a082 1230 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1231 {
mbed_official 573:ad23fe03a082 1232 /* Process Locked */
mbed_official 573:ad23fe03a082 1233 __HAL_LOCK(heth);
mbed_official 573:ad23fe03a082 1234
mbed_official 573:ad23fe03a082 1235 /* Set the ETH peripheral state to BUSY */
mbed_official 573:ad23fe03a082 1236 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 1237
mbed_official 573:ad23fe03a082 1238 /* Stop DMA transmission */
mbed_official 573:ad23fe03a082 1239 ETH_DMATransmissionDisable(heth);
mbed_official 573:ad23fe03a082 1240
mbed_official 573:ad23fe03a082 1241 /* Stop DMA reception */
mbed_official 573:ad23fe03a082 1242 ETH_DMAReceptionDisable(heth);
mbed_official 573:ad23fe03a082 1243
mbed_official 573:ad23fe03a082 1244 /* Disable receive state machine of the MAC for reception from the MII */
mbed_official 573:ad23fe03a082 1245 ETH_MACReceptionDisable(heth);
mbed_official 573:ad23fe03a082 1246
mbed_official 573:ad23fe03a082 1247 /* Flush Transmit FIFO */
mbed_official 573:ad23fe03a082 1248 ETH_FlushTransmitFIFO(heth);
mbed_official 573:ad23fe03a082 1249
mbed_official 573:ad23fe03a082 1250 /* Disable transmit state machine of the MAC for transmission on the MII */
mbed_official 573:ad23fe03a082 1251 ETH_MACTransmissionDisable(heth);
mbed_official 573:ad23fe03a082 1252
mbed_official 573:ad23fe03a082 1253 /* Set the ETH state*/
mbed_official 573:ad23fe03a082 1254 heth->State = HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 1255
mbed_official 573:ad23fe03a082 1256 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1257 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 1258
mbed_official 573:ad23fe03a082 1259 /* Return function status */
mbed_official 573:ad23fe03a082 1260 return HAL_OK;
mbed_official 573:ad23fe03a082 1261 }
mbed_official 573:ad23fe03a082 1262
mbed_official 573:ad23fe03a082 1263 /**
mbed_official 573:ad23fe03a082 1264 * @brief Set ETH MAC Configuration.
mbed_official 573:ad23fe03a082 1265 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1266 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1267 * @param macconf: MAC Configuration structure
mbed_official 573:ad23fe03a082 1268 * @retval HAL status
mbed_official 573:ad23fe03a082 1269 */
mbed_official 573:ad23fe03a082 1270 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
mbed_official 573:ad23fe03a082 1271 {
mbed_official 573:ad23fe03a082 1272 uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1273
mbed_official 573:ad23fe03a082 1274 /* Process Locked */
mbed_official 573:ad23fe03a082 1275 __HAL_LOCK(heth);
mbed_official 573:ad23fe03a082 1276
mbed_official 573:ad23fe03a082 1277 /* Set the ETH peripheral state to BUSY */
mbed_official 573:ad23fe03a082 1278 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 1279
mbed_official 573:ad23fe03a082 1280 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 573:ad23fe03a082 1281 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 573:ad23fe03a082 1282
mbed_official 573:ad23fe03a082 1283 if (macconf != NULL)
mbed_official 573:ad23fe03a082 1284 {
mbed_official 573:ad23fe03a082 1285 /* Check the parameters */
mbed_official 573:ad23fe03a082 1286 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
mbed_official 573:ad23fe03a082 1287 assert_param(IS_ETH_JABBER(macconf->Jabber));
mbed_official 573:ad23fe03a082 1288 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
mbed_official 573:ad23fe03a082 1289 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
mbed_official 573:ad23fe03a082 1290 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
mbed_official 573:ad23fe03a082 1291 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
mbed_official 573:ad23fe03a082 1292 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
mbed_official 573:ad23fe03a082 1293 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
mbed_official 573:ad23fe03a082 1294 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
mbed_official 573:ad23fe03a082 1295 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
mbed_official 573:ad23fe03a082 1296 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
mbed_official 573:ad23fe03a082 1297 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
mbed_official 573:ad23fe03a082 1298 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
mbed_official 573:ad23fe03a082 1299 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
mbed_official 573:ad23fe03a082 1300 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
mbed_official 573:ad23fe03a082 1301 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
mbed_official 573:ad23fe03a082 1302 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
mbed_official 573:ad23fe03a082 1303 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
mbed_official 573:ad23fe03a082 1304 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
mbed_official 573:ad23fe03a082 1305 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
mbed_official 573:ad23fe03a082 1306 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
mbed_official 573:ad23fe03a082 1307 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
mbed_official 573:ad23fe03a082 1308 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
mbed_official 573:ad23fe03a082 1309 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
mbed_official 573:ad23fe03a082 1310 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
mbed_official 573:ad23fe03a082 1311 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
mbed_official 573:ad23fe03a082 1312 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
mbed_official 573:ad23fe03a082 1313
mbed_official 573:ad23fe03a082 1314 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 573:ad23fe03a082 1315 /* Get the ETHERNET MACCR value */
mbed_official 573:ad23fe03a082 1316 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1317 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 573:ad23fe03a082 1318 tmpreg &= ETH_MACCR_CLEAR_MASK;
mbed_official 573:ad23fe03a082 1319
mbed_official 573:ad23fe03a082 1320 tmpreg |= (uint32_t)(macconf->Watchdog |
mbed_official 573:ad23fe03a082 1321 macconf->Jabber |
mbed_official 573:ad23fe03a082 1322 macconf->InterFrameGap |
mbed_official 573:ad23fe03a082 1323 macconf->CarrierSense |
mbed_official 573:ad23fe03a082 1324 (heth->Init).Speed |
mbed_official 573:ad23fe03a082 1325 macconf->ReceiveOwn |
mbed_official 573:ad23fe03a082 1326 macconf->LoopbackMode |
mbed_official 573:ad23fe03a082 1327 (heth->Init).DuplexMode |
mbed_official 573:ad23fe03a082 1328 macconf->ChecksumOffload |
mbed_official 573:ad23fe03a082 1329 macconf->RetryTransmission |
mbed_official 573:ad23fe03a082 1330 macconf->AutomaticPadCRCStrip |
mbed_official 573:ad23fe03a082 1331 macconf->BackOffLimit |
mbed_official 573:ad23fe03a082 1332 macconf->DeferralCheck);
mbed_official 573:ad23fe03a082 1333
mbed_official 573:ad23fe03a082 1334 /* Write to ETHERNET MACCR */
mbed_official 573:ad23fe03a082 1335 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 573:ad23fe03a082 1336
mbed_official 573:ad23fe03a082 1337 /* Wait until the write operation will be taken into account :
mbed_official 573:ad23fe03a082 1338 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1339 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1340 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1341 (heth->Instance)->MACCR = tmpreg;
mbed_official 573:ad23fe03a082 1342
mbed_official 573:ad23fe03a082 1343 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 573:ad23fe03a082 1344 /* Write to ETHERNET MACFFR */
mbed_official 573:ad23fe03a082 1345 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
mbed_official 573:ad23fe03a082 1346 macconf->SourceAddrFilter |
mbed_official 573:ad23fe03a082 1347 macconf->PassControlFrames |
mbed_official 573:ad23fe03a082 1348 macconf->BroadcastFramesReception |
mbed_official 573:ad23fe03a082 1349 macconf->DestinationAddrFilter |
mbed_official 573:ad23fe03a082 1350 macconf->PromiscuousMode |
mbed_official 573:ad23fe03a082 1351 macconf->MulticastFramesFilter |
mbed_official 573:ad23fe03a082 1352 macconf->UnicastFramesFilter);
mbed_official 573:ad23fe03a082 1353
mbed_official 573:ad23fe03a082 1354 /* Wait until the write operation will be taken into account :
mbed_official 573:ad23fe03a082 1355 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1356 tmpreg = (heth->Instance)->MACFFR;
mbed_official 573:ad23fe03a082 1357 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1358 (heth->Instance)->MACFFR = tmpreg;
mbed_official 573:ad23fe03a082 1359
mbed_official 573:ad23fe03a082 1360 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
mbed_official 573:ad23fe03a082 1361 /* Write to ETHERNET MACHTHR */
mbed_official 573:ad23fe03a082 1362 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
mbed_official 573:ad23fe03a082 1363
mbed_official 573:ad23fe03a082 1364 /* Write to ETHERNET MACHTLR */
mbed_official 573:ad23fe03a082 1365 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
mbed_official 573:ad23fe03a082 1366 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
mbed_official 573:ad23fe03a082 1367
mbed_official 573:ad23fe03a082 1368 /* Get the ETHERNET MACFCR value */
mbed_official 573:ad23fe03a082 1369 tmpreg = (heth->Instance)->MACFCR;
mbed_official 573:ad23fe03a082 1370 /* Clear xx bits */
mbed_official 573:ad23fe03a082 1371 tmpreg &= ETH_MACFCR_CLEAR_MASK;
mbed_official 573:ad23fe03a082 1372
mbed_official 573:ad23fe03a082 1373 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
mbed_official 573:ad23fe03a082 1374 macconf->ZeroQuantaPause |
mbed_official 573:ad23fe03a082 1375 macconf->PauseLowThreshold |
mbed_official 573:ad23fe03a082 1376 macconf->UnicastPauseFrameDetect |
mbed_official 573:ad23fe03a082 1377 macconf->ReceiveFlowControl |
mbed_official 573:ad23fe03a082 1378 macconf->TransmitFlowControl);
mbed_official 573:ad23fe03a082 1379
mbed_official 573:ad23fe03a082 1380 /* Write to ETHERNET MACFCR */
mbed_official 573:ad23fe03a082 1381 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 573:ad23fe03a082 1382
mbed_official 573:ad23fe03a082 1383 /* Wait until the write operation will be taken into account :
mbed_official 573:ad23fe03a082 1384 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1385 tmpreg = (heth->Instance)->MACFCR;
mbed_official 573:ad23fe03a082 1386 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1387 (heth->Instance)->MACFCR = tmpreg;
mbed_official 573:ad23fe03a082 1388
mbed_official 573:ad23fe03a082 1389 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
mbed_official 573:ad23fe03a082 1390 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
mbed_official 573:ad23fe03a082 1391 macconf->VLANTagIdentifier);
mbed_official 573:ad23fe03a082 1392
mbed_official 573:ad23fe03a082 1393 /* Wait until the write operation will be taken into account :
mbed_official 573:ad23fe03a082 1394 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1395 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 573:ad23fe03a082 1396 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1397 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 573:ad23fe03a082 1398 }
mbed_official 573:ad23fe03a082 1399 else /* macconf == NULL : here we just configure Speed and Duplex mode */
mbed_official 573:ad23fe03a082 1400 {
mbed_official 573:ad23fe03a082 1401 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 573:ad23fe03a082 1402 /* Get the ETHERNET MACCR value */
mbed_official 573:ad23fe03a082 1403 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1404
mbed_official 573:ad23fe03a082 1405 /* Clear FES and DM bits */
mbed_official 573:ad23fe03a082 1406 tmpreg &= ~((uint32_t)0x00004800);
mbed_official 573:ad23fe03a082 1407
mbed_official 573:ad23fe03a082 1408 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
mbed_official 573:ad23fe03a082 1409
mbed_official 573:ad23fe03a082 1410 /* Write to ETHERNET MACCR */
mbed_official 573:ad23fe03a082 1411 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 573:ad23fe03a082 1412
mbed_official 573:ad23fe03a082 1413 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1414 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1415 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1416 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1417 (heth->Instance)->MACCR = tmpreg;
mbed_official 573:ad23fe03a082 1418 }
mbed_official 573:ad23fe03a082 1419
mbed_official 573:ad23fe03a082 1420 /* Set the ETH state to Ready */
mbed_official 573:ad23fe03a082 1421 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 1422
mbed_official 573:ad23fe03a082 1423 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1424 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 1425
mbed_official 573:ad23fe03a082 1426 /* Return function status */
mbed_official 573:ad23fe03a082 1427 return HAL_OK;
mbed_official 573:ad23fe03a082 1428 }
mbed_official 573:ad23fe03a082 1429
mbed_official 573:ad23fe03a082 1430 /**
mbed_official 573:ad23fe03a082 1431 * @brief Sets ETH DMA Configuration.
mbed_official 573:ad23fe03a082 1432 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1433 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1434 * @param dmaconf: DMA Configuration structure
mbed_official 573:ad23fe03a082 1435 * @retval HAL status
mbed_official 573:ad23fe03a082 1436 */
mbed_official 573:ad23fe03a082 1437 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
mbed_official 573:ad23fe03a082 1438 {
mbed_official 573:ad23fe03a082 1439 uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1440
mbed_official 573:ad23fe03a082 1441 /* Process Locked */
mbed_official 573:ad23fe03a082 1442 __HAL_LOCK(heth);
mbed_official 573:ad23fe03a082 1443
mbed_official 573:ad23fe03a082 1444 /* Set the ETH peripheral state to BUSY */
mbed_official 573:ad23fe03a082 1445 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 573:ad23fe03a082 1446
mbed_official 573:ad23fe03a082 1447 /* Check parameters */
mbed_official 573:ad23fe03a082 1448 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
mbed_official 573:ad23fe03a082 1449 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
mbed_official 573:ad23fe03a082 1450 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
mbed_official 573:ad23fe03a082 1451 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
mbed_official 573:ad23fe03a082 1452 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
mbed_official 573:ad23fe03a082 1453 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
mbed_official 573:ad23fe03a082 1454 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
mbed_official 573:ad23fe03a082 1455 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
mbed_official 573:ad23fe03a082 1456 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
mbed_official 573:ad23fe03a082 1457 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
mbed_official 573:ad23fe03a082 1458 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
mbed_official 573:ad23fe03a082 1459 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
mbed_official 573:ad23fe03a082 1460 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
mbed_official 573:ad23fe03a082 1461 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
mbed_official 573:ad23fe03a082 1462 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
mbed_official 573:ad23fe03a082 1463 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
mbed_official 573:ad23fe03a082 1464
mbed_official 573:ad23fe03a082 1465 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
mbed_official 573:ad23fe03a082 1466 /* Get the ETHERNET DMAOMR value */
mbed_official 573:ad23fe03a082 1467 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 573:ad23fe03a082 1468 /* Clear xx bits */
mbed_official 573:ad23fe03a082 1469 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
mbed_official 573:ad23fe03a082 1470
mbed_official 573:ad23fe03a082 1471 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
mbed_official 573:ad23fe03a082 1472 dmaconf->ReceiveStoreForward |
mbed_official 573:ad23fe03a082 1473 dmaconf->FlushReceivedFrame |
mbed_official 573:ad23fe03a082 1474 dmaconf->TransmitStoreForward |
mbed_official 573:ad23fe03a082 1475 dmaconf->TransmitThresholdControl |
mbed_official 573:ad23fe03a082 1476 dmaconf->ForwardErrorFrames |
mbed_official 573:ad23fe03a082 1477 dmaconf->ForwardUndersizedGoodFrames |
mbed_official 573:ad23fe03a082 1478 dmaconf->ReceiveThresholdControl |
mbed_official 573:ad23fe03a082 1479 dmaconf->SecondFrameOperate);
mbed_official 573:ad23fe03a082 1480
mbed_official 573:ad23fe03a082 1481 /* Write to ETHERNET DMAOMR */
mbed_official 573:ad23fe03a082 1482 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 573:ad23fe03a082 1483
mbed_official 573:ad23fe03a082 1484 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1485 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1486 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 573:ad23fe03a082 1487 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1488 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 573:ad23fe03a082 1489
mbed_official 573:ad23fe03a082 1490 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
mbed_official 573:ad23fe03a082 1491 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
mbed_official 573:ad23fe03a082 1492 dmaconf->FixedBurst |
mbed_official 573:ad23fe03a082 1493 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 573:ad23fe03a082 1494 dmaconf->TxDMABurstLength |
mbed_official 573:ad23fe03a082 1495 dmaconf->EnhancedDescriptorFormat |
mbed_official 573:ad23fe03a082 1496 (dmaconf->DescriptorSkipLength << 2) |
mbed_official 573:ad23fe03a082 1497 dmaconf->DMAArbitration |
mbed_official 573:ad23fe03a082 1498 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 573:ad23fe03a082 1499
mbed_official 573:ad23fe03a082 1500 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1501 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1502 tmpreg = (heth->Instance)->DMABMR;
mbed_official 573:ad23fe03a082 1503 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1504 (heth->Instance)->DMABMR = tmpreg;
mbed_official 573:ad23fe03a082 1505
mbed_official 573:ad23fe03a082 1506 /* Set the ETH state to Ready */
mbed_official 573:ad23fe03a082 1507 heth->State= HAL_ETH_STATE_READY;
mbed_official 573:ad23fe03a082 1508
mbed_official 573:ad23fe03a082 1509 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1510 __HAL_UNLOCK(heth);
mbed_official 573:ad23fe03a082 1511
mbed_official 573:ad23fe03a082 1512 /* Return function status */
mbed_official 573:ad23fe03a082 1513 return HAL_OK;
mbed_official 573:ad23fe03a082 1514 }
mbed_official 573:ad23fe03a082 1515
mbed_official 573:ad23fe03a082 1516 /**
mbed_official 573:ad23fe03a082 1517 * @}
mbed_official 573:ad23fe03a082 1518 */
mbed_official 573:ad23fe03a082 1519
mbed_official 573:ad23fe03a082 1520 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
mbed_official 573:ad23fe03a082 1521 * @brief Peripheral State functions
mbed_official 573:ad23fe03a082 1522 *
mbed_official 573:ad23fe03a082 1523 @verbatim
mbed_official 573:ad23fe03a082 1524 ===============================================================================
mbed_official 573:ad23fe03a082 1525 ##### Peripheral State functions #####
mbed_official 573:ad23fe03a082 1526 ===============================================================================
mbed_official 573:ad23fe03a082 1527 [..]
mbed_official 573:ad23fe03a082 1528 This subsection permits to get in run-time the status of the peripheral
mbed_official 573:ad23fe03a082 1529 and the data flow.
mbed_official 573:ad23fe03a082 1530 (+) Get the ETH handle state:
mbed_official 573:ad23fe03a082 1531 HAL_ETH_GetState();
mbed_official 573:ad23fe03a082 1532
mbed_official 573:ad23fe03a082 1533
mbed_official 573:ad23fe03a082 1534 @endverbatim
mbed_official 573:ad23fe03a082 1535 * @{
mbed_official 573:ad23fe03a082 1536 */
mbed_official 573:ad23fe03a082 1537
mbed_official 573:ad23fe03a082 1538 /**
mbed_official 573:ad23fe03a082 1539 * @brief Return the ETH HAL state
mbed_official 573:ad23fe03a082 1540 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1541 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1542 * @retval HAL state
mbed_official 573:ad23fe03a082 1543 */
mbed_official 573:ad23fe03a082 1544 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1545 {
mbed_official 573:ad23fe03a082 1546 /* Return ETH state */
mbed_official 573:ad23fe03a082 1547 return heth->State;
mbed_official 573:ad23fe03a082 1548 }
mbed_official 573:ad23fe03a082 1549
mbed_official 573:ad23fe03a082 1550 /**
mbed_official 573:ad23fe03a082 1551 * @}
mbed_official 573:ad23fe03a082 1552 */
mbed_official 573:ad23fe03a082 1553
mbed_official 573:ad23fe03a082 1554 /**
mbed_official 573:ad23fe03a082 1555 * @}
mbed_official 573:ad23fe03a082 1556 */
mbed_official 573:ad23fe03a082 1557
mbed_official 573:ad23fe03a082 1558 /** @addtogroup ETH_Private_Functions
mbed_official 573:ad23fe03a082 1559 * @{
mbed_official 573:ad23fe03a082 1560 */
mbed_official 573:ad23fe03a082 1561
mbed_official 573:ad23fe03a082 1562 /**
mbed_official 573:ad23fe03a082 1563 * @brief Configures Ethernet MAC and DMA with default parameters.
mbed_official 573:ad23fe03a082 1564 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1565 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1566 * @param err: Ethernet Init error
mbed_official 573:ad23fe03a082 1567 * @retval HAL status
mbed_official 573:ad23fe03a082 1568 */
mbed_official 573:ad23fe03a082 1569 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
mbed_official 573:ad23fe03a082 1570 {
mbed_official 573:ad23fe03a082 1571 ETH_MACInitTypeDef macinit;
mbed_official 573:ad23fe03a082 1572 ETH_DMAInitTypeDef dmainit;
mbed_official 573:ad23fe03a082 1573 uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1574
mbed_official 573:ad23fe03a082 1575 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
mbed_official 573:ad23fe03a082 1576 {
mbed_official 573:ad23fe03a082 1577 /* Set Ethernet duplex mode to Full-duplex */
mbed_official 573:ad23fe03a082 1578 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 573:ad23fe03a082 1579
mbed_official 573:ad23fe03a082 1580 /* Set Ethernet speed to 100M */
mbed_official 573:ad23fe03a082 1581 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 573:ad23fe03a082 1582 }
mbed_official 573:ad23fe03a082 1583
mbed_official 573:ad23fe03a082 1584 /* Ethernet MAC default initialization **************************************/
mbed_official 573:ad23fe03a082 1585 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
mbed_official 573:ad23fe03a082 1586 macinit.Jabber = ETH_JABBER_ENABLE;
mbed_official 573:ad23fe03a082 1587 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
mbed_official 573:ad23fe03a082 1588 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
mbed_official 573:ad23fe03a082 1589 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
mbed_official 573:ad23fe03a082 1590 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
mbed_official 573:ad23fe03a082 1591 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 573:ad23fe03a082 1592 {
mbed_official 573:ad23fe03a082 1593 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
mbed_official 573:ad23fe03a082 1594 }
mbed_official 573:ad23fe03a082 1595 else
mbed_official 573:ad23fe03a082 1596 {
mbed_official 573:ad23fe03a082 1597 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
mbed_official 573:ad23fe03a082 1598 }
mbed_official 573:ad23fe03a082 1599 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
mbed_official 573:ad23fe03a082 1600 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
mbed_official 573:ad23fe03a082 1601 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
mbed_official 573:ad23fe03a082 1602 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
mbed_official 573:ad23fe03a082 1603 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
mbed_official 573:ad23fe03a082 1604 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
mbed_official 573:ad23fe03a082 1605 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
mbed_official 573:ad23fe03a082 1606 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
mbed_official 573:ad23fe03a082 1607 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
mbed_official 573:ad23fe03a082 1608 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
mbed_official 573:ad23fe03a082 1609 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
mbed_official 573:ad23fe03a082 1610 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
mbed_official 573:ad23fe03a082 1611 macinit.HashTableHigh = 0x0;
mbed_official 573:ad23fe03a082 1612 macinit.HashTableLow = 0x0;
mbed_official 573:ad23fe03a082 1613 macinit.PauseTime = 0x0;
mbed_official 573:ad23fe03a082 1614 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
mbed_official 573:ad23fe03a082 1615 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
mbed_official 573:ad23fe03a082 1616 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
mbed_official 573:ad23fe03a082 1617 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
mbed_official 573:ad23fe03a082 1618 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
mbed_official 573:ad23fe03a082 1619 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
mbed_official 573:ad23fe03a082 1620 macinit.VLANTagIdentifier = 0x0;
mbed_official 573:ad23fe03a082 1621
mbed_official 573:ad23fe03a082 1622 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 573:ad23fe03a082 1623 /* Get the ETHERNET MACCR value */
mbed_official 573:ad23fe03a082 1624 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1625 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 573:ad23fe03a082 1626 tmpreg &= ETH_MACCR_CLEAR_MASK;
mbed_official 573:ad23fe03a082 1627 /* Set the WD bit according to ETH Watchdog value */
mbed_official 573:ad23fe03a082 1628 /* Set the JD: bit according to ETH Jabber value */
mbed_official 573:ad23fe03a082 1629 /* Set the IFG bit according to ETH InterFrameGap value */
mbed_official 573:ad23fe03a082 1630 /* Set the DCRS bit according to ETH CarrierSense value */
mbed_official 573:ad23fe03a082 1631 /* Set the FES bit according to ETH Speed value */
mbed_official 573:ad23fe03a082 1632 /* Set the DO bit according to ETH ReceiveOwn value */
mbed_official 573:ad23fe03a082 1633 /* Set the LM bit according to ETH LoopbackMode value */
mbed_official 573:ad23fe03a082 1634 /* Set the DM bit according to ETH Mode value */
mbed_official 573:ad23fe03a082 1635 /* Set the IPCO bit according to ETH ChecksumOffload value */
mbed_official 573:ad23fe03a082 1636 /* Set the DR bit according to ETH RetryTransmission value */
mbed_official 573:ad23fe03a082 1637 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
mbed_official 573:ad23fe03a082 1638 /* Set the BL bit according to ETH BackOffLimit value */
mbed_official 573:ad23fe03a082 1639 /* Set the DC bit according to ETH DeferralCheck value */
mbed_official 573:ad23fe03a082 1640 tmpreg |= (uint32_t)(macinit.Watchdog |
mbed_official 573:ad23fe03a082 1641 macinit.Jabber |
mbed_official 573:ad23fe03a082 1642 macinit.InterFrameGap |
mbed_official 573:ad23fe03a082 1643 macinit.CarrierSense |
mbed_official 573:ad23fe03a082 1644 (heth->Init).Speed |
mbed_official 573:ad23fe03a082 1645 macinit.ReceiveOwn |
mbed_official 573:ad23fe03a082 1646 macinit.LoopbackMode |
mbed_official 573:ad23fe03a082 1647 (heth->Init).DuplexMode |
mbed_official 573:ad23fe03a082 1648 macinit.ChecksumOffload |
mbed_official 573:ad23fe03a082 1649 macinit.RetryTransmission |
mbed_official 573:ad23fe03a082 1650 macinit.AutomaticPadCRCStrip |
mbed_official 573:ad23fe03a082 1651 macinit.BackOffLimit |
mbed_official 573:ad23fe03a082 1652 macinit.DeferralCheck);
mbed_official 573:ad23fe03a082 1653
mbed_official 573:ad23fe03a082 1654 /* Write to ETHERNET MACCR */
mbed_official 573:ad23fe03a082 1655 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 573:ad23fe03a082 1656
mbed_official 573:ad23fe03a082 1657 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1658 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1659 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1660 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1661 (heth->Instance)->MACCR = tmpreg;
mbed_official 573:ad23fe03a082 1662
mbed_official 573:ad23fe03a082 1663 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 573:ad23fe03a082 1664 /* Set the RA bit according to ETH ReceiveAll value */
mbed_official 573:ad23fe03a082 1665 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
mbed_official 573:ad23fe03a082 1666 /* Set the PCF bit according to ETH PassControlFrames value */
mbed_official 573:ad23fe03a082 1667 /* Set the DBF bit according to ETH BroadcastFramesReception value */
mbed_official 573:ad23fe03a082 1668 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
mbed_official 573:ad23fe03a082 1669 /* Set the PR bit according to ETH PromiscuousMode value */
mbed_official 573:ad23fe03a082 1670 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
mbed_official 573:ad23fe03a082 1671 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
mbed_official 573:ad23fe03a082 1672 /* Write to ETHERNET MACFFR */
mbed_official 573:ad23fe03a082 1673 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
mbed_official 573:ad23fe03a082 1674 macinit.SourceAddrFilter |
mbed_official 573:ad23fe03a082 1675 macinit.PassControlFrames |
mbed_official 573:ad23fe03a082 1676 macinit.BroadcastFramesReception |
mbed_official 573:ad23fe03a082 1677 macinit.DestinationAddrFilter |
mbed_official 573:ad23fe03a082 1678 macinit.PromiscuousMode |
mbed_official 573:ad23fe03a082 1679 macinit.MulticastFramesFilter |
mbed_official 573:ad23fe03a082 1680 macinit.UnicastFramesFilter);
mbed_official 573:ad23fe03a082 1681
mbed_official 573:ad23fe03a082 1682 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1683 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1684 tmpreg = (heth->Instance)->MACFFR;
mbed_official 573:ad23fe03a082 1685 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1686 (heth->Instance)->MACFFR = tmpreg;
mbed_official 573:ad23fe03a082 1687
mbed_official 573:ad23fe03a082 1688 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
mbed_official 573:ad23fe03a082 1689 /* Write to ETHERNET MACHTHR */
mbed_official 573:ad23fe03a082 1690 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
mbed_official 573:ad23fe03a082 1691
mbed_official 573:ad23fe03a082 1692 /* Write to ETHERNET MACHTLR */
mbed_official 573:ad23fe03a082 1693 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
mbed_official 573:ad23fe03a082 1694 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
mbed_official 573:ad23fe03a082 1695
mbed_official 573:ad23fe03a082 1696 /* Get the ETHERNET MACFCR value */
mbed_official 573:ad23fe03a082 1697 tmpreg = (heth->Instance)->MACFCR;
mbed_official 573:ad23fe03a082 1698 /* Clear xx bits */
mbed_official 573:ad23fe03a082 1699 tmpreg &= ETH_MACFCR_CLEAR_MASK;
mbed_official 573:ad23fe03a082 1700
mbed_official 573:ad23fe03a082 1701 /* Set the PT bit according to ETH PauseTime value */
mbed_official 573:ad23fe03a082 1702 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
mbed_official 573:ad23fe03a082 1703 /* Set the PLT bit according to ETH PauseLowThreshold value */
mbed_official 573:ad23fe03a082 1704 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
mbed_official 573:ad23fe03a082 1705 /* Set the RFE bit according to ETH ReceiveFlowControl value */
mbed_official 573:ad23fe03a082 1706 /* Set the TFE bit according to ETH TransmitFlowControl value */
mbed_official 573:ad23fe03a082 1707 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
mbed_official 573:ad23fe03a082 1708 macinit.ZeroQuantaPause |
mbed_official 573:ad23fe03a082 1709 macinit.PauseLowThreshold |
mbed_official 573:ad23fe03a082 1710 macinit.UnicastPauseFrameDetect |
mbed_official 573:ad23fe03a082 1711 macinit.ReceiveFlowControl |
mbed_official 573:ad23fe03a082 1712 macinit.TransmitFlowControl);
mbed_official 573:ad23fe03a082 1713
mbed_official 573:ad23fe03a082 1714 /* Write to ETHERNET MACFCR */
mbed_official 573:ad23fe03a082 1715 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 573:ad23fe03a082 1716
mbed_official 573:ad23fe03a082 1717 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1718 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1719 tmpreg = (heth->Instance)->MACFCR;
mbed_official 573:ad23fe03a082 1720 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1721 (heth->Instance)->MACFCR = tmpreg;
mbed_official 573:ad23fe03a082 1722
mbed_official 573:ad23fe03a082 1723 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
mbed_official 573:ad23fe03a082 1724 /* Set the ETV bit according to ETH VLANTagComparison value */
mbed_official 573:ad23fe03a082 1725 /* Set the VL bit according to ETH VLANTagIdentifier value */
mbed_official 573:ad23fe03a082 1726 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
mbed_official 573:ad23fe03a082 1727 macinit.VLANTagIdentifier);
mbed_official 573:ad23fe03a082 1728
mbed_official 573:ad23fe03a082 1729 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1730 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1731 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 573:ad23fe03a082 1732 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1733 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 573:ad23fe03a082 1734
mbed_official 573:ad23fe03a082 1735 /* Ethernet DMA default initialization ************************************/
mbed_official 573:ad23fe03a082 1736 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
mbed_official 573:ad23fe03a082 1737 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
mbed_official 573:ad23fe03a082 1738 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
mbed_official 573:ad23fe03a082 1739 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
mbed_official 573:ad23fe03a082 1740 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
mbed_official 573:ad23fe03a082 1741 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
mbed_official 573:ad23fe03a082 1742 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
mbed_official 573:ad23fe03a082 1743 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
mbed_official 573:ad23fe03a082 1744 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
mbed_official 573:ad23fe03a082 1745 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
mbed_official 573:ad23fe03a082 1746 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
mbed_official 573:ad23fe03a082 1747 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
mbed_official 573:ad23fe03a082 1748 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
mbed_official 573:ad23fe03a082 1749 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
mbed_official 573:ad23fe03a082 1750 dmainit.DescriptorSkipLength = 0x0;
mbed_official 573:ad23fe03a082 1751 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
mbed_official 573:ad23fe03a082 1752
mbed_official 573:ad23fe03a082 1753 /* Get the ETHERNET DMAOMR value */
mbed_official 573:ad23fe03a082 1754 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 573:ad23fe03a082 1755 /* Clear xx bits */
mbed_official 573:ad23fe03a082 1756 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
mbed_official 573:ad23fe03a082 1757
mbed_official 573:ad23fe03a082 1758 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
mbed_official 573:ad23fe03a082 1759 /* Set the RSF bit according to ETH ReceiveStoreForward value */
mbed_official 573:ad23fe03a082 1760 /* Set the DFF bit according to ETH FlushReceivedFrame value */
mbed_official 573:ad23fe03a082 1761 /* Set the TSF bit according to ETH TransmitStoreForward value */
mbed_official 573:ad23fe03a082 1762 /* Set the TTC bit according to ETH TransmitThresholdControl value */
mbed_official 573:ad23fe03a082 1763 /* Set the FEF bit according to ETH ForwardErrorFrames value */
mbed_official 573:ad23fe03a082 1764 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
mbed_official 573:ad23fe03a082 1765 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
mbed_official 573:ad23fe03a082 1766 /* Set the OSF bit according to ETH SecondFrameOperate value */
mbed_official 573:ad23fe03a082 1767 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
mbed_official 573:ad23fe03a082 1768 dmainit.ReceiveStoreForward |
mbed_official 573:ad23fe03a082 1769 dmainit.FlushReceivedFrame |
mbed_official 573:ad23fe03a082 1770 dmainit.TransmitStoreForward |
mbed_official 573:ad23fe03a082 1771 dmainit.TransmitThresholdControl |
mbed_official 573:ad23fe03a082 1772 dmainit.ForwardErrorFrames |
mbed_official 573:ad23fe03a082 1773 dmainit.ForwardUndersizedGoodFrames |
mbed_official 573:ad23fe03a082 1774 dmainit.ReceiveThresholdControl |
mbed_official 573:ad23fe03a082 1775 dmainit.SecondFrameOperate);
mbed_official 573:ad23fe03a082 1776
mbed_official 573:ad23fe03a082 1777 /* Write to ETHERNET DMAOMR */
mbed_official 573:ad23fe03a082 1778 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 573:ad23fe03a082 1779
mbed_official 573:ad23fe03a082 1780 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1781 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1782 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 573:ad23fe03a082 1783 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1784 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 573:ad23fe03a082 1785
mbed_official 573:ad23fe03a082 1786 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
mbed_official 573:ad23fe03a082 1787 /* Set the AAL bit according to ETH AddressAlignedBeats value */
mbed_official 573:ad23fe03a082 1788 /* Set the FB bit according to ETH FixedBurst value */
mbed_official 573:ad23fe03a082 1789 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
mbed_official 573:ad23fe03a082 1790 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
mbed_official 573:ad23fe03a082 1791 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
mbed_official 573:ad23fe03a082 1792 /* Set the DSL bit according to ETH DesciptorSkipLength value */
mbed_official 573:ad23fe03a082 1793 /* Set the PR and DA bits according to ETH DMAArbitration value */
mbed_official 573:ad23fe03a082 1794 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
mbed_official 573:ad23fe03a082 1795 dmainit.FixedBurst |
mbed_official 573:ad23fe03a082 1796 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 573:ad23fe03a082 1797 dmainit.TxDMABurstLength |
mbed_official 573:ad23fe03a082 1798 dmainit.EnhancedDescriptorFormat |
mbed_official 573:ad23fe03a082 1799 (dmainit.DescriptorSkipLength << 2) |
mbed_official 573:ad23fe03a082 1800 dmainit.DMAArbitration |
mbed_official 573:ad23fe03a082 1801 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 573:ad23fe03a082 1802
mbed_official 573:ad23fe03a082 1803 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1804 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1805 tmpreg = (heth->Instance)->DMABMR;
mbed_official 573:ad23fe03a082 1806 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1807 (heth->Instance)->DMABMR = tmpreg;
mbed_official 573:ad23fe03a082 1808
mbed_official 573:ad23fe03a082 1809 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 573:ad23fe03a082 1810 {
mbed_official 573:ad23fe03a082 1811 /* Enable the Ethernet Rx Interrupt */
mbed_official 573:ad23fe03a082 1812 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
mbed_official 573:ad23fe03a082 1813 }
mbed_official 573:ad23fe03a082 1814
mbed_official 573:ad23fe03a082 1815 /* Initialize MAC address in ethernet MAC */
mbed_official 573:ad23fe03a082 1816 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
mbed_official 573:ad23fe03a082 1817 }
mbed_official 573:ad23fe03a082 1818
mbed_official 573:ad23fe03a082 1819 /**
mbed_official 573:ad23fe03a082 1820 * @brief Configures the selected MAC address.
mbed_official 573:ad23fe03a082 1821 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1822 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1823 * @param MacAddr: The MAC address to configure
mbed_official 573:ad23fe03a082 1824 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 1825 * @arg ETH_MAC_Address0: MAC Address0
mbed_official 573:ad23fe03a082 1826 * @arg ETH_MAC_Address1: MAC Address1
mbed_official 573:ad23fe03a082 1827 * @arg ETH_MAC_Address2: MAC Address2
mbed_official 573:ad23fe03a082 1828 * @arg ETH_MAC_Address3: MAC Address3
mbed_official 573:ad23fe03a082 1829 * @param Addr: Pointer to MAC address buffer data (6 bytes)
mbed_official 573:ad23fe03a082 1830 * @retval HAL status
mbed_official 573:ad23fe03a082 1831 */
mbed_official 573:ad23fe03a082 1832 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
mbed_official 573:ad23fe03a082 1833 {
mbed_official 573:ad23fe03a082 1834 uint32_t tmpreg;
mbed_official 573:ad23fe03a082 1835
mbed_official 573:ad23fe03a082 1836 /* Check the parameters */
mbed_official 573:ad23fe03a082 1837 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
mbed_official 573:ad23fe03a082 1838
mbed_official 573:ad23fe03a082 1839 /* Calculate the selected MAC address high register */
mbed_official 573:ad23fe03a082 1840 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
mbed_official 573:ad23fe03a082 1841 /* Load the selected MAC address high register */
mbed_official 573:ad23fe03a082 1842 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
mbed_official 573:ad23fe03a082 1843 /* Calculate the selected MAC address low register */
mbed_official 573:ad23fe03a082 1844 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
mbed_official 573:ad23fe03a082 1845
mbed_official 573:ad23fe03a082 1846 /* Load the selected MAC address low register */
mbed_official 573:ad23fe03a082 1847 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
mbed_official 573:ad23fe03a082 1848 }
mbed_official 573:ad23fe03a082 1849
mbed_official 573:ad23fe03a082 1850 /**
mbed_official 573:ad23fe03a082 1851 * @brief Enables the MAC transmission.
mbed_official 573:ad23fe03a082 1852 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1853 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1854 * @retval None
mbed_official 573:ad23fe03a082 1855 */
mbed_official 573:ad23fe03a082 1856 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1857 {
mbed_official 573:ad23fe03a082 1858 __IO uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1859
mbed_official 573:ad23fe03a082 1860 /* Enable the MAC transmission */
mbed_official 573:ad23fe03a082 1861 (heth->Instance)->MACCR |= ETH_MACCR_TE;
mbed_official 573:ad23fe03a082 1862
mbed_official 573:ad23fe03a082 1863 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1864 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1865 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1866 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1867 (heth->Instance)->MACCR = tmpreg;
mbed_official 573:ad23fe03a082 1868 }
mbed_official 573:ad23fe03a082 1869
mbed_official 573:ad23fe03a082 1870 /**
mbed_official 573:ad23fe03a082 1871 * @brief Disables the MAC transmission.
mbed_official 573:ad23fe03a082 1872 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1873 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1874 * @retval None
mbed_official 573:ad23fe03a082 1875 */
mbed_official 573:ad23fe03a082 1876 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1877 {
mbed_official 573:ad23fe03a082 1878 __IO uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1879
mbed_official 573:ad23fe03a082 1880 /* Disable the MAC transmission */
mbed_official 573:ad23fe03a082 1881 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
mbed_official 573:ad23fe03a082 1882
mbed_official 573:ad23fe03a082 1883 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1884 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1885 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1886 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1887 (heth->Instance)->MACCR = tmpreg;
mbed_official 573:ad23fe03a082 1888 }
mbed_official 573:ad23fe03a082 1889
mbed_official 573:ad23fe03a082 1890 /**
mbed_official 573:ad23fe03a082 1891 * @brief Enables the MAC reception.
mbed_official 573:ad23fe03a082 1892 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1893 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1894 * @retval None
mbed_official 573:ad23fe03a082 1895 */
mbed_official 573:ad23fe03a082 1896 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1897 {
mbed_official 573:ad23fe03a082 1898 __IO uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1899
mbed_official 573:ad23fe03a082 1900 /* Enable the MAC reception */
mbed_official 573:ad23fe03a082 1901 (heth->Instance)->MACCR |= ETH_MACCR_RE;
mbed_official 573:ad23fe03a082 1902
mbed_official 573:ad23fe03a082 1903 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1904 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1905 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1906 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1907 (heth->Instance)->MACCR = tmpreg;
mbed_official 573:ad23fe03a082 1908 }
mbed_official 573:ad23fe03a082 1909
mbed_official 573:ad23fe03a082 1910 /**
mbed_official 573:ad23fe03a082 1911 * @brief Disables the MAC reception.
mbed_official 573:ad23fe03a082 1912 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1913 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1914 * @retval None
mbed_official 573:ad23fe03a082 1915 */
mbed_official 573:ad23fe03a082 1916 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1917 {
mbed_official 573:ad23fe03a082 1918 __IO uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1919
mbed_official 573:ad23fe03a082 1920 /* Disable the MAC reception */
mbed_official 573:ad23fe03a082 1921 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
mbed_official 573:ad23fe03a082 1922
mbed_official 573:ad23fe03a082 1923 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1924 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1925 tmpreg = (heth->Instance)->MACCR;
mbed_official 573:ad23fe03a082 1926 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1927 (heth->Instance)->MACCR = tmpreg;
mbed_official 573:ad23fe03a082 1928 }
mbed_official 573:ad23fe03a082 1929
mbed_official 573:ad23fe03a082 1930 /**
mbed_official 573:ad23fe03a082 1931 * @brief Enables the DMA transmission.
mbed_official 573:ad23fe03a082 1932 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1933 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1934 * @retval None
mbed_official 573:ad23fe03a082 1935 */
mbed_official 573:ad23fe03a082 1936 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1937 {
mbed_official 573:ad23fe03a082 1938 /* Enable the DMA transmission */
mbed_official 573:ad23fe03a082 1939 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
mbed_official 573:ad23fe03a082 1940 }
mbed_official 573:ad23fe03a082 1941
mbed_official 573:ad23fe03a082 1942 /**
mbed_official 573:ad23fe03a082 1943 * @brief Disables the DMA transmission.
mbed_official 573:ad23fe03a082 1944 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1945 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1946 * @retval None
mbed_official 573:ad23fe03a082 1947 */
mbed_official 573:ad23fe03a082 1948 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1949 {
mbed_official 573:ad23fe03a082 1950 /* Disable the DMA transmission */
mbed_official 573:ad23fe03a082 1951 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
mbed_official 573:ad23fe03a082 1952 }
mbed_official 573:ad23fe03a082 1953
mbed_official 573:ad23fe03a082 1954 /**
mbed_official 573:ad23fe03a082 1955 * @brief Enables the DMA reception.
mbed_official 573:ad23fe03a082 1956 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1957 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1958 * @retval None
mbed_official 573:ad23fe03a082 1959 */
mbed_official 573:ad23fe03a082 1960 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1961 {
mbed_official 573:ad23fe03a082 1962 /* Enable the DMA reception */
mbed_official 573:ad23fe03a082 1963 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
mbed_official 573:ad23fe03a082 1964 }
mbed_official 573:ad23fe03a082 1965
mbed_official 573:ad23fe03a082 1966 /**
mbed_official 573:ad23fe03a082 1967 * @brief Disables the DMA reception.
mbed_official 573:ad23fe03a082 1968 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1969 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1970 * @retval None
mbed_official 573:ad23fe03a082 1971 */
mbed_official 573:ad23fe03a082 1972 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1973 {
mbed_official 573:ad23fe03a082 1974 /* Disable the DMA reception */
mbed_official 573:ad23fe03a082 1975 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
mbed_official 573:ad23fe03a082 1976 }
mbed_official 573:ad23fe03a082 1977
mbed_official 573:ad23fe03a082 1978 /**
mbed_official 573:ad23fe03a082 1979 * @brief Clears the ETHERNET transmit FIFO.
mbed_official 573:ad23fe03a082 1980 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1981 * the configuration information for ETHERNET module
mbed_official 573:ad23fe03a082 1982 * @retval None
mbed_official 573:ad23fe03a082 1983 */
mbed_official 573:ad23fe03a082 1984 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
mbed_official 573:ad23fe03a082 1985 {
mbed_official 573:ad23fe03a082 1986 __IO uint32_t tmpreg = 0;
mbed_official 573:ad23fe03a082 1987
mbed_official 573:ad23fe03a082 1988 /* Set the Flush Transmit FIFO bit */
mbed_official 573:ad23fe03a082 1989 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
mbed_official 573:ad23fe03a082 1990
mbed_official 573:ad23fe03a082 1991 /* Wait until the write operation will be taken into account:
mbed_official 573:ad23fe03a082 1992 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 573:ad23fe03a082 1993 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 573:ad23fe03a082 1994 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 573:ad23fe03a082 1995 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 573:ad23fe03a082 1996 }
mbed_official 573:ad23fe03a082 1997
mbed_official 573:ad23fe03a082 1998 /**
mbed_official 573:ad23fe03a082 1999 * @}
mbed_official 573:ad23fe03a082 2000 */
mbed_official 573:ad23fe03a082 2001
mbed_official 573:ad23fe03a082 2002 #endif /* HAL_ETH_MODULE_ENABLED */
mbed_official 573:ad23fe03a082 2003 /**
mbed_official 573:ad23fe03a082 2004 * @}
mbed_official 573:ad23fe03a082 2005 */
mbed_official 573:ad23fe03a082 2006
mbed_official 573:ad23fe03a082 2007 /**
mbed_official 573:ad23fe03a082 2008 * @}
mbed_official 573:ad23fe03a082 2009 */
mbed_official 573:ad23fe03a082 2010
mbed_official 573:ad23fe03a082 2011 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/