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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c@380:510f0c3515e3, 2014-11-03 (annotated)

Committer:
mbed_official
Date:
Mon Nov 03 10:15:07 2014 +0000
Revision:
380:510f0c3515e3
Parent:
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_ll_fmc.c@235:685d5f11838f
Child:
532:fe11edbda85c
Synchronized with git revision 417f470ba9f4882d7079611cbc576afd9c49b0ef



Full URL: https://github.com/mbedmicro/mbed/commit/417f470ba9f4882d7079611cbc576afd9c49b0ef/



Targets: Factorisation of NUCLEO_F401RE and F411RE cmsis folders

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 235:685d5f11838f 1 /**
mbed_official 235:685d5f11838f 2 ******************************************************************************
mbed_official 235:685d5f11838f 3 * @file stm32f4xx_ll_fmc.c
mbed_official 235:685d5f11838f 4 * @author MCD Application Team
mbed_official 235:685d5f11838f 5 * @version V1.1.0
mbed_official 235:685d5f11838f 6 * @date 19-June-2014
mbed_official 235:685d5f11838f 7 * @brief FMC Low Layer HAL module driver.
mbed_official 235:685d5f11838f 8 *
mbed_official 235:685d5f11838f 9 * This file provides firmware functions to manage the following
mbed_official 235:685d5f11838f 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
mbed_official 235:685d5f11838f 11 * + Initialization/de-initialization functions
mbed_official 235:685d5f11838f 12 * + Peripheral Control functions
mbed_official 235:685d5f11838f 13 * + Peripheral State functions
mbed_official 235:685d5f11838f 14 *
mbed_official 235:685d5f11838f 15 @verbatim
mbed_official 235:685d5f11838f 16 ==============================================================================
mbed_official 235:685d5f11838f 17 ##### FMC peripheral features #####
mbed_official 235:685d5f11838f 18 ==============================================================================
mbed_official 235:685d5f11838f 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
mbed_official 235:685d5f11838f 20 (+) The NOR/PSRAM memory controller
mbed_official 235:685d5f11838f 21 (+) The NAND/PC Card memory controller
mbed_official 235:685d5f11838f 22 (+) The Synchronous DRAM (SDRAM) controller
mbed_official 235:685d5f11838f 23
mbed_official 235:685d5f11838f 24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
mbed_official 235:685d5f11838f 25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
mbed_official 235:685d5f11838f 26 (+) to translate AHB transactions into the appropriate external device protocol
mbed_official 235:685d5f11838f 27 (+) to meet the access time requirements of the external memory devices
mbed_official 235:685d5f11838f 28
mbed_official 235:685d5f11838f 29 [..] All external memories share the addresses, data and control signals with the controller.
mbed_official 235:685d5f11838f 30 Each external device is accessed by means of a unique Chip Select. The FMC performs
mbed_official 235:685d5f11838f 31 only one access at a time to an external device.
mbed_official 235:685d5f11838f 32 The main features of the FMC controller are the following:
mbed_official 235:685d5f11838f 33 (+) Interface with static-memory mapped devices including:
mbed_official 235:685d5f11838f 34 (++) Static random access memory (SRAM)
mbed_official 235:685d5f11838f 35 (++) Read-only memory (ROM)
mbed_official 235:685d5f11838f 36 (++) NOR Flash memory/OneNAND Flash memory
mbed_official 235:685d5f11838f 37 (++) PSRAM (4 memory banks)
mbed_official 235:685d5f11838f 38 (++) 16-bit PC Card compatible devices
mbed_official 235:685d5f11838f 39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
mbed_official 235:685d5f11838f 40 data
mbed_official 235:685d5f11838f 41 (+) Interface with synchronous DRAM (SDRAM) memories
mbed_official 235:685d5f11838f 42 (+) Independent Chip Select control for each memory bank
mbed_official 235:685d5f11838f 43 (+) Independent configuration for each memory bank
mbed_official 235:685d5f11838f 44
mbed_official 235:685d5f11838f 45 @endverbatim
mbed_official 235:685d5f11838f 46 ******************************************************************************
mbed_official 235:685d5f11838f 47 * @attention
mbed_official 235:685d5f11838f 48 *
mbed_official 235:685d5f11838f 49 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 235:685d5f11838f 50 *
mbed_official 235:685d5f11838f 51 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 235:685d5f11838f 52 * are permitted provided that the following conditions are met:
mbed_official 235:685d5f11838f 53 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 235:685d5f11838f 54 * this list of conditions and the following disclaimer.
mbed_official 235:685d5f11838f 55 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 235:685d5f11838f 56 * this list of conditions and the following disclaimer in the documentation
mbed_official 235:685d5f11838f 57 * and/or other materials provided with the distribution.
mbed_official 235:685d5f11838f 58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 235:685d5f11838f 59 * may be used to endorse or promote products derived from this software
mbed_official 235:685d5f11838f 60 * without specific prior written permission.
mbed_official 235:685d5f11838f 61 *
mbed_official 235:685d5f11838f 62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 235:685d5f11838f 63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 235:685d5f11838f 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 235:685d5f11838f 65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 235:685d5f11838f 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 235:685d5f11838f 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 235:685d5f11838f 68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 235:685d5f11838f 69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 235:685d5f11838f 70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 235:685d5f11838f 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 235:685d5f11838f 72 *
mbed_official 235:685d5f11838f 73 ******************************************************************************
mbed_official 235:685d5f11838f 74 */
mbed_official 235:685d5f11838f 75
mbed_official 235:685d5f11838f 76 /* Includes ------------------------------------------------------------------*/
mbed_official 235:685d5f11838f 77 #include "stm32f4xx_hal.h"
mbed_official 235:685d5f11838f 78
mbed_official 235:685d5f11838f 79 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 235:685d5f11838f 80 * @{
mbed_official 235:685d5f11838f 81 */
mbed_official 235:685d5f11838f 82
mbed_official 235:685d5f11838f 83 /** @defgroup FMC
mbed_official 235:685d5f11838f 84 * @brief FMC driver modules
mbed_official 235:685d5f11838f 85 * @{
mbed_official 235:685d5f11838f 86 */
mbed_official 235:685d5f11838f 87
mbed_official 235:685d5f11838f 88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
mbed_official 235:685d5f11838f 89
mbed_official 235:685d5f11838f 90 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 235:685d5f11838f 91
mbed_official 235:685d5f11838f 92 /* Private typedef -----------------------------------------------------------*/
mbed_official 235:685d5f11838f 93 /* Private define ------------------------------------------------------------*/
mbed_official 235:685d5f11838f 94 /* Private macro -------------------------------------------------------------*/
mbed_official 235:685d5f11838f 95 /* Private variables ---------------------------------------------------------*/
mbed_official 235:685d5f11838f 96 /* Private function prototypes -----------------------------------------------*/
mbed_official 235:685d5f11838f 97 /* Private functions ---------------------------------------------------------*/
mbed_official 235:685d5f11838f 98
mbed_official 235:685d5f11838f 99 /** @defgroup FMC_Private_Functions
mbed_official 235:685d5f11838f 100 * @{
mbed_official 235:685d5f11838f 101 */
mbed_official 235:685d5f11838f 102
mbed_official 235:685d5f11838f 103 /** @defgroup FMC_NORSRAM Controller functions
mbed_official 235:685d5f11838f 104 * @brief NORSRAM Controller functions
mbed_official 235:685d5f11838f 105 *
mbed_official 235:685d5f11838f 106 @verbatim
mbed_official 235:685d5f11838f 107 ==============================================================================
mbed_official 235:685d5f11838f 108 ##### How to use NORSRAM device driver #####
mbed_official 235:685d5f11838f 109 ==============================================================================
mbed_official 235:685d5f11838f 110
mbed_official 235:685d5f11838f 111 [..]
mbed_official 235:685d5f11838f 112 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
mbed_official 235:685d5f11838f 113 to run the NORSRAM external devices.
mbed_official 235:685d5f11838f 114
mbed_official 235:685d5f11838f 115 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
mbed_official 235:685d5f11838f 116 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
mbed_official 235:685d5f11838f 117 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
mbed_official 235:685d5f11838f 118 (+) FMC NORSRAM bank extended timing configuration using the function
mbed_official 235:685d5f11838f 119 FMC_NORSRAM_Extended_Timing_Init()
mbed_official 235:685d5f11838f 120 (+) FMC NORSRAM bank enable/disable write operation using the functions
mbed_official 235:685d5f11838f 121 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
mbed_official 235:685d5f11838f 122
mbed_official 235:685d5f11838f 123
mbed_official 235:685d5f11838f 124 @endverbatim
mbed_official 235:685d5f11838f 125 * @{
mbed_official 235:685d5f11838f 126 */
mbed_official 235:685d5f11838f 127
mbed_official 235:685d5f11838f 128 /** @defgroup HAL_FMC_NORSRAM_Group1 Initialization/de-initialization functions
mbed_official 235:685d5f11838f 129 * @brief Initialization and Configuration functions
mbed_official 235:685d5f11838f 130 *
mbed_official 235:685d5f11838f 131 @verbatim
mbed_official 235:685d5f11838f 132 ==============================================================================
mbed_official 235:685d5f11838f 133 ##### Initialization and de_initialization functions #####
mbed_official 235:685d5f11838f 134 ==============================================================================
mbed_official 235:685d5f11838f 135 [..]
mbed_official 235:685d5f11838f 136 This section provides functions allowing to:
mbed_official 235:685d5f11838f 137 (+) Initialize and configure the FMC NORSRAM interface
mbed_official 235:685d5f11838f 138 (+) De-initialize the FMC NORSRAM interface
mbed_official 235:685d5f11838f 139 (+) Configure the FMC clock and associated GPIOs
mbed_official 235:685d5f11838f 140
mbed_official 235:685d5f11838f 141 @endverbatim
mbed_official 235:685d5f11838f 142 * @{
mbed_official 235:685d5f11838f 143 */
mbed_official 235:685d5f11838f 144
mbed_official 235:685d5f11838f 145 /**
mbed_official 235:685d5f11838f 146 * @brief Initialize the FMC_NORSRAM device according to the specified
mbed_official 235:685d5f11838f 147 * control parameters in the FMC_NORSRAM_InitTypeDef
mbed_official 235:685d5f11838f 148 * @param Device: Pointer to NORSRAM device instance
mbed_official 235:685d5f11838f 149 * @param Init: Pointer to NORSRAM Initialization structure
mbed_official 235:685d5f11838f 150 * @retval HAL status
mbed_official 235:685d5f11838f 151 */
mbed_official 235:685d5f11838f 152 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
mbed_official 235:685d5f11838f 153 {
mbed_official 235:685d5f11838f 154 uint32_t tmpr = 0;
mbed_official 235:685d5f11838f 155
mbed_official 235:685d5f11838f 156 /* Check the parameters */
mbed_official 235:685d5f11838f 157 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 158 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
mbed_official 235:685d5f11838f 159 assert_param(IS_FMC_MUX(Init->DataAddressMux));
mbed_official 235:685d5f11838f 160 assert_param(IS_FMC_MEMORY(Init->MemoryType));
mbed_official 235:685d5f11838f 161 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 235:685d5f11838f 162 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
mbed_official 235:685d5f11838f 163 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
mbed_official 235:685d5f11838f 164 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
mbed_official 235:685d5f11838f 165 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
mbed_official 235:685d5f11838f 166 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
mbed_official 235:685d5f11838f 167 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
mbed_official 235:685d5f11838f 168 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
mbed_official 235:685d5f11838f 169 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
mbed_official 235:685d5f11838f 170 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
mbed_official 235:685d5f11838f 171 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
mbed_official 235:685d5f11838f 172
mbed_official 235:685d5f11838f 173 /* Set NORSRAM device control parameters */
mbed_official 235:685d5f11838f 174 tmpr = (uint32_t)(Init->DataAddressMux |\
mbed_official 235:685d5f11838f 175 Init->MemoryType |\
mbed_official 235:685d5f11838f 176 Init->MemoryDataWidth |\
mbed_official 235:685d5f11838f 177 Init->BurstAccessMode |\
mbed_official 235:685d5f11838f 178 Init->WaitSignalPolarity |\
mbed_official 235:685d5f11838f 179 Init->WrapMode |\
mbed_official 235:685d5f11838f 180 Init->WaitSignalActive |\
mbed_official 235:685d5f11838f 181 Init->WriteOperation |\
mbed_official 235:685d5f11838f 182 Init->WaitSignal |\
mbed_official 235:685d5f11838f 183 Init->ExtendedMode |\
mbed_official 235:685d5f11838f 184 Init->AsynchronousWait |\
mbed_official 235:685d5f11838f 185 Init->WriteBurst |\
mbed_official 235:685d5f11838f 186 Init->ContinuousClock
mbed_official 235:685d5f11838f 187 );
mbed_official 235:685d5f11838f 188
mbed_official 235:685d5f11838f 189 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
mbed_official 235:685d5f11838f 190 {
mbed_official 235:685d5f11838f 191 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
mbed_official 235:685d5f11838f 192 }
mbed_official 235:685d5f11838f 193
mbed_official 235:685d5f11838f 194 Device->BTCR[Init->NSBank] = tmpr;
mbed_official 235:685d5f11838f 195
mbed_official 235:685d5f11838f 196 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
mbed_official 235:685d5f11838f 197 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
mbed_official 235:685d5f11838f 198 {
mbed_official 235:685d5f11838f 199 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
mbed_official 235:685d5f11838f 200 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
mbed_official 235:685d5f11838f 201 Init->ContinuousClock);
mbed_official 235:685d5f11838f 202 }
mbed_official 235:685d5f11838f 203
mbed_official 235:685d5f11838f 204 return HAL_OK;
mbed_official 235:685d5f11838f 205 }
mbed_official 235:685d5f11838f 206
mbed_official 235:685d5f11838f 207
mbed_official 235:685d5f11838f 208 /**
mbed_official 235:685d5f11838f 209 * @brief DeInitialize the FMC_NORSRAM peripheral
mbed_official 235:685d5f11838f 210 * @param Device: Pointer to NORSRAM device instance
mbed_official 235:685d5f11838f 211 * @param ExDevice: Pointer to NORSRAM extended mode device instance
mbed_official 235:685d5f11838f 212 * @param Bank: NORSRAM bank number
mbed_official 235:685d5f11838f 213 * @retval HAL status
mbed_official 235:685d5f11838f 214 */
mbed_official 235:685d5f11838f 215 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
mbed_official 235:685d5f11838f 216 {
mbed_official 235:685d5f11838f 217 /* Check the parameters */
mbed_official 235:685d5f11838f 218 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 219 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
mbed_official 235:685d5f11838f 220 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 235:685d5f11838f 221
mbed_official 235:685d5f11838f 222 /* Disable the FMC_NORSRAM device */
mbed_official 235:685d5f11838f 223 __FMC_NORSRAM_DISABLE(Device, Bank);
mbed_official 235:685d5f11838f 224
mbed_official 235:685d5f11838f 225 /* De-initialize the FMC_NORSRAM device */
mbed_official 235:685d5f11838f 226 /* FMC_NORSRAM_BANK1 */
mbed_official 235:685d5f11838f 227 if(Bank == FMC_NORSRAM_BANK1)
mbed_official 235:685d5f11838f 228 {
mbed_official 235:685d5f11838f 229 Device->BTCR[Bank] = 0x000030DB;
mbed_official 235:685d5f11838f 230 }
mbed_official 235:685d5f11838f 231 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
mbed_official 235:685d5f11838f 232 else
mbed_official 235:685d5f11838f 233 {
mbed_official 235:685d5f11838f 234 Device->BTCR[Bank] = 0x000030D2;
mbed_official 235:685d5f11838f 235 }
mbed_official 235:685d5f11838f 236
mbed_official 235:685d5f11838f 237 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
mbed_official 235:685d5f11838f 238 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
mbed_official 235:685d5f11838f 239
mbed_official 235:685d5f11838f 240 return HAL_OK;
mbed_official 235:685d5f11838f 241 }
mbed_official 235:685d5f11838f 242
mbed_official 235:685d5f11838f 243
mbed_official 235:685d5f11838f 244 /**
mbed_official 235:685d5f11838f 245 * @brief Initialize the FMC_NORSRAM Timing according to the specified
mbed_official 235:685d5f11838f 246 * parameters in the FMC_NORSRAM_TimingTypeDef
mbed_official 235:685d5f11838f 247 * @param Device: Pointer to NORSRAM device instance
mbed_official 235:685d5f11838f 248 * @param Timing: Pointer to NORSRAM Timing structure
mbed_official 235:685d5f11838f 249 * @param Bank: NORSRAM bank number
mbed_official 235:685d5f11838f 250 * @retval HAL status
mbed_official 235:685d5f11838f 251 */
mbed_official 235:685d5f11838f 252 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 235:685d5f11838f 253 {
mbed_official 235:685d5f11838f 254 uint32_t tmpr = 0;
mbed_official 235:685d5f11838f 255
mbed_official 235:685d5f11838f 256 /* Check the parameters */
mbed_official 235:685d5f11838f 257 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 258 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
mbed_official 235:685d5f11838f 259 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
mbed_official 235:685d5f11838f 260 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
mbed_official 235:685d5f11838f 261 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
mbed_official 235:685d5f11838f 262 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
mbed_official 235:685d5f11838f 263 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
mbed_official 235:685d5f11838f 264 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
mbed_official 235:685d5f11838f 265 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 235:685d5f11838f 266
mbed_official 235:685d5f11838f 267 /* Set FMC_NORSRAM device timing parameters */
mbed_official 235:685d5f11838f 268 tmpr = (uint32_t)(Timing->AddressSetupTime |\
mbed_official 235:685d5f11838f 269 ((Timing->AddressHoldTime) << 4) |\
mbed_official 235:685d5f11838f 270 ((Timing->DataSetupTime) << 8) |\
mbed_official 235:685d5f11838f 271 ((Timing->BusTurnAroundDuration) << 16) |\
mbed_official 235:685d5f11838f 272 (((Timing->CLKDivision)-1) << 20) |\
mbed_official 235:685d5f11838f 273 (((Timing->DataLatency)-2) << 24) |\
mbed_official 235:685d5f11838f 274 (Timing->AccessMode)
mbed_official 235:685d5f11838f 275 );
mbed_official 235:685d5f11838f 276
mbed_official 235:685d5f11838f 277 Device->BTCR[Bank + 1] = tmpr;
mbed_official 235:685d5f11838f 278
mbed_official 235:685d5f11838f 279 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
mbed_official 235:685d5f11838f 280 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
mbed_official 235:685d5f11838f 281 {
mbed_official 235:685d5f11838f 282 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
mbed_official 235:685d5f11838f 283 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
mbed_official 235:685d5f11838f 284 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
mbed_official 235:685d5f11838f 285 }
mbed_official 235:685d5f11838f 286
mbed_official 235:685d5f11838f 287 return HAL_OK;
mbed_official 235:685d5f11838f 288 }
mbed_official 235:685d5f11838f 289
mbed_official 235:685d5f11838f 290 /**
mbed_official 235:685d5f11838f 291 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
mbed_official 235:685d5f11838f 292 * parameters in the FMC_NORSRAM_TimingTypeDef
mbed_official 235:685d5f11838f 293 * @param Device: Pointer to NORSRAM device instance
mbed_official 235:685d5f11838f 294 * @param Timing: Pointer to NORSRAM Timing structure
mbed_official 235:685d5f11838f 295 * @param Bank: NORSRAM bank number
mbed_official 235:685d5f11838f 296 * @retval HAL status
mbed_official 235:685d5f11838f 297 */
mbed_official 235:685d5f11838f 298 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
mbed_official 235:685d5f11838f 299 {
mbed_official 235:685d5f11838f 300 /* Check the parameters */
mbed_official 235:685d5f11838f 301 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
mbed_official 235:685d5f11838f 302
mbed_official 235:685d5f11838f 303 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
mbed_official 235:685d5f11838f 304 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
mbed_official 235:685d5f11838f 305 {
mbed_official 235:685d5f11838f 306 /* Check the parameters */
mbed_official 235:685d5f11838f 307 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
mbed_official 235:685d5f11838f 308 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
mbed_official 235:685d5f11838f 309 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
mbed_official 235:685d5f11838f 310 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
mbed_official 235:685d5f11838f 311 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
mbed_official 235:685d5f11838f 312 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
mbed_official 235:685d5f11838f 313 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
mbed_official 235:685d5f11838f 314 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
mbed_official 235:685d5f11838f 315 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 235:685d5f11838f 316
mbed_official 235:685d5f11838f 317 Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime |\
mbed_official 235:685d5f11838f 318 ((Timing->AddressHoldTime) << 4) |\
mbed_official 235:685d5f11838f 319 ((Timing->DataSetupTime) << 8) |\
mbed_official 235:685d5f11838f 320 ((Timing->BusTurnAroundDuration) << 16) |\
mbed_official 235:685d5f11838f 321 (((Timing->CLKDivision)-1) << 20) |\
mbed_official 235:685d5f11838f 322 (((Timing->DataLatency)-2) << 24) |\
mbed_official 235:685d5f11838f 323 (Timing->AccessMode));
mbed_official 235:685d5f11838f 324 }
mbed_official 235:685d5f11838f 325 else
mbed_official 235:685d5f11838f 326 {
mbed_official 235:685d5f11838f 327 Device->BWTR[Bank] = 0x0FFFFFFF;
mbed_official 235:685d5f11838f 328 }
mbed_official 235:685d5f11838f 329
mbed_official 235:685d5f11838f 330 return HAL_OK;
mbed_official 235:685d5f11838f 331 }
mbed_official 235:685d5f11838f 332
mbed_official 235:685d5f11838f 333
mbed_official 235:685d5f11838f 334 /**
mbed_official 235:685d5f11838f 335 * @}
mbed_official 235:685d5f11838f 336 */
mbed_official 235:685d5f11838f 337
mbed_official 235:685d5f11838f 338
mbed_official 235:685d5f11838f 339 /** @defgroup HAL_FMC_NORSRAM_Group3 Control functions
mbed_official 235:685d5f11838f 340 * @brief management functions
mbed_official 235:685d5f11838f 341 *
mbed_official 235:685d5f11838f 342 @verbatim
mbed_official 235:685d5f11838f 343 ==============================================================================
mbed_official 235:685d5f11838f 344 ##### FMC_NORSRAM Control functions #####
mbed_official 235:685d5f11838f 345 ==============================================================================
mbed_official 235:685d5f11838f 346 [..]
mbed_official 235:685d5f11838f 347 This subsection provides a set of functions allowing to control dynamically
mbed_official 235:685d5f11838f 348 the FMC NORSRAM interface.
mbed_official 235:685d5f11838f 349
mbed_official 235:685d5f11838f 350 @endverbatim
mbed_official 235:685d5f11838f 351 * @{
mbed_official 235:685d5f11838f 352 */
mbed_official 235:685d5f11838f 353
mbed_official 235:685d5f11838f 354 /**
mbed_official 235:685d5f11838f 355 * @brief Enables dynamically FMC_NORSRAM write operation.
mbed_official 235:685d5f11838f 356 * @param Device: Pointer to NORSRAM device instance
mbed_official 235:685d5f11838f 357 * @param Bank: NORSRAM bank number
mbed_official 235:685d5f11838f 358 * @retval HAL status
mbed_official 235:685d5f11838f 359 */
mbed_official 235:685d5f11838f 360 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
mbed_official 235:685d5f11838f 361 {
mbed_official 235:685d5f11838f 362 /* Check the parameters */
mbed_official 235:685d5f11838f 363 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 364 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 235:685d5f11838f 365
mbed_official 235:685d5f11838f 366 /* Enable write operation */
mbed_official 235:685d5f11838f 367 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
mbed_official 235:685d5f11838f 368
mbed_official 235:685d5f11838f 369 return HAL_OK;
mbed_official 235:685d5f11838f 370 }
mbed_official 235:685d5f11838f 371
mbed_official 235:685d5f11838f 372 /**
mbed_official 235:685d5f11838f 373 * @brief Disables dynamically FMC_NORSRAM write operation.
mbed_official 235:685d5f11838f 374 * @param Device: Pointer to NORSRAM device instance
mbed_official 235:685d5f11838f 375 * @param Bank: NORSRAM bank number
mbed_official 235:685d5f11838f 376 * @retval HAL status
mbed_official 235:685d5f11838f 377 */
mbed_official 235:685d5f11838f 378 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
mbed_official 235:685d5f11838f 379 {
mbed_official 235:685d5f11838f 380 /* Check the parameters */
mbed_official 235:685d5f11838f 381 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 382 assert_param(IS_FMC_NORSRAM_BANK(Bank));
mbed_official 235:685d5f11838f 383
mbed_official 235:685d5f11838f 384 /* Disable write operation */
mbed_official 235:685d5f11838f 385 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
mbed_official 235:685d5f11838f 386
mbed_official 235:685d5f11838f 387 return HAL_OK;
mbed_official 235:685d5f11838f 388 }
mbed_official 235:685d5f11838f 389
mbed_official 235:685d5f11838f 390 /**
mbed_official 235:685d5f11838f 391 * @}
mbed_official 235:685d5f11838f 392 */
mbed_official 235:685d5f11838f 393
mbed_official 235:685d5f11838f 394 /**
mbed_official 235:685d5f11838f 395 * @}
mbed_official 235:685d5f11838f 396 */
mbed_official 235:685d5f11838f 397
mbed_official 235:685d5f11838f 398 /** @defgroup FMC_PCCARD Controller functions
mbed_official 235:685d5f11838f 399 * @brief PCCARD Controller functions
mbed_official 235:685d5f11838f 400 *
mbed_official 235:685d5f11838f 401 @verbatim
mbed_official 235:685d5f11838f 402 ==============================================================================
mbed_official 235:685d5f11838f 403 ##### How to use NAND device driver #####
mbed_official 235:685d5f11838f 404 ==============================================================================
mbed_official 235:685d5f11838f 405 [..]
mbed_official 235:685d5f11838f 406 This driver contains a set of APIs to interface with the FMC NAND banks in order
mbed_official 235:685d5f11838f 407 to run the NAND external devices.
mbed_official 235:685d5f11838f 408
mbed_official 235:685d5f11838f 409 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
mbed_official 235:685d5f11838f 410 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
mbed_official 235:685d5f11838f 411 (+) FMC NAND bank common space timing configuration using the function
mbed_official 235:685d5f11838f 412 FMC_NAND_CommonSpace_Timing_Init()
mbed_official 235:685d5f11838f 413 (+) FMC NAND bank attribute space timing configuration using the function
mbed_official 235:685d5f11838f 414 FMC_NAND_AttributeSpace_Timing_Init()
mbed_official 235:685d5f11838f 415 (+) FMC NAND bank enable/disable ECC correction feature using the functions
mbed_official 235:685d5f11838f 416 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
mbed_official 235:685d5f11838f 417 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
mbed_official 235:685d5f11838f 418
mbed_official 235:685d5f11838f 419 @endverbatim
mbed_official 235:685d5f11838f 420 * @{
mbed_official 235:685d5f11838f 421 */
mbed_official 235:685d5f11838f 422
mbed_official 235:685d5f11838f 423 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
mbed_official 235:685d5f11838f 424 * @brief Initialization and Configuration functions
mbed_official 235:685d5f11838f 425 *
mbed_official 235:685d5f11838f 426 @verbatim
mbed_official 235:685d5f11838f 427 ==============================================================================
mbed_official 235:685d5f11838f 428 ##### Initialization and de_initialization functions #####
mbed_official 235:685d5f11838f 429 ==============================================================================
mbed_official 235:685d5f11838f 430 [..]
mbed_official 235:685d5f11838f 431 This section provides functions allowing to:
mbed_official 235:685d5f11838f 432 (+) Initialize and configure the FMC NAND interface
mbed_official 235:685d5f11838f 433 (+) De-initialize the FMC NAND interface
mbed_official 235:685d5f11838f 434 (+) Configure the FMC clock and associated GPIOs
mbed_official 235:685d5f11838f 435
mbed_official 235:685d5f11838f 436 @endverbatim
mbed_official 235:685d5f11838f 437 * @{
mbed_official 235:685d5f11838f 438 */
mbed_official 235:685d5f11838f 439
mbed_official 235:685d5f11838f 440 /**
mbed_official 235:685d5f11838f 441 * @brief Initializes the FMC_NAND device according to the specified
mbed_official 235:685d5f11838f 442 * control parameters in the FMC_NAND_HandleTypeDef
mbed_official 235:685d5f11838f 443 * @param Device: Pointer to NAND device instance
mbed_official 235:685d5f11838f 444 * @param Init: Pointer to NAND Initialization structure
mbed_official 235:685d5f11838f 445 * @retval HAL status
mbed_official 235:685d5f11838f 446 */
mbed_official 235:685d5f11838f 447 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
mbed_official 235:685d5f11838f 448 {
mbed_official 235:685d5f11838f 449 uint32_t tmppcr = 0;
mbed_official 235:685d5f11838f 450
mbed_official 235:685d5f11838f 451 /* Check the parameters */
mbed_official 235:685d5f11838f 452 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 235:685d5f11838f 453 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
mbed_official 235:685d5f11838f 454 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
mbed_official 235:685d5f11838f 455 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 235:685d5f11838f 456 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
mbed_official 235:685d5f11838f 457 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
mbed_official 235:685d5f11838f 458 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
mbed_official 235:685d5f11838f 459 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
mbed_official 235:685d5f11838f 460
mbed_official 235:685d5f11838f 461 /* Set NAND device control parameters */
mbed_official 235:685d5f11838f 462 tmppcr = (uint32_t)(Init->Waitfeature |\
mbed_official 235:685d5f11838f 463 FMC_PCR_MEMORY_TYPE_NAND |\
mbed_official 235:685d5f11838f 464 Init->MemoryDataWidth |\
mbed_official 235:685d5f11838f 465 Init->EccComputation |\
mbed_official 235:685d5f11838f 466 Init->ECCPageSize |\
mbed_official 235:685d5f11838f 467 ((Init->TCLRSetupTime) << 9) |\
mbed_official 235:685d5f11838f 468 ((Init->TARSetupTime) << 13)
mbed_official 235:685d5f11838f 469 );
mbed_official 235:685d5f11838f 470
mbed_official 235:685d5f11838f 471 if(Init->NandBank == FMC_NAND_BANK2)
mbed_official 235:685d5f11838f 472 {
mbed_official 235:685d5f11838f 473 /* NAND bank 2 registers configuration */
mbed_official 235:685d5f11838f 474 Device->PCR2 = tmppcr;
mbed_official 235:685d5f11838f 475 }
mbed_official 235:685d5f11838f 476 else
mbed_official 235:685d5f11838f 477 {
mbed_official 235:685d5f11838f 478 /* NAND bank 3 registers configuration */
mbed_official 235:685d5f11838f 479 Device->PCR3 = tmppcr;
mbed_official 235:685d5f11838f 480 }
mbed_official 235:685d5f11838f 481
mbed_official 235:685d5f11838f 482 return HAL_OK;
mbed_official 235:685d5f11838f 483
mbed_official 235:685d5f11838f 484 }
mbed_official 235:685d5f11838f 485
mbed_official 235:685d5f11838f 486 /**
mbed_official 235:685d5f11838f 487 * @brief Initializes the FMC_NAND Common space Timing according to the specified
mbed_official 235:685d5f11838f 488 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 235:685d5f11838f 489 * @param Device: Pointer to NAND device instance
mbed_official 235:685d5f11838f 490 * @param Timing: Pointer to NAND timing structure
mbed_official 235:685d5f11838f 491 * @param Bank: NAND bank number
mbed_official 235:685d5f11838f 492 * @retval HAL status
mbed_official 235:685d5f11838f 493 */
mbed_official 235:685d5f11838f 494 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 235:685d5f11838f 495 {
mbed_official 235:685d5f11838f 496 uint32_t tmppmem = 0;
mbed_official 235:685d5f11838f 497
mbed_official 235:685d5f11838f 498 /* Check the parameters */
mbed_official 235:685d5f11838f 499 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 235:685d5f11838f 500 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 235:685d5f11838f 501 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 235:685d5f11838f 502 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 235:685d5f11838f 503 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 235:685d5f11838f 504 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 235:685d5f11838f 505
mbed_official 235:685d5f11838f 506 /* Set FMC_NAND device timing parameters */
mbed_official 235:685d5f11838f 507 tmppmem = (uint32_t)(Timing->SetupTime |\
mbed_official 235:685d5f11838f 508 ((Timing->WaitSetupTime) << 8) |\
mbed_official 235:685d5f11838f 509 ((Timing->HoldSetupTime) << 16) |\
mbed_official 235:685d5f11838f 510 ((Timing->HiZSetupTime) << 24)
mbed_official 235:685d5f11838f 511 );
mbed_official 235:685d5f11838f 512
mbed_official 235:685d5f11838f 513 if(Bank == FMC_NAND_BANK2)
mbed_official 235:685d5f11838f 514 {
mbed_official 235:685d5f11838f 515 /* NAND bank 2 registers configuration */
mbed_official 235:685d5f11838f 516 Device->PMEM2 = tmppmem;
mbed_official 235:685d5f11838f 517 }
mbed_official 235:685d5f11838f 518 else
mbed_official 235:685d5f11838f 519 {
mbed_official 235:685d5f11838f 520 /* NAND bank 3 registers configuration */
mbed_official 235:685d5f11838f 521 Device->PMEM3 = tmppmem;
mbed_official 235:685d5f11838f 522 }
mbed_official 235:685d5f11838f 523
mbed_official 235:685d5f11838f 524 return HAL_OK;
mbed_official 235:685d5f11838f 525 }
mbed_official 235:685d5f11838f 526
mbed_official 235:685d5f11838f 527 /**
mbed_official 235:685d5f11838f 528 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
mbed_official 235:685d5f11838f 529 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 235:685d5f11838f 530 * @param Device: Pointer to NAND device instance
mbed_official 235:685d5f11838f 531 * @param Timing: Pointer to NAND timing structure
mbed_official 235:685d5f11838f 532 * @param Bank: NAND bank number
mbed_official 235:685d5f11838f 533 * @retval HAL status
mbed_official 235:685d5f11838f 534 */
mbed_official 235:685d5f11838f 535 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 235:685d5f11838f 536 {
mbed_official 235:685d5f11838f 537 uint32_t tmppatt = 0;
mbed_official 235:685d5f11838f 538
mbed_official 235:685d5f11838f 539 /* Check the parameters */
mbed_official 235:685d5f11838f 540 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 235:685d5f11838f 541 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 235:685d5f11838f 542 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 235:685d5f11838f 543 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 235:685d5f11838f 544 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 235:685d5f11838f 545 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 235:685d5f11838f 546
mbed_official 235:685d5f11838f 547 /* Set FMC_NAND device timing parameters */
mbed_official 235:685d5f11838f 548 tmppatt = (uint32_t)(Timing->SetupTime |\
mbed_official 235:685d5f11838f 549 ((Timing->WaitSetupTime) << 8) |\
mbed_official 235:685d5f11838f 550 ((Timing->HoldSetupTime) << 16) |\
mbed_official 235:685d5f11838f 551 ((Timing->HiZSetupTime) << 24)
mbed_official 235:685d5f11838f 552 );
mbed_official 235:685d5f11838f 553
mbed_official 235:685d5f11838f 554 if(Bank == FMC_NAND_BANK2)
mbed_official 235:685d5f11838f 555 {
mbed_official 235:685d5f11838f 556 /* NAND bank 2 registers configuration */
mbed_official 235:685d5f11838f 557 Device->PATT2 = tmppatt;
mbed_official 235:685d5f11838f 558 }
mbed_official 235:685d5f11838f 559 else
mbed_official 235:685d5f11838f 560 {
mbed_official 235:685d5f11838f 561 /* NAND bank 3 registers configuration */
mbed_official 235:685d5f11838f 562 Device->PATT3 = tmppatt;
mbed_official 235:685d5f11838f 563 }
mbed_official 235:685d5f11838f 564
mbed_official 235:685d5f11838f 565 return HAL_OK;
mbed_official 235:685d5f11838f 566 }
mbed_official 235:685d5f11838f 567
mbed_official 235:685d5f11838f 568
mbed_official 235:685d5f11838f 569 /**
mbed_official 235:685d5f11838f 570 * @brief DeInitializes the FMC_NAND device
mbed_official 235:685d5f11838f 571 * @param Device: Pointer to NAND device instance
mbed_official 235:685d5f11838f 572 * @param Bank: NAND bank number
mbed_official 235:685d5f11838f 573 * @retval HAL status
mbed_official 235:685d5f11838f 574 */
mbed_official 235:685d5f11838f 575 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 235:685d5f11838f 576 {
mbed_official 235:685d5f11838f 577 /* Check the parameters */
mbed_official 235:685d5f11838f 578 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 235:685d5f11838f 579 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 235:685d5f11838f 580
mbed_official 235:685d5f11838f 581 /* Disable the NAND Bank */
mbed_official 235:685d5f11838f 582 __FMC_NAND_DISABLE(Device, Bank);
mbed_official 235:685d5f11838f 583
mbed_official 235:685d5f11838f 584 /* De-initialize the NAND Bank */
mbed_official 235:685d5f11838f 585 if(Bank == FMC_NAND_BANK2)
mbed_official 235:685d5f11838f 586 {
mbed_official 235:685d5f11838f 587 /* Set the FMC_NAND_BANK2 registers to their reset values */
mbed_official 235:685d5f11838f 588 Device->PCR2 = 0x00000018;
mbed_official 235:685d5f11838f 589 Device->SR2 = 0x00000040;
mbed_official 235:685d5f11838f 590 Device->PMEM2 = 0xFCFCFCFC;
mbed_official 235:685d5f11838f 591 Device->PATT2 = 0xFCFCFCFC;
mbed_official 235:685d5f11838f 592 }
mbed_official 235:685d5f11838f 593 /* FMC_Bank3_NAND */
mbed_official 235:685d5f11838f 594 else
mbed_official 235:685d5f11838f 595 {
mbed_official 235:685d5f11838f 596 /* Set the FMC_NAND_BANK3 registers to their reset values */
mbed_official 235:685d5f11838f 597 Device->PCR3 = 0x00000018;
mbed_official 235:685d5f11838f 598 Device->SR3 = 0x00000040;
mbed_official 235:685d5f11838f 599 Device->PMEM3 = 0xFCFCFCFC;
mbed_official 235:685d5f11838f 600 Device->PATT3 = 0xFCFCFCFC;
mbed_official 235:685d5f11838f 601 }
mbed_official 235:685d5f11838f 602
mbed_official 235:685d5f11838f 603 return HAL_OK;
mbed_official 235:685d5f11838f 604 }
mbed_official 235:685d5f11838f 605
mbed_official 235:685d5f11838f 606 /**
mbed_official 235:685d5f11838f 607 * @}
mbed_official 235:685d5f11838f 608 */
mbed_official 235:685d5f11838f 609
mbed_official 235:685d5f11838f 610
mbed_official 235:685d5f11838f 611 /** @defgroup HAL_FMC_NAND_Group3 Control functions
mbed_official 235:685d5f11838f 612 * @brief management functions
mbed_official 235:685d5f11838f 613 *
mbed_official 235:685d5f11838f 614 @verbatim
mbed_official 235:685d5f11838f 615 ==============================================================================
mbed_official 235:685d5f11838f 616 ##### FMC_NAND Control functions #####
mbed_official 235:685d5f11838f 617 ==============================================================================
mbed_official 235:685d5f11838f 618 [..]
mbed_official 235:685d5f11838f 619 This subsection provides a set of functions allowing to control dynamically
mbed_official 235:685d5f11838f 620 the FMC NAND interface.
mbed_official 235:685d5f11838f 621
mbed_official 235:685d5f11838f 622 @endverbatim
mbed_official 235:685d5f11838f 623 * @{
mbed_official 235:685d5f11838f 624 */
mbed_official 235:685d5f11838f 625
mbed_official 235:685d5f11838f 626
mbed_official 235:685d5f11838f 627 /**
mbed_official 235:685d5f11838f 628 * @brief Enables dynamically FMC_NAND ECC feature.
mbed_official 235:685d5f11838f 629 * @param Device: Pointer to NAND device instance
mbed_official 235:685d5f11838f 630 * @param Bank: NAND bank number
mbed_official 235:685d5f11838f 631 * @retval HAL status
mbed_official 235:685d5f11838f 632 */
mbed_official 235:685d5f11838f 633 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 235:685d5f11838f 634 {
mbed_official 235:685d5f11838f 635 /* Check the parameters */
mbed_official 235:685d5f11838f 636 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 235:685d5f11838f 637 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 235:685d5f11838f 638
mbed_official 235:685d5f11838f 639 /* Enable ECC feature */
mbed_official 235:685d5f11838f 640 if(Bank == FMC_NAND_BANK2)
mbed_official 235:685d5f11838f 641 {
mbed_official 235:685d5f11838f 642 Device->PCR2 |= FMC_PCR2_ECCEN;
mbed_official 235:685d5f11838f 643 }
mbed_official 235:685d5f11838f 644 else
mbed_official 235:685d5f11838f 645 {
mbed_official 235:685d5f11838f 646 Device->PCR3 |= FMC_PCR3_ECCEN;
mbed_official 235:685d5f11838f 647 }
mbed_official 235:685d5f11838f 648
mbed_official 235:685d5f11838f 649 return HAL_OK;
mbed_official 235:685d5f11838f 650 }
mbed_official 235:685d5f11838f 651
mbed_official 235:685d5f11838f 652
mbed_official 235:685d5f11838f 653 /**
mbed_official 235:685d5f11838f 654 * @brief Disables dynamically FMC_NAND ECC feature.
mbed_official 235:685d5f11838f 655 * @param Device: Pointer to NAND device instance
mbed_official 235:685d5f11838f 656 * @param Bank: NAND bank number
mbed_official 235:685d5f11838f 657 * @retval HAL status
mbed_official 235:685d5f11838f 658 */
mbed_official 235:685d5f11838f 659 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
mbed_official 235:685d5f11838f 660 {
mbed_official 235:685d5f11838f 661 /* Check the parameters */
mbed_official 235:685d5f11838f 662 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 235:685d5f11838f 663 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 235:685d5f11838f 664
mbed_official 235:685d5f11838f 665 /* Disable ECC feature */
mbed_official 235:685d5f11838f 666 if(Bank == FMC_NAND_BANK2)
mbed_official 235:685d5f11838f 667 {
mbed_official 235:685d5f11838f 668 Device->PCR2 &= ~FMC_PCR2_ECCEN;
mbed_official 235:685d5f11838f 669 }
mbed_official 235:685d5f11838f 670 else
mbed_official 235:685d5f11838f 671 {
mbed_official 235:685d5f11838f 672 Device->PCR3 &= ~FMC_PCR3_ECCEN;
mbed_official 235:685d5f11838f 673 }
mbed_official 235:685d5f11838f 674
mbed_official 235:685d5f11838f 675 return HAL_OK;
mbed_official 235:685d5f11838f 676 }
mbed_official 235:685d5f11838f 677
mbed_official 235:685d5f11838f 678 /**
mbed_official 235:685d5f11838f 679 * @brief Disables dynamically FMC_NAND ECC feature.
mbed_official 235:685d5f11838f 680 * @param Device: Pointer to NAND device instance
mbed_official 235:685d5f11838f 681 * @param ECCval: Pointer to ECC value
mbed_official 235:685d5f11838f 682 * @param Bank: NAND bank number
mbed_official 235:685d5f11838f 683 * @param Timeout: Timeout wait value
mbed_official 235:685d5f11838f 684 * @retval HAL status
mbed_official 235:685d5f11838f 685 */
mbed_official 235:685d5f11838f 686 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
mbed_official 235:685d5f11838f 687 {
mbed_official 235:685d5f11838f 688 uint32_t tickstart = 0;
mbed_official 235:685d5f11838f 689
mbed_official 235:685d5f11838f 690 /* Check the parameters */
mbed_official 235:685d5f11838f 691 assert_param(IS_FMC_NAND_DEVICE(Device));
mbed_official 235:685d5f11838f 692 assert_param(IS_FMC_NAND_BANK(Bank));
mbed_official 235:685d5f11838f 693
mbed_official 235:685d5f11838f 694 /* Get tick */
mbed_official 235:685d5f11838f 695 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 696
mbed_official 235:685d5f11838f 697 /* Wait untill FIFO is empty */
mbed_official 235:685d5f11838f 698 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT))
mbed_official 235:685d5f11838f 699 {
mbed_official 235:685d5f11838f 700 /* Check for the Timeout */
mbed_official 235:685d5f11838f 701 if(Timeout != HAL_MAX_DELAY)
mbed_official 235:685d5f11838f 702 {
mbed_official 235:685d5f11838f 703 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
mbed_official 235:685d5f11838f 704 {
mbed_official 235:685d5f11838f 705 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 706 }
mbed_official 235:685d5f11838f 707 }
mbed_official 235:685d5f11838f 708 }
mbed_official 235:685d5f11838f 709
mbed_official 235:685d5f11838f 710 if(Bank == FMC_NAND_BANK2)
mbed_official 235:685d5f11838f 711 {
mbed_official 235:685d5f11838f 712 /* Get the ECCR2 register value */
mbed_official 235:685d5f11838f 713 *ECCval = (uint32_t)Device->ECCR2;
mbed_official 235:685d5f11838f 714 }
mbed_official 235:685d5f11838f 715 else
mbed_official 235:685d5f11838f 716 {
mbed_official 235:685d5f11838f 717 /* Get the ECCR3 register value */
mbed_official 235:685d5f11838f 718 *ECCval = (uint32_t)Device->ECCR3;
mbed_official 235:685d5f11838f 719 }
mbed_official 235:685d5f11838f 720
mbed_official 235:685d5f11838f 721 return HAL_OK;
mbed_official 235:685d5f11838f 722 }
mbed_official 235:685d5f11838f 723
mbed_official 235:685d5f11838f 724 /**
mbed_official 235:685d5f11838f 725 * @}
mbed_official 235:685d5f11838f 726 */
mbed_official 235:685d5f11838f 727
mbed_official 235:685d5f11838f 728 /**
mbed_official 235:685d5f11838f 729 * @}
mbed_official 235:685d5f11838f 730 */
mbed_official 235:685d5f11838f 731
mbed_official 235:685d5f11838f 732 /** @defgroup FMC_PCCARD Controller functions
mbed_official 235:685d5f11838f 733 * @brief PCCARD Controller functions
mbed_official 235:685d5f11838f 734 *
mbed_official 235:685d5f11838f 735 @verbatim
mbed_official 235:685d5f11838f 736 ==============================================================================
mbed_official 235:685d5f11838f 737 ##### How to use PCCARD device driver #####
mbed_official 235:685d5f11838f 738 ==============================================================================
mbed_official 235:685d5f11838f 739 [..]
mbed_official 235:685d5f11838f 740 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
mbed_official 235:685d5f11838f 741 to run the PCCARD/compact flash external devices.
mbed_official 235:685d5f11838f 742
mbed_official 235:685d5f11838f 743 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
mbed_official 235:685d5f11838f 744 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
mbed_official 235:685d5f11838f 745 (+) FMC PCCARD bank common space timing configuration using the function
mbed_official 235:685d5f11838f 746 FMC_PCCARD_CommonSpace_Timing_Init()
mbed_official 235:685d5f11838f 747 (+) FMC PCCARD bank attribute space timing configuration using the function
mbed_official 235:685d5f11838f 748 FMC_PCCARD_AttributeSpace_Timing_Init()
mbed_official 235:685d5f11838f 749 (+) FMC PCCARD bank IO space timing configuration using the function
mbed_official 235:685d5f11838f 750 FMC_PCCARD_IOSpace_Timing_Init()
mbed_official 235:685d5f11838f 751
mbed_official 235:685d5f11838f 752
mbed_official 235:685d5f11838f 753 @endverbatim
mbed_official 235:685d5f11838f 754 * @{
mbed_official 235:685d5f11838f 755 */
mbed_official 235:685d5f11838f 756
mbed_official 235:685d5f11838f 757 /** @defgroup HAL_FMC_PCCARD_Group1 Initialization/de-initialization functions
mbed_official 235:685d5f11838f 758 * @brief Initialization and Configuration functions
mbed_official 235:685d5f11838f 759 *
mbed_official 235:685d5f11838f 760 @verbatim
mbed_official 235:685d5f11838f 761 ==============================================================================
mbed_official 235:685d5f11838f 762 ##### Initialization and de_initialization functions #####
mbed_official 235:685d5f11838f 763 ==============================================================================
mbed_official 235:685d5f11838f 764 [..]
mbed_official 235:685d5f11838f 765 This section provides functions allowing to:
mbed_official 235:685d5f11838f 766 (+) Initialize and configure the FMC PCCARD interface
mbed_official 235:685d5f11838f 767 (+) De-initialize the FMC PCCARD interface
mbed_official 235:685d5f11838f 768 (+) Configure the FMC clock and associated GPIOs
mbed_official 235:685d5f11838f 769
mbed_official 235:685d5f11838f 770 @endverbatim
mbed_official 235:685d5f11838f 771 * @{
mbed_official 235:685d5f11838f 772 */
mbed_official 235:685d5f11838f 773
mbed_official 235:685d5f11838f 774 /**
mbed_official 235:685d5f11838f 775 * @brief Initializes the FMC_PCCARD device according to the specified
mbed_official 235:685d5f11838f 776 * control parameters in the FMC_PCCARD_HandleTypeDef
mbed_official 235:685d5f11838f 777 * @param Device: Pointer to PCCARD device instance
mbed_official 235:685d5f11838f 778 * @param Init: Pointer to PCCARD Initialization structure
mbed_official 235:685d5f11838f 779 * @retval HAL status
mbed_official 235:685d5f11838f 780 */
mbed_official 235:685d5f11838f 781 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
mbed_official 235:685d5f11838f 782 {
mbed_official 235:685d5f11838f 783 /* Check the parameters */
mbed_official 235:685d5f11838f 784 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 235:685d5f11838f 785 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
mbed_official 235:685d5f11838f 786 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
mbed_official 235:685d5f11838f 787 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
mbed_official 235:685d5f11838f 788
mbed_official 235:685d5f11838f 789 /* Set FMC_PCCARD device control parameters */
mbed_official 235:685d5f11838f 790 Device->PCR4 = (uint32_t)(Init->Waitfeature |\
mbed_official 235:685d5f11838f 791 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
mbed_official 235:685d5f11838f 792 (Init->TCLRSetupTime << 9) |\
mbed_official 235:685d5f11838f 793 (Init->TARSetupTime << 13));
mbed_official 235:685d5f11838f 794
mbed_official 235:685d5f11838f 795 return HAL_OK;
mbed_official 235:685d5f11838f 796
mbed_official 235:685d5f11838f 797 }
mbed_official 235:685d5f11838f 798
mbed_official 235:685d5f11838f 799 /**
mbed_official 235:685d5f11838f 800 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
mbed_official 235:685d5f11838f 801 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 235:685d5f11838f 802 * @param Device: Pointer to PCCARD device instance
mbed_official 235:685d5f11838f 803 * @param Timing: Pointer to PCCARD timing structure
mbed_official 235:685d5f11838f 804 * @retval HAL status
mbed_official 235:685d5f11838f 805 */
mbed_official 235:685d5f11838f 806 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
mbed_official 235:685d5f11838f 807 {
mbed_official 235:685d5f11838f 808 /* Check the parameters */
mbed_official 235:685d5f11838f 809 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 235:685d5f11838f 810 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 235:685d5f11838f 811 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 235:685d5f11838f 812 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 235:685d5f11838f 813 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 235:685d5f11838f 814
mbed_official 235:685d5f11838f 815 /* Set PCCARD timing parameters */
mbed_official 235:685d5f11838f 816 Device->PMEM4 = (uint32_t)((Timing->SetupTime |\
mbed_official 235:685d5f11838f 817 ((Timing->WaitSetupTime) << 8) |\
mbed_official 235:685d5f11838f 818 (Timing->HoldSetupTime) << 16) |\
mbed_official 235:685d5f11838f 819 ((Timing->HiZSetupTime) << 24)
mbed_official 235:685d5f11838f 820 );
mbed_official 235:685d5f11838f 821
mbed_official 235:685d5f11838f 822 return HAL_OK;
mbed_official 235:685d5f11838f 823 }
mbed_official 235:685d5f11838f 824
mbed_official 235:685d5f11838f 825 /**
mbed_official 235:685d5f11838f 826 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
mbed_official 235:685d5f11838f 827 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 235:685d5f11838f 828 * @param Device: Pointer to PCCARD device instance
mbed_official 235:685d5f11838f 829 * @param Timing: Pointer to PCCARD timing structure
mbed_official 235:685d5f11838f 830 * @retval HAL status
mbed_official 235:685d5f11838f 831 */
mbed_official 235:685d5f11838f 832 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
mbed_official 235:685d5f11838f 833 {
mbed_official 235:685d5f11838f 834 /* Check the parameters */
mbed_official 235:685d5f11838f 835 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 235:685d5f11838f 836 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 235:685d5f11838f 837 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 235:685d5f11838f 838 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 235:685d5f11838f 839 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 235:685d5f11838f 840
mbed_official 235:685d5f11838f 841 /* Set PCCARD timing parameters */
mbed_official 235:685d5f11838f 842 Device->PATT4 = (uint32_t)((Timing->SetupTime |\
mbed_official 235:685d5f11838f 843 ((Timing->WaitSetupTime) << 8) |\
mbed_official 235:685d5f11838f 844 (Timing->HoldSetupTime) << 16) |\
mbed_official 235:685d5f11838f 845 ((Timing->HiZSetupTime) << 24)
mbed_official 235:685d5f11838f 846 );
mbed_official 235:685d5f11838f 847
mbed_official 235:685d5f11838f 848 return HAL_OK;
mbed_official 235:685d5f11838f 849 }
mbed_official 235:685d5f11838f 850
mbed_official 235:685d5f11838f 851 /**
mbed_official 235:685d5f11838f 852 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
mbed_official 235:685d5f11838f 853 * parameters in the FMC_NAND_PCC_TimingTypeDef
mbed_official 235:685d5f11838f 854 * @param Device: Pointer to PCCARD device instance
mbed_official 235:685d5f11838f 855 * @param Timing: Pointer to PCCARD timing structure
mbed_official 235:685d5f11838f 856 * @retval HAL status
mbed_official 235:685d5f11838f 857 */
mbed_official 235:685d5f11838f 858 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
mbed_official 235:685d5f11838f 859 {
mbed_official 235:685d5f11838f 860 /* Check the parameters */
mbed_official 235:685d5f11838f 861 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 235:685d5f11838f 862 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
mbed_official 235:685d5f11838f 863 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
mbed_official 235:685d5f11838f 864 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
mbed_official 235:685d5f11838f 865 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
mbed_official 235:685d5f11838f 866
mbed_official 235:685d5f11838f 867 /* Set FMC_PCCARD device timing parameters */
mbed_official 235:685d5f11838f 868 Device->PIO4 = (uint32_t)((Timing->SetupTime |\
mbed_official 235:685d5f11838f 869 ((Timing->WaitSetupTime) << 8) |\
mbed_official 235:685d5f11838f 870 (Timing->HoldSetupTime) << 16) |\
mbed_official 235:685d5f11838f 871 ((Timing->HiZSetupTime) << 24)
mbed_official 235:685d5f11838f 872 );
mbed_official 235:685d5f11838f 873
mbed_official 235:685d5f11838f 874 return HAL_OK;
mbed_official 235:685d5f11838f 875 }
mbed_official 235:685d5f11838f 876
mbed_official 235:685d5f11838f 877 /**
mbed_official 235:685d5f11838f 878 * @brief DeInitializes the FMC_PCCARD device
mbed_official 235:685d5f11838f 879 * @param Device: Pointer to PCCARD device instance
mbed_official 235:685d5f11838f 880 * @retval HAL status
mbed_official 235:685d5f11838f 881 */
mbed_official 235:685d5f11838f 882 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
mbed_official 235:685d5f11838f 883 {
mbed_official 235:685d5f11838f 884 /* Check the parameters */
mbed_official 235:685d5f11838f 885 assert_param(IS_FMC_PCCARD_DEVICE(Device));
mbed_official 235:685d5f11838f 886
mbed_official 235:685d5f11838f 887 /* Disable the FMC_PCCARD device */
mbed_official 235:685d5f11838f 888 __FMC_PCCARD_DISABLE(Device);
mbed_official 235:685d5f11838f 889
mbed_official 235:685d5f11838f 890 /* De-initialize the FMC_PCCARD device */
mbed_official 235:685d5f11838f 891 Device->PCR4 = 0x00000018;
mbed_official 235:685d5f11838f 892 Device->SR4 = 0x00000000;
mbed_official 235:685d5f11838f 893 Device->PMEM4 = 0xFCFCFCFC;
mbed_official 235:685d5f11838f 894 Device->PATT4 = 0xFCFCFCFC;
mbed_official 235:685d5f11838f 895 Device->PIO4 = 0xFCFCFCFC;
mbed_official 235:685d5f11838f 896
mbed_official 235:685d5f11838f 897 return HAL_OK;
mbed_official 235:685d5f11838f 898 }
mbed_official 235:685d5f11838f 899
mbed_official 235:685d5f11838f 900 /**
mbed_official 235:685d5f11838f 901 * @}
mbed_official 235:685d5f11838f 902 */
mbed_official 235:685d5f11838f 903
mbed_official 235:685d5f11838f 904
mbed_official 235:685d5f11838f 905 /** @defgroup FMC_SDRAM Controller functions
mbed_official 235:685d5f11838f 906 * @brief SDRAM Controller functions
mbed_official 235:685d5f11838f 907 *
mbed_official 235:685d5f11838f 908 @verbatim
mbed_official 235:685d5f11838f 909 ==============================================================================
mbed_official 235:685d5f11838f 910 ##### How to use SDRAM device driver #####
mbed_official 235:685d5f11838f 911 ==============================================================================
mbed_official 235:685d5f11838f 912 [..]
mbed_official 235:685d5f11838f 913 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
mbed_official 235:685d5f11838f 914 to run the SDRAM external devices.
mbed_official 235:685d5f11838f 915
mbed_official 235:685d5f11838f 916 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
mbed_official 235:685d5f11838f 917 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
mbed_official 235:685d5f11838f 918 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
mbed_official 235:685d5f11838f 919 (+) FMC SDRAM bank enable/disable write operation using the functions
mbed_official 235:685d5f11838f 920 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
mbed_official 235:685d5f11838f 921 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
mbed_official 235:685d5f11838f 922
mbed_official 235:685d5f11838f 923 @endverbatim
mbed_official 235:685d5f11838f 924 * @{
mbed_official 235:685d5f11838f 925 */
mbed_official 235:685d5f11838f 926
mbed_official 235:685d5f11838f 927 /** @defgroup HAL_FMC_SDRAM_Group1 Initialization/de-initialization functions
mbed_official 235:685d5f11838f 928 * @brief Initialization and Configuration functions
mbed_official 235:685d5f11838f 929 *
mbed_official 235:685d5f11838f 930 @verbatim
mbed_official 235:685d5f11838f 931 ==============================================================================
mbed_official 235:685d5f11838f 932 ##### Initialization and de_initialization functions #####
mbed_official 235:685d5f11838f 933 ==============================================================================
mbed_official 235:685d5f11838f 934 [..]
mbed_official 235:685d5f11838f 935 This section provides functions allowing to:
mbed_official 235:685d5f11838f 936 (+) Initialize and configure the FMC SDRAM interface
mbed_official 235:685d5f11838f 937 (+) De-initialize the FMC SDRAM interface
mbed_official 235:685d5f11838f 938 (+) Configure the FMC clock and associated GPIOs
mbed_official 235:685d5f11838f 939
mbed_official 235:685d5f11838f 940 @endverbatim
mbed_official 235:685d5f11838f 941 * @{
mbed_official 235:685d5f11838f 942 */
mbed_official 235:685d5f11838f 943
mbed_official 235:685d5f11838f 944 /**
mbed_official 235:685d5f11838f 945 * @brief Initializes the FMC_SDRAM device according to the specified
mbed_official 235:685d5f11838f 946 * control parameters in the FMC_SDRAM_InitTypeDef
mbed_official 235:685d5f11838f 947 * @param Device: Pointer to SDRAM device instance
mbed_official 235:685d5f11838f 948 * @param Init: Pointer to SDRAM Initialization structure
mbed_official 235:685d5f11838f 949 * @retval HAL status
mbed_official 235:685d5f11838f 950 */
mbed_official 235:685d5f11838f 951 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
mbed_official 235:685d5f11838f 952 {
mbed_official 235:685d5f11838f 953 uint32_t tmpr1 = 0;
mbed_official 235:685d5f11838f 954 uint32_t tmpr2 = 0;
mbed_official 235:685d5f11838f 955
mbed_official 235:685d5f11838f 956 /* Check the parameters */
mbed_official 235:685d5f11838f 957 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 958 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
mbed_official 235:685d5f11838f 959 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
mbed_official 235:685d5f11838f 960 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
mbed_official 235:685d5f11838f 961 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
mbed_official 235:685d5f11838f 962 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
mbed_official 235:685d5f11838f 963 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
mbed_official 235:685d5f11838f 964 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
mbed_official 235:685d5f11838f 965 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
mbed_official 235:685d5f11838f 966 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
mbed_official 235:685d5f11838f 967 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
mbed_official 235:685d5f11838f 968
mbed_official 235:685d5f11838f 969 /* Set SDRAM bank configuration parameters */
mbed_official 235:685d5f11838f 970 if (Init->SDBank != FMC_SDRAM_BANK2)
mbed_official 235:685d5f11838f 971 {
mbed_official 235:685d5f11838f 972 Device->SDCR[FMC_SDRAM_BANK1] = (uint32_t)(Init->ColumnBitsNumber |\
mbed_official 235:685d5f11838f 973 Init->RowBitsNumber |\
mbed_official 235:685d5f11838f 974 Init->MemoryDataWidth |\
mbed_official 235:685d5f11838f 975 Init->InternalBankNumber |\
mbed_official 235:685d5f11838f 976 Init->CASLatency |\
mbed_official 235:685d5f11838f 977 Init->WriteProtection |\
mbed_official 235:685d5f11838f 978 Init->SDClockPeriod |\
mbed_official 235:685d5f11838f 979 Init->ReadBurst |\
mbed_official 235:685d5f11838f 980 Init->ReadPipeDelay
mbed_official 235:685d5f11838f 981 );
mbed_official 235:685d5f11838f 982 }
mbed_official 235:685d5f11838f 983 else /* FMC_Bank2_SDRAM */
mbed_official 235:685d5f11838f 984 {
mbed_official 235:685d5f11838f 985 tmpr1 = (uint32_t)(Init->SDClockPeriod |\
mbed_official 235:685d5f11838f 986 Init->ReadBurst |\
mbed_official 235:685d5f11838f 987 Init->ReadPipeDelay
mbed_official 235:685d5f11838f 988 );
mbed_official 235:685d5f11838f 989
mbed_official 235:685d5f11838f 990 tmpr2 = (uint32_t)(Init->ColumnBitsNumber |\
mbed_official 235:685d5f11838f 991 Init->RowBitsNumber |\
mbed_official 235:685d5f11838f 992 Init->MemoryDataWidth |\
mbed_official 235:685d5f11838f 993 Init->InternalBankNumber |\
mbed_official 235:685d5f11838f 994 Init->CASLatency |\
mbed_official 235:685d5f11838f 995 Init->WriteProtection
mbed_official 235:685d5f11838f 996 );
mbed_official 235:685d5f11838f 997
mbed_official 235:685d5f11838f 998 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
mbed_official 235:685d5f11838f 999 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
mbed_official 235:685d5f11838f 1000 }
mbed_official 235:685d5f11838f 1001
mbed_official 235:685d5f11838f 1002 return HAL_OK;
mbed_official 235:685d5f11838f 1003 }
mbed_official 235:685d5f11838f 1004
mbed_official 235:685d5f11838f 1005 /**
mbed_official 235:685d5f11838f 1006 * @brief Initializes the FMC_SDRAM device timing according to the specified
mbed_official 235:685d5f11838f 1007 * parameters in the FMC_SDRAM_TimingTypeDef
mbed_official 235:685d5f11838f 1008 * @param Device: Pointer to SDRAM device instance
mbed_official 235:685d5f11838f 1009 * @param Timing: Pointer to SDRAM Timing structure
mbed_official 235:685d5f11838f 1010 * @param Bank: SDRAM bank number
mbed_official 235:685d5f11838f 1011 * @retval HAL status
mbed_official 235:685d5f11838f 1012 */
mbed_official 235:685d5f11838f 1013 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
mbed_official 235:685d5f11838f 1014 {
mbed_official 235:685d5f11838f 1015 uint32_t tmpr1 = 0;
mbed_official 235:685d5f11838f 1016 uint32_t tmpr2 = 0;
mbed_official 235:685d5f11838f 1017
mbed_official 235:685d5f11838f 1018 /* Check the parameters */
mbed_official 235:685d5f11838f 1019 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 1020 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
mbed_official 235:685d5f11838f 1021 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
mbed_official 235:685d5f11838f 1022 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
mbed_official 235:685d5f11838f 1023 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
mbed_official 235:685d5f11838f 1024 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
mbed_official 235:685d5f11838f 1025 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
mbed_official 235:685d5f11838f 1026 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
mbed_official 235:685d5f11838f 1027 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 235:685d5f11838f 1028
mbed_official 235:685d5f11838f 1029 /* Set SDRAM device timing parameters */
mbed_official 235:685d5f11838f 1030 if (Bank != FMC_SDRAM_BANK2)
mbed_official 235:685d5f11838f 1031 {
mbed_official 235:685d5f11838f 1032 Device->SDTR[FMC_SDRAM_BANK1] = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
mbed_official 235:685d5f11838f 1033 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
mbed_official 235:685d5f11838f 1034 (((Timing->SelfRefreshTime)-1) << 8) |\
mbed_official 235:685d5f11838f 1035 (((Timing->RowCycleDelay)-1) << 12) |\
mbed_official 235:685d5f11838f 1036 (((Timing->WriteRecoveryTime)-1) <<16) |\
mbed_official 235:685d5f11838f 1037 (((Timing->RPDelay)-1) << 20) |\
mbed_official 235:685d5f11838f 1038 (((Timing->RCDDelay)-1) << 24)
mbed_official 235:685d5f11838f 1039 );
mbed_official 235:685d5f11838f 1040 }
mbed_official 235:685d5f11838f 1041 else /* FMC_Bank2_SDRAM */
mbed_official 235:685d5f11838f 1042 {
mbed_official 235:685d5f11838f 1043
mbed_official 235:685d5f11838f 1044 tmpr1 = (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
mbed_official 235:685d5f11838f 1045 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
mbed_official 235:685d5f11838f 1046 (((Timing->SelfRefreshTime)-1) << 8) |\
mbed_official 235:685d5f11838f 1047 (((Timing->WriteRecoveryTime)-1) <<16) |\
mbed_official 235:685d5f11838f 1048 (((Timing->RCDDelay)-1) << 24)
mbed_official 235:685d5f11838f 1049 );
mbed_official 235:685d5f11838f 1050
mbed_official 235:685d5f11838f 1051 tmpr2 = (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
mbed_official 235:685d5f11838f 1052 (((Timing->RPDelay)-1) << 20)
mbed_official 235:685d5f11838f 1053 );
mbed_official 235:685d5f11838f 1054
mbed_official 235:685d5f11838f 1055 Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
mbed_official 235:685d5f11838f 1056 Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
mbed_official 235:685d5f11838f 1057 }
mbed_official 235:685d5f11838f 1058
mbed_official 235:685d5f11838f 1059 return HAL_OK;
mbed_official 235:685d5f11838f 1060 }
mbed_official 235:685d5f11838f 1061
mbed_official 235:685d5f11838f 1062 /**
mbed_official 235:685d5f11838f 1063 * @brief DeInitializes the FMC_SDRAM peripheral
mbed_official 235:685d5f11838f 1064 * @param Device: Pointer to SDRAM device instance
mbed_official 235:685d5f11838f 1065 * @retval HAL status
mbed_official 235:685d5f11838f 1066 */
mbed_official 235:685d5f11838f 1067 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 235:685d5f11838f 1068 {
mbed_official 235:685d5f11838f 1069 /* Check the parameters */
mbed_official 235:685d5f11838f 1070 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 1071 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 235:685d5f11838f 1072
mbed_official 235:685d5f11838f 1073 /* De-initialize the SDRAM device */
mbed_official 235:685d5f11838f 1074 Device->SDCR[Bank] = 0x000002D0;
mbed_official 235:685d5f11838f 1075 Device->SDTR[Bank] = 0x0FFFFFFF;
mbed_official 235:685d5f11838f 1076 Device->SDCMR = 0x00000000;
mbed_official 235:685d5f11838f 1077 Device->SDRTR = 0x00000000;
mbed_official 235:685d5f11838f 1078 Device->SDSR = 0x00000000;
mbed_official 235:685d5f11838f 1079
mbed_official 235:685d5f11838f 1080 return HAL_OK;
mbed_official 235:685d5f11838f 1081 }
mbed_official 235:685d5f11838f 1082
mbed_official 235:685d5f11838f 1083 /**
mbed_official 235:685d5f11838f 1084 * @}
mbed_official 235:685d5f11838f 1085 */
mbed_official 235:685d5f11838f 1086
mbed_official 235:685d5f11838f 1087
mbed_official 235:685d5f11838f 1088 /** @defgroup HAL_FMC_SDRAM_Group3 Control functions
mbed_official 235:685d5f11838f 1089 * @brief management functions
mbed_official 235:685d5f11838f 1090 *
mbed_official 235:685d5f11838f 1091 @verbatim
mbed_official 235:685d5f11838f 1092 ==============================================================================
mbed_official 235:685d5f11838f 1093 ##### FMC_SDRAM Control functions #####
mbed_official 235:685d5f11838f 1094 ==============================================================================
mbed_official 235:685d5f11838f 1095 [..]
mbed_official 235:685d5f11838f 1096 This subsection provides a set of functions allowing to control dynamically
mbed_official 235:685d5f11838f 1097 the FMC SDRAM interface.
mbed_official 235:685d5f11838f 1098
mbed_official 235:685d5f11838f 1099 @endverbatim
mbed_official 235:685d5f11838f 1100 * @{
mbed_official 235:685d5f11838f 1101 */
mbed_official 235:685d5f11838f 1102
mbed_official 235:685d5f11838f 1103 /**
mbed_official 235:685d5f11838f 1104 * @brief Enables dynamically FMC_SDRAM write protection.
mbed_official 235:685d5f11838f 1105 * @param Device: Pointer to SDRAM device instance
mbed_official 235:685d5f11838f 1106 * @param Bank: SDRAM bank number
mbed_official 235:685d5f11838f 1107 * @retval HAL status
mbed_official 235:685d5f11838f 1108 */
mbed_official 235:685d5f11838f 1109 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 235:685d5f11838f 1110 {
mbed_official 235:685d5f11838f 1111 /* Check the parameters */
mbed_official 235:685d5f11838f 1112 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 1113 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 235:685d5f11838f 1114
mbed_official 235:685d5f11838f 1115 /* Enable write protection */
mbed_official 235:685d5f11838f 1116 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
mbed_official 235:685d5f11838f 1117
mbed_official 235:685d5f11838f 1118 return HAL_OK;
mbed_official 235:685d5f11838f 1119 }
mbed_official 235:685d5f11838f 1120
mbed_official 235:685d5f11838f 1121 /**
mbed_official 235:685d5f11838f 1122 * @brief Disables dynamically FMC_SDRAM write protection.
mbed_official 235:685d5f11838f 1123 * @param hsdram: FMC_SDRAM handle
mbed_official 235:685d5f11838f 1124 * @retval HAL status
mbed_official 235:685d5f11838f 1125 */
mbed_official 235:685d5f11838f 1126 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 235:685d5f11838f 1127 {
mbed_official 235:685d5f11838f 1128 /* Check the parameters */
mbed_official 235:685d5f11838f 1129 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 1130 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 235:685d5f11838f 1131
mbed_official 235:685d5f11838f 1132 /* Disable write protection */
mbed_official 235:685d5f11838f 1133 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
mbed_official 235:685d5f11838f 1134
mbed_official 235:685d5f11838f 1135 return HAL_OK;
mbed_official 235:685d5f11838f 1136 }
mbed_official 235:685d5f11838f 1137
mbed_official 235:685d5f11838f 1138 /**
mbed_official 235:685d5f11838f 1139 * @brief Send Command to the FMC SDRAM bank
mbed_official 235:685d5f11838f 1140 * @param Device: Pointer to SDRAM device instance
mbed_official 235:685d5f11838f 1141 * @param Command: Pointer to SDRAM command structure
mbed_official 235:685d5f11838f 1142 * @param Timing: Pointer to SDRAM Timing structure
mbed_official 235:685d5f11838f 1143 * @param Timeout: Timeout wait value
mbed_official 235:685d5f11838f 1144 * @retval HAL state
mbed_official 235:685d5f11838f 1145 */
mbed_official 235:685d5f11838f 1146 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
mbed_official 235:685d5f11838f 1147 {
mbed_official 235:685d5f11838f 1148 __IO uint32_t tmpr = 0;
mbed_official 235:685d5f11838f 1149 uint32_t tickstart = 0;
mbed_official 235:685d5f11838f 1150
mbed_official 235:685d5f11838f 1151 /* Check the parameters */
mbed_official 235:685d5f11838f 1152 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 1153 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
mbed_official 235:685d5f11838f 1154 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
mbed_official 235:685d5f11838f 1155 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
mbed_official 235:685d5f11838f 1156 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
mbed_official 235:685d5f11838f 1157
mbed_official 235:685d5f11838f 1158 /* Set command register */
mbed_official 235:685d5f11838f 1159 tmpr = (uint32_t)((Command->CommandMode) |\
mbed_official 235:685d5f11838f 1160 (Command->CommandTarget) |\
mbed_official 235:685d5f11838f 1161 (((Command->AutoRefreshNumber)-1) << 5) |\
mbed_official 235:685d5f11838f 1162 ((Command->ModeRegisterDefinition) << 9)
mbed_official 235:685d5f11838f 1163 );
mbed_official 235:685d5f11838f 1164
mbed_official 235:685d5f11838f 1165 Device->SDCMR = tmpr;
mbed_official 235:685d5f11838f 1166
mbed_official 235:685d5f11838f 1167 /* Get tick */
mbed_official 235:685d5f11838f 1168 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 1169
mbed_official 235:685d5f11838f 1170 /* wait until command is send */
mbed_official 235:685d5f11838f 1171 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
mbed_official 235:685d5f11838f 1172 {
mbed_official 235:685d5f11838f 1173 /* Check for the Timeout */
mbed_official 235:685d5f11838f 1174 if(Timeout != HAL_MAX_DELAY)
mbed_official 235:685d5f11838f 1175 {
mbed_official 235:685d5f11838f 1176 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
mbed_official 235:685d5f11838f 1177 {
mbed_official 235:685d5f11838f 1178 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 1179 }
mbed_official 235:685d5f11838f 1180 }
mbed_official 235:685d5f11838f 1181
mbed_official 235:685d5f11838f 1182 return HAL_ERROR;
mbed_official 235:685d5f11838f 1183 }
mbed_official 235:685d5f11838f 1184
mbed_official 235:685d5f11838f 1185 return HAL_OK;
mbed_official 235:685d5f11838f 1186 }
mbed_official 235:685d5f11838f 1187
mbed_official 235:685d5f11838f 1188 /**
mbed_official 235:685d5f11838f 1189 * @brief Program the SDRAM Memory Refresh rate.
mbed_official 235:685d5f11838f 1190 * @param Device: Pointer to SDRAM device instance
mbed_official 235:685d5f11838f 1191 * @param RefreshRate: The SDRAM refresh rate value.
mbed_official 235:685d5f11838f 1192 * @retval HAL state
mbed_official 235:685d5f11838f 1193 */
mbed_official 235:685d5f11838f 1194 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
mbed_official 235:685d5f11838f 1195 {
mbed_official 235:685d5f11838f 1196 /* Check the parameters */
mbed_official 235:685d5f11838f 1197 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 1198 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
mbed_official 235:685d5f11838f 1199
mbed_official 235:685d5f11838f 1200 /* Set the refresh rate in command register */
mbed_official 235:685d5f11838f 1201 Device->SDRTR |= (RefreshRate<<1);
mbed_official 235:685d5f11838f 1202
mbed_official 235:685d5f11838f 1203 return HAL_OK;
mbed_official 235:685d5f11838f 1204 }
mbed_official 235:685d5f11838f 1205
mbed_official 235:685d5f11838f 1206 /**
mbed_official 235:685d5f11838f 1207 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
mbed_official 235:685d5f11838f 1208 * @param Device: Pointer to SDRAM device instance
mbed_official 235:685d5f11838f 1209 * @param AutoRefreshNumber: Specifies the auto Refresh number.
mbed_official 235:685d5f11838f 1210 * @retval None
mbed_official 235:685d5f11838f 1211 */
mbed_official 235:685d5f11838f 1212 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
mbed_official 235:685d5f11838f 1213 {
mbed_official 235:685d5f11838f 1214 /* Check the parameters */
mbed_official 235:685d5f11838f 1215 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 1216 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
mbed_official 235:685d5f11838f 1217
mbed_official 235:685d5f11838f 1218 /* Set the Auto-refresh number in command register */
mbed_official 235:685d5f11838f 1219 Device->SDCMR |= (AutoRefreshNumber << 5);
mbed_official 235:685d5f11838f 1220
mbed_official 235:685d5f11838f 1221 return HAL_OK;
mbed_official 235:685d5f11838f 1222 }
mbed_official 235:685d5f11838f 1223
mbed_official 235:685d5f11838f 1224 /**
mbed_official 235:685d5f11838f 1225 * @brief Returns the indicated FMC SDRAM bank mode status.
mbed_official 235:685d5f11838f 1226 * @param Device: Pointer to SDRAM device instance
mbed_official 235:685d5f11838f 1227 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
mbed_official 235:685d5f11838f 1228 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
mbed_official 235:685d5f11838f 1229 * @retval The FMC SDRAM bank mode status, could be on of the following values:
mbed_official 235:685d5f11838f 1230 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
mbed_official 235:685d5f11838f 1231 * FMC_SDRAM_POWER_DOWN_MODE.
mbed_official 235:685d5f11838f 1232 */
mbed_official 235:685d5f11838f 1233 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
mbed_official 235:685d5f11838f 1234 {
mbed_official 235:685d5f11838f 1235 uint32_t tmpreg = 0;
mbed_official 235:685d5f11838f 1236
mbed_official 235:685d5f11838f 1237 /* Check the parameters */
mbed_official 235:685d5f11838f 1238 assert_param(IS_FMC_SDRAM_DEVICE(Device));
mbed_official 235:685d5f11838f 1239 assert_param(IS_FMC_SDRAM_BANK(Bank));
mbed_official 235:685d5f11838f 1240
mbed_official 235:685d5f11838f 1241 /* Get the corresponding bank mode */
mbed_official 235:685d5f11838f 1242 if(Bank == FMC_SDRAM_BANK1)
mbed_official 235:685d5f11838f 1243 {
mbed_official 235:685d5f11838f 1244 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
mbed_official 235:685d5f11838f 1245 }
mbed_official 235:685d5f11838f 1246 else
mbed_official 235:685d5f11838f 1247 {
mbed_official 235:685d5f11838f 1248 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
mbed_official 235:685d5f11838f 1249 }
mbed_official 235:685d5f11838f 1250
mbed_official 235:685d5f11838f 1251 /* Return the mode status */
mbed_official 235:685d5f11838f 1252 return tmpreg;
mbed_official 235:685d5f11838f 1253 }
mbed_official 235:685d5f11838f 1254
mbed_official 235:685d5f11838f 1255 /**
mbed_official 235:685d5f11838f 1256 * @}
mbed_official 235:685d5f11838f 1257 */
mbed_official 235:685d5f11838f 1258
mbed_official 235:685d5f11838f 1259 /**
mbed_official 235:685d5f11838f 1260 * @}
mbed_official 235:685d5f11838f 1261 */
mbed_official 235:685d5f11838f 1262
mbed_official 235:685d5f11838f 1263 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 235:685d5f11838f 1264
mbed_official 235:685d5f11838f 1265 #endif /* HAL_FMC_MODULE_ENABLED */
mbed_official 235:685d5f11838f 1266
mbed_official 235:685d5f11838f 1267 /**
mbed_official 235:685d5f11838f 1268 * @}
mbed_official 235:685d5f11838f 1269 */
mbed_official 235:685d5f11838f 1270
mbed_official 235:685d5f11838f 1271 /**
mbed_official 235:685d5f11838f 1272 * @}
mbed_official 235:685d5f11838f 1273 */
mbed_official 235:685d5f11838f 1274
mbed_official 235:685d5f11838f 1275 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/