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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c@380:510f0c3515e3, 2014-11-03 (annotated)

Committer:: mbed_official
Date:: Mon Nov 03 10:15:07 2014 +0000
Revision:: 380:510f0c3515e3
Parent:: targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_tim.c@369:2e96f1b71984
Child:: 532:fe11edbda85c

Synchronized with git revision 417f470ba9f4882d7079611cbc576afd9c49b0ef

Full URL: https://github.com/mbedmicro/mbed/commit/417f470ba9f4882d7079611cbc576afd9c49b0ef/

Targets: Factorisation of NUCLEO_F401RE and F411RE cmsis folders

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_tim.c
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	369:2e96f1b71984	5	* @version V1.1.0
mbed_official	369:2e96f1b71984	6	* @date 19-June-2014
mbed_official	87:085cde657901	7	* @brief TIM HAL module driver.
mbed_official	87:085cde657901	8	* This file provides firmware functions to manage the following
mbed_official	87:085cde657901	9	* functionalities of the Timer (TIM) peripheral:
mbed_official	87:085cde657901	10	* + Time Base Initialization
mbed_official	87:085cde657901	11	* + Time Base Start
mbed_official	87:085cde657901	12	* + Time Base Start Interruption
mbed_official	87:085cde657901	13	* + Time Base Start DMA
mbed_official	87:085cde657901	14	* + Time Output Compare/PWM Initialization
mbed_official	87:085cde657901	15	* + Time Output Compare/PWM Channel Configuration
mbed_official	87:085cde657901	16	* + Time Output Compare/PWM Start
mbed_official	87:085cde657901	17	* + Time Output Compare/PWM Start Interruption
mbed_official	87:085cde657901	18	* + Time Output Compare/PWM Start DMA
mbed_official	87:085cde657901	19	* + Time Input Capture Initialization
mbed_official	87:085cde657901	20	* + Time Input Capture Channel Configuration
mbed_official	87:085cde657901	21	* + Time Input Capture Start
mbed_official	87:085cde657901	22	* + Time Input Capture Start Interruption
mbed_official	87:085cde657901	23	* + Time Input Capture Start DMA
mbed_official	87:085cde657901	24	* + Time One Pulse Initialization
mbed_official	87:085cde657901	25	* + Time One Pulse Channel Configuration
mbed_official	87:085cde657901	26	* + Time One Pulse Start
mbed_official	87:085cde657901	27	* + Time Encoder Interface Initialization
mbed_official	87:085cde657901	28	* + Time Encoder Interface Start
mbed_official	87:085cde657901	29	* + Time Encoder Interface Start Interruption
mbed_official	87:085cde657901	30	* + Time Encoder Interface Start DMA
mbed_official	87:085cde657901	31	* + Commutation Event configuration with Interruption and DMA
mbed_official	87:085cde657901	32	* + Time OCRef clear configuration
mbed_official	87:085cde657901	33	* + Time External Clock configuration
mbed_official	87:085cde657901	34	@verbatim
mbed_official	87:085cde657901	35	==============================================================================
mbed_official	87:085cde657901	36	##### TIMER Generic features #####
mbed_official	87:085cde657901	37	==============================================================================
mbed_official	87:085cde657901	38	[..] The Timer features include:
mbed_official	87:085cde657901	39	(#) 16-bit up, down, up/down auto-reload counter.
mbed_official	87:085cde657901	40	(#) 16-bit programmable prescaler allowing dividing (also on the fly) the
mbed_official	87:085cde657901	41	counter clock frequency either by any factor between 1 and 65536.
mbed_official	87:085cde657901	42	(#) Up to 4 independent channels for:
mbed_official	87:085cde657901	43	(++) Input Capture
mbed_official	87:085cde657901	44	(++) Output Compare
mbed_official	87:085cde657901	45	(++) PWM generation (Edge and Center-aligned Mode)
mbed_official	87:085cde657901	46	(++) One-pulse mode output
mbed_official	87:085cde657901	47
mbed_official	87:085cde657901	48	##### How to use this driver #####
mbed_official	87:085cde657901	49	==============================================================================
mbed_official	87:085cde657901	50	[..]
mbed_official	87:085cde657901	51	(#) Initialize the TIM low level resources by implementing the following functions
mbed_official	87:085cde657901	52	depending from feature used :
mbed_official	87:085cde657901	53	(++) Time Base : HAL_TIM_Base_MspInit()
mbed_official	87:085cde657901	54	(++) Input Capture : HAL_TIM_IC_MspInit()
mbed_official	87:085cde657901	55	(++) Output Compare : HAL_TIM_OC_MspInit()
mbed_official	87:085cde657901	56	(++) PWM generation : HAL_TIM_PWM_MspInit()
mbed_official	87:085cde657901	57	(++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
mbed_official	87:085cde657901	58	(++) Encoder mode output : HAL_TIM_Encoder_MspInit()
mbed_official	87:085cde657901	59
mbed_official	87:085cde657901	60	(#) Initialize the TIM low level resources :
mbed_official	87:085cde657901	61	(##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
mbed_official	87:085cde657901	62	(##) TIM pins configuration
mbed_official	87:085cde657901	63	(+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official	87:085cde657901	64	__GPIOx_CLK_ENABLE();
mbed_official	87:085cde657901	65	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
mbed_official	87:085cde657901	66
mbed_official	87:085cde657901	67	(#) The external Clock can be configured, if needed (the default clock is the
mbed_official	87:085cde657901	68	internal clock from the APBx), using the following function:
mbed_official	87:085cde657901	69	HAL_TIM_ConfigClockSource, the clock configuration should be done before
mbed_official	87:085cde657901	70	any start function.
mbed_official	87:085cde657901	71
mbed_official	87:085cde657901	72	(#) Configure the TIM in the desired functioning mode using one of the
mbed_official	87:085cde657901	73	initialization function of this driver:
mbed_official	87:085cde657901	74	(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
mbed_official	87:085cde657901	75	(++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
mbed_official	87:085cde657901	76	Output Compare signal.
mbed_official	87:085cde657901	77	(++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
mbed_official	87:085cde657901	78	PWM signal.
mbed_official	87:085cde657901	79	(++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
mbed_official	87:085cde657901	80	external signal.
mbed_official	87:085cde657901	81	(++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
mbed_official	87:085cde657901	82	in One Pulse Mode.
mbed_official	87:085cde657901	83	(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
mbed_official	87:085cde657901	84
mbed_official	87:085cde657901	85	(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
mbed_official	87:085cde657901	86	(++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
mbed_official	87:085cde657901	87	(++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
mbed_official	87:085cde657901	88	(++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
mbed_official	87:085cde657901	89	(++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
mbed_official	87:085cde657901	90	(++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
mbed_official	87:085cde657901	91	(++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
mbed_official	87:085cde657901	92
mbed_official	87:085cde657901	93	(#) The DMA Burst is managed with the two following functions:
mbed_official	87:085cde657901	94	HAL_TIM_DMABurst_WriteStart()
mbed_official	87:085cde657901	95	HAL_TIM_DMABurst_ReadStart()
mbed_official	87:085cde657901	96
mbed_official	87:085cde657901	97	@endverbatim
mbed_official	87:085cde657901	98	******************************************************************************
mbed_official	87:085cde657901	99	* @attention
mbed_official	87:085cde657901	100	*
mbed_official	87:085cde657901	101	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	102	*
mbed_official	87:085cde657901	103	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	104	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	105	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	106	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	107	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	108	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	109	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	110	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	111	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	112	* without specific prior written permission.
mbed_official	87:085cde657901	113	*
mbed_official	87:085cde657901	114	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	115	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	116	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	117	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	118	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	119	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	120	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	121	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	122	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	123	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	124	*
mbed_official	87:085cde657901	125	******************************************************************************
mbed_official	87:085cde657901	126	*/
mbed_official	87:085cde657901	127
mbed_official	87:085cde657901	128	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	129	#include "stm32f4xx_hal.h"
mbed_official	87:085cde657901	130
mbed_official	87:085cde657901	131	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	132	* @{
mbed_official	87:085cde657901	133	*/
mbed_official	87:085cde657901	134
mbed_official	87:085cde657901	135	/** @defgroup TIM
mbed_official	87:085cde657901	136	* @brief TIM HAL module driver
mbed_official	87:085cde657901	137	* @{
mbed_official	87:085cde657901	138	*/
mbed_official	87:085cde657901	139
mbed_official	87:085cde657901	140	#ifdef HAL_TIM_MODULE_ENABLED
mbed_official	87:085cde657901	141
mbed_official	87:085cde657901	142	/* Private typedef -----------------------------------------------------------*/
mbed_official	87:085cde657901	143	/* Private define ------------------------------------------------------------*/
mbed_official	87:085cde657901	144	/* Private macro -------------------------------------------------------------*/
mbed_official	87:085cde657901	145	/* Private variables ---------------------------------------------------------*/
mbed_official	87:085cde657901	146	/* Private function prototypes -----------------------------------------------*/
mbed_official	87:085cde657901	147	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	87:085cde657901	148	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	87:085cde657901	149	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	87:085cde657901	150
mbed_official	87:085cde657901	151	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	152	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	153	uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	154	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	155	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	156	uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	157	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	158	uint32_t TIM_ICFilter);
mbed_official	87:085cde657901	159
mbed_official	87:085cde657901	160	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official	87:085cde657901	161	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official	87:085cde657901	162
mbed_official	87:085cde657901	163	static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
mbed_official	87:085cde657901	164	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	165	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	166	/* Private functions ---------------------------------------------------------*/
mbed_official	87:085cde657901	167
mbed_official	87:085cde657901	168	/** @defgroup TIM_Private_Functions
mbed_official	87:085cde657901	169	* @{
mbed_official	87:085cde657901	170	*/
mbed_official	87:085cde657901	171
mbed_official	87:085cde657901	172	/** @defgroup TIM_Group1 Time Base functions
mbed_official	87:085cde657901	173	* @brief Time Base functions
mbed_official	87:085cde657901	174	*
mbed_official	87:085cde657901	175	@verbatim
mbed_official	87:085cde657901	176	==============================================================================
mbed_official	87:085cde657901	177	##### Time Base functions #####
mbed_official	87:085cde657901	178	==============================================================================
mbed_official	87:085cde657901	179	[..]
mbed_official	87:085cde657901	180	This section provides functions allowing to:
mbed_official	87:085cde657901	181	(+) Initialize and configure the TIM base.
mbed_official	87:085cde657901	182	(+) De-initialize the TIM base.
mbed_official	87:085cde657901	183	(+) Start the Time Base.
mbed_official	87:085cde657901	184	(+) Stop the Time Base.
mbed_official	87:085cde657901	185	(+) Start the Time Base and enable interrupt.
mbed_official	87:085cde657901	186	(+) Stop the Time Base and disable interrupt.
mbed_official	87:085cde657901	187	(+) Start the Time Base and enable DMA transfer.
mbed_official	87:085cde657901	188	(+) Stop the Time Base and disable DMA transfer.
mbed_official	87:085cde657901	189
mbed_official	87:085cde657901	190	@endverbatim
mbed_official	87:085cde657901	191	* @{
mbed_official	87:085cde657901	192	*/
mbed_official	87:085cde657901	193	/**
mbed_official	87:085cde657901	194	* @brief Initializes the TIM Time base Unit according to the specified
mbed_official	87:085cde657901	195	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	226:b062af740e40	196	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	197	* the configuration information for TIM module.
mbed_official	87:085cde657901	198	* @retval HAL status
mbed_official	87:085cde657901	199	*/
mbed_official	87:085cde657901	200	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	201	{
mbed_official	87:085cde657901	202	/* Check the TIM handle allocation */
mbed_official	369:2e96f1b71984	203	if(htim == HAL_NULL)
mbed_official	87:085cde657901	204	{
mbed_official	87:085cde657901	205	return HAL_ERROR;
mbed_official	87:085cde657901	206	}
mbed_official	87:085cde657901	207
mbed_official	87:085cde657901	208	/* Check the parameters */
mbed_official	87:085cde657901	209	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	210	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	211	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	212
mbed_official	87:085cde657901	213	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	214	{
mbed_official	87:085cde657901	215	/* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official	87:085cde657901	216	HAL_TIM_Base_MspInit(htim);
mbed_official	87:085cde657901	217	}
mbed_official	87:085cde657901	218
mbed_official	87:085cde657901	219	/* Set the TIM state */
mbed_official	87:085cde657901	220	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	221
mbed_official	87:085cde657901	222	/* Set the Time Base configuration */
mbed_official	87:085cde657901	223	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	224
mbed_official	87:085cde657901	225	/* Initialize the TIM state*/
mbed_official	87:085cde657901	226	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	227
mbed_official	87:085cde657901	228	return HAL_OK;
mbed_official	87:085cde657901	229	}
mbed_official	87:085cde657901	230
mbed_official	87:085cde657901	231	/**
mbed_official	87:085cde657901	232	* @brief DeInitializes the TIM Base peripheral
mbed_official	226:b062af740e40	233	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	234	* the configuration information for TIM module.
mbed_official	87:085cde657901	235	* @retval HAL status
mbed_official	87:085cde657901	236	*/
mbed_official	87:085cde657901	237	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	238	{
mbed_official	87:085cde657901	239	/* Check the parameters */
mbed_official	87:085cde657901	240	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	241
mbed_official	87:085cde657901	242	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	243
mbed_official	87:085cde657901	244	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	245	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	246
mbed_official	87:085cde657901	247	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	87:085cde657901	248	HAL_TIM_Base_MspDeInit(htim);
mbed_official	87:085cde657901	249
mbed_official	87:085cde657901	250	/* Change TIM state */
mbed_official	87:085cde657901	251	htim->State = HAL_TIM_STATE_RESET;
mbed_official	87:085cde657901	252
mbed_official	106:ced8cbb51063	253	/* Release Lock */
mbed_official	106:ced8cbb51063	254	__HAL_UNLOCK(htim);
mbed_official	106:ced8cbb51063	255
mbed_official	87:085cde657901	256	return HAL_OK;
mbed_official	87:085cde657901	257	}
mbed_official	87:085cde657901	258
mbed_official	87:085cde657901	259	/**
mbed_official	87:085cde657901	260	* @brief Initializes the TIM Base MSP.
mbed_official	226:b062af740e40	261	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	262	* the configuration information for TIM module.
mbed_official	87:085cde657901	263	* @retval None
mbed_official	87:085cde657901	264	*/
mbed_official	87:085cde657901	265	__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	266	{
mbed_official	87:085cde657901	267	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	268	the HAL_TIM_Base_MspInit could be implemented in the user file
mbed_official	87:085cde657901	269	*/
mbed_official	87:085cde657901	270	}
mbed_official	87:085cde657901	271
mbed_official	87:085cde657901	272	/**
mbed_official	87:085cde657901	273	* @brief DeInitializes TIM Base MSP.
mbed_official	226:b062af740e40	274	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	275	* the configuration information for TIM module.
mbed_official	87:085cde657901	276	* @retval None
mbed_official	87:085cde657901	277	*/
mbed_official	87:085cde657901	278	__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	279	{
mbed_official	87:085cde657901	280	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	281	the HAL_TIM_Base_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	282	*/
mbed_official	87:085cde657901	283	}
mbed_official	87:085cde657901	284
mbed_official	87:085cde657901	285	/**
mbed_official	87:085cde657901	286	* @brief Starts the TIM Base generation.
mbed_official	226:b062af740e40	287	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	288	* the configuration information for TIM module.
mbed_official	87:085cde657901	289	* @retval HAL status
mbed_official	87:085cde657901	290	*/
mbed_official	87:085cde657901	291	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	292	{
mbed_official	87:085cde657901	293	/* Check the parameters */
mbed_official	87:085cde657901	294	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	295
mbed_official	87:085cde657901	296	/* Set the TIM state */
mbed_official	87:085cde657901	297	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	298
mbed_official	87:085cde657901	299	/* Enable the Peripheral */
mbed_official	87:085cde657901	300	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	301
mbed_official	87:085cde657901	302	/* Change the TIM state*/
mbed_official	87:085cde657901	303	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	304
mbed_official	87:085cde657901	305	/* Return function status */
mbed_official	87:085cde657901	306	return HAL_OK;
mbed_official	87:085cde657901	307	}
mbed_official	87:085cde657901	308
mbed_official	87:085cde657901	309	/**
mbed_official	87:085cde657901	310	* @brief Stops the TIM Base generation.
mbed_official	226:b062af740e40	311	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	312	* the configuration information for TIM module.
mbed_official	87:085cde657901	313	* @retval HAL status
mbed_official	87:085cde657901	314	*/
mbed_official	87:085cde657901	315	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	316	{
mbed_official	87:085cde657901	317	/* Check the parameters */
mbed_official	87:085cde657901	318	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	319
mbed_official	87:085cde657901	320	/* Set the TIM state */
mbed_official	87:085cde657901	321	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	322
mbed_official	87:085cde657901	323	/* Disable the Peripheral */
mbed_official	87:085cde657901	324	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	325
mbed_official	87:085cde657901	326	/* Change the TIM state*/
mbed_official	87:085cde657901	327	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	328
mbed_official	87:085cde657901	329	/* Return function status */
mbed_official	87:085cde657901	330	return HAL_OK;
mbed_official	87:085cde657901	331	}
mbed_official	87:085cde657901	332
mbed_official	87:085cde657901	333	/**
mbed_official	87:085cde657901	334	* @brief Starts the TIM Base generation in interrupt mode.
mbed_official	226:b062af740e40	335	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	336	* the configuration information for TIM module.
mbed_official	87:085cde657901	337	* @retval HAL status
mbed_official	87:085cde657901	338	*/
mbed_official	87:085cde657901	339	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	340	{
mbed_official	87:085cde657901	341	/* Check the parameters */
mbed_official	87:085cde657901	342	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	343
mbed_official	87:085cde657901	344	/* Enable the TIM Update interrupt */
mbed_official	87:085cde657901	345	__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
mbed_official	87:085cde657901	346
mbed_official	87:085cde657901	347	/* Enable the Peripheral */
mbed_official	87:085cde657901	348	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	349
mbed_official	87:085cde657901	350	/* Return function status */
mbed_official	87:085cde657901	351	return HAL_OK;
mbed_official	87:085cde657901	352	}
mbed_official	87:085cde657901	353
mbed_official	87:085cde657901	354	/**
mbed_official	87:085cde657901	355	* @brief Stops the TIM Base generation in interrupt mode.
mbed_official	226:b062af740e40	356	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	357	* the configuration information for TIM module.
mbed_official	87:085cde657901	358	* @retval HAL status
mbed_official	87:085cde657901	359	*/
mbed_official	87:085cde657901	360	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	361	{
mbed_official	87:085cde657901	362	/* Check the parameters */
mbed_official	87:085cde657901	363	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	364	/* Disable the TIM Update interrupt */
mbed_official	87:085cde657901	365	__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
mbed_official	87:085cde657901	366
mbed_official	87:085cde657901	367	/* Disable the Peripheral */
mbed_official	87:085cde657901	368	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	369
mbed_official	87:085cde657901	370	/* Return function status */
mbed_official	87:085cde657901	371	return HAL_OK;
mbed_official	87:085cde657901	372	}
mbed_official	87:085cde657901	373
mbed_official	87:085cde657901	374	/**
mbed_official	87:085cde657901	375	* @brief Starts the TIM Base generation in DMA mode.
mbed_official	226:b062af740e40	376	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	377	* the configuration information for TIM module.
mbed_official	87:085cde657901	378	* @param pData: The source Buffer address.
mbed_official	87:085cde657901	379	* @param Length: The length of data to be transferred from memory to peripheral.
mbed_official	87:085cde657901	380	* @retval HAL status
mbed_official	87:085cde657901	381	*/
mbed_official	87:085cde657901	382	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
mbed_official	87:085cde657901	383	{
mbed_official	87:085cde657901	384	/* Check the parameters */
mbed_official	87:085cde657901	385	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	386
mbed_official	87:085cde657901	387	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	388	{
mbed_official	87:085cde657901	389	return HAL_BUSY;
mbed_official	87:085cde657901	390	}
mbed_official	87:085cde657901	391	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	392	{
mbed_official	87:085cde657901	393	if((pData == 0 ) && (Length > 0))
mbed_official	87:085cde657901	394	{
mbed_official	87:085cde657901	395	return HAL_ERROR;
mbed_official	87:085cde657901	396	}
mbed_official	87:085cde657901	397	else
mbed_official	87:085cde657901	398	{
mbed_official	87:085cde657901	399	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	400	}
mbed_official	87:085cde657901	401	}
mbed_official	87:085cde657901	402	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	403	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official	87:085cde657901	404
mbed_official	87:085cde657901	405	/* Set the DMA error callback */
mbed_official	87:085cde657901	406	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	407
mbed_official	87:085cde657901	408	/* Enable the DMA Stream */
mbed_official	87:085cde657901	409	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
mbed_official	87:085cde657901	410
mbed_official	87:085cde657901	411	/* Enable the TIM Update DMA request */
mbed_official	87:085cde657901	412	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official	87:085cde657901	413
mbed_official	87:085cde657901	414	/* Enable the Peripheral */
mbed_official	87:085cde657901	415	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	416
mbed_official	87:085cde657901	417	/* Return function status */
mbed_official	87:085cde657901	418	return HAL_OK;
mbed_official	87:085cde657901	419	}
mbed_official	87:085cde657901	420
mbed_official	87:085cde657901	421	/**
mbed_official	87:085cde657901	422	* @brief Stops the TIM Base generation in DMA mode.
mbed_official	226:b062af740e40	423	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	424	* the configuration information for TIM module.
mbed_official	87:085cde657901	425	* @retval HAL status
mbed_official	87:085cde657901	426	*/
mbed_official	87:085cde657901	427	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	428	{
mbed_official	87:085cde657901	429	/* Check the parameters */
mbed_official	87:085cde657901	430	assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	431
mbed_official	87:085cde657901	432	/* Disable the TIM Update DMA request */
mbed_official	87:085cde657901	433	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official	87:085cde657901	434
mbed_official	87:085cde657901	435	/* Disable the Peripheral */
mbed_official	87:085cde657901	436	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	437
mbed_official	87:085cde657901	438	/* Change the htim state */
mbed_official	87:085cde657901	439	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	440
mbed_official	87:085cde657901	441	/* Return function status */
mbed_official	87:085cde657901	442	return HAL_OK;
mbed_official	87:085cde657901	443	}
mbed_official	87:085cde657901	444
mbed_official	87:085cde657901	445	/**
mbed_official	87:085cde657901	446	* @}
mbed_official	87:085cde657901	447	*/
mbed_official	87:085cde657901	448
mbed_official	87:085cde657901	449	/** @defgroup TIM_Group2 Time Output Compare functions
mbed_official	87:085cde657901	450	* @brief Time Output Compare functions
mbed_official	87:085cde657901	451	*
mbed_official	87:085cde657901	452	@verbatim
mbed_official	87:085cde657901	453	==============================================================================
mbed_official	87:085cde657901	454	##### Time Output Compare functions #####
mbed_official	87:085cde657901	455	==============================================================================
mbed_official	87:085cde657901	456	[..]
mbed_official	87:085cde657901	457	This section provides functions allowing to:
mbed_official	87:085cde657901	458	(+) Initialize and configure the TIM Output Compare.
mbed_official	87:085cde657901	459	(+) De-initialize the TIM Output Compare.
mbed_official	87:085cde657901	460	(+) Start the Time Output Compare.
mbed_official	87:085cde657901	461	(+) Stop the Time Output Compare.
mbed_official	87:085cde657901	462	(+) Start the Time Output Compare and enable interrupt.
mbed_official	87:085cde657901	463	(+) Stop the Time Output Compare and disable interrupt.
mbed_official	87:085cde657901	464	(+) Start the Time Output Compare and enable DMA transfer.
mbed_official	87:085cde657901	465	(+) Stop the Time Output Compare and disable DMA transfer.
mbed_official	87:085cde657901	466
mbed_official	87:085cde657901	467	@endverbatim
mbed_official	87:085cde657901	468	* @{
mbed_official	87:085cde657901	469	*/
mbed_official	87:085cde657901	470	/**
mbed_official	87:085cde657901	471	* @brief Initializes the TIM Output Compare according to the specified
mbed_official	87:085cde657901	472	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	226:b062af740e40	473	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	474	* the configuration information for TIM module.
mbed_official	87:085cde657901	475	* @retval HAL status
mbed_official	87:085cde657901	476	*/
mbed_official	87:085cde657901	477	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
mbed_official	87:085cde657901	478	{
mbed_official	87:085cde657901	479	/* Check the TIM handle allocation */
mbed_official	369:2e96f1b71984	480	if(htim == HAL_NULL)
mbed_official	87:085cde657901	481	{
mbed_official	87:085cde657901	482	return HAL_ERROR;
mbed_official	87:085cde657901	483	}
mbed_official	87:085cde657901	484
mbed_official	87:085cde657901	485	/* Check the parameters */
mbed_official	87:085cde657901	486	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	487	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	488	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	489
mbed_official	87:085cde657901	490	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	491	{
mbed_official	87:085cde657901	492	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	493	HAL_TIM_OC_MspInit(htim);
mbed_official	87:085cde657901	494	}
mbed_official	87:085cde657901	495
mbed_official	87:085cde657901	496	/* Set the TIM state */
mbed_official	87:085cde657901	497	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	498
mbed_official	87:085cde657901	499	/* Init the base time for the Output Compare */
mbed_official	87:085cde657901	500	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	501
mbed_official	87:085cde657901	502	/* Initialize the TIM state*/
mbed_official	87:085cde657901	503	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	504
mbed_official	87:085cde657901	505	return HAL_OK;
mbed_official	87:085cde657901	506	}
mbed_official	87:085cde657901	507
mbed_official	87:085cde657901	508	/**
mbed_official	87:085cde657901	509	* @brief DeInitializes the TIM peripheral
mbed_official	226:b062af740e40	510	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	511	* the configuration information for TIM module.
mbed_official	87:085cde657901	512	* @retval HAL status
mbed_official	87:085cde657901	513	*/
mbed_official	87:085cde657901	514	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	515	{
mbed_official	87:085cde657901	516	/* Check the parameters */
mbed_official	87:085cde657901	517	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	518
mbed_official	87:085cde657901	519	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	520
mbed_official	87:085cde657901	521	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	522	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	523
mbed_official	87:085cde657901	524	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	525	HAL_TIM_OC_MspDeInit(htim);
mbed_official	87:085cde657901	526
mbed_official	87:085cde657901	527	/* Change TIM state */
mbed_official	87:085cde657901	528	htim->State = HAL_TIM_STATE_RESET;
mbed_official	106:ced8cbb51063	529
mbed_official	106:ced8cbb51063	530	/* Release Lock */
mbed_official	106:ced8cbb51063	531	__HAL_UNLOCK(htim);
mbed_official	106:ced8cbb51063	532
mbed_official	87:085cde657901	533	return HAL_OK;
mbed_official	87:085cde657901	534	}
mbed_official	87:085cde657901	535
mbed_official	87:085cde657901	536	/**
mbed_official	87:085cde657901	537	* @brief Initializes the TIM Output Compare MSP.
mbed_official	226:b062af740e40	538	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	539	* the configuration information for TIM module.
mbed_official	87:085cde657901	540	* @retval None
mbed_official	87:085cde657901	541	*/
mbed_official	87:085cde657901	542	__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	543	{
mbed_official	87:085cde657901	544	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	545	the HAL_TIM_OC_MspInit could be implemented in the user file
mbed_official	87:085cde657901	546	*/
mbed_official	87:085cde657901	547	}
mbed_official	87:085cde657901	548
mbed_official	87:085cde657901	549	/**
mbed_official	87:085cde657901	550	* @brief DeInitializes TIM Output Compare MSP.
mbed_official	226:b062af740e40	551	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	552	* the configuration information for TIM module.
mbed_official	87:085cde657901	553	* @retval None
mbed_official	87:085cde657901	554	*/
mbed_official	87:085cde657901	555	__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	556	{
mbed_official	87:085cde657901	557	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	558	the HAL_TIM_OC_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	559	*/
mbed_official	87:085cde657901	560	}
mbed_official	87:085cde657901	561
mbed_official	87:085cde657901	562	/**
mbed_official	87:085cde657901	563	* @brief Starts the TIM Output Compare signal generation.
mbed_official	226:b062af740e40	564	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	565	* the configuration information for TIM module.
mbed_official	226:b062af740e40	566	* @param Channel: TIM Channel to be enabled.
mbed_official	87:085cde657901	567	* This parameter can be one of the following values:
mbed_official	87:085cde657901	568	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	569	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	570	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	571	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	572	* @retval HAL status
mbed_official	87:085cde657901	573	*/
mbed_official	87:085cde657901	574	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	575	{
mbed_official	87:085cde657901	576	/* Check the parameters */
mbed_official	87:085cde657901	577	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	578
mbed_official	87:085cde657901	579	/* Enable the Output compare channel */
mbed_official	87:085cde657901	580	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	581
mbed_official	87:085cde657901	582	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	583	{
mbed_official	87:085cde657901	584	/* Enable the main output */
mbed_official	87:085cde657901	585	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	586	}
mbed_official	87:085cde657901	587
mbed_official	87:085cde657901	588	/* Enable the Peripheral */
mbed_official	87:085cde657901	589	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	590
mbed_official	87:085cde657901	591	/* Return function status */
mbed_official	87:085cde657901	592	return HAL_OK;
mbed_official	87:085cde657901	593	}
mbed_official	87:085cde657901	594
mbed_official	87:085cde657901	595	/**
mbed_official	87:085cde657901	596	* @brief Stops the TIM Output Compare signal generation.
mbed_official	226:b062af740e40	597	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	598	* the configuration information for TIM module.
mbed_official	226:b062af740e40	599	* @param Channel: TIM Channel to be disabled.
mbed_official	87:085cde657901	600	* This parameter can be one of the following values:
mbed_official	87:085cde657901	601	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	602	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	603	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	604	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	605	* @retval HAL status
mbed_official	87:085cde657901	606	*/
mbed_official	87:085cde657901	607	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	608	{
mbed_official	87:085cde657901	609	/* Check the parameters */
mbed_official	87:085cde657901	610	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	611
mbed_official	87:085cde657901	612	/* Disable the Output compare channel */
mbed_official	87:085cde657901	613	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	614
mbed_official	87:085cde657901	615	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	616	{
mbed_official	87:085cde657901	617	/* Disable the Main Ouput */
mbed_official	87:085cde657901	618	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	619	}
mbed_official	87:085cde657901	620
mbed_official	87:085cde657901	621	/* Disable the Peripheral */
mbed_official	87:085cde657901	622	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	623
mbed_official	87:085cde657901	624	/* Return function status */
mbed_official	87:085cde657901	625	return HAL_OK;
mbed_official	87:085cde657901	626	}
mbed_official	87:085cde657901	627
mbed_official	87:085cde657901	628	/**
mbed_official	87:085cde657901	629	* @brief Starts the TIM Output Compare signal generation in interrupt mode.
mbed_official	226:b062af740e40	630	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	631	* the configuration information for TIM module.
mbed_official	226:b062af740e40	632	* @param Channel: TIM Channel to be enabled.
mbed_official	87:085cde657901	633	* This parameter can be one of the following values:
mbed_official	87:085cde657901	634	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	635	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	636	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	637	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	638	* @retval HAL status
mbed_official	87:085cde657901	639	*/
mbed_official	87:085cde657901	640	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	641	{
mbed_official	87:085cde657901	642	/* Check the parameters */
mbed_official	87:085cde657901	643	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	644
mbed_official	87:085cde657901	645	switch (Channel)
mbed_official	87:085cde657901	646	{
mbed_official	87:085cde657901	647	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	648	{
mbed_official	87:085cde657901	649	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	650	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	651	}
mbed_official	87:085cde657901	652	break;
mbed_official	87:085cde657901	653
mbed_official	87:085cde657901	654	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	655	{
mbed_official	87:085cde657901	656	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	657	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	658	}
mbed_official	87:085cde657901	659	break;
mbed_official	87:085cde657901	660
mbed_official	87:085cde657901	661	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	662	{
mbed_official	87:085cde657901	663	/* Enable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	664	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	665	}
mbed_official	87:085cde657901	666	break;
mbed_official	87:085cde657901	667
mbed_official	87:085cde657901	668	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	669	{
mbed_official	87:085cde657901	670	/* Enable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	671	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	672	}
mbed_official	87:085cde657901	673	break;
mbed_official	87:085cde657901	674
mbed_official	87:085cde657901	675	default:
mbed_official	87:085cde657901	676	break;
mbed_official	87:085cde657901	677	}
mbed_official	87:085cde657901	678
mbed_official	87:085cde657901	679	/* Enable the Output compare channel */
mbed_official	87:085cde657901	680	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	681
mbed_official	87:085cde657901	682	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	683	{
mbed_official	87:085cde657901	684	/* Enable the main output */
mbed_official	87:085cde657901	685	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	686	}
mbed_official	87:085cde657901	687
mbed_official	87:085cde657901	688	/* Enable the Peripheral */
mbed_official	87:085cde657901	689	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	690
mbed_official	87:085cde657901	691	/* Return function status */
mbed_official	87:085cde657901	692	return HAL_OK;
mbed_official	87:085cde657901	693	}
mbed_official	87:085cde657901	694
mbed_official	87:085cde657901	695	/**
mbed_official	87:085cde657901	696	* @brief Stops the TIM Output Compare signal generation in interrupt mode.
mbed_official	226:b062af740e40	697	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	698	* the configuration information for TIM module.
mbed_official	226:b062af740e40	699	* @param Channel: TIM Channel to be disabled.
mbed_official	87:085cde657901	700	* This parameter can be one of the following values:
mbed_official	87:085cde657901	701	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	702	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	703	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	704	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	705	* @retval HAL status
mbed_official	87:085cde657901	706	*/
mbed_official	87:085cde657901	707	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	708	{
mbed_official	87:085cde657901	709	/* Check the parameters */
mbed_official	87:085cde657901	710	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	711
mbed_official	87:085cde657901	712	switch (Channel)
mbed_official	87:085cde657901	713	{
mbed_official	87:085cde657901	714	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	715	{
mbed_official	87:085cde657901	716	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	717	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	718	}
mbed_official	87:085cde657901	719	break;
mbed_official	87:085cde657901	720
mbed_official	87:085cde657901	721	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	722	{
mbed_official	87:085cde657901	723	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	724	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	725	}
mbed_official	87:085cde657901	726	break;
mbed_official	87:085cde657901	727
mbed_official	87:085cde657901	728	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	729	{
mbed_official	87:085cde657901	730	/* Disable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	731	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	732	}
mbed_official	87:085cde657901	733	break;
mbed_official	87:085cde657901	734
mbed_official	87:085cde657901	735	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	736	{
mbed_official	87:085cde657901	737	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	738	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	739	}
mbed_official	87:085cde657901	740	break;
mbed_official	87:085cde657901	741
mbed_official	87:085cde657901	742	default:
mbed_official	87:085cde657901	743	break;
mbed_official	87:085cde657901	744	}
mbed_official	87:085cde657901	745
mbed_official	87:085cde657901	746	/* Disable the Output compare channel */
mbed_official	87:085cde657901	747	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	748
mbed_official	87:085cde657901	749	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	750	{
mbed_official	87:085cde657901	751	/* Disable the Main Ouput */
mbed_official	87:085cde657901	752	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	753	}
mbed_official	87:085cde657901	754
mbed_official	87:085cde657901	755	/* Disable the Peripheral */
mbed_official	87:085cde657901	756	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	757
mbed_official	87:085cde657901	758	/* Return function status */
mbed_official	87:085cde657901	759	return HAL_OK;
mbed_official	87:085cde657901	760	}
mbed_official	87:085cde657901	761
mbed_official	87:085cde657901	762	/**
mbed_official	87:085cde657901	763	* @brief Starts the TIM Output Compare signal generation in DMA mode.
mbed_official	226:b062af740e40	764	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	765	* the configuration information for TIM module.
mbed_official	226:b062af740e40	766	* @param Channel: TIM Channel to be enabled.
mbed_official	87:085cde657901	767	* This parameter can be one of the following values:
mbed_official	87:085cde657901	768	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	769	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	770	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	771	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	772	* @param pData: The source Buffer address.
mbed_official	87:085cde657901	773	* @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official	87:085cde657901	774	* @retval HAL status
mbed_official	87:085cde657901	775	*/
mbed_official	87:085cde657901	776	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
mbed_official	87:085cde657901	777	{
mbed_official	87:085cde657901	778	/* Check the parameters */
mbed_official	87:085cde657901	779	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	780
mbed_official	87:085cde657901	781	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	782	{
mbed_official	87:085cde657901	783	return HAL_BUSY;
mbed_official	87:085cde657901	784	}
mbed_official	87:085cde657901	785	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	786	{
mbed_official	87:085cde657901	787	if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official	87:085cde657901	788	{
mbed_official	87:085cde657901	789	return HAL_ERROR;
mbed_official	87:085cde657901	790	}
mbed_official	87:085cde657901	791	else
mbed_official	87:085cde657901	792	{
mbed_official	87:085cde657901	793	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	794	}
mbed_official	87:085cde657901	795	}
mbed_official	87:085cde657901	796	switch (Channel)
mbed_official	87:085cde657901	797	{
mbed_official	87:085cde657901	798	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	799	{
mbed_official	87:085cde657901	800	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	801	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	802
mbed_official	87:085cde657901	803	/* Set the DMA error callback */
mbed_official	87:085cde657901	804	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	805
mbed_official	87:085cde657901	806	/* Enable the DMA Stream */
mbed_official	87:085cde657901	807	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official	87:085cde657901	808
mbed_official	87:085cde657901	809	/* Enable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	810	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	811	}
mbed_official	87:085cde657901	812	break;
mbed_official	87:085cde657901	813
mbed_official	87:085cde657901	814	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	815	{
mbed_official	87:085cde657901	816	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	817	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	818
mbed_official	87:085cde657901	819	/* Set the DMA error callback */
mbed_official	87:085cde657901	820	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	821
mbed_official	87:085cde657901	822	/* Enable the DMA Stream */
mbed_official	87:085cde657901	823	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official	87:085cde657901	824
mbed_official	87:085cde657901	825	/* Enable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	826	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	827	}
mbed_official	87:085cde657901	828	break;
mbed_official	87:085cde657901	829
mbed_official	87:085cde657901	830	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	831	{
mbed_official	87:085cde657901	832	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	833	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	834
mbed_official	87:085cde657901	835	/* Set the DMA error callback */
mbed_official	87:085cde657901	836	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	837
mbed_official	87:085cde657901	838	/* Enable the DMA Stream */
mbed_official	87:085cde657901	839	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official	87:085cde657901	840
mbed_official	87:085cde657901	841	/* Enable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	842	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	843	}
mbed_official	87:085cde657901	844	break;
mbed_official	87:085cde657901	845
mbed_official	87:085cde657901	846	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	847	{
mbed_official	87:085cde657901	848	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	849	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	850
mbed_official	87:085cde657901	851	/* Set the DMA error callback */
mbed_official	87:085cde657901	852	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	853
mbed_official	87:085cde657901	854	/* Enable the DMA Stream */
mbed_official	87:085cde657901	855	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official	87:085cde657901	856
mbed_official	87:085cde657901	857	/* Enable the TIM Capture/Compare 4 DMA request */
mbed_official	87:085cde657901	858	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	859	}
mbed_official	87:085cde657901	860	break;
mbed_official	87:085cde657901	861
mbed_official	87:085cde657901	862	default:
mbed_official	87:085cde657901	863	break;
mbed_official	87:085cde657901	864	}
mbed_official	87:085cde657901	865
mbed_official	87:085cde657901	866	/* Enable the Output compare channel */
mbed_official	87:085cde657901	867	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	868
mbed_official	87:085cde657901	869	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	870	{
mbed_official	87:085cde657901	871	/* Enable the main output */
mbed_official	87:085cde657901	872	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	873	}
mbed_official	87:085cde657901	874
mbed_official	87:085cde657901	875	/* Enable the Peripheral */
mbed_official	87:085cde657901	876	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	877
mbed_official	87:085cde657901	878	/* Return function status */
mbed_official	87:085cde657901	879	return HAL_OK;
mbed_official	87:085cde657901	880	}
mbed_official	87:085cde657901	881
mbed_official	87:085cde657901	882	/**
mbed_official	87:085cde657901	883	* @brief Stops the TIM Output Compare signal generation in DMA mode.
mbed_official	226:b062af740e40	884	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	885	* the configuration information for TIM module.
mbed_official	226:b062af740e40	886	* @param Channel: TIM Channel to be disabled.
mbed_official	87:085cde657901	887	* This parameter can be one of the following values:
mbed_official	87:085cde657901	888	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	889	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	890	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	891	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	892	* @retval HAL status
mbed_official	87:085cde657901	893	*/
mbed_official	87:085cde657901	894	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	895	{
mbed_official	87:085cde657901	896	/* Check the parameters */
mbed_official	87:085cde657901	897	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	898
mbed_official	87:085cde657901	899	switch (Channel)
mbed_official	87:085cde657901	900	{
mbed_official	87:085cde657901	901	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	902	{
mbed_official	87:085cde657901	903	/* Disable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	904	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	905	}
mbed_official	87:085cde657901	906	break;
mbed_official	87:085cde657901	907
mbed_official	87:085cde657901	908	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	909	{
mbed_official	87:085cde657901	910	/* Disable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	911	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	912	}
mbed_official	87:085cde657901	913	break;
mbed_official	87:085cde657901	914
mbed_official	87:085cde657901	915	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	916	{
mbed_official	87:085cde657901	917	/* Disable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	918	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	919	}
mbed_official	87:085cde657901	920	break;
mbed_official	87:085cde657901	921
mbed_official	87:085cde657901	922	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	923	{
mbed_official	87:085cde657901	924	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	925	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	926	}
mbed_official	87:085cde657901	927	break;
mbed_official	87:085cde657901	928
mbed_official	87:085cde657901	929	default:
mbed_official	87:085cde657901	930	break;
mbed_official	87:085cde657901	931	}
mbed_official	87:085cde657901	932
mbed_official	87:085cde657901	933	/* Disable the Output compare channel */
mbed_official	87:085cde657901	934	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	935
mbed_official	87:085cde657901	936	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	937	{
mbed_official	87:085cde657901	938	/* Disable the Main Ouput */
mbed_official	87:085cde657901	939	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	940	}
mbed_official	87:085cde657901	941
mbed_official	87:085cde657901	942	/* Disable the Peripheral */
mbed_official	87:085cde657901	943	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	944
mbed_official	87:085cde657901	945	/* Change the htim state */
mbed_official	87:085cde657901	946	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	947
mbed_official	87:085cde657901	948	/* Return function status */
mbed_official	87:085cde657901	949	return HAL_OK;
mbed_official	87:085cde657901	950	}
mbed_official	87:085cde657901	951
mbed_official	87:085cde657901	952	/**
mbed_official	87:085cde657901	953	* @}
mbed_official	87:085cde657901	954	*/
mbed_official	87:085cde657901	955
mbed_official	87:085cde657901	956	/** @defgroup TIM_Group3 Time PWM functions
mbed_official	87:085cde657901	957	* @brief Time PWM functions
mbed_official	87:085cde657901	958	*
mbed_official	87:085cde657901	959	@verbatim
mbed_official	87:085cde657901	960	==============================================================================
mbed_official	87:085cde657901	961	##### Time PWM functions #####
mbed_official	87:085cde657901	962	==============================================================================
mbed_official	87:085cde657901	963	[..]
mbed_official	87:085cde657901	964	This section provides functions allowing to:
mbed_official	87:085cde657901	965	(+) Initialize and configure the TIM OPWM.
mbed_official	87:085cde657901	966	(+) De-initialize the TIM PWM.
mbed_official	87:085cde657901	967	(+) Start the Time PWM.
mbed_official	87:085cde657901	968	(+) Stop the Time PWM.
mbed_official	87:085cde657901	969	(+) Start the Time PWM and enable interrupt.
mbed_official	87:085cde657901	970	(+) Stop the Time PWM and disable interrupt.
mbed_official	87:085cde657901	971	(+) Start the Time PWM and enable DMA transfer.
mbed_official	87:085cde657901	972	(+) Stop the Time PWM and disable DMA transfer.
mbed_official	87:085cde657901	973
mbed_official	87:085cde657901	974	@endverbatim
mbed_official	87:085cde657901	975	* @{
mbed_official	87:085cde657901	976	*/
mbed_official	87:085cde657901	977	/**
mbed_official	87:085cde657901	978	* @brief Initializes the TIM PWM Time Base according to the specified
mbed_official	87:085cde657901	979	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	226:b062af740e40	980	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	981	* the configuration information for TIM module.
mbed_official	87:085cde657901	982	* @retval HAL status
mbed_official	87:085cde657901	983	*/
mbed_official	87:085cde657901	984	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	985	{
mbed_official	87:085cde657901	986	/* Check the TIM handle allocation */
mbed_official	369:2e96f1b71984	987	if(htim == HAL_NULL)
mbed_official	87:085cde657901	988	{
mbed_official	87:085cde657901	989	return HAL_ERROR;
mbed_official	87:085cde657901	990	}
mbed_official	87:085cde657901	991
mbed_official	87:085cde657901	992	/* Check the parameters */
mbed_official	87:085cde657901	993	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	994	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	995	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	996
mbed_official	87:085cde657901	997	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	998	{
mbed_official	87:085cde657901	999	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	1000	HAL_TIM_PWM_MspInit(htim);
mbed_official	87:085cde657901	1001	}
mbed_official	87:085cde657901	1002
mbed_official	87:085cde657901	1003	/* Set the TIM state */
mbed_official	87:085cde657901	1004	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1005
mbed_official	87:085cde657901	1006	/* Init the base time for the PWM */
mbed_official	87:085cde657901	1007	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	1008
mbed_official	87:085cde657901	1009	/* Initialize the TIM state*/
mbed_official	87:085cde657901	1010	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1011
mbed_official	87:085cde657901	1012	return HAL_OK;
mbed_official	87:085cde657901	1013	}
mbed_official	87:085cde657901	1014
mbed_official	87:085cde657901	1015	/**
mbed_official	87:085cde657901	1016	* @brief DeInitializes the TIM peripheral
mbed_official	226:b062af740e40	1017	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1018	* the configuration information for TIM module.
mbed_official	87:085cde657901	1019	* @retval HAL status
mbed_official	87:085cde657901	1020	*/
mbed_official	87:085cde657901	1021	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1022	{
mbed_official	87:085cde657901	1023	/* Check the parameters */
mbed_official	87:085cde657901	1024	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1025
mbed_official	87:085cde657901	1026	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1027
mbed_official	87:085cde657901	1028	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	1029	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1030
mbed_official	87:085cde657901	1031	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	1032	HAL_TIM_PWM_MspDeInit(htim);
mbed_official	87:085cde657901	1033
mbed_official	87:085cde657901	1034	/* Change TIM state */
mbed_official	87:085cde657901	1035	htim->State = HAL_TIM_STATE_RESET;
mbed_official	106:ced8cbb51063	1036
mbed_official	106:ced8cbb51063	1037	/* Release Lock */
mbed_official	106:ced8cbb51063	1038	__HAL_UNLOCK(htim);
mbed_official	106:ced8cbb51063	1039
mbed_official	87:085cde657901	1040	return HAL_OK;
mbed_official	87:085cde657901	1041	}
mbed_official	87:085cde657901	1042
mbed_official	87:085cde657901	1043	/**
mbed_official	87:085cde657901	1044	* @brief Initializes the TIM PWM MSP.
mbed_official	226:b062af740e40	1045	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1046	* the configuration information for TIM module.
mbed_official	87:085cde657901	1047	* @retval None
mbed_official	87:085cde657901	1048	*/
mbed_official	87:085cde657901	1049	__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1050	{
mbed_official	87:085cde657901	1051	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1052	the HAL_TIM_PWM_MspInit could be implemented in the user file
mbed_official	87:085cde657901	1053	*/
mbed_official	87:085cde657901	1054	}
mbed_official	87:085cde657901	1055
mbed_official	87:085cde657901	1056	/**
mbed_official	87:085cde657901	1057	* @brief DeInitializes TIM PWM MSP.
mbed_official	226:b062af740e40	1058	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1059	* the configuration information for TIM module.
mbed_official	87:085cde657901	1060	* @retval None
mbed_official	87:085cde657901	1061	*/
mbed_official	87:085cde657901	1062	__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1063	{
mbed_official	87:085cde657901	1064	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1065	the HAL_TIM_PWM_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	1066	*/
mbed_official	87:085cde657901	1067	}
mbed_official	87:085cde657901	1068
mbed_official	87:085cde657901	1069	/**
mbed_official	87:085cde657901	1070	* @brief Starts the PWM signal generation.
mbed_official	226:b062af740e40	1071	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1072	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1073	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	1074	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1075	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1076	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1077	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1078	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1079	* @retval HAL status
mbed_official	87:085cde657901	1080	*/
mbed_official	87:085cde657901	1081	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1082	{
mbed_official	87:085cde657901	1083	/* Check the parameters */
mbed_official	87:085cde657901	1084	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1085
mbed_official	87:085cde657901	1086	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	1087	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1088
mbed_official	87:085cde657901	1089	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1090	{
mbed_official	87:085cde657901	1091	/* Enable the main output */
mbed_official	87:085cde657901	1092	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	1093	}
mbed_official	87:085cde657901	1094
mbed_official	87:085cde657901	1095	/* Enable the Peripheral */
mbed_official	87:085cde657901	1096	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1097
mbed_official	87:085cde657901	1098	/* Return function status */
mbed_official	87:085cde657901	1099	return HAL_OK;
mbed_official	87:085cde657901	1100	}
mbed_official	87:085cde657901	1101
mbed_official	87:085cde657901	1102	/**
mbed_official	87:085cde657901	1103	* @brief Stops the PWM signal generation.
mbed_official	226:b062af740e40	1104	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1105	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1106	* @param Channel: TIM Channels to be disabled.
mbed_official	87:085cde657901	1107	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1108	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1109	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1110	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1111	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1112	* @retval HAL status
mbed_official	87:085cde657901	1113	*/
mbed_official	87:085cde657901	1114	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1115	{
mbed_official	87:085cde657901	1116	/* Check the parameters */
mbed_official	87:085cde657901	1117	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1118
mbed_official	87:085cde657901	1119	/* Disable the Capture compare channel */
mbed_official	87:085cde657901	1120	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1121
mbed_official	87:085cde657901	1122	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1123	{
mbed_official	87:085cde657901	1124	/* Disable the Main Ouput */
mbed_official	87:085cde657901	1125	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	1126	}
mbed_official	87:085cde657901	1127
mbed_official	87:085cde657901	1128	/* Disable the Peripheral */
mbed_official	87:085cde657901	1129	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1130
mbed_official	87:085cde657901	1131	/* Change the htim state */
mbed_official	87:085cde657901	1132	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1133
mbed_official	87:085cde657901	1134	/* Return function status */
mbed_official	87:085cde657901	1135	return HAL_OK;
mbed_official	87:085cde657901	1136	}
mbed_official	87:085cde657901	1137
mbed_official	87:085cde657901	1138	/**
mbed_official	87:085cde657901	1139	* @brief Starts the PWM signal generation in interrupt mode.
mbed_official	226:b062af740e40	1140	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1141	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1142	* @param Channel: TIM Channel to be disabled.
mbed_official	87:085cde657901	1143	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1144	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1145	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1146	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1147	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1148	* @retval HAL status
mbed_official	87:085cde657901	1149	*/
mbed_official	87:085cde657901	1150	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1151	{
mbed_official	87:085cde657901	1152	/* Check the parameters */
mbed_official	87:085cde657901	1153	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1154
mbed_official	87:085cde657901	1155	switch (Channel)
mbed_official	87:085cde657901	1156	{
mbed_official	87:085cde657901	1157	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1158	{
mbed_official	87:085cde657901	1159	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	1160	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	1161	}
mbed_official	87:085cde657901	1162	break;
mbed_official	87:085cde657901	1163
mbed_official	87:085cde657901	1164	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1165	{
mbed_official	87:085cde657901	1166	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	1167	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	1168	}
mbed_official	87:085cde657901	1169	break;
mbed_official	87:085cde657901	1170
mbed_official	87:085cde657901	1171	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1172	{
mbed_official	87:085cde657901	1173	/* Enable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	1174	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	1175	}
mbed_official	87:085cde657901	1176	break;
mbed_official	87:085cde657901	1177
mbed_official	87:085cde657901	1178	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1179	{
mbed_official	87:085cde657901	1180	/* Enable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1181	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	1182	}
mbed_official	87:085cde657901	1183	break;
mbed_official	87:085cde657901	1184
mbed_official	87:085cde657901	1185	default:
mbed_official	87:085cde657901	1186	break;
mbed_official	87:085cde657901	1187	}
mbed_official	87:085cde657901	1188
mbed_official	87:085cde657901	1189	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	1190	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1191
mbed_official	87:085cde657901	1192	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1193	{
mbed_official	87:085cde657901	1194	/* Enable the main output */
mbed_official	87:085cde657901	1195	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	1196	}
mbed_official	87:085cde657901	1197
mbed_official	87:085cde657901	1198	/* Enable the Peripheral */
mbed_official	87:085cde657901	1199	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1200
mbed_official	87:085cde657901	1201	/* Return function status */
mbed_official	87:085cde657901	1202	return HAL_OK;
mbed_official	87:085cde657901	1203	}
mbed_official	87:085cde657901	1204
mbed_official	87:085cde657901	1205	/**
mbed_official	87:085cde657901	1206	* @brief Stops the PWM signal generation in interrupt mode.
mbed_official	226:b062af740e40	1207	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1208	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1209	* @param Channel: TIM Channels to be disabled.
mbed_official	87:085cde657901	1210	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1211	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1212	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1213	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1214	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1215	* @retval HAL status
mbed_official	87:085cde657901	1216	*/
mbed_official	87:085cde657901	1217	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1218	{
mbed_official	87:085cde657901	1219	/* Check the parameters */
mbed_official	87:085cde657901	1220	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1221
mbed_official	87:085cde657901	1222	switch (Channel)
mbed_official	87:085cde657901	1223	{
mbed_official	87:085cde657901	1224	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1225	{
mbed_official	87:085cde657901	1226	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	1227	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	1228	}
mbed_official	87:085cde657901	1229	break;
mbed_official	87:085cde657901	1230
mbed_official	87:085cde657901	1231	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1232	{
mbed_official	87:085cde657901	1233	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	1234	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	1235	}
mbed_official	87:085cde657901	1236	break;
mbed_official	87:085cde657901	1237
mbed_official	87:085cde657901	1238	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1239	{
mbed_official	87:085cde657901	1240	/* Disable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	1241	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	1242	}
mbed_official	87:085cde657901	1243	break;
mbed_official	87:085cde657901	1244
mbed_official	87:085cde657901	1245	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1246	{
mbed_official	87:085cde657901	1247	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1248	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	1249	}
mbed_official	87:085cde657901	1250	break;
mbed_official	87:085cde657901	1251
mbed_official	87:085cde657901	1252	default:
mbed_official	87:085cde657901	1253	break;
mbed_official	87:085cde657901	1254	}
mbed_official	87:085cde657901	1255
mbed_official	87:085cde657901	1256	/* Disable the Capture compare channel */
mbed_official	87:085cde657901	1257	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1258
mbed_official	87:085cde657901	1259	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1260	{
mbed_official	87:085cde657901	1261	/* Disable the Main Ouput */
mbed_official	87:085cde657901	1262	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	1263	}
mbed_official	87:085cde657901	1264
mbed_official	87:085cde657901	1265	/* Disable the Peripheral */
mbed_official	87:085cde657901	1266	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1267
mbed_official	87:085cde657901	1268	/* Return function status */
mbed_official	87:085cde657901	1269	return HAL_OK;
mbed_official	87:085cde657901	1270	}
mbed_official	87:085cde657901	1271
mbed_official	87:085cde657901	1272	/**
mbed_official	87:085cde657901	1273	* @brief Starts the TIM PWM signal generation in DMA mode.
mbed_official	226:b062af740e40	1274	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1275	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1276	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	1277	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1278	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1279	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1280	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1281	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1282	* @param pData: The source Buffer address.
mbed_official	87:085cde657901	1283	* @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official	87:085cde657901	1284	* @retval HAL status
mbed_official	87:085cde657901	1285	*/
mbed_official	87:085cde657901	1286	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
mbed_official	87:085cde657901	1287	{
mbed_official	87:085cde657901	1288	/* Check the parameters */
mbed_official	87:085cde657901	1289	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1290
mbed_official	87:085cde657901	1291	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	1292	{
mbed_official	87:085cde657901	1293	return HAL_BUSY;
mbed_official	87:085cde657901	1294	}
mbed_official	87:085cde657901	1295	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	1296	{
mbed_official	87:085cde657901	1297	if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official	87:085cde657901	1298	{
mbed_official	87:085cde657901	1299	return HAL_ERROR;
mbed_official	87:085cde657901	1300	}
mbed_official	87:085cde657901	1301	else
mbed_official	87:085cde657901	1302	{
mbed_official	87:085cde657901	1303	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1304	}
mbed_official	87:085cde657901	1305	}
mbed_official	87:085cde657901	1306	switch (Channel)
mbed_official	87:085cde657901	1307	{
mbed_official	87:085cde657901	1308	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1309	{
mbed_official	87:085cde657901	1310	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1311	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	1312
mbed_official	87:085cde657901	1313	/* Set the DMA error callback */
mbed_official	87:085cde657901	1314	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1315
mbed_official	87:085cde657901	1316	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1317	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official	87:085cde657901	1318
mbed_official	87:085cde657901	1319	/* Enable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	1320	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	1321	}
mbed_official	87:085cde657901	1322	break;
mbed_official	87:085cde657901	1323
mbed_official	87:085cde657901	1324	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1325	{
mbed_official	87:085cde657901	1326	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1327	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	1328
mbed_official	87:085cde657901	1329	/* Set the DMA error callback */
mbed_official	87:085cde657901	1330	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1331
mbed_official	87:085cde657901	1332	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1333	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official	87:085cde657901	1334
mbed_official	87:085cde657901	1335	/* Enable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	1336	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	1337	}
mbed_official	87:085cde657901	1338	break;
mbed_official	87:085cde657901	1339
mbed_official	87:085cde657901	1340	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1341	{
mbed_official	87:085cde657901	1342	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1343	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	1344
mbed_official	87:085cde657901	1345	/* Set the DMA error callback */
mbed_official	87:085cde657901	1346	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1347
mbed_official	87:085cde657901	1348	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1349	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official	87:085cde657901	1350
mbed_official	87:085cde657901	1351	/* Enable the TIM Output Capture/Compare 3 request */
mbed_official	87:085cde657901	1352	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	1353	}
mbed_official	87:085cde657901	1354	break;
mbed_official	87:085cde657901	1355
mbed_official	87:085cde657901	1356	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1357	{
mbed_official	87:085cde657901	1358	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1359	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	1360
mbed_official	87:085cde657901	1361	/* Set the DMA error callback */
mbed_official	87:085cde657901	1362	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1363
mbed_official	87:085cde657901	1364	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1365	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official	87:085cde657901	1366
mbed_official	87:085cde657901	1367	/* Enable the TIM Capture/Compare 4 DMA request */
mbed_official	87:085cde657901	1368	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	1369	}
mbed_official	87:085cde657901	1370	break;
mbed_official	87:085cde657901	1371
mbed_official	87:085cde657901	1372	default:
mbed_official	87:085cde657901	1373	break;
mbed_official	87:085cde657901	1374	}
mbed_official	87:085cde657901	1375
mbed_official	87:085cde657901	1376	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	1377	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1378
mbed_official	87:085cde657901	1379	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1380	{
mbed_official	87:085cde657901	1381	/* Enable the main output */
mbed_official	87:085cde657901	1382	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	1383	}
mbed_official	87:085cde657901	1384
mbed_official	87:085cde657901	1385	/* Enable the Peripheral */
mbed_official	87:085cde657901	1386	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1387
mbed_official	87:085cde657901	1388	/* Return function status */
mbed_official	87:085cde657901	1389	return HAL_OK;
mbed_official	87:085cde657901	1390	}
mbed_official	87:085cde657901	1391
mbed_official	87:085cde657901	1392	/**
mbed_official	87:085cde657901	1393	* @brief Stops the TIM PWM signal generation in DMA mode.
mbed_official	226:b062af740e40	1394	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1395	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1396	* @param Channel: TIM Channels to be disabled.
mbed_official	87:085cde657901	1397	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1398	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1399	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1400	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1401	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1402	* @retval HAL status
mbed_official	87:085cde657901	1403	*/
mbed_official	87:085cde657901	1404	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1405	{
mbed_official	87:085cde657901	1406	/* Check the parameters */
mbed_official	87:085cde657901	1407	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1408
mbed_official	87:085cde657901	1409	switch (Channel)
mbed_official	87:085cde657901	1410	{
mbed_official	87:085cde657901	1411	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1412	{
mbed_official	87:085cde657901	1413	/* Disable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	1414	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	1415	}
mbed_official	87:085cde657901	1416	break;
mbed_official	87:085cde657901	1417
mbed_official	87:085cde657901	1418	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1419	{
mbed_official	87:085cde657901	1420	/* Disable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	1421	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	1422	}
mbed_official	87:085cde657901	1423	break;
mbed_official	87:085cde657901	1424
mbed_official	87:085cde657901	1425	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1426	{
mbed_official	87:085cde657901	1427	/* Disable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	1428	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	1429	}
mbed_official	87:085cde657901	1430	break;
mbed_official	87:085cde657901	1431
mbed_official	87:085cde657901	1432	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1433	{
mbed_official	87:085cde657901	1434	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1435	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	1436	}
mbed_official	87:085cde657901	1437	break;
mbed_official	87:085cde657901	1438
mbed_official	87:085cde657901	1439	default:
mbed_official	87:085cde657901	1440	break;
mbed_official	87:085cde657901	1441	}
mbed_official	87:085cde657901	1442
mbed_official	87:085cde657901	1443	/* Disable the Capture compare channel */
mbed_official	87:085cde657901	1444	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1445
mbed_official	87:085cde657901	1446	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	1447	{
mbed_official	87:085cde657901	1448	/* Disable the Main Ouput */
mbed_official	87:085cde657901	1449	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	1450	}
mbed_official	87:085cde657901	1451
mbed_official	87:085cde657901	1452	/* Disable the Peripheral */
mbed_official	87:085cde657901	1453	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1454
mbed_official	87:085cde657901	1455	/* Change the htim state */
mbed_official	87:085cde657901	1456	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1457
mbed_official	87:085cde657901	1458	/* Return function status */
mbed_official	87:085cde657901	1459	return HAL_OK;
mbed_official	87:085cde657901	1460	}
mbed_official	87:085cde657901	1461
mbed_official	87:085cde657901	1462	/**
mbed_official	87:085cde657901	1463	* @}
mbed_official	87:085cde657901	1464	*/
mbed_official	87:085cde657901	1465
mbed_official	87:085cde657901	1466	/** @defgroup TIM_Group4 Time Input Capture functions
mbed_official	87:085cde657901	1467	* @brief Time Input Capture functions
mbed_official	87:085cde657901	1468	*
mbed_official	87:085cde657901	1469	@verbatim
mbed_official	87:085cde657901	1470	==============================================================================
mbed_official	87:085cde657901	1471	##### Time Input Capture functions #####
mbed_official	87:085cde657901	1472	==============================================================================
mbed_official	87:085cde657901	1473	[..]
mbed_official	87:085cde657901	1474	This section provides functions allowing to:
mbed_official	87:085cde657901	1475	(+) Initialize and configure the TIM Input Capture.
mbed_official	87:085cde657901	1476	(+) De-initialize the TIM Input Capture.
mbed_official	87:085cde657901	1477	(+) Start the Time Input Capture.
mbed_official	87:085cde657901	1478	(+) Stop the Time Input Capture.
mbed_official	87:085cde657901	1479	(+) Start the Time Input Capture and enable interrupt.
mbed_official	87:085cde657901	1480	(+) Stop the Time Input Capture and disable interrupt.
mbed_official	87:085cde657901	1481	(+) Start the Time Input Capture and enable DMA transfer.
mbed_official	87:085cde657901	1482	(+) Stop the Time Input Capture and disable DMA transfer.
mbed_official	87:085cde657901	1483
mbed_official	87:085cde657901	1484	@endverbatim
mbed_official	87:085cde657901	1485	* @{
mbed_official	87:085cde657901	1486	*/
mbed_official	87:085cde657901	1487	/**
mbed_official	87:085cde657901	1488	* @brief Initializes the TIM Input Capture Time base according to the specified
mbed_official	87:085cde657901	1489	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	226:b062af740e40	1490	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1491	* the configuration information for TIM module.
mbed_official	87:085cde657901	1492	* @retval HAL status
mbed_official	87:085cde657901	1493	*/
mbed_official	87:085cde657901	1494	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1495	{
mbed_official	87:085cde657901	1496	/* Check the TIM handle allocation */
mbed_official	369:2e96f1b71984	1497	if(htim == HAL_NULL)
mbed_official	87:085cde657901	1498	{
mbed_official	87:085cde657901	1499	return HAL_ERROR;
mbed_official	87:085cde657901	1500	}
mbed_official	87:085cde657901	1501
mbed_official	87:085cde657901	1502	/* Check the parameters */
mbed_official	87:085cde657901	1503	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1504	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	1505	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	1506
mbed_official	87:085cde657901	1507	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	1508	{
mbed_official	87:085cde657901	1509	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	1510	HAL_TIM_IC_MspInit(htim);
mbed_official	87:085cde657901	1511	}
mbed_official	87:085cde657901	1512
mbed_official	87:085cde657901	1513	/* Set the TIM state */
mbed_official	87:085cde657901	1514	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1515
mbed_official	87:085cde657901	1516	/* Init the base time for the input capture */
mbed_official	87:085cde657901	1517	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	1518
mbed_official	87:085cde657901	1519	/* Initialize the TIM state*/
mbed_official	87:085cde657901	1520	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1521
mbed_official	87:085cde657901	1522	return HAL_OK;
mbed_official	87:085cde657901	1523	}
mbed_official	87:085cde657901	1524
mbed_official	87:085cde657901	1525	/**
mbed_official	87:085cde657901	1526	* @brief DeInitializes the TIM peripheral
mbed_official	226:b062af740e40	1527	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1528	* the configuration information for TIM module.
mbed_official	87:085cde657901	1529	* @retval HAL status
mbed_official	87:085cde657901	1530	*/
mbed_official	87:085cde657901	1531	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1532	{
mbed_official	87:085cde657901	1533	/* Check the parameters */
mbed_official	87:085cde657901	1534	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1535
mbed_official	87:085cde657901	1536	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1537
mbed_official	87:085cde657901	1538	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	1539	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1540
mbed_official	87:085cde657901	1541	/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	1542	HAL_TIM_IC_MspDeInit(htim);
mbed_official	87:085cde657901	1543
mbed_official	87:085cde657901	1544	/* Change TIM state */
mbed_official	87:085cde657901	1545	htim->State = HAL_TIM_STATE_RESET;
mbed_official	106:ced8cbb51063	1546
mbed_official	106:ced8cbb51063	1547	/* Release Lock */
mbed_official	106:ced8cbb51063	1548	__HAL_UNLOCK(htim);
mbed_official	106:ced8cbb51063	1549
mbed_official	87:085cde657901	1550	return HAL_OK;
mbed_official	87:085cde657901	1551	}
mbed_official	87:085cde657901	1552
mbed_official	87:085cde657901	1553	/**
mbed_official	87:085cde657901	1554	* @brief Initializes the TIM INput Capture MSP.
mbed_official	226:b062af740e40	1555	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1556	* the configuration information for TIM module.
mbed_official	87:085cde657901	1557	* @retval None
mbed_official	87:085cde657901	1558	*/
mbed_official	87:085cde657901	1559	__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1560	{
mbed_official	87:085cde657901	1561	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1562	the HAL_TIM_IC_MspInit could be implemented in the user file
mbed_official	87:085cde657901	1563	*/
mbed_official	87:085cde657901	1564	}
mbed_official	87:085cde657901	1565
mbed_official	87:085cde657901	1566	/**
mbed_official	87:085cde657901	1567	* @brief DeInitializes TIM Input Capture MSP.
mbed_official	226:b062af740e40	1568	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1569	* the configuration information for TIM module.
mbed_official	87:085cde657901	1570	* @retval None
mbed_official	87:085cde657901	1571	*/
mbed_official	87:085cde657901	1572	__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	1573	{
mbed_official	87:085cde657901	1574	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1575	the HAL_TIM_IC_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	1576	*/
mbed_official	87:085cde657901	1577	}
mbed_official	87:085cde657901	1578
mbed_official	87:085cde657901	1579	/**
mbed_official	87:085cde657901	1580	* @brief Starts the TIM Input Capture measurement.
mbed_official	226:b062af740e40	1581	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1582	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1583	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	1584	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1585	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1586	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1587	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1588	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1589	* @retval HAL status
mbed_official	87:085cde657901	1590	*/
mbed_official	87:085cde657901	1591	HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1592	{
mbed_official	87:085cde657901	1593	/* Check the parameters */
mbed_official	87:085cde657901	1594	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1595
mbed_official	87:085cde657901	1596	/* Enable the Input Capture channel */
mbed_official	87:085cde657901	1597	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1598
mbed_official	87:085cde657901	1599	/* Enable the Peripheral */
mbed_official	87:085cde657901	1600	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1601
mbed_official	87:085cde657901	1602	/* Return function status */
mbed_official	87:085cde657901	1603	return HAL_OK;
mbed_official	87:085cde657901	1604	}
mbed_official	87:085cde657901	1605
mbed_official	87:085cde657901	1606	/**
mbed_official	87:085cde657901	1607	* @brief Stops the TIM Input Capture measurement.
mbed_official	226:b062af740e40	1608	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1609	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1610	* @param Channel: TIM Channels to be disabled.
mbed_official	87:085cde657901	1611	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1612	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1613	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1614	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1615	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1616	* @retval HAL status
mbed_official	87:085cde657901	1617	*/
mbed_official	87:085cde657901	1618	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1619	{
mbed_official	87:085cde657901	1620	/* Check the parameters */
mbed_official	87:085cde657901	1621	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1622
mbed_official	87:085cde657901	1623	/* Disable the Input Capture channel */
mbed_official	87:085cde657901	1624	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1625
mbed_official	87:085cde657901	1626	/* Disable the Peripheral */
mbed_official	87:085cde657901	1627	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1628
mbed_official	87:085cde657901	1629	/* Return function status */
mbed_official	87:085cde657901	1630	return HAL_OK;
mbed_official	87:085cde657901	1631	}
mbed_official	87:085cde657901	1632
mbed_official	87:085cde657901	1633	/**
mbed_official	87:085cde657901	1634	* @brief Starts the TIM Input Capture measurement in interrupt mode.
mbed_official	226:b062af740e40	1635	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1636	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1637	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	1638	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1639	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1640	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1641	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1642	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1643	* @retval HAL status
mbed_official	87:085cde657901	1644	*/
mbed_official	87:085cde657901	1645	HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1646	{
mbed_official	87:085cde657901	1647	/* Check the parameters */
mbed_official	87:085cde657901	1648	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1649
mbed_official	87:085cde657901	1650	switch (Channel)
mbed_official	87:085cde657901	1651	{
mbed_official	87:085cde657901	1652	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1653	{
mbed_official	87:085cde657901	1654	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	1655	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	1656	}
mbed_official	87:085cde657901	1657	break;
mbed_official	87:085cde657901	1658
mbed_official	87:085cde657901	1659	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1660	{
mbed_official	87:085cde657901	1661	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	1662	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	1663	}
mbed_official	87:085cde657901	1664	break;
mbed_official	87:085cde657901	1665
mbed_official	87:085cde657901	1666	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1667	{
mbed_official	87:085cde657901	1668	/* Enable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	1669	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	1670	}
mbed_official	87:085cde657901	1671	break;
mbed_official	87:085cde657901	1672
mbed_official	87:085cde657901	1673	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1674	{
mbed_official	87:085cde657901	1675	/* Enable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1676	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	1677	}
mbed_official	87:085cde657901	1678	break;
mbed_official	87:085cde657901	1679
mbed_official	87:085cde657901	1680	default:
mbed_official	87:085cde657901	1681	break;
mbed_official	87:085cde657901	1682	}
mbed_official	87:085cde657901	1683	/* Enable the Input Capture channel */
mbed_official	87:085cde657901	1684	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1685
mbed_official	87:085cde657901	1686	/* Enable the Peripheral */
mbed_official	87:085cde657901	1687	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1688
mbed_official	87:085cde657901	1689	/* Return function status */
mbed_official	87:085cde657901	1690	return HAL_OK;
mbed_official	87:085cde657901	1691	}
mbed_official	87:085cde657901	1692
mbed_official	87:085cde657901	1693	/**
mbed_official	87:085cde657901	1694	* @brief Stops the TIM Input Capture measurement in interrupt mode.
mbed_official	226:b062af740e40	1695	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1696	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1697	* @param Channel: TIM Channels to be disabled.
mbed_official	87:085cde657901	1698	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1699	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1700	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1701	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1702	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1703	* @retval HAL status
mbed_official	87:085cde657901	1704	*/
mbed_official	87:085cde657901	1705	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1706	{
mbed_official	87:085cde657901	1707	/* Check the parameters */
mbed_official	87:085cde657901	1708	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1709
mbed_official	87:085cde657901	1710	switch (Channel)
mbed_official	87:085cde657901	1711	{
mbed_official	87:085cde657901	1712	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1713	{
mbed_official	87:085cde657901	1714	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	1715	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	1716	}
mbed_official	87:085cde657901	1717	break;
mbed_official	87:085cde657901	1718
mbed_official	87:085cde657901	1719	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1720	{
mbed_official	87:085cde657901	1721	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	1722	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	1723	}
mbed_official	87:085cde657901	1724	break;
mbed_official	87:085cde657901	1725
mbed_official	87:085cde657901	1726	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1727	{
mbed_official	87:085cde657901	1728	/* Disable the TIM Capture/Compare 3 interrupt */
mbed_official	87:085cde657901	1729	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	1730	}
mbed_official	87:085cde657901	1731	break;
mbed_official	87:085cde657901	1732
mbed_official	87:085cde657901	1733	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1734	{
mbed_official	87:085cde657901	1735	/* Disable the TIM Capture/Compare 4 interrupt */
mbed_official	87:085cde657901	1736	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	1737	}
mbed_official	87:085cde657901	1738	break;
mbed_official	87:085cde657901	1739
mbed_official	87:085cde657901	1740	default:
mbed_official	87:085cde657901	1741	break;
mbed_official	87:085cde657901	1742	}
mbed_official	87:085cde657901	1743
mbed_official	87:085cde657901	1744	/* Disable the Input Capture channel */
mbed_official	87:085cde657901	1745	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1746
mbed_official	87:085cde657901	1747	/* Disable the Peripheral */
mbed_official	87:085cde657901	1748	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1749
mbed_official	87:085cde657901	1750	/* Return function status */
mbed_official	87:085cde657901	1751	return HAL_OK;
mbed_official	87:085cde657901	1752	}
mbed_official	87:085cde657901	1753
mbed_official	87:085cde657901	1754	/**
mbed_official	87:085cde657901	1755	* @brief Starts the TIM Input Capture measurement on in DMA mode.
mbed_official	226:b062af740e40	1756	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1757	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1758	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	1759	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1760	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1761	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1762	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1763	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1764	* @param pData: The destination Buffer address.
mbed_official	87:085cde657901	1765	* @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official	87:085cde657901	1766	* @retval HAL status
mbed_official	87:085cde657901	1767	*/
mbed_official	87:085cde657901	1768	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
mbed_official	87:085cde657901	1769	{
mbed_official	87:085cde657901	1770	/* Check the parameters */
mbed_official	87:085cde657901	1771	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1772	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1773
mbed_official	87:085cde657901	1774	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	1775	{
mbed_official	87:085cde657901	1776	return HAL_BUSY;
mbed_official	87:085cde657901	1777	}
mbed_official	87:085cde657901	1778	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	1779	{
mbed_official	87:085cde657901	1780	if((pData == 0 ) && (Length > 0))
mbed_official	87:085cde657901	1781	{
mbed_official	87:085cde657901	1782	return HAL_ERROR;
mbed_official	87:085cde657901	1783	}
mbed_official	87:085cde657901	1784	else
mbed_official	87:085cde657901	1785	{
mbed_official	87:085cde657901	1786	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1787	}
mbed_official	87:085cde657901	1788	}
mbed_official	87:085cde657901	1789
mbed_official	87:085cde657901	1790	switch (Channel)
mbed_official	87:085cde657901	1791	{
mbed_official	87:085cde657901	1792	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1793	{
mbed_official	87:085cde657901	1794	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1795	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	1796
mbed_official	87:085cde657901	1797	/* Set the DMA error callback */
mbed_official	87:085cde657901	1798	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1799
mbed_official	87:085cde657901	1800	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1801	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
mbed_official	87:085cde657901	1802
mbed_official	87:085cde657901	1803	/* Enable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	1804	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	1805	}
mbed_official	87:085cde657901	1806	break;
mbed_official	87:085cde657901	1807
mbed_official	87:085cde657901	1808	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1809	{
mbed_official	87:085cde657901	1810	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1811	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	1812
mbed_official	87:085cde657901	1813	/* Set the DMA error callback */
mbed_official	87:085cde657901	1814	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1815
mbed_official	87:085cde657901	1816	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1817	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
mbed_official	87:085cde657901	1818
mbed_official	87:085cde657901	1819	/* Enable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	1820	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	1821	}
mbed_official	87:085cde657901	1822	break;
mbed_official	87:085cde657901	1823
mbed_official	87:085cde657901	1824	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1825	{
mbed_official	87:085cde657901	1826	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1827	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	1828
mbed_official	87:085cde657901	1829	/* Set the DMA error callback */
mbed_official	87:085cde657901	1830	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1831
mbed_official	87:085cde657901	1832	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1833	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
mbed_official	87:085cde657901	1834
mbed_official	87:085cde657901	1835	/* Enable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	1836	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	1837	}
mbed_official	87:085cde657901	1838	break;
mbed_official	87:085cde657901	1839
mbed_official	87:085cde657901	1840	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1841	{
mbed_official	87:085cde657901	1842	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	1843	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	1844
mbed_official	87:085cde657901	1845	/* Set the DMA error callback */
mbed_official	87:085cde657901	1846	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	1847
mbed_official	87:085cde657901	1848	/* Enable the DMA Stream */
mbed_official	87:085cde657901	1849	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
mbed_official	87:085cde657901	1850
mbed_official	87:085cde657901	1851	/* Enable the TIM Capture/Compare 4 DMA request */
mbed_official	87:085cde657901	1852	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	1853	}
mbed_official	87:085cde657901	1854	break;
mbed_official	87:085cde657901	1855
mbed_official	87:085cde657901	1856	default:
mbed_official	87:085cde657901	1857	break;
mbed_official	87:085cde657901	1858	}
mbed_official	87:085cde657901	1859
mbed_official	87:085cde657901	1860	/* Enable the Input Capture channel */
mbed_official	87:085cde657901	1861	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	1862
mbed_official	87:085cde657901	1863	/* Enable the Peripheral */
mbed_official	87:085cde657901	1864	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	1865
mbed_official	87:085cde657901	1866	/* Return function status */
mbed_official	87:085cde657901	1867	return HAL_OK;
mbed_official	87:085cde657901	1868	}
mbed_official	87:085cde657901	1869
mbed_official	87:085cde657901	1870	/**
mbed_official	87:085cde657901	1871	* @brief Stops the TIM Input Capture measurement on in DMA mode.
mbed_official	226:b062af740e40	1872	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1873	* the configuration information for TIM module.
mbed_official	226:b062af740e40	1874	* @param Channel: TIM Channels to be disabled.
mbed_official	87:085cde657901	1875	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1876	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	1877	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	1878	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	1879	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	1880	* @retval HAL status
mbed_official	87:085cde657901	1881	*/
mbed_official	87:085cde657901	1882	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	1883	{
mbed_official	87:085cde657901	1884	/* Check the parameters */
mbed_official	87:085cde657901	1885	assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official	87:085cde657901	1886	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1887
mbed_official	87:085cde657901	1888	switch (Channel)
mbed_official	87:085cde657901	1889	{
mbed_official	87:085cde657901	1890	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	1891	{
mbed_official	87:085cde657901	1892	/* Disable the TIM Capture/Compare 1 DMA request */
mbed_official	87:085cde657901	1893	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	1894	}
mbed_official	87:085cde657901	1895	break;
mbed_official	87:085cde657901	1896
mbed_official	87:085cde657901	1897	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	1898	{
mbed_official	87:085cde657901	1899	/* Disable the TIM Capture/Compare 2 DMA request */
mbed_official	87:085cde657901	1900	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	1901	}
mbed_official	87:085cde657901	1902	break;
mbed_official	87:085cde657901	1903
mbed_official	87:085cde657901	1904	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	1905	{
mbed_official	87:085cde657901	1906	/* Disable the TIM Capture/Compare 3 DMA request */
mbed_official	87:085cde657901	1907	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official	87:085cde657901	1908	}
mbed_official	87:085cde657901	1909	break;
mbed_official	87:085cde657901	1910
mbed_official	87:085cde657901	1911	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	1912	{
mbed_official	87:085cde657901	1913	/* Disable the TIM Capture/Compare 4 DMA request */
mbed_official	87:085cde657901	1914	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official	87:085cde657901	1915	}
mbed_official	87:085cde657901	1916	break;
mbed_official	87:085cde657901	1917
mbed_official	87:085cde657901	1918	default:
mbed_official	87:085cde657901	1919	break;
mbed_official	87:085cde657901	1920	}
mbed_official	87:085cde657901	1921
mbed_official	87:085cde657901	1922	/* Disable the Input Capture channel */
mbed_official	87:085cde657901	1923	TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	1924
mbed_official	87:085cde657901	1925	/* Disable the Peripheral */
mbed_official	87:085cde657901	1926	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	1927
mbed_official	87:085cde657901	1928	/* Change the htim state */
mbed_official	87:085cde657901	1929	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	1930
mbed_official	87:085cde657901	1931	/* Return function status */
mbed_official	87:085cde657901	1932	return HAL_OK;
mbed_official	87:085cde657901	1933	}
mbed_official	87:085cde657901	1934	/**
mbed_official	87:085cde657901	1935	* @}
mbed_official	87:085cde657901	1936	*/
mbed_official	87:085cde657901	1937
mbed_official	87:085cde657901	1938	/** @defgroup TIM_Group5 Time One Pulse functions
mbed_official	87:085cde657901	1939	* @brief Time One Pulse functions
mbed_official	87:085cde657901	1940	*
mbed_official	87:085cde657901	1941	@verbatim
mbed_official	87:085cde657901	1942	==============================================================================
mbed_official	87:085cde657901	1943	##### Time One Pulse functions #####
mbed_official	87:085cde657901	1944	==============================================================================
mbed_official	87:085cde657901	1945	[..]
mbed_official	87:085cde657901	1946	This section provides functions allowing to:
mbed_official	87:085cde657901	1947	(+) Initialize and configure the TIM One Pulse.
mbed_official	87:085cde657901	1948	(+) De-initialize the TIM One Pulse.
mbed_official	87:085cde657901	1949	(+) Start the Time One Pulse.
mbed_official	87:085cde657901	1950	(+) Stop the Time One Pulse.
mbed_official	87:085cde657901	1951	(+) Start the Time One Pulse and enable interrupt.
mbed_official	87:085cde657901	1952	(+) Stop the Time One Pulse and disable interrupt.
mbed_official	87:085cde657901	1953	(+) Start the Time One Pulse and enable DMA transfer.
mbed_official	87:085cde657901	1954	(+) Stop the Time One Pulse and disable DMA transfer.
mbed_official	87:085cde657901	1955
mbed_official	87:085cde657901	1956	@endverbatim
mbed_official	87:085cde657901	1957	* @{
mbed_official	87:085cde657901	1958	*/
mbed_official	87:085cde657901	1959	/**
mbed_official	87:085cde657901	1960	* @brief Initializes the TIM One Pulse Time Base according to the specified
mbed_official	87:085cde657901	1961	* parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official	226:b062af740e40	1962	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1963	* the configuration information for TIM module.
mbed_official	87:085cde657901	1964	* @param OnePulseMode: Select the One pulse mode.
mbed_official	87:085cde657901	1965	* This parameter can be one of the following values:
mbed_official	87:085cde657901	1966	* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
mbed_official	87:085cde657901	1967	* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
mbed_official	87:085cde657901	1968	* @retval HAL status
mbed_official	87:085cde657901	1969	*/
mbed_official	87:085cde657901	1970	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
mbed_official	87:085cde657901	1971	{
mbed_official	87:085cde657901	1972	/* Check the TIM handle allocation */
mbed_official	369:2e96f1b71984	1973	if(htim == HAL_NULL)
mbed_official	87:085cde657901	1974	{
mbed_official	87:085cde657901	1975	return HAL_ERROR;
mbed_official	87:085cde657901	1976	}
mbed_official	87:085cde657901	1977
mbed_official	87:085cde657901	1978	/* Check the parameters */
mbed_official	87:085cde657901	1979	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	1980	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official	87:085cde657901	1981	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official	87:085cde657901	1982	assert_param(IS_TIM_OPM_MODE(OnePulseMode));
mbed_official	87:085cde657901	1983
mbed_official	87:085cde657901	1984	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	1985	{
mbed_official	87:085cde657901	1986	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	1987	HAL_TIM_OnePulse_MspInit(htim);
mbed_official	87:085cde657901	1988	}
mbed_official	87:085cde657901	1989
mbed_official	87:085cde657901	1990	/* Set the TIM state */
mbed_official	87:085cde657901	1991	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	1992
mbed_official	87:085cde657901	1993	/* Configure the Time base in the One Pulse Mode */
mbed_official	87:085cde657901	1994	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	1995
mbed_official	87:085cde657901	1996	/* Reset the OPM Bit */
mbed_official	87:085cde657901	1997	htim->Instance->CR1 &= ~TIM_CR1_OPM;
mbed_official	87:085cde657901	1998
mbed_official	87:085cde657901	1999	/* Configure the OPM Mode */
mbed_official	87:085cde657901	2000	htim->Instance->CR1 \|= OnePulseMode;
mbed_official	87:085cde657901	2001
mbed_official	87:085cde657901	2002	/* Initialize the TIM state*/
mbed_official	87:085cde657901	2003	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2004
mbed_official	87:085cde657901	2005	return HAL_OK;
mbed_official	87:085cde657901	2006	}
mbed_official	87:085cde657901	2007
mbed_official	87:085cde657901	2008	/**
mbed_official	87:085cde657901	2009	* @brief DeInitializes the TIM One Pulse
mbed_official	226:b062af740e40	2010	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2011	* the configuration information for TIM module.
mbed_official	87:085cde657901	2012	* @retval HAL status
mbed_official	87:085cde657901	2013	*/
mbed_official	87:085cde657901	2014	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2015	{
mbed_official	87:085cde657901	2016	/* Check the parameters */
mbed_official	87:085cde657901	2017	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2018
mbed_official	87:085cde657901	2019	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2020
mbed_official	87:085cde657901	2021	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	2022	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2023
mbed_official	87:085cde657901	2024	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	87:085cde657901	2025	HAL_TIM_OnePulse_MspDeInit(htim);
mbed_official	87:085cde657901	2026
mbed_official	87:085cde657901	2027	/* Change TIM state */
mbed_official	106:ced8cbb51063	2028	htim->State = HAL_TIM_STATE_RESET;
mbed_official	106:ced8cbb51063	2029
mbed_official	106:ced8cbb51063	2030	/* Release Lock */
mbed_official	106:ced8cbb51063	2031	__HAL_UNLOCK(htim);
mbed_official	106:ced8cbb51063	2032
mbed_official	87:085cde657901	2033	return HAL_OK;
mbed_official	87:085cde657901	2034	}
mbed_official	87:085cde657901	2035
mbed_official	87:085cde657901	2036	/**
mbed_official	87:085cde657901	2037	* @brief Initializes the TIM One Pulse MSP.
mbed_official	226:b062af740e40	2038	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2039	* the configuration information for TIM module.
mbed_official	87:085cde657901	2040	* @retval None
mbed_official	87:085cde657901	2041	*/
mbed_official	87:085cde657901	2042	__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2043	{
mbed_official	87:085cde657901	2044	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	2045	the HAL_TIM_OnePulse_MspInit could be implemented in the user file
mbed_official	87:085cde657901	2046	*/
mbed_official	87:085cde657901	2047	}
mbed_official	87:085cde657901	2048
mbed_official	87:085cde657901	2049	/**
mbed_official	87:085cde657901	2050	* @brief DeInitializes TIM One Pulse MSP.
mbed_official	226:b062af740e40	2051	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2052	* the configuration information for TIM module.
mbed_official	87:085cde657901	2053	* @retval None
mbed_official	87:085cde657901	2054	*/
mbed_official	87:085cde657901	2055	__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2056	{
mbed_official	87:085cde657901	2057	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	2058	the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	2059	*/
mbed_official	87:085cde657901	2060	}
mbed_official	87:085cde657901	2061
mbed_official	87:085cde657901	2062	/**
mbed_official	87:085cde657901	2063	* @brief Starts the TIM One Pulse signal generation.
mbed_official	226:b062af740e40	2064	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2065	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2066	* @param OutputChannel : TIM Channels to be enabled.
mbed_official	87:085cde657901	2067	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2068	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2069	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2070	* @retval HAL status
mbed_official	87:085cde657901	2071	*/
mbed_official	87:085cde657901	2072	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	87:085cde657901	2073	{
mbed_official	87:085cde657901	2074	/* Enable the Capture compare and the Input Capture channels
mbed_official	87:085cde657901	2075	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	87:085cde657901	2076	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	87:085cde657901	2077	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	87:085cde657901	2078	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official	87:085cde657901	2079
mbed_official	87:085cde657901	2080	No need to enable the counter, it's enabled automatically by hardware
mbed_official	87:085cde657901	2081	(the counter starts in response to a stimulus and generate a pulse */
mbed_official	87:085cde657901	2082
mbed_official	87:085cde657901	2083	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2084	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2085
mbed_official	87:085cde657901	2086	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	2087	{
mbed_official	87:085cde657901	2088	/* Enable the main output */
mbed_official	87:085cde657901	2089	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	2090	}
mbed_official	87:085cde657901	2091
mbed_official	87:085cde657901	2092	/* Return function status */
mbed_official	87:085cde657901	2093	return HAL_OK;
mbed_official	87:085cde657901	2094	}
mbed_official	87:085cde657901	2095
mbed_official	87:085cde657901	2096	/**
mbed_official	87:085cde657901	2097	* @brief Stops the TIM One Pulse signal generation.
mbed_official	226:b062af740e40	2098	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2099	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2100	* @param OutputChannel : TIM Channels to be disable.
mbed_official	87:085cde657901	2101	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2102	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2103	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2104	* @retval HAL status
mbed_official	87:085cde657901	2105	*/
mbed_official	87:085cde657901	2106	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	87:085cde657901	2107	{
mbed_official	87:085cde657901	2108	/* Disable the Capture compare and the Input Capture channels
mbed_official	87:085cde657901	2109	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	87:085cde657901	2110	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	87:085cde657901	2111	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	87:085cde657901	2112	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official	87:085cde657901	2113
mbed_official	87:085cde657901	2114	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2115	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2116
mbed_official	87:085cde657901	2117	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	2118	{
mbed_official	87:085cde657901	2119	/* Disable the Main Ouput */
mbed_official	87:085cde657901	2120	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	2121	}
mbed_official	87:085cde657901	2122
mbed_official	87:085cde657901	2123	/* Disable the Peripheral */
mbed_official	87:085cde657901	2124	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2125
mbed_official	87:085cde657901	2126	/* Return function status */
mbed_official	87:085cde657901	2127	return HAL_OK;
mbed_official	87:085cde657901	2128	}
mbed_official	87:085cde657901	2129
mbed_official	87:085cde657901	2130	/**
mbed_official	87:085cde657901	2131	* @brief Starts the TIM One Pulse signal generation in interrupt mode.
mbed_official	226:b062af740e40	2132	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2133	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2134	* @param OutputChannel : TIM Channels to be enabled.
mbed_official	87:085cde657901	2135	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2136	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2137	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2138	* @retval HAL status
mbed_official	87:085cde657901	2139	*/
mbed_official	87:085cde657901	2140	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	87:085cde657901	2141	{
mbed_official	87:085cde657901	2142	/* Enable the Capture compare and the Input Capture channels
mbed_official	87:085cde657901	2143	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	87:085cde657901	2144	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	87:085cde657901	2145	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	87:085cde657901	2146	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official	87:085cde657901	2147
mbed_official	87:085cde657901	2148	No need to enable the counter, it's enabled automatically by hardware
mbed_official	87:085cde657901	2149	(the counter starts in response to a stimulus and generate a pulse */
mbed_official	87:085cde657901	2150
mbed_official	87:085cde657901	2151	/* Enable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	2152	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2153
mbed_official	87:085cde657901	2154	/* Enable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	2155	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2156
mbed_official	87:085cde657901	2157	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2158	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2159
mbed_official	87:085cde657901	2160	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	2161	{
mbed_official	87:085cde657901	2162	/* Enable the main output */
mbed_official	87:085cde657901	2163	__HAL_TIM_MOE_ENABLE(htim);
mbed_official	87:085cde657901	2164	}
mbed_official	87:085cde657901	2165
mbed_official	87:085cde657901	2166	/* Return function status */
mbed_official	87:085cde657901	2167	return HAL_OK;
mbed_official	87:085cde657901	2168	}
mbed_official	87:085cde657901	2169
mbed_official	87:085cde657901	2170	/**
mbed_official	87:085cde657901	2171	* @brief Stops the TIM One Pulse signal generation in interrupt mode.
mbed_official	226:b062af740e40	2172	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2173	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2174	* @param OutputChannel : TIM Channels to be enabled.
mbed_official	87:085cde657901	2175	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2176	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2177	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2178	* @retval HAL status
mbed_official	87:085cde657901	2179	*/
mbed_official	87:085cde657901	2180	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official	87:085cde657901	2181	{
mbed_official	87:085cde657901	2182	/* Disable the TIM Capture/Compare 1 interrupt */
mbed_official	87:085cde657901	2183	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2184
mbed_official	87:085cde657901	2185	/* Disable the TIM Capture/Compare 2 interrupt */
mbed_official	87:085cde657901	2186	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2187
mbed_official	87:085cde657901	2188	/* Disable the Capture compare and the Input Capture channels
mbed_official	87:085cde657901	2189	(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official	87:085cde657901	2190	if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official	87:085cde657901	2191	if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official	87:085cde657901	2192	in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official	87:085cde657901	2193	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2194	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2195
mbed_official	87:085cde657901	2196	if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official	87:085cde657901	2197	{
mbed_official	87:085cde657901	2198	/* Disable the Main Ouput */
mbed_official	87:085cde657901	2199	__HAL_TIM_MOE_DISABLE(htim);
mbed_official	87:085cde657901	2200	}
mbed_official	87:085cde657901	2201
mbed_official	87:085cde657901	2202	/* Disable the Peripheral */
mbed_official	87:085cde657901	2203	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2204
mbed_official	87:085cde657901	2205	/* Return function status */
mbed_official	87:085cde657901	2206	return HAL_OK;
mbed_official	87:085cde657901	2207	}
mbed_official	87:085cde657901	2208
mbed_official	87:085cde657901	2209	/**
mbed_official	87:085cde657901	2210	* @}
mbed_official	87:085cde657901	2211	*/
mbed_official	87:085cde657901	2212
mbed_official	87:085cde657901	2213	/** @defgroup TIM_Group6 Time Encoder functions
mbed_official	87:085cde657901	2214	* @brief Time Encoder functions
mbed_official	87:085cde657901	2215	*
mbed_official	87:085cde657901	2216	@verbatim
mbed_official	87:085cde657901	2217	==============================================================================
mbed_official	87:085cde657901	2218	##### Time Encoder functions #####
mbed_official	87:085cde657901	2219	==============================================================================
mbed_official	87:085cde657901	2220	[..]
mbed_official	87:085cde657901	2221	This section provides functions allowing to:
mbed_official	87:085cde657901	2222	(+) Initialize and configure the TIM Encoder.
mbed_official	87:085cde657901	2223	(+) De-initialize the TIM Encoder.
mbed_official	87:085cde657901	2224	(+) Start the Time Encoder.
mbed_official	87:085cde657901	2225	(+) Stop the Time Encoder.
mbed_official	87:085cde657901	2226	(+) Start the Time Encoder and enable interrupt.
mbed_official	87:085cde657901	2227	(+) Stop the Time Encoder and disable interrupt.
mbed_official	87:085cde657901	2228	(+) Start the Time Encoder and enable DMA transfer.
mbed_official	87:085cde657901	2229	(+) Stop the Time Encoder and disable DMA transfer.
mbed_official	87:085cde657901	2230
mbed_official	87:085cde657901	2231	@endverbatim
mbed_official	87:085cde657901	2232	* @{
mbed_official	87:085cde657901	2233	*/
mbed_official	87:085cde657901	2234	/**
mbed_official	87:085cde657901	2235	* @brief Initializes the TIM Encoder Interface and create the associated handle.
mbed_official	226:b062af740e40	2236	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2237	* the configuration information for TIM module.
mbed_official	87:085cde657901	2238	* @param sConfig: TIM Encoder Interface configuration structure
mbed_official	87:085cde657901	2239	* @retval HAL status
mbed_official	87:085cde657901	2240	*/
mbed_official	87:085cde657901	2241	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig)
mbed_official	87:085cde657901	2242	{
mbed_official	87:085cde657901	2243	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	2244	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	2245	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	2246
mbed_official	87:085cde657901	2247	/* Check the TIM handle allocation */
mbed_official	369:2e96f1b71984	2248	if(htim == HAL_NULL)
mbed_official	87:085cde657901	2249	{
mbed_official	87:085cde657901	2250	return HAL_ERROR;
mbed_official	87:085cde657901	2251	}
mbed_official	87:085cde657901	2252
mbed_official	87:085cde657901	2253	/* Check the parameters */
mbed_official	87:085cde657901	2254	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2255	assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
mbed_official	87:085cde657901	2256	assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
mbed_official	87:085cde657901	2257	assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
mbed_official	87:085cde657901	2258	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
mbed_official	87:085cde657901	2259	assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
mbed_official	87:085cde657901	2260	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
mbed_official	87:085cde657901	2261	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
mbed_official	87:085cde657901	2262	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
mbed_official	87:085cde657901	2263	assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
mbed_official	87:085cde657901	2264
mbed_official	87:085cde657901	2265	if(htim->State == HAL_TIM_STATE_RESET)
mbed_official	87:085cde657901	2266	{
mbed_official	87:085cde657901	2267	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official	87:085cde657901	2268	HAL_TIM_Encoder_MspInit(htim);
mbed_official	87:085cde657901	2269	}
mbed_official	87:085cde657901	2270
mbed_official	87:085cde657901	2271	/* Set the TIM state */
mbed_official	87:085cde657901	2272	htim->State= HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2273
mbed_official	87:085cde657901	2274	/* Reset the SMS bits */
mbed_official	87:085cde657901	2275	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	2276
mbed_official	87:085cde657901	2277	/* Configure the Time base in the Encoder Mode */
mbed_official	87:085cde657901	2278	TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official	87:085cde657901	2279
mbed_official	87:085cde657901	2280	/* Get the TIMx SMCR register value */
mbed_official	87:085cde657901	2281	tmpsmcr = htim->Instance->SMCR;
mbed_official	87:085cde657901	2282
mbed_official	87:085cde657901	2283	/* Get the TIMx CCMR1 register value */
mbed_official	87:085cde657901	2284	tmpccmr1 = htim->Instance->CCMR1;
mbed_official	87:085cde657901	2285
mbed_official	87:085cde657901	2286	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	2287	tmpccer = htim->Instance->CCER;
mbed_official	87:085cde657901	2288
mbed_official	87:085cde657901	2289	/* Set the encoder Mode */
mbed_official	87:085cde657901	2290	tmpsmcr \|= sConfig->EncoderMode;
mbed_official	87:085cde657901	2291
mbed_official	87:085cde657901	2292	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official	87:085cde657901	2293	tmpccmr1 &= ~(TIM_CCMR1_CC1S \| TIM_CCMR1_CC2S);
mbed_official	87:085cde657901	2294	tmpccmr1 \|= (sConfig->IC1Selection \| (sConfig->IC2Selection << 8));
mbed_official	87:085cde657901	2295
mbed_official	87:085cde657901	2296	/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
mbed_official	87:085cde657901	2297	tmpccmr1 &= ~(TIM_CCMR1_IC1PSC \| TIM_CCMR1_IC2PSC);
mbed_official	87:085cde657901	2298	tmpccmr1 &= ~(TIM_CCMR1_IC1F \| TIM_CCMR1_IC2F);
mbed_official	87:085cde657901	2299	tmpccmr1 \|= sConfig->IC1Prescaler \| (sConfig->IC2Prescaler << 8);
mbed_official	87:085cde657901	2300	tmpccmr1 \|= (sConfig->IC1Filter << 4) \| (sConfig->IC2Filter << 12);
mbed_official	87:085cde657901	2301
mbed_official	87:085cde657901	2302	/* Set the TI1 and the TI2 Polarities */
mbed_official	87:085cde657901	2303	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC2P);
mbed_official	87:085cde657901	2304	tmpccer &= ~(TIM_CCER_CC1NP \| TIM_CCER_CC2NP);
mbed_official	87:085cde657901	2305	tmpccer \|= sConfig->IC1Polarity \| (sConfig->IC2Polarity << 4);
mbed_official	87:085cde657901	2306
mbed_official	87:085cde657901	2307	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	2308	htim->Instance->SMCR = tmpsmcr;
mbed_official	87:085cde657901	2309
mbed_official	87:085cde657901	2310	/* Write to TIMx CCMR1 */
mbed_official	87:085cde657901	2311	htim->Instance->CCMR1 = tmpccmr1;
mbed_official	87:085cde657901	2312
mbed_official	87:085cde657901	2313	/* Write to TIMx CCER */
mbed_official	87:085cde657901	2314	htim->Instance->CCER = tmpccer;
mbed_official	87:085cde657901	2315
mbed_official	87:085cde657901	2316	/* Initialize the TIM state*/
mbed_official	87:085cde657901	2317	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2318
mbed_official	87:085cde657901	2319	return HAL_OK;
mbed_official	87:085cde657901	2320	}
mbed_official	87:085cde657901	2321
mbed_official	87:085cde657901	2322	/**
mbed_official	87:085cde657901	2323	* @brief DeInitializes the TIM Encoder interface
mbed_official	226:b062af740e40	2324	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2325	* the configuration information for TIM module.
mbed_official	87:085cde657901	2326	* @retval HAL status
mbed_official	87:085cde657901	2327	*/
mbed_official	87:085cde657901	2328	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2329	{
mbed_official	87:085cde657901	2330	/* Check the parameters */
mbed_official	87:085cde657901	2331	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2332
mbed_official	87:085cde657901	2333	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2334
mbed_official	87:085cde657901	2335	/* Disable the TIM Peripheral Clock */
mbed_official	87:085cde657901	2336	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2337
mbed_official	87:085cde657901	2338	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official	87:085cde657901	2339	HAL_TIM_Encoder_MspDeInit(htim);
mbed_official	87:085cde657901	2340
mbed_official	87:085cde657901	2341	/* Change TIM state */
mbed_official	106:ced8cbb51063	2342	htim->State = HAL_TIM_STATE_RESET;
mbed_official	106:ced8cbb51063	2343
mbed_official	106:ced8cbb51063	2344	/* Release Lock */
mbed_official	106:ced8cbb51063	2345	__HAL_UNLOCK(htim);
mbed_official	106:ced8cbb51063	2346
mbed_official	87:085cde657901	2347	return HAL_OK;
mbed_official	87:085cde657901	2348	}
mbed_official	87:085cde657901	2349
mbed_official	87:085cde657901	2350	/**
mbed_official	87:085cde657901	2351	* @brief Initializes the TIM Encoder Interface MSP.
mbed_official	226:b062af740e40	2352	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2353	* the configuration information for TIM module.
mbed_official	87:085cde657901	2354	* @retval None
mbed_official	87:085cde657901	2355	*/
mbed_official	87:085cde657901	2356	__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2357	{
mbed_official	87:085cde657901	2358	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	2359	the HAL_TIM_Encoder_MspInit could be implemented in the user file
mbed_official	87:085cde657901	2360	*/
mbed_official	87:085cde657901	2361	}
mbed_official	87:085cde657901	2362
mbed_official	87:085cde657901	2363	/**
mbed_official	87:085cde657901	2364	* @brief DeInitializes TIM Encoder Interface MSP.
mbed_official	226:b062af740e40	2365	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2366	* the configuration information for TIM module.
mbed_official	87:085cde657901	2367	* @retval None
mbed_official	87:085cde657901	2368	*/
mbed_official	87:085cde657901	2369	__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2370	{
mbed_official	87:085cde657901	2371	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	2372	the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
mbed_official	87:085cde657901	2373	*/
mbed_official	87:085cde657901	2374	}
mbed_official	87:085cde657901	2375
mbed_official	87:085cde657901	2376	/**
mbed_official	87:085cde657901	2377	* @brief Starts the TIM Encoder Interface.
mbed_official	226:b062af740e40	2378	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2379	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2380	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	2381	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2382	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2383	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2384	* @retval HAL status
mbed_official	87:085cde657901	2385	*/
mbed_official	87:085cde657901	2386	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2387	{
mbed_official	87:085cde657901	2388	/* Check the parameters */
mbed_official	87:085cde657901	2389	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2390
mbed_official	87:085cde657901	2391	/* Enable the encoder interface channels */
mbed_official	87:085cde657901	2392	switch (Channel)
mbed_official	87:085cde657901	2393	{
mbed_official	87:085cde657901	2394	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2395	{
mbed_official	87:085cde657901	2396	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2397	break;
mbed_official	87:085cde657901	2398	}
mbed_official	87:085cde657901	2399	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2400	{
mbed_official	87:085cde657901	2401	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2402	break;
mbed_official	87:085cde657901	2403	}
mbed_official	87:085cde657901	2404	default :
mbed_official	87:085cde657901	2405	{
mbed_official	87:085cde657901	2406	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2407	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2408	break;
mbed_official	87:085cde657901	2409	}
mbed_official	87:085cde657901	2410	}
mbed_official	87:085cde657901	2411	/* Enable the Peripheral */
mbed_official	87:085cde657901	2412	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2413
mbed_official	87:085cde657901	2414	/* Return function status */
mbed_official	87:085cde657901	2415	return HAL_OK;
mbed_official	87:085cde657901	2416	}
mbed_official	87:085cde657901	2417
mbed_official	87:085cde657901	2418	/**
mbed_official	87:085cde657901	2419	* @brief Stops the TIM Encoder Interface.
mbed_official	226:b062af740e40	2420	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2421	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2422	* @param Channel: TIM Channels to be disabled.
mbed_official	87:085cde657901	2423	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2424	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2425	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2426	* @retval HAL status
mbed_official	87:085cde657901	2427	*/
mbed_official	87:085cde657901	2428	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2429	{
mbed_official	87:085cde657901	2430	/* Check the parameters */
mbed_official	87:085cde657901	2431	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2432
mbed_official	87:085cde657901	2433	/* Disable the Input Capture channels 1 and 2
mbed_official	87:085cde657901	2434	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official	87:085cde657901	2435	switch (Channel)
mbed_official	87:085cde657901	2436	{
mbed_official	87:085cde657901	2437	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2438	{
mbed_official	87:085cde657901	2439	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2440	break;
mbed_official	87:085cde657901	2441	}
mbed_official	87:085cde657901	2442	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2443	{
mbed_official	87:085cde657901	2444	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2445	break;
mbed_official	87:085cde657901	2446	}
mbed_official	87:085cde657901	2447	default :
mbed_official	87:085cde657901	2448	{
mbed_official	87:085cde657901	2449	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2450	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2451	break;
mbed_official	87:085cde657901	2452	}
mbed_official	87:085cde657901	2453	}
mbed_official	87:085cde657901	2454	/* Disable the Peripheral */
mbed_official	87:085cde657901	2455	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2456
mbed_official	87:085cde657901	2457	/* Return function status */
mbed_official	87:085cde657901	2458	return HAL_OK;
mbed_official	87:085cde657901	2459	}
mbed_official	87:085cde657901	2460
mbed_official	87:085cde657901	2461	/**
mbed_official	87:085cde657901	2462	* @brief Starts the TIM Encoder Interface in interrupt mode.
mbed_official	226:b062af740e40	2463	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2464	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2465	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	2466	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2467	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2468	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2469	* @retval HAL status
mbed_official	87:085cde657901	2470	*/
mbed_official	87:085cde657901	2471	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2472	{
mbed_official	87:085cde657901	2473	/* Check the parameters */
mbed_official	87:085cde657901	2474	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2475
mbed_official	87:085cde657901	2476	/* Enable the encoder interface channels */
mbed_official	87:085cde657901	2477	/* Enable the capture compare Interrupts 1 and/or 2 */
mbed_official	87:085cde657901	2478	switch (Channel)
mbed_official	87:085cde657901	2479	{
mbed_official	87:085cde657901	2480	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2481	{
mbed_official	87:085cde657901	2482	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2483	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2484	break;
mbed_official	87:085cde657901	2485	}
mbed_official	87:085cde657901	2486	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2487	{
mbed_official	87:085cde657901	2488	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2489	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2490	break;
mbed_official	87:085cde657901	2491	}
mbed_official	87:085cde657901	2492	default :
mbed_official	87:085cde657901	2493	{
mbed_official	87:085cde657901	2494	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2495	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2496	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2497	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2498	break;
mbed_official	87:085cde657901	2499	}
mbed_official	87:085cde657901	2500	}
mbed_official	87:085cde657901	2501
mbed_official	87:085cde657901	2502	/* Enable the Peripheral */
mbed_official	87:085cde657901	2503	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2504
mbed_official	87:085cde657901	2505	/* Return function status */
mbed_official	87:085cde657901	2506	return HAL_OK;
mbed_official	87:085cde657901	2507	}
mbed_official	87:085cde657901	2508
mbed_official	87:085cde657901	2509	/**
mbed_official	87:085cde657901	2510	* @brief Stops the TIM Encoder Interface in interrupt mode.
mbed_official	226:b062af740e40	2511	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2512	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2513	* @param Channel: TIM Channels to be disabled.
mbed_official	87:085cde657901	2514	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2515	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2516	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2517	* @retval HAL status
mbed_official	87:085cde657901	2518	*/
mbed_official	87:085cde657901	2519	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2520	{
mbed_official	87:085cde657901	2521	/* Check the parameters */
mbed_official	87:085cde657901	2522	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2523
mbed_official	87:085cde657901	2524	/* Disable the Input Capture channels 1 and 2
mbed_official	87:085cde657901	2525	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official	87:085cde657901	2526	if(Channel == TIM_CHANNEL_1)
mbed_official	87:085cde657901	2527	{
mbed_official	87:085cde657901	2528	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2529
mbed_official	87:085cde657901	2530	/* Disable the capture compare Interrupts 1 */
mbed_official	87:085cde657901	2531	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2532	}
mbed_official	87:085cde657901	2533	else if(Channel == TIM_CHANNEL_2)
mbed_official	87:085cde657901	2534	{
mbed_official	87:085cde657901	2535	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2536
mbed_official	87:085cde657901	2537	/* Disable the capture compare Interrupts 2 */
mbed_official	87:085cde657901	2538	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2539	}
mbed_official	87:085cde657901	2540	else
mbed_official	87:085cde657901	2541	{
mbed_official	87:085cde657901	2542	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2543	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2544
mbed_official	87:085cde657901	2545	/* Disable the capture compare Interrupts 1 and 2 */
mbed_official	87:085cde657901	2546	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2547	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2548	}
mbed_official	87:085cde657901	2549
mbed_official	87:085cde657901	2550	/* Disable the Peripheral */
mbed_official	87:085cde657901	2551	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2552
mbed_official	87:085cde657901	2553	/* Change the htim state */
mbed_official	87:085cde657901	2554	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2555
mbed_official	87:085cde657901	2556	/* Return function status */
mbed_official	87:085cde657901	2557	return HAL_OK;
mbed_official	87:085cde657901	2558	}
mbed_official	87:085cde657901	2559
mbed_official	87:085cde657901	2560	/**
mbed_official	87:085cde657901	2561	* @brief Starts the TIM Encoder Interface in DMA mode.
mbed_official	226:b062af740e40	2562	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2563	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2564	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	2565	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2566	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2567	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2568	* @param pData1: The destination Buffer address for IC1.
mbed_official	87:085cde657901	2569	* @param pData2: The destination Buffer address for IC2.
mbed_official	87:085cde657901	2570	* @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official	87:085cde657901	2571	* @retval HAL status
mbed_official	87:085cde657901	2572	*/
mbed_official	87:085cde657901	2573	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length)
mbed_official	87:085cde657901	2574	{
mbed_official	87:085cde657901	2575	/* Check the parameters */
mbed_official	87:085cde657901	2576	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2577
mbed_official	87:085cde657901	2578	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	2579	{
mbed_official	87:085cde657901	2580	return HAL_BUSY;
mbed_official	87:085cde657901	2581	}
mbed_official	87:085cde657901	2582	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	2583	{
mbed_official	87:085cde657901	2584	if((((pData1 == 0) \|\| (pData2 == 0) )) && (Length > 0))
mbed_official	87:085cde657901	2585	{
mbed_official	87:085cde657901	2586	return HAL_ERROR;
mbed_official	87:085cde657901	2587	}
mbed_official	87:085cde657901	2588	else
mbed_official	87:085cde657901	2589	{
mbed_official	87:085cde657901	2590	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2591	}
mbed_official	87:085cde657901	2592	}
mbed_official	87:085cde657901	2593
mbed_official	87:085cde657901	2594	switch (Channel)
mbed_official	87:085cde657901	2595	{
mbed_official	87:085cde657901	2596	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2597	{
mbed_official	87:085cde657901	2598	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	2599	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	2600
mbed_official	87:085cde657901	2601	/* Set the DMA error callback */
mbed_official	87:085cde657901	2602	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	2603
mbed_official	87:085cde657901	2604	/* Enable the DMA Stream */
mbed_official	87:085cde657901	2605	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
mbed_official	87:085cde657901	2606
mbed_official	87:085cde657901	2607	/* Enable the TIM Input Capture DMA request */
mbed_official	87:085cde657901	2608	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	2609
mbed_official	87:085cde657901	2610	/* Enable the Peripheral */
mbed_official	87:085cde657901	2611	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2612
mbed_official	87:085cde657901	2613	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	2614	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2615	}
mbed_official	87:085cde657901	2616	break;
mbed_official	87:085cde657901	2617
mbed_official	87:085cde657901	2618	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2619	{
mbed_official	87:085cde657901	2620	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	2621	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	2622
mbed_official	87:085cde657901	2623	/* Set the DMA error callback */
mbed_official	87:085cde657901	2624	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
mbed_official	87:085cde657901	2625	/* Enable the DMA Stream */
mbed_official	87:085cde657901	2626	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official	87:085cde657901	2627
mbed_official	87:085cde657901	2628	/* Enable the TIM Input Capture DMA request */
mbed_official	87:085cde657901	2629	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	2630
mbed_official	87:085cde657901	2631	/* Enable the Peripheral */
mbed_official	87:085cde657901	2632	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2633
mbed_official	87:085cde657901	2634	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	2635	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2636	}
mbed_official	87:085cde657901	2637	break;
mbed_official	87:085cde657901	2638
mbed_official	87:085cde657901	2639	case TIM_CHANNEL_ALL:
mbed_official	87:085cde657901	2640	{
mbed_official	87:085cde657901	2641	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	2642	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	2643
mbed_official	87:085cde657901	2644	/* Set the DMA error callback */
mbed_official	87:085cde657901	2645	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	2646
mbed_official	87:085cde657901	2647	/* Enable the DMA Stream */
mbed_official	87:085cde657901	2648	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
mbed_official	87:085cde657901	2649
mbed_official	87:085cde657901	2650	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	2651	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	2652
mbed_official	87:085cde657901	2653	/* Set the DMA error callback */
mbed_official	87:085cde657901	2654	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	2655
mbed_official	87:085cde657901	2656	/* Enable the DMA Stream */
mbed_official	87:085cde657901	2657	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official	87:085cde657901	2658
mbed_official	87:085cde657901	2659	/* Enable the Peripheral */
mbed_official	87:085cde657901	2660	__HAL_TIM_ENABLE(htim);
mbed_official	87:085cde657901	2661
mbed_official	87:085cde657901	2662	/* Enable the Capture compare channel */
mbed_official	87:085cde657901	2663	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2664	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official	87:085cde657901	2665
mbed_official	87:085cde657901	2666	/* Enable the TIM Input Capture DMA request */
mbed_official	87:085cde657901	2667	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	2668	/* Enable the TIM Input Capture DMA request */
mbed_official	87:085cde657901	2669	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	2670	}
mbed_official	87:085cde657901	2671	break;
mbed_official	87:085cde657901	2672
mbed_official	87:085cde657901	2673	default:
mbed_official	87:085cde657901	2674	break;
mbed_official	87:085cde657901	2675	}
mbed_official	87:085cde657901	2676	/* Return function status */
mbed_official	87:085cde657901	2677	return HAL_OK;
mbed_official	87:085cde657901	2678	}
mbed_official	87:085cde657901	2679
mbed_official	87:085cde657901	2680	/**
mbed_official	87:085cde657901	2681	* @brief Stops the TIM Encoder Interface in DMA mode.
mbed_official	226:b062af740e40	2682	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2683	* the configuration information for TIM module.
mbed_official	226:b062af740e40	2684	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	2685	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2686	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2687	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2688	* @retval HAL status
mbed_official	87:085cde657901	2689	*/
mbed_official	87:085cde657901	2690	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	2691	{
mbed_official	87:085cde657901	2692	/* Check the parameters */
mbed_official	87:085cde657901	2693	assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2694
mbed_official	87:085cde657901	2695	/* Disable the Input Capture channels 1 and 2
mbed_official	87:085cde657901	2696	(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official	87:085cde657901	2697	if(Channel == TIM_CHANNEL_1)
mbed_official	87:085cde657901	2698	{
mbed_official	87:085cde657901	2699	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2700
mbed_official	87:085cde657901	2701	/* Disable the capture compare DMA Request 1 */
mbed_official	87:085cde657901	2702	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	2703	}
mbed_official	87:085cde657901	2704	else if(Channel == TIM_CHANNEL_2)
mbed_official	87:085cde657901	2705	{
mbed_official	87:085cde657901	2706	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2707
mbed_official	87:085cde657901	2708	/* Disable the capture compare DMA Request 2 */
mbed_official	87:085cde657901	2709	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	2710	}
mbed_official	87:085cde657901	2711	else
mbed_official	87:085cde657901	2712	{
mbed_official	87:085cde657901	2713	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2714	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official	87:085cde657901	2715
mbed_official	87:085cde657901	2716	/* Disable the capture compare DMA Request 1 and 2 */
mbed_official	87:085cde657901	2717	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official	87:085cde657901	2718	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official	87:085cde657901	2719	}
mbed_official	87:085cde657901	2720
mbed_official	87:085cde657901	2721	/* Disable the Peripheral */
mbed_official	87:085cde657901	2722	__HAL_TIM_DISABLE(htim);
mbed_official	87:085cde657901	2723
mbed_official	87:085cde657901	2724	/* Change the htim state */
mbed_official	87:085cde657901	2725	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2726
mbed_official	87:085cde657901	2727	/* Return function status */
mbed_official	87:085cde657901	2728	return HAL_OK;
mbed_official	87:085cde657901	2729	}
mbed_official	87:085cde657901	2730
mbed_official	87:085cde657901	2731	/**
mbed_official	87:085cde657901	2732	* @}
mbed_official	87:085cde657901	2733	*/
mbed_official	87:085cde657901	2734	/** @defgroup TIM_Group7 TIM IRQ handler management
mbed_official	87:085cde657901	2735	* @brief IRQ handler management
mbed_official	87:085cde657901	2736	*
mbed_official	87:085cde657901	2737	@verbatim
mbed_official	87:085cde657901	2738	==============================================================================
mbed_official	87:085cde657901	2739	##### IRQ handler management #####
mbed_official	87:085cde657901	2740	==============================================================================
mbed_official	87:085cde657901	2741	[..]
mbed_official	87:085cde657901	2742	This section provides Timer IRQ handler function.
mbed_official	87:085cde657901	2743
mbed_official	87:085cde657901	2744	@endverbatim
mbed_official	87:085cde657901	2745	* @{
mbed_official	87:085cde657901	2746	*/
mbed_official	87:085cde657901	2747	/**
mbed_official	87:085cde657901	2748	* @brief This function handles TIM interrupts requests.
mbed_official	226:b062af740e40	2749	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2750	* the configuration information for TIM module.
mbed_official	87:085cde657901	2751	* @retval None
mbed_official	87:085cde657901	2752	*/
mbed_official	87:085cde657901	2753	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	2754	{
mbed_official	87:085cde657901	2755	/* Capture compare 1 event */
mbed_official	87:085cde657901	2756	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
mbed_official	87:085cde657901	2757	{
mbed_official	87:085cde657901	2758	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
mbed_official	87:085cde657901	2759	{
mbed_official	87:085cde657901	2760	{
mbed_official	87:085cde657901	2761	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
mbed_official	87:085cde657901	2762	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official	87:085cde657901	2763
mbed_official	87:085cde657901	2764	/* Input capture event */
mbed_official	87:085cde657901	2765	if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
mbed_official	87:085cde657901	2766	{
mbed_official	87:085cde657901	2767	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	2768	}
mbed_official	87:085cde657901	2769	/* Output compare event */
mbed_official	87:085cde657901	2770	else
mbed_official	87:085cde657901	2771	{
mbed_official	87:085cde657901	2772	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	87:085cde657901	2773	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	2774	}
mbed_official	87:085cde657901	2775	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	87:085cde657901	2776	}
mbed_official	87:085cde657901	2777	}
mbed_official	87:085cde657901	2778	}
mbed_official	87:085cde657901	2779	/* Capture compare 2 event */
mbed_official	87:085cde657901	2780	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
mbed_official	87:085cde657901	2781	{
mbed_official	87:085cde657901	2782	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
mbed_official	87:085cde657901	2783	{
mbed_official	87:085cde657901	2784	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
mbed_official	87:085cde657901	2785	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official	87:085cde657901	2786	/* Input capture event */
mbed_official	87:085cde657901	2787	if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
mbed_official	87:085cde657901	2788	{
mbed_official	87:085cde657901	2789	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	2790	}
mbed_official	87:085cde657901	2791	/* Output compare event */
mbed_official	87:085cde657901	2792	else
mbed_official	87:085cde657901	2793	{
mbed_official	87:085cde657901	2794	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	87:085cde657901	2795	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	2796	}
mbed_official	87:085cde657901	2797	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	87:085cde657901	2798	}
mbed_official	87:085cde657901	2799	}
mbed_official	87:085cde657901	2800	/* Capture compare 3 event */
mbed_official	87:085cde657901	2801	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
mbed_official	87:085cde657901	2802	{
mbed_official	87:085cde657901	2803	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
mbed_official	87:085cde657901	2804	{
mbed_official	87:085cde657901	2805	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
mbed_official	87:085cde657901	2806	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official	87:085cde657901	2807	/* Input capture event */
mbed_official	369:2e96f1b71984	2808	if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
mbed_official	87:085cde657901	2809	{
mbed_official	87:085cde657901	2810	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	2811	}
mbed_official	87:085cde657901	2812	/* Output compare event */
mbed_official	87:085cde657901	2813	else
mbed_official	87:085cde657901	2814	{
mbed_official	87:085cde657901	2815	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	87:085cde657901	2816	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	2817	}
mbed_official	87:085cde657901	2818	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	87:085cde657901	2819	}
mbed_official	87:085cde657901	2820	}
mbed_official	87:085cde657901	2821	/* Capture compare 4 event */
mbed_official	87:085cde657901	2822	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
mbed_official	87:085cde657901	2823	{
mbed_official	87:085cde657901	2824	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
mbed_official	87:085cde657901	2825	{
mbed_official	87:085cde657901	2826	__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
mbed_official	87:085cde657901	2827	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official	87:085cde657901	2828	/* Input capture event */
mbed_official	369:2e96f1b71984	2829	if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
mbed_official	87:085cde657901	2830	{
mbed_official	87:085cde657901	2831	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	2832	}
mbed_official	87:085cde657901	2833	/* Output compare event */
mbed_official	87:085cde657901	2834	else
mbed_official	87:085cde657901	2835	{
mbed_official	87:085cde657901	2836	HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official	87:085cde657901	2837	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	2838	}
mbed_official	87:085cde657901	2839	htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official	87:085cde657901	2840	}
mbed_official	87:085cde657901	2841	}
mbed_official	87:085cde657901	2842	/* TIM Update event */
mbed_official	87:085cde657901	2843	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
mbed_official	87:085cde657901	2844	{
mbed_official	87:085cde657901	2845	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
mbed_official	87:085cde657901	2846	{
mbed_official	87:085cde657901	2847	__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
mbed_official	87:085cde657901	2848	HAL_TIM_PeriodElapsedCallback(htim);
mbed_official	87:085cde657901	2849	}
mbed_official	87:085cde657901	2850	}
mbed_official	87:085cde657901	2851	/* TIM Break input event */
mbed_official	87:085cde657901	2852	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
mbed_official	87:085cde657901	2853	{
mbed_official	87:085cde657901	2854	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
mbed_official	87:085cde657901	2855	{
mbed_official	87:085cde657901	2856	__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
mbed_official	87:085cde657901	2857	HAL_TIMEx_BreakCallback(htim);
mbed_official	87:085cde657901	2858	}
mbed_official	87:085cde657901	2859	}
mbed_official	87:085cde657901	2860	/* TIM Trigger detection event */
mbed_official	87:085cde657901	2861	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
mbed_official	87:085cde657901	2862	{
mbed_official	87:085cde657901	2863	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
mbed_official	87:085cde657901	2864	{
mbed_official	87:085cde657901	2865	__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
mbed_official	87:085cde657901	2866	HAL_TIM_TriggerCallback(htim);
mbed_official	87:085cde657901	2867	}
mbed_official	87:085cde657901	2868	}
mbed_official	87:085cde657901	2869	/* TIM commutation event */
mbed_official	87:085cde657901	2870	if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
mbed_official	87:085cde657901	2871	{
mbed_official	87:085cde657901	2872	if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
mbed_official	87:085cde657901	2873	{
mbed_official	87:085cde657901	2874	__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
mbed_official	87:085cde657901	2875	HAL_TIMEx_CommutationCallback(htim);
mbed_official	87:085cde657901	2876	}
mbed_official	87:085cde657901	2877	}
mbed_official	87:085cde657901	2878	}
mbed_official	87:085cde657901	2879
mbed_official	87:085cde657901	2880	/**
mbed_official	87:085cde657901	2881	* @}
mbed_official	87:085cde657901	2882	*/
mbed_official	87:085cde657901	2883
mbed_official	87:085cde657901	2884	/** @defgroup TIM_Group8 Peripheral Control functions
mbed_official	87:085cde657901	2885	* @brief Peripheral Control functions
mbed_official	87:085cde657901	2886	*
mbed_official	87:085cde657901	2887	@verbatim
mbed_official	87:085cde657901	2888	==============================================================================
mbed_official	87:085cde657901	2889	##### Peripheral Control functions #####
mbed_official	87:085cde657901	2890	==============================================================================
mbed_official	87:085cde657901	2891	[..]
mbed_official	87:085cde657901	2892	This section provides functions allowing to:
mbed_official	87:085cde657901	2893	(+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
mbed_official	87:085cde657901	2894	(+) Configure External Clock source.
mbed_official	87:085cde657901	2895	(+) Configure Complementary channels, break features and dead time.
mbed_official	87:085cde657901	2896	(+) Configure Master and the Slave synchronization.
mbed_official	87:085cde657901	2897	(+) Configure the DMA Burst Mode.
mbed_official	87:085cde657901	2898
mbed_official	87:085cde657901	2899	@endverbatim
mbed_official	87:085cde657901	2900	* @{
mbed_official	87:085cde657901	2901	*/
mbed_official	87:085cde657901	2902
mbed_official	87:085cde657901	2903	/**
mbed_official	87:085cde657901	2904	* @brief Initializes the TIM Output Compare Channels according to the specified
mbed_official	87:085cde657901	2905	* parameters in the TIM_OC_InitTypeDef.
mbed_official	226:b062af740e40	2906	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2907	* the configuration information for TIM module.
mbed_official	87:085cde657901	2908	* @param sConfig: TIM Output Compare configuration structure
mbed_official	226:b062af740e40	2909	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	2910	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2911	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2912	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2913	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	2914	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	2915	* @retval HAL status
mbed_official	87:085cde657901	2916	*/
mbed_official	87:085cde657901	2917	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
mbed_official	87:085cde657901	2918	{
mbed_official	87:085cde657901	2919	/* Check the parameters */
mbed_official	87:085cde657901	2920	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	87:085cde657901	2921	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
mbed_official	87:085cde657901	2922	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official	87:085cde657901	2923	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official	87:085cde657901	2924	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
mbed_official	87:085cde657901	2925	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official	87:085cde657901	2926	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official	87:085cde657901	2927
mbed_official	87:085cde657901	2928	/* Check input state */
mbed_official	87:085cde657901	2929	__HAL_LOCK(htim);
mbed_official	87:085cde657901	2930
mbed_official	87:085cde657901	2931	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	2932
mbed_official	87:085cde657901	2933	switch (Channel)
mbed_official	87:085cde657901	2934	{
mbed_official	87:085cde657901	2935	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	2936	{
mbed_official	87:085cde657901	2937	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2938	/* Configure the TIM Channel 1 in Output Compare */
mbed_official	87:085cde657901	2939	TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	2940	}
mbed_official	87:085cde657901	2941	break;
mbed_official	87:085cde657901	2942
mbed_official	87:085cde657901	2943	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	2944	{
mbed_official	87:085cde657901	2945	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2946	/* Configure the TIM Channel 2 in Output Compare */
mbed_official	87:085cde657901	2947	TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	2948	}
mbed_official	87:085cde657901	2949	break;
mbed_official	87:085cde657901	2950
mbed_official	87:085cde657901	2951	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	2952	{
mbed_official	87:085cde657901	2953	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2954	/* Configure the TIM Channel 3 in Output Compare */
mbed_official	87:085cde657901	2955	TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	2956	}
mbed_official	87:085cde657901	2957	break;
mbed_official	87:085cde657901	2958
mbed_official	87:085cde657901	2959	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	2960	{
mbed_official	87:085cde657901	2961	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2962	/* Configure the TIM Channel 4 in Output Compare */
mbed_official	87:085cde657901	2963	TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	2964	}
mbed_official	87:085cde657901	2965	break;
mbed_official	87:085cde657901	2966
mbed_official	87:085cde657901	2967	default:
mbed_official	87:085cde657901	2968	break;
mbed_official	87:085cde657901	2969	}
mbed_official	87:085cde657901	2970	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	2971
mbed_official	87:085cde657901	2972	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	2973
mbed_official	87:085cde657901	2974	return HAL_OK;
mbed_official	87:085cde657901	2975	}
mbed_official	87:085cde657901	2976
mbed_official	87:085cde657901	2977	/**
mbed_official	87:085cde657901	2978	* @brief Initializes the TIM Input Capture Channels according to the specified
mbed_official	87:085cde657901	2979	* parameters in the TIM_IC_InitTypeDef.
mbed_official	226:b062af740e40	2980	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2981	* the configuration information for TIM module.
mbed_official	87:085cde657901	2982	* @param sConfig: TIM Input Capture configuration structure
mbed_official	226:b062af740e40	2983	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	2984	* This parameter can be one of the following values:
mbed_official	87:085cde657901	2985	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	2986	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	2987	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	2988	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	2989	* @retval HAL status
mbed_official	87:085cde657901	2990	*/
mbed_official	87:085cde657901	2991	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel)
mbed_official	87:085cde657901	2992	{
mbed_official	87:085cde657901	2993	/* Check the parameters */
mbed_official	87:085cde657901	2994	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	2995	assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
mbed_official	87:085cde657901	2996	assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
mbed_official	87:085cde657901	2997	assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
mbed_official	87:085cde657901	2998	assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
mbed_official	87:085cde657901	2999
mbed_official	87:085cde657901	3000	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3001
mbed_official	87:085cde657901	3002	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3003
mbed_official	87:085cde657901	3004	if (Channel == TIM_CHANNEL_1)
mbed_official	87:085cde657901	3005	{
mbed_official	87:085cde657901	3006	/* TI1 Configuration */
mbed_official	87:085cde657901	3007	TIM_TI1_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3008	sConfig->ICPolarity,
mbed_official	87:085cde657901	3009	sConfig->ICSelection,
mbed_official	87:085cde657901	3010	sConfig->ICFilter);
mbed_official	87:085cde657901	3011
mbed_official	87:085cde657901	3012	/* Reset the IC1PSC Bits */
mbed_official	87:085cde657901	3013	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official	87:085cde657901	3014
mbed_official	87:085cde657901	3015	/* Set the IC1PSC value */
mbed_official	87:085cde657901	3016	htim->Instance->CCMR1 \|= sConfig->ICPrescaler;
mbed_official	87:085cde657901	3017	}
mbed_official	87:085cde657901	3018	else if (Channel == TIM_CHANNEL_2)
mbed_official	87:085cde657901	3019	{
mbed_official	87:085cde657901	3020	/* TI2 Configuration */
mbed_official	87:085cde657901	3021	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3022
mbed_official	87:085cde657901	3023	TIM_TI2_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3024	sConfig->ICPolarity,
mbed_official	87:085cde657901	3025	sConfig->ICSelection,
mbed_official	87:085cde657901	3026	sConfig->ICFilter);
mbed_official	87:085cde657901	3027
mbed_official	87:085cde657901	3028	/* Reset the IC2PSC Bits */
mbed_official	87:085cde657901	3029	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official	87:085cde657901	3030
mbed_official	87:085cde657901	3031	/* Set the IC2PSC value */
mbed_official	87:085cde657901	3032	htim->Instance->CCMR1 \|= (sConfig->ICPrescaler << 8);
mbed_official	87:085cde657901	3033	}
mbed_official	87:085cde657901	3034	else if (Channel == TIM_CHANNEL_3)
mbed_official	87:085cde657901	3035	{
mbed_official	87:085cde657901	3036	/* TI3 Configuration */
mbed_official	87:085cde657901	3037	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3038
mbed_official	87:085cde657901	3039	TIM_TI3_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3040	sConfig->ICPolarity,
mbed_official	87:085cde657901	3041	sConfig->ICSelection,
mbed_official	87:085cde657901	3042	sConfig->ICFilter);
mbed_official	87:085cde657901	3043
mbed_official	87:085cde657901	3044	/* Reset the IC3PSC Bits */
mbed_official	87:085cde657901	3045	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
mbed_official	87:085cde657901	3046
mbed_official	87:085cde657901	3047	/* Set the IC3PSC value */
mbed_official	87:085cde657901	3048	htim->Instance->CCMR2 \|= sConfig->ICPrescaler;
mbed_official	87:085cde657901	3049	}
mbed_official	87:085cde657901	3050	else
mbed_official	87:085cde657901	3051	{
mbed_official	87:085cde657901	3052	/* TI4 Configuration */
mbed_official	87:085cde657901	3053	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3054
mbed_official	87:085cde657901	3055	TIM_TI4_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3056	sConfig->ICPolarity,
mbed_official	87:085cde657901	3057	sConfig->ICSelection,
mbed_official	87:085cde657901	3058	sConfig->ICFilter);
mbed_official	87:085cde657901	3059
mbed_official	87:085cde657901	3060	/* Reset the IC4PSC Bits */
mbed_official	87:085cde657901	3061	htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
mbed_official	87:085cde657901	3062
mbed_official	87:085cde657901	3063	/* Set the IC4PSC value */
mbed_official	87:085cde657901	3064	htim->Instance->CCMR2 \|= (sConfig->ICPrescaler << 8);
mbed_official	87:085cde657901	3065	}
mbed_official	87:085cde657901	3066
mbed_official	87:085cde657901	3067	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3068
mbed_official	87:085cde657901	3069	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3070
mbed_official	87:085cde657901	3071	return HAL_OK;
mbed_official	87:085cde657901	3072	}
mbed_official	87:085cde657901	3073
mbed_official	87:085cde657901	3074	/**
mbed_official	87:085cde657901	3075	* @brief Initializes the TIM PWM channels according to the specified
mbed_official	87:085cde657901	3076	* parameters in the TIM_OC_InitTypeDef.
mbed_official	226:b062af740e40	3077	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3078	* the configuration information for TIM module.
mbed_official	87:085cde657901	3079	* @param sConfig: TIM PWM configuration structure
mbed_official	226:b062af740e40	3080	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	3081	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3082	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	3083	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	3084	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	3085	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	3086	* @retval HAL status
mbed_official	87:085cde657901	3087	*/
mbed_official	87:085cde657901	3088	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel)
mbed_official	87:085cde657901	3089	{
mbed_official	87:085cde657901	3090	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3091
mbed_official	87:085cde657901	3092	/* Check the parameters */
mbed_official	87:085cde657901	3093	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	87:085cde657901	3094	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
mbed_official	87:085cde657901	3095	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official	87:085cde657901	3096	assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official	87:085cde657901	3097	assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official	87:085cde657901	3098	assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official	87:085cde657901	3099
mbed_official	87:085cde657901	3100	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3101
mbed_official	87:085cde657901	3102	switch (Channel)
mbed_official	87:085cde657901	3103	{
mbed_official	87:085cde657901	3104	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	3105	{
mbed_official	87:085cde657901	3106	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3107	/* Configure the Channel 1 in PWM mode */
mbed_official	87:085cde657901	3108	TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	3109
mbed_official	87:085cde657901	3110	/* Set the Preload enable bit for channel1 */
mbed_official	87:085cde657901	3111	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
mbed_official	87:085cde657901	3112
mbed_official	87:085cde657901	3113	/* Configure the Output Fast mode */
mbed_official	87:085cde657901	3114	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
mbed_official	87:085cde657901	3115	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
mbed_official	87:085cde657901	3116	}
mbed_official	87:085cde657901	3117	break;
mbed_official	87:085cde657901	3118
mbed_official	87:085cde657901	3119	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	3120	{
mbed_official	87:085cde657901	3121	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3122	/* Configure the Channel 2 in PWM mode */
mbed_official	87:085cde657901	3123	TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	3124
mbed_official	87:085cde657901	3125	/* Set the Preload enable bit for channel2 */
mbed_official	87:085cde657901	3126	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
mbed_official	87:085cde657901	3127
mbed_official	87:085cde657901	3128	/* Configure the Output Fast mode */
mbed_official	87:085cde657901	3129	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
mbed_official	87:085cde657901	3130	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
mbed_official	87:085cde657901	3131	}
mbed_official	87:085cde657901	3132	break;
mbed_official	87:085cde657901	3133
mbed_official	87:085cde657901	3134	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	3135	{
mbed_official	87:085cde657901	3136	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3137	/* Configure the Channel 3 in PWM mode */
mbed_official	87:085cde657901	3138	TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	3139
mbed_official	87:085cde657901	3140	/* Set the Preload enable bit for channel3 */
mbed_official	87:085cde657901	3141	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
mbed_official	87:085cde657901	3142
mbed_official	87:085cde657901	3143	/* Configure the Output Fast mode */
mbed_official	87:085cde657901	3144	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
mbed_official	87:085cde657901	3145	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
mbed_official	87:085cde657901	3146	}
mbed_official	87:085cde657901	3147	break;
mbed_official	87:085cde657901	3148
mbed_official	87:085cde657901	3149	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	3150	{
mbed_official	87:085cde657901	3151	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3152	/* Configure the Channel 4 in PWM mode */
mbed_official	87:085cde657901	3153	TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official	87:085cde657901	3154
mbed_official	87:085cde657901	3155	/* Set the Preload enable bit for channel4 */
mbed_official	87:085cde657901	3156	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
mbed_official	87:085cde657901	3157
mbed_official	87:085cde657901	3158	/* Configure the Output Fast mode */
mbed_official	87:085cde657901	3159	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
mbed_official	87:085cde657901	3160	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
mbed_official	87:085cde657901	3161	}
mbed_official	87:085cde657901	3162	break;
mbed_official	87:085cde657901	3163
mbed_official	87:085cde657901	3164	default:
mbed_official	87:085cde657901	3165	break;
mbed_official	87:085cde657901	3166	}
mbed_official	87:085cde657901	3167
mbed_official	87:085cde657901	3168	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3169
mbed_official	87:085cde657901	3170	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3171
mbed_official	87:085cde657901	3172	return HAL_OK;
mbed_official	87:085cde657901	3173	}
mbed_official	87:085cde657901	3174
mbed_official	87:085cde657901	3175	/**
mbed_official	87:085cde657901	3176	* @brief Initializes the TIM One Pulse Channels according to the specified
mbed_official	87:085cde657901	3177	* parameters in the TIM_OnePulse_InitTypeDef.
mbed_official	226:b062af740e40	3178	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3179	* the configuration information for TIM module.
mbed_official	87:085cde657901	3180	* @param sConfig: TIM One Pulse configuration structure
mbed_official	226:b062af740e40	3181	* @param OutputChannel: TIM Channels to be enabled.
mbed_official	87:085cde657901	3182	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3183	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	3184	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	226:b062af740e40	3185	* @param InputChannel: TIM Channels to be enabled.
mbed_official	87:085cde657901	3186	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3187	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	3188	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	3189	* @retval HAL status
mbed_official	87:085cde657901	3190	*/
mbed_official	87:085cde657901	3191	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel)
mbed_official	87:085cde657901	3192	{
mbed_official	87:085cde657901	3193	TIM_OC_InitTypeDef temp1;
mbed_official	87:085cde657901	3194
mbed_official	87:085cde657901	3195	/* Check the parameters */
mbed_official	87:085cde657901	3196	assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
mbed_official	87:085cde657901	3197	assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
mbed_official	87:085cde657901	3198
mbed_official	87:085cde657901	3199	if(OutputChannel != InputChannel)
mbed_official	87:085cde657901	3200	{
mbed_official	87:085cde657901	3201	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3202
mbed_official	87:085cde657901	3203	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3204
mbed_official	87:085cde657901	3205	/* Extract the Ouput compare configuration from sConfig structure */
mbed_official	87:085cde657901	3206	temp1.OCMode = sConfig->OCMode;
mbed_official	87:085cde657901	3207	temp1.Pulse = sConfig->Pulse;
mbed_official	87:085cde657901	3208	temp1.OCPolarity = sConfig->OCPolarity;
mbed_official	87:085cde657901	3209	temp1.OCNPolarity = sConfig->OCNPolarity;
mbed_official	87:085cde657901	3210	temp1.OCIdleState = sConfig->OCIdleState;
mbed_official	87:085cde657901	3211	temp1.OCNIdleState = sConfig->OCNIdleState;
mbed_official	87:085cde657901	3212
mbed_official	87:085cde657901	3213	switch (OutputChannel)
mbed_official	87:085cde657901	3214	{
mbed_official	87:085cde657901	3215	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	3216	{
mbed_official	87:085cde657901	3217	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3218
mbed_official	87:085cde657901	3219	TIM_OC1_SetConfig(htim->Instance, &temp1);
mbed_official	87:085cde657901	3220	}
mbed_official	87:085cde657901	3221	break;
mbed_official	87:085cde657901	3222	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	3223	{
mbed_official	87:085cde657901	3224	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3225
mbed_official	87:085cde657901	3226	TIM_OC2_SetConfig(htim->Instance, &temp1);
mbed_official	87:085cde657901	3227	}
mbed_official	87:085cde657901	3228	break;
mbed_official	87:085cde657901	3229	default:
mbed_official	87:085cde657901	3230	break;
mbed_official	87:085cde657901	3231	}
mbed_official	87:085cde657901	3232	switch (InputChannel)
mbed_official	87:085cde657901	3233	{
mbed_official	87:085cde657901	3234	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	3235	{
mbed_official	87:085cde657901	3236	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3237
mbed_official	87:085cde657901	3238	TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official	87:085cde657901	3239	sConfig->ICSelection, sConfig->ICFilter);
mbed_official	87:085cde657901	3240
mbed_official	87:085cde657901	3241	/* Reset the IC1PSC Bits */
mbed_official	87:085cde657901	3242	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official	87:085cde657901	3243
mbed_official	87:085cde657901	3244	/* Select the Trigger source */
mbed_official	87:085cde657901	3245	htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official	87:085cde657901	3246	htim->Instance->SMCR \|= TIM_TS_TI1FP1;
mbed_official	87:085cde657901	3247
mbed_official	87:085cde657901	3248	/* Select the Slave Mode */
mbed_official	87:085cde657901	3249	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	3250	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
mbed_official	87:085cde657901	3251	}
mbed_official	87:085cde657901	3252	break;
mbed_official	87:085cde657901	3253	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	3254	{
mbed_official	87:085cde657901	3255	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3256
mbed_official	87:085cde657901	3257	TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official	87:085cde657901	3258	sConfig->ICSelection, sConfig->ICFilter);
mbed_official	87:085cde657901	3259
mbed_official	87:085cde657901	3260	/* Reset the IC2PSC Bits */
mbed_official	87:085cde657901	3261	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official	87:085cde657901	3262
mbed_official	87:085cde657901	3263	/* Select the Trigger source */
mbed_official	87:085cde657901	3264	htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official	87:085cde657901	3265	htim->Instance->SMCR \|= TIM_TS_TI2FP2;
mbed_official	87:085cde657901	3266
mbed_official	87:085cde657901	3267	/* Select the Slave Mode */
mbed_official	87:085cde657901	3268	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	3269	htim->Instance->SMCR \|= TIM_SLAVEMODE_TRIGGER;
mbed_official	87:085cde657901	3270	}
mbed_official	87:085cde657901	3271	break;
mbed_official	87:085cde657901	3272
mbed_official	87:085cde657901	3273	default:
mbed_official	87:085cde657901	3274	break;
mbed_official	87:085cde657901	3275	}
mbed_official	87:085cde657901	3276
mbed_official	87:085cde657901	3277	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3278
mbed_official	87:085cde657901	3279	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3280
mbed_official	87:085cde657901	3281	return HAL_OK;
mbed_official	87:085cde657901	3282	}
mbed_official	87:085cde657901	3283	else
mbed_official	87:085cde657901	3284	{
mbed_official	87:085cde657901	3285	return HAL_ERROR;
mbed_official	87:085cde657901	3286	}
mbed_official	87:085cde657901	3287	}
mbed_official	87:085cde657901	3288
mbed_official	87:085cde657901	3289	/**
mbed_official	87:085cde657901	3290	* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
mbed_official	226:b062af740e40	3291	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3292	* the configuration information for TIM module.
mbed_official	226:b062af740e40	3293	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
mbed_official	87:085cde657901	3294	* This parameters can be on of the following values:
mbed_official	87:085cde657901	3295	* @arg TIM_DMABase_CR1
mbed_official	87:085cde657901	3296	* @arg TIM_DMABase_CR2
mbed_official	87:085cde657901	3297	* @arg TIM_DMABase_SMCR
mbed_official	87:085cde657901	3298	* @arg TIM_DMABase_DIER
mbed_official	87:085cde657901	3299	* @arg TIM_DMABase_SR
mbed_official	87:085cde657901	3300	* @arg TIM_DMABase_EGR
mbed_official	87:085cde657901	3301	* @arg TIM_DMABase_CCMR1
mbed_official	87:085cde657901	3302	* @arg TIM_DMABase_CCMR2
mbed_official	87:085cde657901	3303	* @arg TIM_DMABase_CCER
mbed_official	87:085cde657901	3304	* @arg TIM_DMABase_CNT
mbed_official	87:085cde657901	3305	* @arg TIM_DMABase_PSC
mbed_official	87:085cde657901	3306	* @arg TIM_DMABase_ARR
mbed_official	87:085cde657901	3307	* @arg TIM_DMABase_RCR
mbed_official	87:085cde657901	3308	* @arg TIM_DMABase_CCR1
mbed_official	87:085cde657901	3309	* @arg TIM_DMABase_CCR2
mbed_official	87:085cde657901	3310	* @arg TIM_DMABase_CCR3
mbed_official	87:085cde657901	3311	* @arg TIM_DMABase_CCR4
mbed_official	87:085cde657901	3312	* @arg TIM_DMABase_BDTR
mbed_official	87:085cde657901	3313	* @arg TIM_DMABase_DCR
mbed_official	226:b062af740e40	3314	* @param BurstRequestSrc: TIM DMA Request sources.
mbed_official	87:085cde657901	3315	* This parameters can be on of the following values:
mbed_official	87:085cde657901	3316	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official	87:085cde657901	3317	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official	87:085cde657901	3318	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official	87:085cde657901	3319	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official	87:085cde657901	3320	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official	87:085cde657901	3321	* @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official	87:085cde657901	3322	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official	87:085cde657901	3323	* @param BurstBuffer: The Buffer address.
mbed_official	87:085cde657901	3324	* @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official	226:b062af740e40	3325	* between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official	87:085cde657901	3326	* @retval HAL status
mbed_official	87:085cde657901	3327	*/
mbed_official	87:085cde657901	3328	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official	87:085cde657901	3329	uint32_t* BurstBuffer, uint32_t BurstLength)
mbed_official	87:085cde657901	3330	{
mbed_official	87:085cde657901	3331	/* Check the parameters */
mbed_official	87:085cde657901	3332	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3333	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official	87:085cde657901	3334	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	87:085cde657901	3335	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official	87:085cde657901	3336
mbed_official	87:085cde657901	3337	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	3338	{
mbed_official	87:085cde657901	3339	return HAL_BUSY;
mbed_official	87:085cde657901	3340	}
mbed_official	87:085cde657901	3341	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	3342	{
mbed_official	87:085cde657901	3343	if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official	87:085cde657901	3344	{
mbed_official	87:085cde657901	3345	return HAL_ERROR;
mbed_official	87:085cde657901	3346	}
mbed_official	87:085cde657901	3347	else
mbed_official	87:085cde657901	3348	{
mbed_official	87:085cde657901	3349	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3350	}
mbed_official	87:085cde657901	3351	}
mbed_official	87:085cde657901	3352	switch(BurstRequestSrc)
mbed_official	87:085cde657901	3353	{
mbed_official	87:085cde657901	3354	case TIM_DMA_UPDATE:
mbed_official	87:085cde657901	3355	{
mbed_official	87:085cde657901	3356	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3357	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official	87:085cde657901	3358
mbed_official	87:085cde657901	3359	/* Set the DMA error callback */
mbed_official	87:085cde657901	3360	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3361
mbed_official	87:085cde657901	3362	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3363	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3364	}
mbed_official	87:085cde657901	3365	break;
mbed_official	87:085cde657901	3366	case TIM_DMA_CC1:
mbed_official	87:085cde657901	3367	{
mbed_official	87:085cde657901	3368	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3369	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	3370
mbed_official	87:085cde657901	3371	/* Set the DMA error callback */
mbed_official	87:085cde657901	3372	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3373
mbed_official	87:085cde657901	3374	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3375	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3376	}
mbed_official	87:085cde657901	3377	break;
mbed_official	87:085cde657901	3378	case TIM_DMA_CC2:
mbed_official	87:085cde657901	3379	{
mbed_official	87:085cde657901	3380	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3381	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	3382
mbed_official	87:085cde657901	3383	/* Set the DMA error callback */
mbed_official	87:085cde657901	3384	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3385
mbed_official	87:085cde657901	3386	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3387	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3388	}
mbed_official	87:085cde657901	3389	break;
mbed_official	87:085cde657901	3390	case TIM_DMA_CC3:
mbed_official	87:085cde657901	3391	{
mbed_official	87:085cde657901	3392	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3393	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	3394
mbed_official	87:085cde657901	3395	/* Set the DMA error callback */
mbed_official	87:085cde657901	3396	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3397
mbed_official	87:085cde657901	3398	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3399	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3400	}
mbed_official	87:085cde657901	3401	break;
mbed_official	87:085cde657901	3402	case TIM_DMA_CC4:
mbed_official	87:085cde657901	3403	{
mbed_official	87:085cde657901	3404	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3405	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
mbed_official	87:085cde657901	3406
mbed_official	87:085cde657901	3407	/* Set the DMA error callback */
mbed_official	87:085cde657901	3408	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3409
mbed_official	87:085cde657901	3410	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3411	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3412	}
mbed_official	87:085cde657901	3413	break;
mbed_official	87:085cde657901	3414	case TIM_DMA_COM:
mbed_official	87:085cde657901	3415	{
mbed_official	87:085cde657901	3416	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3417	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official	87:085cde657901	3418
mbed_official	87:085cde657901	3419	/* Set the DMA error callback */
mbed_official	87:085cde657901	3420	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3421
mbed_official	87:085cde657901	3422	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3423	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3424	}
mbed_official	87:085cde657901	3425	break;
mbed_official	87:085cde657901	3426	case TIM_DMA_TRIGGER:
mbed_official	87:085cde657901	3427	{
mbed_official	87:085cde657901	3428	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3429	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official	87:085cde657901	3430
mbed_official	87:085cde657901	3431	/* Set the DMA error callback */
mbed_official	87:085cde657901	3432	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3433
mbed_official	87:085cde657901	3434	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3435	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3436	}
mbed_official	87:085cde657901	3437	break;
mbed_official	87:085cde657901	3438	default:
mbed_official	87:085cde657901	3439	break;
mbed_official	87:085cde657901	3440	}
mbed_official	87:085cde657901	3441	/* configure the DMA Burst Mode */
mbed_official	87:085cde657901	3442	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
mbed_official	87:085cde657901	3443
mbed_official	87:085cde657901	3444	/* Enable the TIM DMA Request */
mbed_official	87:085cde657901	3445	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official	87:085cde657901	3446
mbed_official	87:085cde657901	3447	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3448
mbed_official	87:085cde657901	3449	/* Return function status */
mbed_official	87:085cde657901	3450	return HAL_OK;
mbed_official	87:085cde657901	3451	}
mbed_official	87:085cde657901	3452
mbed_official	87:085cde657901	3453	/**
mbed_official	87:085cde657901	3454	* @brief Stops the TIM DMA Burst mode
mbed_official	226:b062af740e40	3455	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3456	* the configuration information for TIM module.
mbed_official	87:085cde657901	3457	* @param BurstRequestSrc: TIM DMA Request sources to disable
mbed_official	87:085cde657901	3458	* @retval HAL status
mbed_official	87:085cde657901	3459	*/
mbed_official	87:085cde657901	3460	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official	87:085cde657901	3461	{
mbed_official	87:085cde657901	3462	/* Check the parameters */
mbed_official	87:085cde657901	3463	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	87:085cde657901	3464
mbed_official	87:085cde657901	3465	/* Disable the TIM Update DMA request */
mbed_official	87:085cde657901	3466	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official	87:085cde657901	3467
mbed_official	87:085cde657901	3468	/* Return function status */
mbed_official	87:085cde657901	3469	return HAL_OK;
mbed_official	87:085cde657901	3470	}
mbed_official	87:085cde657901	3471
mbed_official	87:085cde657901	3472	/**
mbed_official	87:085cde657901	3473	* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
mbed_official	226:b062af740e40	3474	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3475	* the configuration information for TIM module.
mbed_official	226:b062af740e40	3476	* @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
mbed_official	87:085cde657901	3477	* This parameters can be on of the following values:
mbed_official	87:085cde657901	3478	* @arg TIM_DMABase_CR1
mbed_official	87:085cde657901	3479	* @arg TIM_DMABase_CR2
mbed_official	87:085cde657901	3480	* @arg TIM_DMABase_SMCR
mbed_official	87:085cde657901	3481	* @arg TIM_DMABase_DIER
mbed_official	87:085cde657901	3482	* @arg TIM_DMABase_SR
mbed_official	87:085cde657901	3483	* @arg TIM_DMABase_EGR
mbed_official	87:085cde657901	3484	* @arg TIM_DMABase_CCMR1
mbed_official	87:085cde657901	3485	* @arg TIM_DMABase_CCMR2
mbed_official	87:085cde657901	3486	* @arg TIM_DMABase_CCER
mbed_official	87:085cde657901	3487	* @arg TIM_DMABase_CNT
mbed_official	87:085cde657901	3488	* @arg TIM_DMABase_PSC
mbed_official	87:085cde657901	3489	* @arg TIM_DMABase_ARR
mbed_official	87:085cde657901	3490	* @arg TIM_DMABase_RCR
mbed_official	87:085cde657901	3491	* @arg TIM_DMABase_CCR1
mbed_official	87:085cde657901	3492	* @arg TIM_DMABase_CCR2
mbed_official	87:085cde657901	3493	* @arg TIM_DMABase_CCR3
mbed_official	87:085cde657901	3494	* @arg TIM_DMABase_CCR4
mbed_official	87:085cde657901	3495	* @arg TIM_DMABase_BDTR
mbed_official	87:085cde657901	3496	* @arg TIM_DMABase_DCR
mbed_official	226:b062af740e40	3497	* @param BurstRequestSrc: TIM DMA Request sources.
mbed_official	87:085cde657901	3498	* This parameters can be on of the following values:
mbed_official	87:085cde657901	3499	* @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official	87:085cde657901	3500	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official	87:085cde657901	3501	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official	87:085cde657901	3502	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official	87:085cde657901	3503	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official	87:085cde657901	3504	* @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official	87:085cde657901	3505	* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official	87:085cde657901	3506	* @param BurstBuffer: The Buffer address.
mbed_official	87:085cde657901	3507	* @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official	226:b062af740e40	3508	* between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official	87:085cde657901	3509	* @retval HAL status
mbed_official	87:085cde657901	3510	*/
mbed_official	87:085cde657901	3511	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official	87:085cde657901	3512	uint32_t *BurstBuffer, uint32_t BurstLength)
mbed_official	87:085cde657901	3513	{
mbed_official	87:085cde657901	3514	/* Check the parameters */
mbed_official	87:085cde657901	3515	assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3516	assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official	87:085cde657901	3517	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	87:085cde657901	3518	assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official	87:085cde657901	3519
mbed_official	87:085cde657901	3520	if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official	87:085cde657901	3521	{
mbed_official	87:085cde657901	3522	return HAL_BUSY;
mbed_official	87:085cde657901	3523	}
mbed_official	87:085cde657901	3524	else if((htim->State == HAL_TIM_STATE_READY))
mbed_official	87:085cde657901	3525	{
mbed_official	87:085cde657901	3526	if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official	87:085cde657901	3527	{
mbed_official	87:085cde657901	3528	return HAL_ERROR;
mbed_official	87:085cde657901	3529	}
mbed_official	87:085cde657901	3530	else
mbed_official	87:085cde657901	3531	{
mbed_official	87:085cde657901	3532	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3533	}
mbed_official	87:085cde657901	3534	}
mbed_official	87:085cde657901	3535	switch(BurstRequestSrc)
mbed_official	87:085cde657901	3536	{
mbed_official	87:085cde657901	3537	case TIM_DMA_UPDATE:
mbed_official	87:085cde657901	3538	{
mbed_official	87:085cde657901	3539	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3540	htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official	87:085cde657901	3541
mbed_official	87:085cde657901	3542	/* Set the DMA error callback */
mbed_official	87:085cde657901	3543	htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3544
mbed_official	87:085cde657901	3545	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3546	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3547	}
mbed_official	87:085cde657901	3548	break;
mbed_official	87:085cde657901	3549	case TIM_DMA_CC1:
mbed_official	87:085cde657901	3550	{
mbed_official	87:085cde657901	3551	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3552	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	3553
mbed_official	87:085cde657901	3554	/* Set the DMA error callback */
mbed_official	87:085cde657901	3555	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3556
mbed_official	87:085cde657901	3557	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3558	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3559	}
mbed_official	87:085cde657901	3560	break;
mbed_official	87:085cde657901	3561	case TIM_DMA_CC2:
mbed_official	87:085cde657901	3562	{
mbed_official	87:085cde657901	3563	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3564	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	3565
mbed_official	87:085cde657901	3566	/* Set the DMA error callback */
mbed_official	87:085cde657901	3567	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3568
mbed_official	87:085cde657901	3569	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3570	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3571	}
mbed_official	87:085cde657901	3572	break;
mbed_official	87:085cde657901	3573	case TIM_DMA_CC3:
mbed_official	87:085cde657901	3574	{
mbed_official	87:085cde657901	3575	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3576	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	3577
mbed_official	87:085cde657901	3578	/* Set the DMA error callback */
mbed_official	87:085cde657901	3579	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3580
mbed_official	87:085cde657901	3581	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3582	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3583	}
mbed_official	87:085cde657901	3584	break;
mbed_official	87:085cde657901	3585	case TIM_DMA_CC4:
mbed_official	87:085cde657901	3586	{
mbed_official	87:085cde657901	3587	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3588	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
mbed_official	87:085cde657901	3589
mbed_official	87:085cde657901	3590	/* Set the DMA error callback */
mbed_official	87:085cde657901	3591	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3592
mbed_official	87:085cde657901	3593	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3594	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3595	}
mbed_official	87:085cde657901	3596	break;
mbed_official	87:085cde657901	3597	case TIM_DMA_COM:
mbed_official	87:085cde657901	3598	{
mbed_official	87:085cde657901	3599	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3600	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
mbed_official	87:085cde657901	3601
mbed_official	87:085cde657901	3602	/* Set the DMA error callback */
mbed_official	87:085cde657901	3603	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3604
mbed_official	87:085cde657901	3605	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3606	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3607	}
mbed_official	87:085cde657901	3608	break;
mbed_official	87:085cde657901	3609	case TIM_DMA_TRIGGER:
mbed_official	87:085cde657901	3610	{
mbed_official	87:085cde657901	3611	/* Set the DMA Period elapsed callback */
mbed_official	87:085cde657901	3612	htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official	87:085cde657901	3613
mbed_official	87:085cde657901	3614	/* Set the DMA error callback */
mbed_official	87:085cde657901	3615	htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
mbed_official	87:085cde657901	3616
mbed_official	87:085cde657901	3617	/* Enable the DMA Stream */
mbed_official	87:085cde657901	3618	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official	87:085cde657901	3619	}
mbed_official	87:085cde657901	3620	break;
mbed_official	87:085cde657901	3621	default:
mbed_official	87:085cde657901	3622	break;
mbed_official	87:085cde657901	3623	}
mbed_official	87:085cde657901	3624
mbed_official	87:085cde657901	3625	/* configure the DMA Burst Mode */
mbed_official	87:085cde657901	3626	htim->Instance->DCR = BurstBaseAddress \| BurstLength;
mbed_official	87:085cde657901	3627
mbed_official	87:085cde657901	3628	/* Enable the TIM DMA Request */
mbed_official	87:085cde657901	3629	__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official	87:085cde657901	3630
mbed_official	87:085cde657901	3631	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3632
mbed_official	87:085cde657901	3633	/* Return function status */
mbed_official	87:085cde657901	3634	return HAL_OK;
mbed_official	87:085cde657901	3635	}
mbed_official	87:085cde657901	3636
mbed_official	87:085cde657901	3637	/**
mbed_official	87:085cde657901	3638	* @brief Stop the DMA burst reading
mbed_official	226:b062af740e40	3639	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3640	* the configuration information for TIM module.
mbed_official	87:085cde657901	3641	* @param BurstRequestSrc: TIM DMA Request sources to disable.
mbed_official	87:085cde657901	3642	* @retval HAL status
mbed_official	87:085cde657901	3643	*/
mbed_official	87:085cde657901	3644	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official	87:085cde657901	3645	{
mbed_official	87:085cde657901	3646	/* Check the parameters */
mbed_official	87:085cde657901	3647	assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official	87:085cde657901	3648
mbed_official	87:085cde657901	3649	/* Disable the TIM Update DMA request */
mbed_official	87:085cde657901	3650	__HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official	87:085cde657901	3651
mbed_official	87:085cde657901	3652	/* Return function status */
mbed_official	87:085cde657901	3653	return HAL_OK;
mbed_official	87:085cde657901	3654	}
mbed_official	87:085cde657901	3655
mbed_official	87:085cde657901	3656	/**
mbed_official	87:085cde657901	3657	* @brief Generate a software event
mbed_official	226:b062af740e40	3658	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3659	* the configuration information for TIM module.
mbed_official	87:085cde657901	3660	* @param EventSource: specifies the event source.
mbed_official	87:085cde657901	3661	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3662	* @arg TIM_EventSource_Update: Timer update Event source
mbed_official	87:085cde657901	3663	* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
mbed_official	87:085cde657901	3664	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
mbed_official	87:085cde657901	3665	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
mbed_official	87:085cde657901	3666	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
mbed_official	87:085cde657901	3667	* @arg TIM_EventSource_COM: Timer COM event source
mbed_official	87:085cde657901	3668	* @arg TIM_EventSource_Trigger: Timer Trigger Event source
mbed_official	87:085cde657901	3669	* @arg TIM_EventSource_Break: Timer Break event source
mbed_official	87:085cde657901	3670	* @note TIM6 and TIM7 can only generate an update event.
mbed_official	87:085cde657901	3671	* @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
mbed_official	87:085cde657901	3672	* @retval HAL status
mbed_official	87:085cde657901	3673	*/
mbed_official	87:085cde657901	3674
mbed_official	87:085cde657901	3675	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
mbed_official	87:085cde657901	3676	{
mbed_official	87:085cde657901	3677	/* Check the parameters */
mbed_official	87:085cde657901	3678	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3679	assert_param(IS_TIM_EVENT_SOURCE(EventSource));
mbed_official	87:085cde657901	3680
mbed_official	87:085cde657901	3681	/* Process Locked */
mbed_official	87:085cde657901	3682	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3683
mbed_official	87:085cde657901	3684	/* Change the TIM state */
mbed_official	87:085cde657901	3685	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3686
mbed_official	87:085cde657901	3687	/* Set the event sources */
mbed_official	87:085cde657901	3688	htim->Instance->EGR = EventSource;
mbed_official	87:085cde657901	3689
mbed_official	87:085cde657901	3690	/* Change the TIM state */
mbed_official	87:085cde657901	3691	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3692
mbed_official	87:085cde657901	3693	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3694
mbed_official	87:085cde657901	3695	/* Return function status */
mbed_official	87:085cde657901	3696	return HAL_OK;
mbed_official	87:085cde657901	3697	}
mbed_official	87:085cde657901	3698
mbed_official	87:085cde657901	3699	/**
mbed_official	87:085cde657901	3700	* @brief Configures the OCRef clear feature
mbed_official	226:b062af740e40	3701	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3702	* the configuration information for TIM module.
mbed_official	87:085cde657901	3703	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
mbed_official	87:085cde657901	3704	* contains the OCREF clear feature and parameters for the TIM peripheral.
mbed_official	226:b062af740e40	3705	* @param Channel: specifies the TIM Channel.
mbed_official	87:085cde657901	3706	* This parameter can be one of the following values:
mbed_official	226:b062af740e40	3707	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	226:b062af740e40	3708	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	226:b062af740e40	3709	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	226:b062af740e40	3710	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	3711	* @retval HAL status
mbed_official	87:085cde657901	3712	*/
mbed_official	87:085cde657901	3713	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel)
mbed_official	87:085cde657901	3714	{
mbed_official	87:085cde657901	3715	/* Check the parameters */
mbed_official	87:085cde657901	3716	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3717	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	87:085cde657901	3718	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
mbed_official	87:085cde657901	3719	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
mbed_official	87:085cde657901	3720	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
mbed_official	87:085cde657901	3721	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
mbed_official	87:085cde657901	3722
mbed_official	87:085cde657901	3723	/* Process Locked */
mbed_official	87:085cde657901	3724	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3725
mbed_official	87:085cde657901	3726	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3727
mbed_official	87:085cde657901	3728	if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
mbed_official	87:085cde657901	3729	{
mbed_official	87:085cde657901	3730	TIM_ETR_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3731	sClearInputConfig->ClearInputPrescaler,
mbed_official	87:085cde657901	3732	sClearInputConfig->ClearInputPolarity,
mbed_official	87:085cde657901	3733	sClearInputConfig->ClearInputFilter);
mbed_official	87:085cde657901	3734	}
mbed_official	87:085cde657901	3735
mbed_official	87:085cde657901	3736	switch (Channel)
mbed_official	87:085cde657901	3737	{
mbed_official	87:085cde657901	3738	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	3739	{
mbed_official	87:085cde657901	3740	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	87:085cde657901	3741	{
mbed_official	87:085cde657901	3742	/* Enable the Ocref clear feature for Channel 1 */
mbed_official	87:085cde657901	3743	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
mbed_official	87:085cde657901	3744	}
mbed_official	87:085cde657901	3745	else
mbed_official	87:085cde657901	3746	{
mbed_official	87:085cde657901	3747	/* Disable the Ocref clear feature for Channel 1 */
mbed_official	87:085cde657901	3748	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
mbed_official	87:085cde657901	3749	}
mbed_official	87:085cde657901	3750	}
mbed_official	87:085cde657901	3751	break;
mbed_official	87:085cde657901	3752	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	3753	{
mbed_official	87:085cde657901	3754	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3755	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	87:085cde657901	3756	{
mbed_official	87:085cde657901	3757	/* Enable the Ocref clear feature for Channel 2 */
mbed_official	87:085cde657901	3758	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
mbed_official	87:085cde657901	3759	}
mbed_official	87:085cde657901	3760	else
mbed_official	87:085cde657901	3761	{
mbed_official	87:085cde657901	3762	/* Disable the Ocref clear feature for Channel 2 */
mbed_official	87:085cde657901	3763	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
mbed_official	87:085cde657901	3764	}
mbed_official	87:085cde657901	3765	}
mbed_official	87:085cde657901	3766	break;
mbed_official	87:085cde657901	3767	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	3768	{
mbed_official	87:085cde657901	3769	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3770	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	87:085cde657901	3771	{
mbed_official	87:085cde657901	3772	/* Enable the Ocref clear feature for Channel 3 */
mbed_official	87:085cde657901	3773	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
mbed_official	87:085cde657901	3774	}
mbed_official	87:085cde657901	3775	else
mbed_official	87:085cde657901	3776	{
mbed_official	87:085cde657901	3777	/* Disable the Ocref clear feature for Channel 3 */
mbed_official	87:085cde657901	3778	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
mbed_official	87:085cde657901	3779	}
mbed_official	87:085cde657901	3780	}
mbed_official	87:085cde657901	3781	break;
mbed_official	87:085cde657901	3782	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	3783	{
mbed_official	87:085cde657901	3784	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3785	if(sClearInputConfig->ClearInputState != RESET)
mbed_official	87:085cde657901	3786	{
mbed_official	87:085cde657901	3787	/* Enable the Ocref clear feature for Channel 4 */
mbed_official	87:085cde657901	3788	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
mbed_official	87:085cde657901	3789	}
mbed_official	87:085cde657901	3790	else
mbed_official	87:085cde657901	3791	{
mbed_official	87:085cde657901	3792	/* Disable the Ocref clear feature for Channel 4 */
mbed_official	87:085cde657901	3793	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
mbed_official	87:085cde657901	3794	}
mbed_official	87:085cde657901	3795	}
mbed_official	87:085cde657901	3796	break;
mbed_official	87:085cde657901	3797	default:
mbed_official	87:085cde657901	3798	break;
mbed_official	87:085cde657901	3799	}
mbed_official	87:085cde657901	3800
mbed_official	87:085cde657901	3801	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3802
mbed_official	87:085cde657901	3803	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3804
mbed_official	87:085cde657901	3805	return HAL_OK;
mbed_official	87:085cde657901	3806	}
mbed_official	87:085cde657901	3807
mbed_official	87:085cde657901	3808	/**
mbed_official	87:085cde657901	3809	* @brief Configures the clock source to be used
mbed_official	226:b062af740e40	3810	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3811	* the configuration information for TIM module.
mbed_official	87:085cde657901	3812	* @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
mbed_official	87:085cde657901	3813	* contains the clock source information for the TIM peripheral.
mbed_official	87:085cde657901	3814	* @retval HAL status
mbed_official	87:085cde657901	3815	*/
mbed_official	87:085cde657901	3816	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig)
mbed_official	87:085cde657901	3817	{
mbed_official	87:085cde657901	3818	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	3819
mbed_official	87:085cde657901	3820	/* Process Locked */
mbed_official	87:085cde657901	3821	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3822
mbed_official	87:085cde657901	3823	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	3824
mbed_official	87:085cde657901	3825	/* Check the parameters */
mbed_official	87:085cde657901	3826	assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
mbed_official	87:085cde657901	3827	assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official	87:085cde657901	3828	assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official	87:085cde657901	3829	assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official	87:085cde657901	3830
mbed_official	87:085cde657901	3831	/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
mbed_official	87:085cde657901	3832	tmpsmcr = htim->Instance->SMCR;
mbed_official	87:085cde657901	3833	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
mbed_official	87:085cde657901	3834	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
mbed_official	87:085cde657901	3835	htim->Instance->SMCR = tmpsmcr;
mbed_official	87:085cde657901	3836
mbed_official	87:085cde657901	3837	switch (sClockSourceConfig->ClockSource)
mbed_official	87:085cde657901	3838	{
mbed_official	87:085cde657901	3839	case TIM_CLOCKSOURCE_INTERNAL:
mbed_official	87:085cde657901	3840	{
mbed_official	87:085cde657901	3841	assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3842	/* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official	87:085cde657901	3843	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	3844	}
mbed_official	87:085cde657901	3845	break;
mbed_official	87:085cde657901	3846
mbed_official	87:085cde657901	3847	case TIM_CLOCKSOURCE_ETRMODE1:
mbed_official	87:085cde657901	3848	{
mbed_official	87:085cde657901	3849	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3850	/* Configure the ETR Clock source */
mbed_official	87:085cde657901	3851	TIM_ETR_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3852	sClockSourceConfig->ClockPrescaler,
mbed_official	87:085cde657901	3853	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3854	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3855	/* Get the TIMx SMCR register value */
mbed_official	87:085cde657901	3856	tmpsmcr = htim->Instance->SMCR;
mbed_official	87:085cde657901	3857	/* Reset the SMS and TS Bits */
mbed_official	87:085cde657901	3858	tmpsmcr &= ~(TIM_SMCR_SMS \| TIM_SMCR_TS);
mbed_official	87:085cde657901	3859	/* Select the External clock mode1 and the ETRF trigger */
mbed_official	87:085cde657901	3860	tmpsmcr \|= (TIM_SLAVEMODE_EXTERNAL1 \| TIM_CLOCKSOURCE_ETRMODE1);
mbed_official	87:085cde657901	3861	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	3862	htim->Instance->SMCR = tmpsmcr;
mbed_official	87:085cde657901	3863	}
mbed_official	87:085cde657901	3864	break;
mbed_official	87:085cde657901	3865
mbed_official	87:085cde657901	3866	case TIM_CLOCKSOURCE_ETRMODE2:
mbed_official	87:085cde657901	3867	{
mbed_official	87:085cde657901	3868	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3869	/* Configure the ETR Clock source */
mbed_official	87:085cde657901	3870	TIM_ETR_SetConfig(htim->Instance,
mbed_official	87:085cde657901	3871	sClockSourceConfig->ClockPrescaler,
mbed_official	87:085cde657901	3872	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3873	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3874	/* Enable the External clock mode2 */
mbed_official	87:085cde657901	3875	htim->Instance->SMCR \|= TIM_SMCR_ECE;
mbed_official	87:085cde657901	3876	}
mbed_official	87:085cde657901	3877	break;
mbed_official	87:085cde657901	3878
mbed_official	87:085cde657901	3879	case TIM_CLOCKSOURCE_TI1:
mbed_official	87:085cde657901	3880	{
mbed_official	87:085cde657901	3881	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3882	TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	3883	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3884	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3885	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
mbed_official	87:085cde657901	3886	}
mbed_official	87:085cde657901	3887	break;
mbed_official	87:085cde657901	3888	case TIM_CLOCKSOURCE_TI2:
mbed_official	87:085cde657901	3889	{
mbed_official	87:085cde657901	3890	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3891	TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	3892	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3893	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3894	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
mbed_official	87:085cde657901	3895	}
mbed_official	87:085cde657901	3896	break;
mbed_official	87:085cde657901	3897	case TIM_CLOCKSOURCE_TI1ED:
mbed_official	87:085cde657901	3898	{
mbed_official	87:085cde657901	3899	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3900	TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	3901	sClockSourceConfig->ClockPolarity,
mbed_official	87:085cde657901	3902	sClockSourceConfig->ClockFilter);
mbed_official	87:085cde657901	3903	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
mbed_official	87:085cde657901	3904	}
mbed_official	87:085cde657901	3905	break;
mbed_official	87:085cde657901	3906	case TIM_CLOCKSOURCE_ITR0:
mbed_official	87:085cde657901	3907	{
mbed_official	87:085cde657901	3908	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3909	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
mbed_official	87:085cde657901	3910	}
mbed_official	87:085cde657901	3911	break;
mbed_official	87:085cde657901	3912	case TIM_CLOCKSOURCE_ITR1:
mbed_official	87:085cde657901	3913	{
mbed_official	87:085cde657901	3914	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3915	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
mbed_official	87:085cde657901	3916	}
mbed_official	87:085cde657901	3917	break;
mbed_official	87:085cde657901	3918	case TIM_CLOCKSOURCE_ITR2:
mbed_official	87:085cde657901	3919	{
mbed_official	87:085cde657901	3920	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3921	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
mbed_official	87:085cde657901	3922	}
mbed_official	87:085cde657901	3923	break;
mbed_official	87:085cde657901	3924	case TIM_CLOCKSOURCE_ITR3:
mbed_official	87:085cde657901	3925	{
mbed_official	87:085cde657901	3926	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3927	TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
mbed_official	87:085cde657901	3928	}
mbed_official	87:085cde657901	3929	break;
mbed_official	87:085cde657901	3930
mbed_official	87:085cde657901	3931	default:
mbed_official	87:085cde657901	3932	break;
mbed_official	87:085cde657901	3933	}
mbed_official	87:085cde657901	3934	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	3935
mbed_official	87:085cde657901	3936	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	3937
mbed_official	87:085cde657901	3938	return HAL_OK;
mbed_official	87:085cde657901	3939	}
mbed_official	87:085cde657901	3940
mbed_official	87:085cde657901	3941	/**
mbed_official	87:085cde657901	3942	* @brief Selects the signal connected to the TI1 input: direct from CH1_input
mbed_official	87:085cde657901	3943	* or a XOR combination between CH1_input, CH2_input & CH3_input
mbed_official	226:b062af740e40	3944	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3945	* the configuration information for TIM module..
mbed_official	87:085cde657901	3946	* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
mbed_official	87:085cde657901	3947	* output of a XOR gate.
mbed_official	87:085cde657901	3948	* This parameter can be one of the following values:
mbed_official	87:085cde657901	3949	* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
mbed_official	87:085cde657901	3950	* @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
mbed_official	87:085cde657901	3951	* pins are connected to the TI1 input (XOR combination)
mbed_official	87:085cde657901	3952	* @retval HAL status
mbed_official	87:085cde657901	3953	*/
mbed_official	87:085cde657901	3954	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
mbed_official	87:085cde657901	3955	{
mbed_official	87:085cde657901	3956	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	3957
mbed_official	87:085cde657901	3958	/* Check the parameters */
mbed_official	87:085cde657901	3959	assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3960	assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
mbed_official	87:085cde657901	3961
mbed_official	87:085cde657901	3962	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	3963	tmpcr2 = htim->Instance->CR2;
mbed_official	87:085cde657901	3964
mbed_official	87:085cde657901	3965	/* Reset the TI1 selection */
mbed_official	87:085cde657901	3966	tmpcr2 &= ~TIM_CR2_TI1S;
mbed_official	87:085cde657901	3967
mbed_official	87:085cde657901	3968	/* Set the the TI1 selection */
mbed_official	87:085cde657901	3969	tmpcr2 \|= TI1_Selection;
mbed_official	87:085cde657901	3970
mbed_official	87:085cde657901	3971	/* Write to TIMxCR2 */
mbed_official	87:085cde657901	3972	htim->Instance->CR2 = tmpcr2;
mbed_official	87:085cde657901	3973
mbed_official	87:085cde657901	3974	return HAL_OK;
mbed_official	87:085cde657901	3975	}
mbed_official	87:085cde657901	3976
mbed_official	87:085cde657901	3977	/**
mbed_official	87:085cde657901	3978	* @brief Configures the TIM in Slave mode
mbed_official	226:b062af740e40	3979	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	3980	* the configuration information for TIM module..
mbed_official	87:085cde657901	3981	* @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official	87:085cde657901	3982	* contains the selected trigger (internal trigger input, filtered
mbed_official	87:085cde657901	3983	* timer input or external trigger input) and the ) and the Slave
mbed_official	87:085cde657901	3984	* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official	87:085cde657901	3985	* @retval HAL status
mbed_official	87:085cde657901	3986	*/
mbed_official	87:085cde657901	3987	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig)
mbed_official	87:085cde657901	3988	{
mbed_official	87:085cde657901	3989	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	3990	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	3991	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	3992
mbed_official	87:085cde657901	3993	/* Check the parameters */
mbed_official	87:085cde657901	3994	assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	3995	assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official	87:085cde657901	3996	assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official	87:085cde657901	3997
mbed_official	87:085cde657901	3998	__HAL_LOCK(htim);
mbed_official	87:085cde657901	3999
mbed_official	87:085cde657901	4000	htim->State = HAL_TIM_STATE_BUSY;
mbed_official	87:085cde657901	4001
mbed_official	87:085cde657901	4002	/* Get the TIMx SMCR register value */
mbed_official	87:085cde657901	4003	tmpsmcr = htim->Instance->SMCR;
mbed_official	87:085cde657901	4004
mbed_official	87:085cde657901	4005	/* Reset the Trigger Selection Bits */
mbed_official	87:085cde657901	4006	tmpsmcr &= ~TIM_SMCR_TS;
mbed_official	87:085cde657901	4007	/* Set the Input Trigger source */
mbed_official	87:085cde657901	4008	tmpsmcr \|= sSlaveConfig->InputTrigger;
mbed_official	87:085cde657901	4009
mbed_official	87:085cde657901	4010	/* Reset the slave mode Bits */
mbed_official	87:085cde657901	4011	tmpsmcr &= ~TIM_SMCR_SMS;
mbed_official	87:085cde657901	4012	/* Set the slave mode */
mbed_official	87:085cde657901	4013	tmpsmcr \|= sSlaveConfig->SlaveMode;
mbed_official	87:085cde657901	4014
mbed_official	87:085cde657901	4015	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	4016	htim->Instance->SMCR = tmpsmcr;
mbed_official	87:085cde657901	4017
mbed_official	87:085cde657901	4018	/* Configure the trigger prescaler, filter, and polarity */
mbed_official	87:085cde657901	4019	switch (sSlaveConfig->InputTrigger)
mbed_official	87:085cde657901	4020	{
mbed_official	87:085cde657901	4021	case TIM_TS_ETRF:
mbed_official	87:085cde657901	4022	{
mbed_official	87:085cde657901	4023	/* Check the parameters */
mbed_official	87:085cde657901	4024	assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4025	assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
mbed_official	87:085cde657901	4026	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	87:085cde657901	4027	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	87:085cde657901	4028	/* Configure the ETR Trigger source */
mbed_official	87:085cde657901	4029	TIM_ETR_SetConfig(htim->Instance,
mbed_official	87:085cde657901	4030	sSlaveConfig->TriggerPrescaler,
mbed_official	87:085cde657901	4031	sSlaveConfig->TriggerPolarity,
mbed_official	87:085cde657901	4032	sSlaveConfig->TriggerFilter);
mbed_official	87:085cde657901	4033	}
mbed_official	87:085cde657901	4034	break;
mbed_official	87:085cde657901	4035
mbed_official	87:085cde657901	4036	case TIM_TS_TI1F_ED:
mbed_official	87:085cde657901	4037	{
mbed_official	87:085cde657901	4038	/* Check the parameters */
mbed_official	87:085cde657901	4039	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4040	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	87:085cde657901	4041
mbed_official	87:085cde657901	4042	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	87:085cde657901	4043	tmpccer = htim->Instance->CCER;
mbed_official	87:085cde657901	4044	htim->Instance->CCER &= ~TIM_CCER_CC1E;
mbed_official	87:085cde657901	4045	tmpccmr1 = htim->Instance->CCMR1;
mbed_official	87:085cde657901	4046
mbed_official	87:085cde657901	4047	/* Set the filter */
mbed_official	87:085cde657901	4048	tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official	87:085cde657901	4049	tmpccmr1 \|= ((sSlaveConfig->TriggerFilter) << 4);
mbed_official	87:085cde657901	4050
mbed_official	87:085cde657901	4051	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	4052	htim->Instance->CCMR1 = tmpccmr1;
mbed_official	87:085cde657901	4053	htim->Instance->CCER = tmpccer;
mbed_official	87:085cde657901	4054
mbed_official	87:085cde657901	4055	}
mbed_official	87:085cde657901	4056	break;
mbed_official	87:085cde657901	4057
mbed_official	87:085cde657901	4058	case TIM_TS_TI1FP1:
mbed_official	87:085cde657901	4059	{
mbed_official	87:085cde657901	4060	/* Check the parameters */
mbed_official	87:085cde657901	4061	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4062	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	87:085cde657901	4063	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	87:085cde657901	4064
mbed_official	87:085cde657901	4065	/* Configure TI1 Filter and Polarity */
mbed_official	87:085cde657901	4066	TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	4067	sSlaveConfig->TriggerPolarity,
mbed_official	87:085cde657901	4068	sSlaveConfig->TriggerFilter);
mbed_official	87:085cde657901	4069	}
mbed_official	87:085cde657901	4070	break;
mbed_official	87:085cde657901	4071
mbed_official	87:085cde657901	4072	case TIM_TS_TI2FP2:
mbed_official	87:085cde657901	4073	{
mbed_official	87:085cde657901	4074	/* Check the parameters */
mbed_official	87:085cde657901	4075	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4076	assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official	87:085cde657901	4077	assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official	87:085cde657901	4078
mbed_official	87:085cde657901	4079	/* Configure TI2 Filter and Polarity */
mbed_official	87:085cde657901	4080	TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official	87:085cde657901	4081	sSlaveConfig->TriggerPolarity,
mbed_official	87:085cde657901	4082	sSlaveConfig->TriggerFilter);
mbed_official	87:085cde657901	4083	}
mbed_official	87:085cde657901	4084	break;
mbed_official	87:085cde657901	4085
mbed_official	87:085cde657901	4086	case TIM_TS_ITR0:
mbed_official	87:085cde657901	4087	{
mbed_official	87:085cde657901	4088	/* Check the parameter */
mbed_official	87:085cde657901	4089	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4090	}
mbed_official	87:085cde657901	4091	break;
mbed_official	87:085cde657901	4092
mbed_official	87:085cde657901	4093	case TIM_TS_ITR1:
mbed_official	87:085cde657901	4094	{
mbed_official	87:085cde657901	4095	/* Check the parameter */
mbed_official	87:085cde657901	4096	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4097	}
mbed_official	87:085cde657901	4098	break;
mbed_official	87:085cde657901	4099
mbed_official	87:085cde657901	4100	case TIM_TS_ITR2:
mbed_official	87:085cde657901	4101	{
mbed_official	87:085cde657901	4102	/* Check the parameter */
mbed_official	87:085cde657901	4103	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4104	}
mbed_official	87:085cde657901	4105	break;
mbed_official	87:085cde657901	4106
mbed_official	87:085cde657901	4107	case TIM_TS_ITR3:
mbed_official	87:085cde657901	4108	{
mbed_official	87:085cde657901	4109	/* Check the parameter */
mbed_official	87:085cde657901	4110	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4111	}
mbed_official	87:085cde657901	4112	break;
mbed_official	87:085cde657901	4113
mbed_official	87:085cde657901	4114	default:
mbed_official	87:085cde657901	4115	break;
mbed_official	87:085cde657901	4116	}
mbed_official	87:085cde657901	4117
mbed_official	87:085cde657901	4118	htim->State = HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4119
mbed_official	87:085cde657901	4120	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	4121
mbed_official	87:085cde657901	4122	return HAL_OK;
mbed_official	87:085cde657901	4123	}
mbed_official	87:085cde657901	4124
mbed_official	87:085cde657901	4125	/**
mbed_official	87:085cde657901	4126	* @brief Read the captured value from Capture Compare unit
mbed_official	226:b062af740e40	4127	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4128	* the configuration information for TIM module..
mbed_official	226:b062af740e40	4129	* @param Channel: TIM Channels to be enabled.
mbed_official	87:085cde657901	4130	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4131	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	87:085cde657901	4132	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	87:085cde657901	4133	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	87:085cde657901	4134	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	87:085cde657901	4135	* @retval Captured value
mbed_official	87:085cde657901	4136	*/
mbed_official	87:085cde657901	4137	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official	87:085cde657901	4138	{
mbed_official	87:085cde657901	4139	uint32_t tmpreg = 0;
mbed_official	87:085cde657901	4140
mbed_official	87:085cde657901	4141	__HAL_LOCK(htim);
mbed_official	87:085cde657901	4142
mbed_official	87:085cde657901	4143	switch (Channel)
mbed_official	87:085cde657901	4144	{
mbed_official	87:085cde657901	4145	case TIM_CHANNEL_1:
mbed_official	87:085cde657901	4146	{
mbed_official	87:085cde657901	4147	/* Check the parameters */
mbed_official	87:085cde657901	4148	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4149
mbed_official	87:085cde657901	4150	/* Return the capture 1 value */
mbed_official	87:085cde657901	4151	tmpreg = htim->Instance->CCR1;
mbed_official	87:085cde657901	4152
mbed_official	87:085cde657901	4153	break;
mbed_official	87:085cde657901	4154	}
mbed_official	87:085cde657901	4155	case TIM_CHANNEL_2:
mbed_official	87:085cde657901	4156	{
mbed_official	87:085cde657901	4157	/* Check the parameters */
mbed_official	87:085cde657901	4158	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4159
mbed_official	87:085cde657901	4160	/* Return the capture 2 value */
mbed_official	87:085cde657901	4161	tmpreg = htim->Instance->CCR2;
mbed_official	87:085cde657901	4162
mbed_official	87:085cde657901	4163	break;
mbed_official	87:085cde657901	4164	}
mbed_official	87:085cde657901	4165
mbed_official	87:085cde657901	4166	case TIM_CHANNEL_3:
mbed_official	87:085cde657901	4167	{
mbed_official	87:085cde657901	4168	/* Check the parameters */
mbed_official	87:085cde657901	4169	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4170
mbed_official	87:085cde657901	4171	/* Return the capture 3 value */
mbed_official	87:085cde657901	4172	tmpreg = htim->Instance->CCR3;
mbed_official	87:085cde657901	4173
mbed_official	87:085cde657901	4174	break;
mbed_official	87:085cde657901	4175	}
mbed_official	87:085cde657901	4176
mbed_official	87:085cde657901	4177	case TIM_CHANNEL_4:
mbed_official	87:085cde657901	4178	{
mbed_official	87:085cde657901	4179	/* Check the parameters */
mbed_official	87:085cde657901	4180	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official	87:085cde657901	4181
mbed_official	87:085cde657901	4182	/* Return the capture 4 value */
mbed_official	87:085cde657901	4183	tmpreg = htim->Instance->CCR4;
mbed_official	87:085cde657901	4184
mbed_official	87:085cde657901	4185	break;
mbed_official	87:085cde657901	4186	}
mbed_official	87:085cde657901	4187
mbed_official	87:085cde657901	4188	default:
mbed_official	87:085cde657901	4189	break;
mbed_official	87:085cde657901	4190	}
mbed_official	87:085cde657901	4191
mbed_official	87:085cde657901	4192	__HAL_UNLOCK(htim);
mbed_official	87:085cde657901	4193	return tmpreg;
mbed_official	87:085cde657901	4194	}
mbed_official	87:085cde657901	4195
mbed_official	87:085cde657901	4196	/**
mbed_official	87:085cde657901	4197	* @}
mbed_official	87:085cde657901	4198	*/
mbed_official	87:085cde657901	4199
mbed_official	87:085cde657901	4200	/** @defgroup TIM_Group9 TIM Callbacks functions
mbed_official	87:085cde657901	4201	* @brief TIM Callbacks functions
mbed_official	87:085cde657901	4202	*
mbed_official	87:085cde657901	4203	@verbatim
mbed_official	87:085cde657901	4204	==============================================================================
mbed_official	87:085cde657901	4205	##### TIM Callbacks functions #####
mbed_official	87:085cde657901	4206	==============================================================================
mbed_official	87:085cde657901	4207	[..]
mbed_official	87:085cde657901	4208	This section provides TIM callback functions:
mbed_official	87:085cde657901	4209	(+) Timer Period elapsed callback
mbed_official	87:085cde657901	4210	(+) Timer Output Compare callback
mbed_official	87:085cde657901	4211	(+) Timer Input capture callback
mbed_official	87:085cde657901	4212	(+) Timer Trigger callback
mbed_official	87:085cde657901	4213	(+) Timer Error callback
mbed_official	87:085cde657901	4214
mbed_official	87:085cde657901	4215	@endverbatim
mbed_official	87:085cde657901	4216	* @{
mbed_official	87:085cde657901	4217	*/
mbed_official	87:085cde657901	4218
mbed_official	87:085cde657901	4219	/**
mbed_official	87:085cde657901	4220	* @brief Period elapsed callback in non blocking mode
mbed_official	226:b062af740e40	4221	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4222	* the configuration information for TIM module.
mbed_official	87:085cde657901	4223	* @retval None
mbed_official	87:085cde657901	4224	*/
mbed_official	87:085cde657901	4225	__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4226	{
mbed_official	87:085cde657901	4227	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4228	the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
mbed_official	87:085cde657901	4229	*/
mbed_official	87:085cde657901	4230
mbed_official	87:085cde657901	4231	}
mbed_official	87:085cde657901	4232	/**
mbed_official	87:085cde657901	4233	* @brief Output Compare callback in non blocking mode
mbed_official	226:b062af740e40	4234	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4235	* the configuration information for TIM module.
mbed_official	87:085cde657901	4236	* @retval None
mbed_official	87:085cde657901	4237	*/
mbed_official	87:085cde657901	4238	__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4239	{
mbed_official	87:085cde657901	4240	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4241	the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
mbed_official	87:085cde657901	4242	*/
mbed_official	87:085cde657901	4243	}
mbed_official	87:085cde657901	4244	/**
mbed_official	87:085cde657901	4245	* @brief Input Capture callback in non blocking mode
mbed_official	226:b062af740e40	4246	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4247	* the configuration information for TIM module.
mbed_official	87:085cde657901	4248	* @retval None
mbed_official	87:085cde657901	4249	*/
mbed_official	87:085cde657901	4250	__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4251	{
mbed_official	87:085cde657901	4252	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4253	the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
mbed_official	87:085cde657901	4254	*/
mbed_official	87:085cde657901	4255	}
mbed_official	87:085cde657901	4256
mbed_official	87:085cde657901	4257	/**
mbed_official	87:085cde657901	4258	* @brief PWM Pulse finished callback in non blocking mode
mbed_official	226:b062af740e40	4259	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4260	* the configuration information for TIM module.
mbed_official	87:085cde657901	4261	* @retval None
mbed_official	87:085cde657901	4262	*/
mbed_official	87:085cde657901	4263	__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4264	{
mbed_official	87:085cde657901	4265	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4266	the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
mbed_official	87:085cde657901	4267	*/
mbed_official	87:085cde657901	4268	}
mbed_official	87:085cde657901	4269
mbed_official	87:085cde657901	4270	/**
mbed_official	87:085cde657901	4271	* @brief Hall Trigger detection callback in non blocking mode
mbed_official	226:b062af740e40	4272	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4273	* the configuration information for TIM module.
mbed_official	87:085cde657901	4274	* @retval None
mbed_official	87:085cde657901	4275	*/
mbed_official	87:085cde657901	4276	__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4277	{
mbed_official	87:085cde657901	4278	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4279	the HAL_TIM_TriggerCallback could be implemented in the user file
mbed_official	87:085cde657901	4280	*/
mbed_official	87:085cde657901	4281	}
mbed_official	87:085cde657901	4282
mbed_official	87:085cde657901	4283	/**
mbed_official	87:085cde657901	4284	* @brief Timer error callback in non blocking mode
mbed_official	226:b062af740e40	4285	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4286	* the configuration information for TIM module.
mbed_official	87:085cde657901	4287	* @retval None
mbed_official	87:085cde657901	4288	*/
mbed_official	87:085cde657901	4289	__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4290	{
mbed_official	87:085cde657901	4291	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	4292	the HAL_TIM_ErrorCallback could be implemented in the user file
mbed_official	87:085cde657901	4293	*/
mbed_official	87:085cde657901	4294	}
mbed_official	87:085cde657901	4295
mbed_official	87:085cde657901	4296	/**
mbed_official	87:085cde657901	4297	* @}
mbed_official	87:085cde657901	4298	*/
mbed_official	87:085cde657901	4299
mbed_official	87:085cde657901	4300	/** @defgroup TIM_Group10 Peripheral State functions
mbed_official	87:085cde657901	4301	* @brief Peripheral State functions
mbed_official	87:085cde657901	4302	*
mbed_official	87:085cde657901	4303	@verbatim
mbed_official	87:085cde657901	4304	==============================================================================
mbed_official	87:085cde657901	4305	##### Peripheral State functions #####
mbed_official	87:085cde657901	4306	==============================================================================
mbed_official	87:085cde657901	4307	[..]
mbed_official	226:b062af740e40	4308	This subsection permits to get in run-time the status of the peripheral
mbed_official	87:085cde657901	4309	and the data flow.
mbed_official	87:085cde657901	4310
mbed_official	87:085cde657901	4311	@endverbatim
mbed_official	87:085cde657901	4312	* @{
mbed_official	87:085cde657901	4313	*/
mbed_official	87:085cde657901	4314
mbed_official	87:085cde657901	4315	/**
mbed_official	87:085cde657901	4316	* @brief Return the TIM Base state
mbed_official	226:b062af740e40	4317	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4318	* the configuration information for TIM module.
mbed_official	87:085cde657901	4319	* @retval HAL state
mbed_official	87:085cde657901	4320	*/
mbed_official	87:085cde657901	4321	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4322	{
mbed_official	87:085cde657901	4323	return htim->State;
mbed_official	87:085cde657901	4324	}
mbed_official	87:085cde657901	4325
mbed_official	87:085cde657901	4326	/**
mbed_official	87:085cde657901	4327	* @brief Return the TIM OC state
mbed_official	226:b062af740e40	4328	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4329	* the configuration information for TIM module.
mbed_official	87:085cde657901	4330	* @retval HAL state
mbed_official	87:085cde657901	4331	*/
mbed_official	87:085cde657901	4332	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4333	{
mbed_official	87:085cde657901	4334	return htim->State;
mbed_official	87:085cde657901	4335	}
mbed_official	87:085cde657901	4336
mbed_official	87:085cde657901	4337	/**
mbed_official	87:085cde657901	4338	* @brief Return the TIM PWM state
mbed_official	226:b062af740e40	4339	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4340	* the configuration information for TIM module.
mbed_official	87:085cde657901	4341	* @retval HAL state
mbed_official	87:085cde657901	4342	*/
mbed_official	87:085cde657901	4343	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4344	{
mbed_official	87:085cde657901	4345	return htim->State;
mbed_official	87:085cde657901	4346	}
mbed_official	87:085cde657901	4347
mbed_official	87:085cde657901	4348	/**
mbed_official	87:085cde657901	4349	* @brief Return the TIM Input Capture state
mbed_official	226:b062af740e40	4350	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4351	* the configuration information for TIM module.
mbed_official	87:085cde657901	4352	* @retval HAL state
mbed_official	87:085cde657901	4353	*/
mbed_official	87:085cde657901	4354	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4355	{
mbed_official	87:085cde657901	4356	return htim->State;
mbed_official	87:085cde657901	4357	}
mbed_official	87:085cde657901	4358
mbed_official	87:085cde657901	4359	/**
mbed_official	87:085cde657901	4360	* @brief Return the TIM One Pulse Mode state
mbed_official	226:b062af740e40	4361	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4362	* the configuration information for TIM module.
mbed_official	87:085cde657901	4363	* @retval HAL state
mbed_official	87:085cde657901	4364	*/
mbed_official	87:085cde657901	4365	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4366	{
mbed_official	87:085cde657901	4367	return htim->State;
mbed_official	87:085cde657901	4368	}
mbed_official	87:085cde657901	4369
mbed_official	87:085cde657901	4370	/**
mbed_official	87:085cde657901	4371	* @brief Return the TIM Encoder Mode state
mbed_official	226:b062af740e40	4372	* @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4373	* the configuration information for TIM module.
mbed_official	87:085cde657901	4374	* @retval HAL state
mbed_official	87:085cde657901	4375	*/
mbed_official	87:085cde657901	4376	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
mbed_official	87:085cde657901	4377	{
mbed_official	87:085cde657901	4378	return htim->State;
mbed_official	87:085cde657901	4379	}
mbed_official	87:085cde657901	4380
mbed_official	87:085cde657901	4381	/**
mbed_official	87:085cde657901	4382	* @}
mbed_official	87:085cde657901	4383	*/
mbed_official	87:085cde657901	4384
mbed_official	87:085cde657901	4385	/**
mbed_official	87:085cde657901	4386	* @brief TIM DMA error callback
mbed_official	226:b062af740e40	4387	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4388	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	4389	* @retval None
mbed_official	87:085cde657901	4390	*/
mbed_official	87:085cde657901	4391	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4392	{
mbed_official	87:085cde657901	4393	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4394
mbed_official	87:085cde657901	4395	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4396
mbed_official	87:085cde657901	4397	HAL_TIM_ErrorCallback(htim);
mbed_official	87:085cde657901	4398	}
mbed_official	87:085cde657901	4399
mbed_official	87:085cde657901	4400	/**
mbed_official	87:085cde657901	4401	* @brief TIM DMA Delay Pulse complete callback.
mbed_official	226:b062af740e40	4402	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4403	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	4404	* @retval None
mbed_official	87:085cde657901	4405	*/
mbed_official	87:085cde657901	4406	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4407	{
mbed_official	87:085cde657901	4408	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4409
mbed_official	87:085cde657901	4410	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4411
mbed_official	87:085cde657901	4412	HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official	87:085cde657901	4413	}
mbed_official	87:085cde657901	4414	/**
mbed_official	87:085cde657901	4415	* @brief TIM DMA Capture complete callback.
mbed_official	226:b062af740e40	4416	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4417	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	4418	* @retval None
mbed_official	87:085cde657901	4419	*/
mbed_official	87:085cde657901	4420	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4421	{
mbed_official	87:085cde657901	4422	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4423
mbed_official	87:085cde657901	4424	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4425
mbed_official	87:085cde657901	4426	HAL_TIM_IC_CaptureCallback(htim);
mbed_official	87:085cde657901	4427
mbed_official	87:085cde657901	4428	}
mbed_official	87:085cde657901	4429
mbed_official	87:085cde657901	4430	/**
mbed_official	87:085cde657901	4431	* @brief TIM DMA Period Elapse complete callback.
mbed_official	226:b062af740e40	4432	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4433	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	4434	* @retval None
mbed_official	87:085cde657901	4435	*/
mbed_official	87:085cde657901	4436	static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4437	{
mbed_official	87:085cde657901	4438	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4439
mbed_official	87:085cde657901	4440	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4441
mbed_official	87:085cde657901	4442	HAL_TIM_PeriodElapsedCallback(htim);
mbed_official	87:085cde657901	4443	}
mbed_official	87:085cde657901	4444
mbed_official	87:085cde657901	4445	/**
mbed_official	87:085cde657901	4446	* @brief TIM DMA Trigger callback.
mbed_official	226:b062af740e40	4447	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	4448	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	4449	* @retval None
mbed_official	87:085cde657901	4450	*/
mbed_official	87:085cde657901	4451	static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	4452	{
mbed_official	87:085cde657901	4453	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	4454
mbed_official	87:085cde657901	4455	htim->State= HAL_TIM_STATE_READY;
mbed_official	87:085cde657901	4456
mbed_official	87:085cde657901	4457	HAL_TIM_TriggerCallback(htim);
mbed_official	87:085cde657901	4458	}
mbed_official	87:085cde657901	4459
mbed_official	87:085cde657901	4460	/**
mbed_official	87:085cde657901	4461	* @brief Time Base configuration
mbed_official	87:085cde657901	4462	* @param TIMx: TIM periheral
mbed_official	87:085cde657901	4463	* @retval None
mbed_official	87:085cde657901	4464	*/
mbed_official	87:085cde657901	4465	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure)
mbed_official	87:085cde657901	4466	{
mbed_official	87:085cde657901	4467	uint32_t tmpcr1 = 0;
mbed_official	87:085cde657901	4468	tmpcr1 = TIMx->CR1;
mbed_official	87:085cde657901	4469
mbed_official	87:085cde657901	4470	/* Set TIM Time Base Unit parameters ---------------------------------------*/
mbed_official	87:085cde657901	4471	if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4472	{
mbed_official	87:085cde657901	4473	/* Select the Counter Mode */
mbed_official	87:085cde657901	4474	tmpcr1 &= ~(TIM_CR1_DIR \| TIM_CR1_CMS);
mbed_official	87:085cde657901	4475	tmpcr1 \|= Structure->CounterMode;
mbed_official	87:085cde657901	4476	}
mbed_official	87:085cde657901	4477
mbed_official	87:085cde657901	4478	if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4479	{
mbed_official	87:085cde657901	4480	/* Set the clock division */
mbed_official	87:085cde657901	4481	tmpcr1 &= ~TIM_CR1_CKD;
mbed_official	87:085cde657901	4482	tmpcr1 \|= (uint32_t)Structure->ClockDivision;
mbed_official	87:085cde657901	4483	}
mbed_official	87:085cde657901	4484
mbed_official	87:085cde657901	4485	TIMx->CR1 = tmpcr1;
mbed_official	87:085cde657901	4486
mbed_official	87:085cde657901	4487	/* Set the Autoreload value */
mbed_official	87:085cde657901	4488	TIMx->ARR = (uint32_t)Structure->Period ;
mbed_official	87:085cde657901	4489
mbed_official	87:085cde657901	4490	/* Set the Prescaler value */
mbed_official	87:085cde657901	4491	TIMx->PSC = (uint32_t)Structure->Prescaler;
mbed_official	87:085cde657901	4492
mbed_official	87:085cde657901	4493	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4494	{
mbed_official	87:085cde657901	4495	/* Set the Repetition Counter value */
mbed_official	87:085cde657901	4496	TIMx->RCR = Structure->RepetitionCounter;
mbed_official	87:085cde657901	4497	}
mbed_official	87:085cde657901	4498
mbed_official	87:085cde657901	4499	/* Generate an update event to reload the Prescaler
mbed_official	87:085cde657901	4500	and the repetition counter(only for TIM1 and TIM8) value immediatly */
mbed_official	87:085cde657901	4501	TIMx->EGR = TIM_EGR_UG;
mbed_official	87:085cde657901	4502	}
mbed_official	87:085cde657901	4503
mbed_official	87:085cde657901	4504	/**
mbed_official	87:085cde657901	4505	* @brief Time Ouput Compare 1 configuration
mbed_official	87:085cde657901	4506	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4507	* @param OC_Config: The ouput configuration structure
mbed_official	87:085cde657901	4508	* @retval None
mbed_official	87:085cde657901	4509	*/
mbed_official	87:085cde657901	4510	static void TIM_OC1_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	87:085cde657901	4511	{
mbed_official	87:085cde657901	4512	uint32_t tmpccmrx = 0;
mbed_official	87:085cde657901	4513	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4514	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	4515
mbed_official	87:085cde657901	4516	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	87:085cde657901	4517	TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official	87:085cde657901	4518
mbed_official	87:085cde657901	4519	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	4520	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4521	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	4522	tmpcr2 = TIMx->CR2;
mbed_official	87:085cde657901	4523
mbed_official	87:085cde657901	4524	/* Get the TIMx CCMR1 register value */
mbed_official	87:085cde657901	4525	tmpccmrx = TIMx->CCMR1;
mbed_official	87:085cde657901	4526
mbed_official	87:085cde657901	4527	/* Reset the Output Compare Mode Bits */
mbed_official	87:085cde657901	4528	tmpccmrx &= ~TIM_CCMR1_OC1M;
mbed_official	87:085cde657901	4529	tmpccmrx &= ~TIM_CCMR1_CC1S;
mbed_official	87:085cde657901	4530	/* Select the Output Compare Mode */
mbed_official	87:085cde657901	4531	tmpccmrx \|= OC_Config->OCMode;
mbed_official	87:085cde657901	4532
mbed_official	87:085cde657901	4533	/* Reset the Output Polarity level */
mbed_official	87:085cde657901	4534	tmpccer &= ~TIM_CCER_CC1P;
mbed_official	87:085cde657901	4535	/* Set the Output Compare Polarity */
mbed_official	87:085cde657901	4536	tmpccer \|= OC_Config->OCPolarity;
mbed_official	87:085cde657901	4537
mbed_official	87:085cde657901	4538
mbed_official	87:085cde657901	4539	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4540	{
mbed_official	87:085cde657901	4541	/* Reset the Output N Polarity level */
mbed_official	87:085cde657901	4542	tmpccer &= ~TIM_CCER_CC1NP;
mbed_official	87:085cde657901	4543	/* Set the Output N Polarity */
mbed_official	87:085cde657901	4544	tmpccer \|= OC_Config->OCNPolarity;
mbed_official	87:085cde657901	4545	/* Reset the Output N State */
mbed_official	87:085cde657901	4546	tmpccer &= ~TIM_CCER_CC1NE;
mbed_official	87:085cde657901	4547
mbed_official	87:085cde657901	4548	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	87:085cde657901	4549	tmpcr2 &= ~TIM_CR2_OIS1;
mbed_official	87:085cde657901	4550	tmpcr2 &= ~TIM_CR2_OIS1N;
mbed_official	87:085cde657901	4551	/* Set the Output Idle state */
mbed_official	87:085cde657901	4552	tmpcr2 \|= OC_Config->OCIdleState;
mbed_official	87:085cde657901	4553	/* Set the Output N Idle state */
mbed_official	87:085cde657901	4554	tmpcr2 \|= OC_Config->OCNIdleState;
mbed_official	87:085cde657901	4555	}
mbed_official	87:085cde657901	4556	/* Write to TIMx CR2 */
mbed_official	87:085cde657901	4557	TIMx->CR2 = tmpcr2;
mbed_official	87:085cde657901	4558
mbed_official	87:085cde657901	4559	/* Write to TIMx CCMR1 */
mbed_official	87:085cde657901	4560	TIMx->CCMR1 = tmpccmrx;
mbed_official	87:085cde657901	4561
mbed_official	87:085cde657901	4562	/* Set the Capture Compare Register value */
mbed_official	87:085cde657901	4563	TIMx->CCR1 = OC_Config->Pulse;
mbed_official	87:085cde657901	4564
mbed_official	87:085cde657901	4565	/* Write to TIMx CCER */
mbed_official	87:085cde657901	4566	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4567	}
mbed_official	87:085cde657901	4568
mbed_official	87:085cde657901	4569	/**
mbed_official	87:085cde657901	4570	* @brief Time Ouput Compare 2 configuration
mbed_official	87:085cde657901	4571	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4572	* @param OC_Config: The ouput configuration structure
mbed_official	87:085cde657901	4573	* @retval None
mbed_official	87:085cde657901	4574	*/
mbed_official	87:085cde657901	4575	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	87:085cde657901	4576	{
mbed_official	87:085cde657901	4577	uint32_t tmpccmrx = 0;
mbed_official	87:085cde657901	4578	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4579	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	4580
mbed_official	87:085cde657901	4581	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	87:085cde657901	4582	TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official	87:085cde657901	4583
mbed_official	87:085cde657901	4584	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	4585	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4586	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	4587	tmpcr2 = TIMx->CR2;
mbed_official	87:085cde657901	4588
mbed_official	87:085cde657901	4589	/* Get the TIMx CCMR1 register value */
mbed_official	87:085cde657901	4590	tmpccmrx = TIMx->CCMR1;
mbed_official	87:085cde657901	4591
mbed_official	87:085cde657901	4592	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	87:085cde657901	4593	tmpccmrx &= ~TIM_CCMR1_OC2M;
mbed_official	87:085cde657901	4594	tmpccmrx &= ~TIM_CCMR1_CC2S;
mbed_official	87:085cde657901	4595
mbed_official	87:085cde657901	4596	/* Select the Output Compare Mode */
mbed_official	87:085cde657901	4597	tmpccmrx \|= (OC_Config->OCMode << 8);
mbed_official	87:085cde657901	4598
mbed_official	87:085cde657901	4599	/* Reset the Output Polarity level */
mbed_official	87:085cde657901	4600	tmpccer &= ~TIM_CCER_CC2P;
mbed_official	87:085cde657901	4601	/* Set the Output Compare Polarity */
mbed_official	87:085cde657901	4602	tmpccer \|= (OC_Config->OCPolarity << 4);
mbed_official	87:085cde657901	4603
mbed_official	87:085cde657901	4604	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4605	{
mbed_official	87:085cde657901	4606	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official	87:085cde657901	4607	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official	87:085cde657901	4608	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	87:085cde657901	4609
mbed_official	87:085cde657901	4610	/* Reset the Output N Polarity level */
mbed_official	87:085cde657901	4611	tmpccer &= ~TIM_CCER_CC2NP;
mbed_official	87:085cde657901	4612	/* Set the Output N Polarity */
mbed_official	87:085cde657901	4613	tmpccer \|= (OC_Config->OCNPolarity << 4);
mbed_official	87:085cde657901	4614	/* Reset the Output N State */
mbed_official	87:085cde657901	4615	tmpccer &= ~TIM_CCER_CC2NE;
mbed_official	87:085cde657901	4616
mbed_official	87:085cde657901	4617	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	87:085cde657901	4618	tmpcr2 &= ~TIM_CR2_OIS2;
mbed_official	87:085cde657901	4619	tmpcr2 &= ~TIM_CR2_OIS2N;
mbed_official	87:085cde657901	4620	/* Set the Output Idle state */
mbed_official	87:085cde657901	4621	tmpcr2 \|= (OC_Config->OCIdleState << 2);
mbed_official	87:085cde657901	4622	/* Set the Output N Idle state */
mbed_official	87:085cde657901	4623	tmpcr2 \|= (OC_Config->OCNIdleState << 2);
mbed_official	87:085cde657901	4624	}
mbed_official	87:085cde657901	4625	/* Write to TIMx CR2 */
mbed_official	87:085cde657901	4626	TIMx->CR2 = tmpcr2;
mbed_official	87:085cde657901	4627
mbed_official	87:085cde657901	4628	/* Write to TIMx CCMR1 */
mbed_official	87:085cde657901	4629	TIMx->CCMR1 = tmpccmrx;
mbed_official	87:085cde657901	4630
mbed_official	87:085cde657901	4631	/* Set the Capture Compare Register value */
mbed_official	87:085cde657901	4632	TIMx->CCR2 = OC_Config->Pulse;
mbed_official	87:085cde657901	4633
mbed_official	87:085cde657901	4634	/* Write to TIMx CCER */
mbed_official	87:085cde657901	4635	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4636	}
mbed_official	87:085cde657901	4637
mbed_official	87:085cde657901	4638	/**
mbed_official	87:085cde657901	4639	* @brief Time Ouput Compare 3 configuration
mbed_official	87:085cde657901	4640	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4641	* @param OC_Config: The ouput configuration structure
mbed_official	87:085cde657901	4642	* @retval None
mbed_official	87:085cde657901	4643	*/
mbed_official	87:085cde657901	4644	static void TIM_OC3_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	87:085cde657901	4645	{
mbed_official	87:085cde657901	4646	uint32_t tmpccmrx = 0;
mbed_official	87:085cde657901	4647	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4648	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	4649
mbed_official	87:085cde657901	4650	/* Disable the Channel 3: Reset the CC2E Bit */
mbed_official	87:085cde657901	4651	TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official	87:085cde657901	4652
mbed_official	87:085cde657901	4653	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	4654	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4655	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	4656	tmpcr2 = TIMx->CR2;
mbed_official	87:085cde657901	4657
mbed_official	87:085cde657901	4658	/* Get the TIMx CCMR2 register value */
mbed_official	87:085cde657901	4659	tmpccmrx = TIMx->CCMR2;
mbed_official	87:085cde657901	4660
mbed_official	87:085cde657901	4661	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	87:085cde657901	4662	tmpccmrx &= ~TIM_CCMR2_OC3M;
mbed_official	87:085cde657901	4663	tmpccmrx &= ~TIM_CCMR2_CC3S;
mbed_official	87:085cde657901	4664	/* Select the Output Compare Mode */
mbed_official	87:085cde657901	4665	tmpccmrx \|= OC_Config->OCMode;
mbed_official	87:085cde657901	4666
mbed_official	87:085cde657901	4667	/* Reset the Output Polarity level */
mbed_official	87:085cde657901	4668	tmpccer &= ~TIM_CCER_CC3P;
mbed_official	87:085cde657901	4669	/* Set the Output Compare Polarity */
mbed_official	87:085cde657901	4670	tmpccer \|= (OC_Config->OCPolarity << 8);
mbed_official	87:085cde657901	4671
mbed_official	87:085cde657901	4672	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4673	{
mbed_official	87:085cde657901	4674	assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official	87:085cde657901	4675	assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official	87:085cde657901	4676	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	87:085cde657901	4677
mbed_official	87:085cde657901	4678	/* Reset the Output N Polarity level */
mbed_official	87:085cde657901	4679	tmpccer &= ~TIM_CCER_CC3NP;
mbed_official	87:085cde657901	4680	/* Set the Output N Polarity */
mbed_official	87:085cde657901	4681	tmpccer \|= (OC_Config->OCNPolarity << 8);
mbed_official	87:085cde657901	4682	/* Reset the Output N State */
mbed_official	87:085cde657901	4683	tmpccer &= ~TIM_CCER_CC3NE;
mbed_official	87:085cde657901	4684
mbed_official	87:085cde657901	4685	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	87:085cde657901	4686	tmpcr2 &= ~TIM_CR2_OIS3;
mbed_official	87:085cde657901	4687	tmpcr2 &= ~TIM_CR2_OIS3N;
mbed_official	87:085cde657901	4688	/* Set the Output Idle state */
mbed_official	87:085cde657901	4689	tmpcr2 \|= (OC_Config->OCIdleState << 4);
mbed_official	87:085cde657901	4690	/* Set the Output N Idle state */
mbed_official	87:085cde657901	4691	tmpcr2 \|= (OC_Config->OCNIdleState << 4);
mbed_official	87:085cde657901	4692	}
mbed_official	87:085cde657901	4693	/* Write to TIMx CR2 */
mbed_official	87:085cde657901	4694	TIMx->CR2 = tmpcr2;
mbed_official	87:085cde657901	4695
mbed_official	87:085cde657901	4696	/* Write to TIMx CCMR2 */
mbed_official	87:085cde657901	4697	TIMx->CCMR2 = tmpccmrx;
mbed_official	87:085cde657901	4698
mbed_official	87:085cde657901	4699	/* Set the Capture Compare Register value */
mbed_official	87:085cde657901	4700	TIMx->CCR3 = OC_Config->Pulse;
mbed_official	87:085cde657901	4701
mbed_official	87:085cde657901	4702	/* Write to TIMx CCER */
mbed_official	87:085cde657901	4703	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4704	}
mbed_official	87:085cde657901	4705
mbed_official	87:085cde657901	4706	/**
mbed_official	87:085cde657901	4707	* @brief Time Ouput Compare 4 configuration
mbed_official	87:085cde657901	4708	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4709	* @param OC_Config: The ouput configuration structure
mbed_official	87:085cde657901	4710	* @retval None
mbed_official	87:085cde657901	4711	*/
mbed_official	87:085cde657901	4712	static void TIM_OC4_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config)
mbed_official	87:085cde657901	4713	{
mbed_official	87:085cde657901	4714	uint32_t tmpccmrx = 0;
mbed_official	87:085cde657901	4715	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4716	uint32_t tmpcr2 = 0;
mbed_official	87:085cde657901	4717
mbed_official	87:085cde657901	4718	/* Disable the Channel 4: Reset the CC4E Bit */
mbed_official	87:085cde657901	4719	TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official	87:085cde657901	4720
mbed_official	87:085cde657901	4721	/* Get the TIMx CCER register value */
mbed_official	87:085cde657901	4722	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4723	/* Get the TIMx CR2 register value */
mbed_official	87:085cde657901	4724	tmpcr2 = TIMx->CR2;
mbed_official	87:085cde657901	4725
mbed_official	87:085cde657901	4726	/* Get the TIMx CCMR2 register value */
mbed_official	87:085cde657901	4727	tmpccmrx = TIMx->CCMR2;
mbed_official	87:085cde657901	4728
mbed_official	87:085cde657901	4729	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	87:085cde657901	4730	tmpccmrx &= ~TIM_CCMR2_OC4M;
mbed_official	87:085cde657901	4731	tmpccmrx &= ~TIM_CCMR2_CC4S;
mbed_official	87:085cde657901	4732
mbed_official	87:085cde657901	4733	/* Select the Output Compare Mode */
mbed_official	87:085cde657901	4734	tmpccmrx \|= (OC_Config->OCMode << 8);
mbed_official	87:085cde657901	4735
mbed_official	87:085cde657901	4736	/* Reset the Output Polarity level */
mbed_official	87:085cde657901	4737	tmpccer &= ~TIM_CCER_CC4P;
mbed_official	87:085cde657901	4738	/* Set the Output Compare Polarity */
mbed_official	87:085cde657901	4739	tmpccer \|= (OC_Config->OCPolarity << 12);
mbed_official	87:085cde657901	4740
mbed_official	87:085cde657901	4741	/if((TIMx == TIM1) \|\| (TIMx == TIM8))/
mbed_official	87:085cde657901	4742	if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4743	{
mbed_official	87:085cde657901	4744	assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official	87:085cde657901	4745	/* Reset the Output Compare IDLE State */
mbed_official	87:085cde657901	4746	tmpcr2 &= ~TIM_CR2_OIS4;
mbed_official	87:085cde657901	4747	/* Set the Output Idle state */
mbed_official	87:085cde657901	4748	tmpcr2 \|= (OC_Config->OCIdleState << 6);
mbed_official	87:085cde657901	4749	}
mbed_official	87:085cde657901	4750	/* Write to TIMx CR2 */
mbed_official	87:085cde657901	4751	TIMx->CR2 = tmpcr2;
mbed_official	87:085cde657901	4752
mbed_official	87:085cde657901	4753	/* Write to TIMx CCMR2 */
mbed_official	87:085cde657901	4754	TIMx->CCMR2 = tmpccmrx;
mbed_official	87:085cde657901	4755
mbed_official	87:085cde657901	4756	/* Set the Capture Compare Register value */
mbed_official	87:085cde657901	4757	TIMx->CCR4 = OC_Config->Pulse;
mbed_official	87:085cde657901	4758
mbed_official	87:085cde657901	4759	/* Write to TIMx CCER */
mbed_official	87:085cde657901	4760	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4761	}
mbed_official	87:085cde657901	4762
mbed_official	87:085cde657901	4763	/**
mbed_official	87:085cde657901	4764	* @brief Configure the TI1 as Input.
mbed_official	87:085cde657901	4765	* @param TIMx to select the TIM peripheral.
mbed_official	87:085cde657901	4766	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4767	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4768	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4769	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4770	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4771	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	87:085cde657901	4772	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4773	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
mbed_official	87:085cde657901	4774	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
mbed_official	87:085cde657901	4775	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
mbed_official	87:085cde657901	4776	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4777	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4778	* @retval None
mbed_official	87:085cde657901	4779	*/
mbed_official	87:085cde657901	4780	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	4781	uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4782	{
mbed_official	87:085cde657901	4783	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	4784	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4785
mbed_official	87:085cde657901	4786	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	87:085cde657901	4787	TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official	87:085cde657901	4788	tmpccmr1 = TIMx->CCMR1;
mbed_official	87:085cde657901	4789	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4790
mbed_official	87:085cde657901	4791	/* Select the Input */
mbed_official	87:085cde657901	4792	if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
mbed_official	87:085cde657901	4793	{
mbed_official	87:085cde657901	4794	tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official	87:085cde657901	4795	tmpccmr1 \|= TIM_ICSelection;
mbed_official	87:085cde657901	4796	}
mbed_official	87:085cde657901	4797	else
mbed_official	87:085cde657901	4798	{
mbed_official	87:085cde657901	4799	tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official	87:085cde657901	4800	tmpccmr1 \|= TIM_CCMR1_CC1S_0;
mbed_official	87:085cde657901	4801	}
mbed_official	87:085cde657901	4802
mbed_official	87:085cde657901	4803	/* Set the filter */
mbed_official	87:085cde657901	4804	tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official	87:085cde657901	4805	tmpccmr1 \|= (TIM_ICFilter << 4);
mbed_official	87:085cde657901	4806
mbed_official	87:085cde657901	4807	/* Select the Polarity and set the CC1E Bit */
mbed_official	87:085cde657901	4808	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
mbed_official	87:085cde657901	4809	tmpccer \|= TIM_ICPolarity;
mbed_official	87:085cde657901	4810
mbed_official	87:085cde657901	4811	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	4812	TIMx->CCMR1 = tmpccmr1;
mbed_official	87:085cde657901	4813	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4814	}
mbed_official	87:085cde657901	4815
mbed_official	87:085cde657901	4816	/**
mbed_official	87:085cde657901	4817	* @brief Configure the Polarity and Filter for TI1.
mbed_official	87:085cde657901	4818	* @param TIMx to select the TIM peripheral.
mbed_official	87:085cde657901	4819	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4820	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4821	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4822	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4823	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4824	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4825	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4826	* @retval None
mbed_official	87:085cde657901	4827	*/
mbed_official	87:085cde657901	4828	static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4829	{
mbed_official	87:085cde657901	4830	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	4831	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4832
mbed_official	87:085cde657901	4833	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	87:085cde657901	4834	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4835	TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official	87:085cde657901	4836	tmpccmr1 = TIMx->CCMR1;
mbed_official	87:085cde657901	4837
mbed_official	87:085cde657901	4838	/* Set the filter */
mbed_official	87:085cde657901	4839	tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official	87:085cde657901	4840	tmpccmr1 \|= (TIM_ICFilter << 4);
mbed_official	87:085cde657901	4841
mbed_official	87:085cde657901	4842	/* Select the Polarity and set the CC1E Bit */
mbed_official	87:085cde657901	4843	tmpccer &= ~(TIM_CCER_CC1P \| TIM_CCER_CC1NP);
mbed_official	87:085cde657901	4844	tmpccer \|= TIM_ICPolarity;
mbed_official	87:085cde657901	4845
mbed_official	87:085cde657901	4846	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	4847	TIMx->CCMR1 = tmpccmr1;
mbed_official	87:085cde657901	4848	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4849	}
mbed_official	87:085cde657901	4850
mbed_official	87:085cde657901	4851	/**
mbed_official	87:085cde657901	4852	* @brief Configure the TI2 as Input.
mbed_official	87:085cde657901	4853	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4854	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4855	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4856	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4857	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4858	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4859	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	87:085cde657901	4860	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4861	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
mbed_official	87:085cde657901	4862	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
mbed_official	87:085cde657901	4863	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
mbed_official	87:085cde657901	4864	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4865	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4866	* @retval None
mbed_official	87:085cde657901	4867	*/
mbed_official	87:085cde657901	4868	static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	4869	uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4870	{
mbed_official	87:085cde657901	4871	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	4872	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4873
mbed_official	87:085cde657901	4874	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	87:085cde657901	4875	TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official	87:085cde657901	4876	tmpccmr1 = TIMx->CCMR1;
mbed_official	87:085cde657901	4877	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4878
mbed_official	87:085cde657901	4879	/* Select the Input */
mbed_official	87:085cde657901	4880	tmpccmr1 &= ~TIM_CCMR1_CC2S;
mbed_official	87:085cde657901	4881	tmpccmr1 \|= (TIM_ICSelection << 8);
mbed_official	87:085cde657901	4882
mbed_official	87:085cde657901	4883	/* Set the filter */
mbed_official	87:085cde657901	4884	tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official	87:085cde657901	4885	tmpccmr1 \|= (TIM_ICFilter << 12);
mbed_official	87:085cde657901	4886
mbed_official	87:085cde657901	4887	/* Select the Polarity and set the CC2E Bit */
mbed_official	87:085cde657901	4888	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
mbed_official	87:085cde657901	4889	tmpccer \|= (TIM_ICPolarity << 4);
mbed_official	87:085cde657901	4890
mbed_official	87:085cde657901	4891	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	4892	TIMx->CCMR1 = tmpccmr1 ;
mbed_official	87:085cde657901	4893	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4894	}
mbed_official	87:085cde657901	4895
mbed_official	87:085cde657901	4896	/**
mbed_official	87:085cde657901	4897	* @brief Configure the Polarity and Filter for TI2.
mbed_official	87:085cde657901	4898	* @param TIMx to select the TIM peripheral.
mbed_official	87:085cde657901	4899	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4900	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4901	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4902	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4903	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4904	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4905	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4906	* @retval None
mbed_official	87:085cde657901	4907	*/
mbed_official	87:085cde657901	4908	static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4909	{
mbed_official	87:085cde657901	4910	uint32_t tmpccmr1 = 0;
mbed_official	87:085cde657901	4911	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4912
mbed_official	87:085cde657901	4913	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	87:085cde657901	4914	TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official	87:085cde657901	4915	tmpccmr1 = TIMx->CCMR1;
mbed_official	87:085cde657901	4916	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4917
mbed_official	87:085cde657901	4918	/* Set the filter */
mbed_official	87:085cde657901	4919	tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official	87:085cde657901	4920	tmpccmr1 \|= (TIM_ICFilter << 12);
mbed_official	87:085cde657901	4921
mbed_official	87:085cde657901	4922	/* Select the Polarity and set the CC2E Bit */
mbed_official	87:085cde657901	4923	tmpccer &= ~(TIM_CCER_CC2P \| TIM_CCER_CC2NP);
mbed_official	87:085cde657901	4924	tmpccer \|= (TIM_ICPolarity << 4);
mbed_official	87:085cde657901	4925
mbed_official	87:085cde657901	4926	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	87:085cde657901	4927	TIMx->CCMR1 = tmpccmr1 ;
mbed_official	87:085cde657901	4928	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4929	}
mbed_official	87:085cde657901	4930
mbed_official	87:085cde657901	4931	/**
mbed_official	87:085cde657901	4932	* @brief Configure the TI3 as Input.
mbed_official	87:085cde657901	4933	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4934	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4935	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4936	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4937	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4938	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4939	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	87:085cde657901	4940	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4941	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
mbed_official	87:085cde657901	4942	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
mbed_official	87:085cde657901	4943	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
mbed_official	87:085cde657901	4944	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4945	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4946	* @retval None
mbed_official	87:085cde657901	4947	*/
mbed_official	87:085cde657901	4948	static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	4949	uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4950	{
mbed_official	87:085cde657901	4951	uint32_t tmpccmr2 = 0;
mbed_official	87:085cde657901	4952	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4953
mbed_official	87:085cde657901	4954	/* Disable the Channel 3: Reset the CC3E Bit */
mbed_official	87:085cde657901	4955	TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official	87:085cde657901	4956	tmpccmr2 = TIMx->CCMR2;
mbed_official	87:085cde657901	4957	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	4958
mbed_official	87:085cde657901	4959	/* Select the Input */
mbed_official	87:085cde657901	4960	tmpccmr2 &= ~TIM_CCMR2_CC3S;
mbed_official	87:085cde657901	4961	tmpccmr2 \|= TIM_ICSelection;
mbed_official	87:085cde657901	4962
mbed_official	87:085cde657901	4963	/* Set the filter */
mbed_official	87:085cde657901	4964	tmpccmr2 &= ~TIM_CCMR2_IC3F;
mbed_official	87:085cde657901	4965	tmpccmr2 \|= (TIM_ICFilter << 4);
mbed_official	87:085cde657901	4966
mbed_official	87:085cde657901	4967	/* Select the Polarity and set the CC3E Bit */
mbed_official	87:085cde657901	4968	tmpccer &= ~(TIM_CCER_CC3P \| TIM_CCER_CC3NP);
mbed_official	87:085cde657901	4969	tmpccer \|= (TIM_ICPolarity << 8);
mbed_official	87:085cde657901	4970
mbed_official	87:085cde657901	4971	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	87:085cde657901	4972	TIMx->CCMR2 = tmpccmr2;
mbed_official	87:085cde657901	4973	TIMx->CCER = tmpccer;
mbed_official	87:085cde657901	4974	}
mbed_official	87:085cde657901	4975
mbed_official	87:085cde657901	4976	/**
mbed_official	87:085cde657901	4977	* @brief Configure the TI4 as Input.
mbed_official	87:085cde657901	4978	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	4979	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	87:085cde657901	4980	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4981	* @arg TIM_ICPolarity_Rising
mbed_official	87:085cde657901	4982	* @arg TIM_ICPolarity_Falling
mbed_official	87:085cde657901	4983	* @arg TIM_ICPolarity_BothEdge
mbed_official	87:085cde657901	4984	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	87:085cde657901	4985	* This parameter can be one of the following values:
mbed_official	87:085cde657901	4986	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
mbed_official	87:085cde657901	4987	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
mbed_official	87:085cde657901	4988	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
mbed_official	87:085cde657901	4989	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	87:085cde657901	4990	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	87:085cde657901	4991	* @retval None
mbed_official	87:085cde657901	4992	*/
mbed_official	87:085cde657901	4993	static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official	87:085cde657901	4994	uint32_t TIM_ICFilter)
mbed_official	87:085cde657901	4995	{
mbed_official	87:085cde657901	4996	uint32_t tmpccmr2 = 0;
mbed_official	87:085cde657901	4997	uint32_t tmpccer = 0;
mbed_official	87:085cde657901	4998
mbed_official	87:085cde657901	4999	/* Disable the Channel 4: Reset the CC4E Bit */
mbed_official	87:085cde657901	5000	TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official	87:085cde657901	5001	tmpccmr2 = TIMx->CCMR2;
mbed_official	87:085cde657901	5002	tmpccer = TIMx->CCER;
mbed_official	87:085cde657901	5003
mbed_official	87:085cde657901	5004	/* Select the Input */
mbed_official	87:085cde657901	5005	tmpccmr2 &= ~TIM_CCMR2_CC4S;
mbed_official	87:085cde657901	5006	tmpccmr2 \|= (TIM_ICSelection << 8);
mbed_official	87:085cde657901	5007
mbed_official	87:085cde657901	5008	/* Set the filter */
mbed_official	87:085cde657901	5009	tmpccmr2 &= ~TIM_CCMR2_IC4F;
mbed_official	87:085cde657901	5010	tmpccmr2 \|= (TIM_ICFilter << 12);
mbed_official	87:085cde657901	5011
mbed_official	87:085cde657901	5012	/* Select the Polarity and set the CC4E Bit */
mbed_official	87:085cde657901	5013	tmpccer &= ~(TIM_CCER_CC4P \| TIM_CCER_CC4NP);
mbed_official	87:085cde657901	5014	tmpccer \|= (TIM_ICPolarity << 12);
mbed_official	87:085cde657901	5015
mbed_official	87:085cde657901	5016	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	87:085cde657901	5017	TIMx->CCMR2 = tmpccmr2;
mbed_official	87:085cde657901	5018	TIMx->CCER = tmpccer ;
mbed_official	87:085cde657901	5019	}
mbed_official	87:085cde657901	5020
mbed_official	87:085cde657901	5021	/**
mbed_official	87:085cde657901	5022	* @brief Selects the Input Trigger source
mbed_official	87:085cde657901	5023	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	5024	* @param InputTriggerSource: The Input Trigger source.
mbed_official	87:085cde657901	5025	* This parameter can be one of the following values:
mbed_official	87:085cde657901	5026	* @arg TIM_TS_ITR0: Internal Trigger 0
mbed_official	87:085cde657901	5027	* @arg TIM_TS_ITR1: Internal Trigger 1
mbed_official	87:085cde657901	5028	* @arg TIM_TS_ITR2: Internal Trigger 2
mbed_official	87:085cde657901	5029	* @arg TIM_TS_ITR3: Internal Trigger 3
mbed_official	87:085cde657901	5030	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
mbed_official	87:085cde657901	5031	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
mbed_official	87:085cde657901	5032	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
mbed_official	87:085cde657901	5033	* @arg TIM_TS_ETRF: External Trigger input
mbed_official	87:085cde657901	5034	* @retval None
mbed_official	87:085cde657901	5035	*/
mbed_official	87:085cde657901	5036	static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
mbed_official	87:085cde657901	5037	{
mbed_official	87:085cde657901	5038	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	5039
mbed_official	87:085cde657901	5040	/* Get the TIMx SMCR register value */
mbed_official	87:085cde657901	5041	tmpsmcr = TIMx->SMCR;
mbed_official	87:085cde657901	5042	/* Reset the TS Bits */
mbed_official	87:085cde657901	5043	tmpsmcr &= ~TIM_SMCR_TS;
mbed_official	87:085cde657901	5044	/* Set the Input Trigger source and the slave mode*/
mbed_official	87:085cde657901	5045	tmpsmcr \|= TIM_ITRx \| TIM_SLAVEMODE_EXTERNAL1;
mbed_official	87:085cde657901	5046	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	5047	TIMx->SMCR = tmpsmcr;
mbed_official	87:085cde657901	5048	}
mbed_official	87:085cde657901	5049	/**
mbed_official	87:085cde657901	5050	* @brief Configures the TIMx External Trigger (ETR).
mbed_official	87:085cde657901	5051	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	5052	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official	87:085cde657901	5053	* This parameter can be one of the following values:
mbed_official	87:085cde657901	5054	* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
mbed_official	87:085cde657901	5055	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official	87:085cde657901	5056	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official	87:085cde657901	5057	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official	87:085cde657901	5058	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official	87:085cde657901	5059	* This parameter can be one of the following values:
mbed_official	87:085cde657901	5060	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official	87:085cde657901	5061	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official	87:085cde657901	5062	* @param ExtTRGFilter: External Trigger Filter.
mbed_official	87:085cde657901	5063	* This parameter must be a value between 0x00 and 0x0F
mbed_official	87:085cde657901	5064	* @retval None
mbed_official	87:085cde657901	5065	*/
mbed_official	87:085cde657901	5066	static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official	87:085cde657901	5067	uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
mbed_official	87:085cde657901	5068	{
mbed_official	87:085cde657901	5069	uint32_t tmpsmcr = 0;
mbed_official	87:085cde657901	5070
mbed_official	87:085cde657901	5071	tmpsmcr = TIMx->SMCR;
mbed_official	87:085cde657901	5072
mbed_official	87:085cde657901	5073	/* Reset the ETR Bits */
mbed_official	87:085cde657901	5074	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
mbed_official	87:085cde657901	5075
mbed_official	87:085cde657901	5076	/* Set the Prescaler, the Filter value and the Polarity */
mbed_official	87:085cde657901	5077	tmpsmcr \|= (uint32_t)(TIM_ExtTRGPrescaler \| (TIM_ExtTRGPolarity \| (ExtTRGFilter << 8)));
mbed_official	87:085cde657901	5078
mbed_official	87:085cde657901	5079	/* Write to TIMx SMCR */
mbed_official	87:085cde657901	5080	TIMx->SMCR = tmpsmcr;
mbed_official	87:085cde657901	5081	}
mbed_official	87:085cde657901	5082
mbed_official	87:085cde657901	5083	/**
mbed_official	87:085cde657901	5084	* @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official	87:085cde657901	5085	* @param TIMx to select the TIM peripheral
mbed_official	87:085cde657901	5086	* @param Channel: specifies the TIM Channel
mbed_official	87:085cde657901	5087	* This parameter can be one of the following values:
mbed_official	87:085cde657901	5088	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	87:085cde657901	5089	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	87:085cde657901	5090	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	87:085cde657901	5091	* @arg TIM_Channel_4: TIM Channel 4
mbed_official	87:085cde657901	5092	* @param ChannelState: specifies the TIM Channel CCxE bit new state.
mbed_official	87:085cde657901	5093	* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
mbed_official	87:085cde657901	5094	* @retval None
mbed_official	87:085cde657901	5095	*/
mbed_official	87:085cde657901	5096	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
mbed_official	87:085cde657901	5097	{
mbed_official	87:085cde657901	5098	uint32_t tmp = 0;
mbed_official	87:085cde657901	5099
mbed_official	87:085cde657901	5100	/* Check the parameters */
mbed_official	87:085cde657901	5101	assert_param(IS_TIM_CC1_INSTANCE(TIMx));
mbed_official	87:085cde657901	5102	assert_param(IS_TIM_CHANNELS(Channel));
mbed_official	87:085cde657901	5103
mbed_official	87:085cde657901	5104	tmp = TIM_CCER_CC1E << Channel;
mbed_official	87:085cde657901	5105
mbed_official	87:085cde657901	5106	/* Reset the CCxE Bit */
mbed_official	87:085cde657901	5107	TIMx->CCER &= ~tmp;
mbed_official	87:085cde657901	5108
mbed_official	87:085cde657901	5109	/* Set or reset the CCxE Bit */
mbed_official	87:085cde657901	5110	TIMx->CCER \|= (uint32_t)(ChannelState << Channel);
mbed_official	87:085cde657901	5111	}
mbed_official	87:085cde657901	5112
mbed_official	87:085cde657901	5113
mbed_official	87:085cde657901	5114	/**
mbed_official	87:085cde657901	5115	* @}
mbed_official	87:085cde657901	5116	*/
mbed_official	87:085cde657901	5117
mbed_official	87:085cde657901	5118	#endif /* HAL_TIM_MODULE_ENABLED */
mbed_official	87:085cde657901	5119	/**
mbed_official	87:085cde657901	5120	* @}
mbed_official	87:085cde657901	5121	*/
mbed_official	87:085cde657901	5122
mbed_official	87:085cde657901	5123	/**
mbed_official	87:085cde657901	5124	* @}
mbed_official	87:085cde657901	5125	*/
mbed_official	87:085cde657901	5126	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	09 Aug 2015
Imports:	2
Forks:	0
Commits:	604
Dependents:	0
Dependencies:	0
Followers:	3

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c@380:510f0c3515e3, 2014-11-03 (annotated)

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