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MFRC522.h@11:d773e5c4cc3a, 2015-12-08 (annotated)

Committer:
mustwillza
Date:
Tue Dec 08 22:46:01 2015 +0000
Revision:
11:d773e5c4cc3a
Parent:
1:568e35232180 
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mustwillza 0:8b94afcb61eb 1 /**
mustwillza 0:8b94afcb61eb 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
mustwillza 0:8b94afcb61eb 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
mustwillza 0:8b94afcb61eb 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
mustwillza 0:8b94afcb61eb 5 * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
mustwillza 0:8b94afcb61eb 6 * Ported to mbed by Martin Olejar, Dec, 2013
mustwillza 0:8b94afcb61eb 7 *
mustwillza 0:8b94afcb61eb 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
mustwillza 0:8b94afcb61eb 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
mustwillza 0:8b94afcb61eb 10 *
mustwillza 0:8b94afcb61eb 11 * There are three hardware components involved:
mustwillza 0:8b94afcb61eb 12 * 1) The micro controller: An Arduino
mustwillza 0:8b94afcb61eb 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
mustwillza 0:8b94afcb61eb 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
mustwillza 0:8b94afcb61eb 15 *
mustwillza 0:8b94afcb61eb 16 * The microcontroller and card reader uses SPI for communication.
mustwillza 0:8b94afcb61eb 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
mustwillza 0:8b94afcb61eb 18 *
mustwillza 0:8b94afcb61eb 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
mustwillza 0:8b94afcb61eb 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
mustwillza 0:8b94afcb61eb 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
mustwillza 0:8b94afcb61eb 22 * Details are found in chapter 6, Type A: Initialization and anticollision.
mustwillza 0:8b94afcb61eb 23 *
mustwillza 0:8b94afcb61eb 24 * If only the PICC UID is wanted, the above documents has all the needed information.
mustwillza 0:8b94afcb61eb 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
mustwillza 0:8b94afcb61eb 26 * The MIFARE Classic chips and protocol is described in the datasheets:
mustwillza 0:8b94afcb61eb 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
mustwillza 0:8b94afcb61eb 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
mustwillza 0:8b94afcb61eb 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
mustwillza 0:8b94afcb61eb 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
mustwillza 0:8b94afcb61eb 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
mustwillza 0:8b94afcb61eb 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
mustwillza 0:8b94afcb61eb 33 *
mustwillza 0:8b94afcb61eb 34 * MIFARE Classic 1K (MF1S503x):
mustwillza 0:8b94afcb61eb 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
mustwillza 0:8b94afcb61eb 36 * The blocks are numbered 0-63.
mustwillza 0:8b94afcb61eb 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
mustwillza 0:8b94afcb61eb 38 * Bytes 0-5: Key A
mustwillza 0:8b94afcb61eb 39 * Bytes 6-8: Access Bits
mustwillza 0:8b94afcb61eb 40 * Bytes 9: User data
mustwillza 0:8b94afcb61eb 41 * Bytes 10-15: Key B (or user data)
mustwillza 0:8b94afcb61eb 42 * Block 0 is read only manufacturer data.
mustwillza 0:8b94afcb61eb 43 * To access a block, an authentication using a key from the block's sector must be performed first.
mustwillza 0:8b94afcb61eb 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
mustwillza 0:8b94afcb61eb 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
mustwillza 0:8b94afcb61eb 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
mustwillza 0:8b94afcb61eb 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
mustwillza 0:8b94afcb61eb 48 * MIFARE Classic 4K (MF1S703x):
mustwillza 0:8b94afcb61eb 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
mustwillza 0:8b94afcb61eb 50 * The blocks are numbered 0-255.
mustwillza 0:8b94afcb61eb 51 * The last block in each sector is the Sector Trailer like above.
mustwillza 0:8b94afcb61eb 52 * MIFARE Classic Mini (MF1 IC S20):
mustwillza 0:8b94afcb61eb 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
mustwillza 0:8b94afcb61eb 54 * The blocks are numbered 0-19.
mustwillza 0:8b94afcb61eb 55 * The last block in each sector is the Sector Trailer like above.
mustwillza 0:8b94afcb61eb 56 *
mustwillza 0:8b94afcb61eb 57 * MIFARE Ultralight (MF0ICU1):
mustwillza 0:8b94afcb61eb 58 * Has 16 pages of 4 bytes = 64 bytes.
mustwillza 0:8b94afcb61eb 59 * Pages 0 + 1 is used for the 7-byte UID.
mustwillza 0:8b94afcb61eb 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
mustwillza 0:8b94afcb61eb 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
mustwillza 0:8b94afcb61eb 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
mustwillza 0:8b94afcb61eb 63 * MIFARE Ultralight C (MF0ICU2):
mustwillza 0:8b94afcb61eb 64 * Has 48 pages of 4 bytes = 64 bytes.
mustwillza 0:8b94afcb61eb 65 * Pages 0 + 1 is used for the 7-byte UID.
mustwillza 0:8b94afcb61eb 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
mustwillza 0:8b94afcb61eb 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
mustwillza 0:8b94afcb61eb 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
mustwillza 0:8b94afcb61eb 69 * Page 40 Lock bytes
mustwillza 0:8b94afcb61eb 70 * Page 41 16 bit one way counter
mustwillza 0:8b94afcb61eb 71 * Pages 42-43 Authentication configuration
mustwillza 0:8b94afcb61eb 72 * Pages 44-47 Authentication key
mustwillza 0:8b94afcb61eb 73 */
mustwillza 0:8b94afcb61eb 74 #ifndef MFRC522_h
mustwillza 0:8b94afcb61eb 75 #define MFRC522_h
mustwillza 0:8b94afcb61eb 76
mustwillza 0:8b94afcb61eb 77 #include "mbed.h"
mustwillza 0:8b94afcb61eb 78
mustwillza 0:8b94afcb61eb 79 /**
mustwillza 0:8b94afcb61eb 80 * MFRC522 example
mustwillza 0:8b94afcb61eb 81 *
mustwillza 0:8b94afcb61eb 82 * @code
mustwillza 0:8b94afcb61eb 83 * #include "mbed.h"
mustwillza 0:8b94afcb61eb 84 * #include "MFRC522.h"
mustwillza 0:8b94afcb61eb 85 *
mustwillza 0:8b94afcb61eb 86 * //KL25Z Pins for MFRC522 SPI interface
mustwillza 0:8b94afcb61eb 87 * #define SPI_MOSI PTC6
mustwillza 0:8b94afcb61eb 88 * #define SPI_MISO PTC7
mustwillza 0:8b94afcb61eb 89 * #define SPI_SCLK PTC5
mustwillza 0:8b94afcb61eb 90 * #define SPI_CS PTC4
mustwillza 0:8b94afcb61eb 91 * // KL25Z Pin for MFRC522 reset
mustwillza 0:8b94afcb61eb 92 * #define MF_RESET PTC3
mustwillza 0:8b94afcb61eb 93 * // KL25Z Pins for Debug UART port
mustwillza 0:8b94afcb61eb 94 * #define UART_RX PTA1
mustwillza 0:8b94afcb61eb 95 * #define UART_TX PTA2
mustwillza 0:8b94afcb61eb 96 *
mustwillza 0:8b94afcb61eb 97 * DigitalOut LedRed (LED_RED);
mustwillza 0:8b94afcb61eb 98 * DigitalOut LedGreen (LED_GREEN);
mustwillza 0:8b94afcb61eb 99 *
mustwillza 0:8b94afcb61eb 100 * Serial DebugUART(UART_TX, UART_RX);
mustwillza 0:8b94afcb61eb 101 * MFRC522 RfChip (SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS, MF_RESET);
mustwillza 0:8b94afcb61eb 102 *
mustwillza 0:8b94afcb61eb 103 * int main(void) {
mustwillza 0:8b94afcb61eb 104 * // Set debug UART speed
mustwillza 0:8b94afcb61eb 105 * DebugUART.baud(115200);
mustwillza 0:8b94afcb61eb 106 *
mustwillza 0:8b94afcb61eb 107 * // Init. RC522 Chip
mustwillza 0:8b94afcb61eb 108 * RfChip.PCD_Init();
mustwillza 0:8b94afcb61eb 109 *
mustwillza 0:8b94afcb61eb 110 * while (true) {
mustwillza 0:8b94afcb61eb 111 * LedRed = 1;
mustwillza 0:8b94afcb61eb 112 * LedGreen = 1;
mustwillza 0:8b94afcb61eb 113 *
mustwillza 0:8b94afcb61eb 114 * // Look for new cards
mustwillza 0:8b94afcb61eb 115 * if ( ! RfChip.PICC_IsNewCardPresent())
mustwillza 0:8b94afcb61eb 116 * {
mustwillza 0:8b94afcb61eb 117 * wait_ms(500);
mustwillza 0:8b94afcb61eb 118 * continue;
mustwillza 0:8b94afcb61eb 119 * }
mustwillza 0:8b94afcb61eb 120 *
mustwillza 0:8b94afcb61eb 121 * LedRed = 0;
mustwillza 0:8b94afcb61eb 122 *
mustwillza 0:8b94afcb61eb 123 * // Select one of the cards
mustwillza 0:8b94afcb61eb 124 * if ( ! RfChip.PICC_ReadCardSerial())
mustwillza 0:8b94afcb61eb 125 * {
mustwillza 0:8b94afcb61eb 126 * wait_ms(500);
mustwillza 0:8b94afcb61eb 127 * continue;
mustwillza 0:8b94afcb61eb 128 * }
mustwillza 0:8b94afcb61eb 129 *
mustwillza 0:8b94afcb61eb 130 * LedRed = 1;
mustwillza 0:8b94afcb61eb 131 * LedGreen = 0;
mustwillza 0:8b94afcb61eb 132 *
mustwillza 0:8b94afcb61eb 133 * // Print Card UID
mustwillza 0:8b94afcb61eb 134 * printf("Card UID: ");
mustwillza 0:8b94afcb61eb 135 * for (uint8_t i = 0; i < RfChip.uid.size; i++)
mustwillza 0:8b94afcb61eb 136 * {
mustwillza 0:8b94afcb61eb 137 * printf(" %X02", RfChip.uid.uidByte[i]);
mustwillza 0:8b94afcb61eb 138 * }
mustwillza 0:8b94afcb61eb 139 * printf("\n\r");
mustwillza 0:8b94afcb61eb 140 *
mustwillza 0:8b94afcb61eb 141 * // Print Card type
mustwillza 0:8b94afcb61eb 142 * uint8_t piccType = RfChip.PICC_GetType(RfChip.uid.sak);
mustwillza 0:8b94afcb61eb 143 * printf("PICC Type: %s \n\r", RfChip.PICC_GetTypeName(piccType));
mustwillza 0:8b94afcb61eb 144 * wait_ms(1000);
mustwillza 0:8b94afcb61eb 145 * }
mustwillza 0:8b94afcb61eb 146 * }
mustwillza 0:8b94afcb61eb 147 * @endcode
mustwillza 0:8b94afcb61eb 148 */
mustwillza 0:8b94afcb61eb 149
mustwillza 0:8b94afcb61eb 150 class MFRC522 {
mustwillza 0:8b94afcb61eb 151 public:
mustwillza 0:8b94afcb61eb 152 void stop(){
mustwillza 0:8b94afcb61eb 153 m_CS =0;
mustwillza 0:8b94afcb61eb 154 }
mustwillza 0:8b94afcb61eb 155 void start(){
mustwillza 0:8b94afcb61eb 156 m_CS =1;
mustwillza 0:8b94afcb61eb 157 }
mustwillza 0:8b94afcb61eb 158 /**
mustwillza 0:8b94afcb61eb 159 * MFRC522 registers (described in chapter 9 of the datasheet).
mustwillza 0:8b94afcb61eb 160 * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
mustwillza 0:8b94afcb61eb 161 */
mustwillza 0:8b94afcb61eb 162 enum PCD_Register {
mustwillza 0:8b94afcb61eb 163 // Page 0: Command and status
mustwillza 0:8b94afcb61eb 164 // 0x00 // reserved for future use
mustwillza 0:8b94afcb61eb 165 CommandReg = 0x01 << 1, // starts and stops command execution
mustwillza 0:8b94afcb61eb 166 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
mustwillza 0:8b94afcb61eb 167 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
mustwillza 0:8b94afcb61eb 168 ComIrqReg = 0x04 << 1, // interrupt request bits
mustwillza 0:8b94afcb61eb 169 DivIrqReg = 0x05 << 1, // interrupt request bits
mustwillza 0:8b94afcb61eb 170 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
mustwillza 0:8b94afcb61eb 171 Status1Reg = 0x07 << 1, // communication status bits
mustwillza 0:8b94afcb61eb 172 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
mustwillza 0:8b94afcb61eb 173 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
mustwillza 0:8b94afcb61eb 174 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
mustwillza 0:8b94afcb61eb 175 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
mustwillza 0:8b94afcb61eb 176 ControlReg = 0x0C << 1, // miscellaneous control registers
mustwillza 0:8b94afcb61eb 177 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
mustwillza 0:8b94afcb61eb 178 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
mustwillza 0:8b94afcb61eb 179 // 0x0F // reserved for future use
mustwillza 0:8b94afcb61eb 180
mustwillza 0:8b94afcb61eb 181 // Page 1:Command
mustwillza 0:8b94afcb61eb 182 // 0x10 // reserved for future use
mustwillza 0:8b94afcb61eb 183 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
mustwillza 0:8b94afcb61eb 184 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
mustwillza 0:8b94afcb61eb 185 RxModeReg = 0x13 << 1, // defines reception data rate and framing
mustwillza 0:8b94afcb61eb 186 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
mustwillza 0:8b94afcb61eb 187 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
mustwillza 0:8b94afcb61eb 188 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
mustwillza 0:8b94afcb61eb 189 RxSelReg = 0x17 << 1, // selects internal receiver settings
mustwillza 0:8b94afcb61eb 190 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
mustwillza 0:8b94afcb61eb 191 DemodReg = 0x19 << 1, // defines demodulator settings
mustwillza 0:8b94afcb61eb 192 // 0x1A // reserved for future use
mustwillza 0:8b94afcb61eb 193 // 0x1B // reserved for future use
mustwillza 0:8b94afcb61eb 194 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
mustwillza 0:8b94afcb61eb 195 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
mustwillza 0:8b94afcb61eb 196 // 0x1E // reserved for future use
mustwillza 0:8b94afcb61eb 197 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
mustwillza 0:8b94afcb61eb 198
mustwillza 0:8b94afcb61eb 199 // Page 2: Configuration
mustwillza 0:8b94afcb61eb 200 // 0x20 // reserved for future use
mustwillza 0:8b94afcb61eb 201 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
mustwillza 0:8b94afcb61eb 202 CRCResultRegL = 0x22 << 1,
mustwillza 0:8b94afcb61eb 203 // 0x23 // reserved for future use
mustwillza 0:8b94afcb61eb 204 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
mustwillza 0:8b94afcb61eb 205 // 0x25 // reserved for future use
mustwillza 0:8b94afcb61eb 206 RFCfgReg = 0x26 << 1, // configures the receiver gain
mustwillza 0:8b94afcb61eb 207 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
mustwillza 0:8b94afcb61eb 208 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
mustwillza 0:8b94afcb61eb 209 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
mustwillza 0:8b94afcb61eb 210 TModeReg = 0x2A << 1, // defines settings for the internal timer
mustwillza 0:8b94afcb61eb 211 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
mustwillza 0:8b94afcb61eb 212 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
mustwillza 0:8b94afcb61eb 213 TReloadRegL = 0x2D << 1,
mustwillza 0:8b94afcb61eb 214 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
mustwillza 0:8b94afcb61eb 215 TCntValueRegL = 0x2F << 1,
mustwillza 0:8b94afcb61eb 216
mustwillza 0:8b94afcb61eb 217 // Page 3:Test Registers
mustwillza 0:8b94afcb61eb 218 // 0x30 // reserved for future use
mustwillza 0:8b94afcb61eb 219 TestSel1Reg = 0x31 << 1, // general test signal configuration
mustwillza 0:8b94afcb61eb 220 TestSel2Reg = 0x32 << 1, // general test signal configuration
mustwillza 0:8b94afcb61eb 221 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
mustwillza 0:8b94afcb61eb 222 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
mustwillza 0:8b94afcb61eb 223 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
mustwillza 0:8b94afcb61eb 224 AutoTestReg = 0x36 << 1, // controls the digital self test
mustwillza 0:8b94afcb61eb 225 VersionReg = 0x37 << 1, // shows the software version
mustwillza 0:8b94afcb61eb 226 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
mustwillza 0:8b94afcb61eb 227 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
mustwillza 0:8b94afcb61eb 228 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
mustwillza 0:8b94afcb61eb 229 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
mustwillza 0:8b94afcb61eb 230 // 0x3C // reserved for production tests
mustwillza 0:8b94afcb61eb 231 // 0x3D // reserved for production tests
mustwillza 0:8b94afcb61eb 232 // 0x3E // reserved for production tests
mustwillza 0:8b94afcb61eb 233 // 0x3F // reserved for production tests
mustwillza 0:8b94afcb61eb 234 };
mustwillza 0:8b94afcb61eb 235
mustwillza 0:8b94afcb61eb 236 // MFRC522 commands Described in chapter 10 of the datasheet.
mustwillza 0:8b94afcb61eb 237 enum PCD_Command {
mustwillza 0:8b94afcb61eb 238 PCD_Idle = 0x00, // no action, cancels current command execution
mustwillza 0:8b94afcb61eb 239 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
mustwillza 0:8b94afcb61eb 240 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
mustwillza 0:8b94afcb61eb 241 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
mustwillza 0:8b94afcb61eb 242 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
mustwillza 0:8b94afcb61eb 243 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
mustwillza 0:8b94afcb61eb 244 PCD_Receive = 0x08, // activates the receiver circuits
mustwillza 0:8b94afcb61eb 245 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
mustwillza 0:8b94afcb61eb 246 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
mustwillza 0:8b94afcb61eb 247 PCD_SoftReset = 0x0F // resets the MFRC522
mustwillza 0:8b94afcb61eb 248 };
mustwillza 0:8b94afcb61eb 249
mustwillza 0:8b94afcb61eb 250 // Commands sent to the PICC.
mustwillza 0:8b94afcb61eb 251 enum PICC_Command {
mustwillza 0:8b94afcb61eb 252 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
mustwillza 0:8b94afcb61eb 253 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:8b94afcb61eb 254 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:8b94afcb61eb 255 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
mustwillza 0:8b94afcb61eb 256 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
mustwillza 0:8b94afcb61eb 257 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
mustwillza 0:8b94afcb61eb 258 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
mustwillza 0:8b94afcb61eb 259 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
mustwillza 0:8b94afcb61eb 260
mustwillza 0:8b94afcb61eb 261 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
mustwillza 0:8b94afcb61eb 262 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
mustwillza 0:8b94afcb61eb 263 // The read/write commands can also be used for MIFARE Ultralight.
mustwillza 0:8b94afcb61eb 264 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
mustwillza 0:8b94afcb61eb 265 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
mustwillza 0:8b94afcb61eb 266 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
mustwillza 0:8b94afcb61eb 267 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
mustwillza 0:8b94afcb61eb 268 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
mustwillza 0:8b94afcb61eb 269 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
mustwillza 0:8b94afcb61eb 270 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
mustwillza 0:8b94afcb61eb 271 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
mustwillza 0:8b94afcb61eb 272
mustwillza 0:8b94afcb61eb 273 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
mustwillza 0:8b94afcb61eb 274 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
mustwillza 0:8b94afcb61eb 275 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
mustwillza 0:8b94afcb61eb 276 };
mustwillza 0:8b94afcb61eb 277
mustwillza 0:8b94afcb61eb 278 // MIFARE constants that does not fit anywhere else
mustwillza 0:8b94afcb61eb 279 enum MIFARE_Misc {
mustwillza 0:8b94afcb61eb 280 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
mustwillza 0:8b94afcb61eb 281 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
mustwillza 0:8b94afcb61eb 282 };
mustwillza 0:8b94afcb61eb 283
mustwillza 0:8b94afcb61eb 284 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
mustwillza 0:8b94afcb61eb 285 enum PICC_Type {
mustwillza 0:8b94afcb61eb 286 PICC_TYPE_UNKNOWN = 0,
mustwillza 0:8b94afcb61eb 287 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
mustwillza 0:8b94afcb61eb 288 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
mustwillza 0:8b94afcb61eb 289 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
mustwillza 0:8b94afcb61eb 290 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
mustwillza 0:8b94afcb61eb 291 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
mustwillza 0:8b94afcb61eb 292 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
mustwillza 0:8b94afcb61eb 293 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
mustwillza 0:8b94afcb61eb 294 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
mustwillza 0:8b94afcb61eb 295 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
mustwillza 0:8b94afcb61eb 296 };
mustwillza 0:8b94afcb61eb 297
mustwillza 0:8b94afcb61eb 298 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
mustwillza 0:8b94afcb61eb 299 enum StatusCode {
mustwillza 0:8b94afcb61eb 300 STATUS_OK = 1, // Success
mustwillza 0:8b94afcb61eb 301 STATUS_ERROR = 2, // Error in communication
mustwillza 0:8b94afcb61eb 302 STATUS_COLLISION = 3, // Collision detected
mustwillza 0:8b94afcb61eb 303 STATUS_TIMEOUT = 4, // Timeout in communication.
mustwillza 0:8b94afcb61eb 304 STATUS_NO_ROOM = 5, // A buffer is not big enough.
mustwillza 0:8b94afcb61eb 305 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
mustwillza 0:8b94afcb61eb 306 STATUS_INVALID = 7, // Invalid argument.
mustwillza 0:8b94afcb61eb 307 STATUS_CRC_WRONG = 8, // The CRC_A does not match
mustwillza 0:8b94afcb61eb 308 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
mustwillza 0:8b94afcb61eb 309 };
mustwillza 0:8b94afcb61eb 310
mustwillza 0:8b94afcb61eb 311 // A struct used for passing the UID of a PICC.
mustwillza 0:8b94afcb61eb 312 typedef struct {
mustwillza 0:8b94afcb61eb 313 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
mustwillza 0:8b94afcb61eb 314 uint8_t uidByte[10];
mustwillza 0:8b94afcb61eb 315 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
mustwillza 0:8b94afcb61eb 316 } Uid;
mustwillza 0:8b94afcb61eb 317
mustwillza 0:8b94afcb61eb 318 // A struct used for passing a MIFARE Crypto1 key
mustwillza 0:8b94afcb61eb 319 typedef struct {
mustwillza 0:8b94afcb61eb 320 uint8_t keyByte[MF_KEY_SIZE];
mustwillza 0:8b94afcb61eb 321 } MIFARE_Key;
mustwillza 0:8b94afcb61eb 322
mustwillza 0:8b94afcb61eb 323 // Member variables
mustwillza 0:8b94afcb61eb 324 Uid uid; // Used by PICC_ReadCardSerial().
mustwillza 0:8b94afcb61eb 325
mustwillza 0:8b94afcb61eb 326 // Size of the MFRC522 FIFO
mustwillza 0:8b94afcb61eb 327 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
mustwillza 0:8b94afcb61eb 328
mustwillza 0:8b94afcb61eb 329 /**
mustwillza 0:8b94afcb61eb 330 * MFRC522 constructor
mustwillza 0:8b94afcb61eb 331 *
mustwillza 0:8b94afcb61eb 332 * @param mosi SPI MOSI pin
mustwillza 0:8b94afcb61eb 333 * @param miso SPI MISO pin
mustwillza 0:8b94afcb61eb 334 * @param sclk SPI SCLK pin
mustwillza 0:8b94afcb61eb 335 * @param cs SPI CS pin
mustwillza 0:8b94afcb61eb 336 * @param reset Reset pin
mustwillza 0:8b94afcb61eb 337 */
mustwillza 0:8b94afcb61eb 338 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
mustwillza 0:8b94afcb61eb 339
mustwillza 0:8b94afcb61eb 340 /**
mustwillza 0:8b94afcb61eb 341 * MFRC522 destructor
mustwillza 0:8b94afcb61eb 342 */
mustwillza 0:8b94afcb61eb 343 ~MFRC522();
mustwillza 0:8b94afcb61eb 344
mustwillza 0:8b94afcb61eb 345
mustwillza 0:8b94afcb61eb 346 // ************************************************************************************
mustwillza 0:8b94afcb61eb 347 //! @name Functions for manipulating the MFRC522
mustwillza 0:8b94afcb61eb 348 // ************************************************************************************
mustwillza 0:8b94afcb61eb 349 //@{
mustwillza 0:8b94afcb61eb 350
mustwillza 0:8b94afcb61eb 351 /**
mustwillza 0:8b94afcb61eb 352 * Initializes the MFRC522 chip.
mustwillza 0:8b94afcb61eb 353 */
mustwillza 0:8b94afcb61eb 354 void PCD_Init (void);
mustwillza 0:8b94afcb61eb 355
mustwillza 0:8b94afcb61eb 356 /**
mustwillza 0:8b94afcb61eb 357 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
mustwillza 0:8b94afcb61eb 358 */
mustwillza 0:8b94afcb61eb 359 void PCD_Reset (void);
mustwillza 0:8b94afcb61eb 360
mustwillza 0:8b94afcb61eb 361 /**
mustwillza 0:8b94afcb61eb 362 * Turns the antenna on by enabling pins TX1 and TX2.
mustwillza 0:8b94afcb61eb 363 * After a reset these pins disabled.
mustwillza 0:8b94afcb61eb 364 */
mustwillza 0:8b94afcb61eb 365 void PCD_AntennaOn (void);
mustwillza 0:8b94afcb61eb 366
mustwillza 0:8b94afcb61eb 367 /**
mustwillza 0:8b94afcb61eb 368 * Writes a byte to the specified register in the MFRC522 chip.
mustwillza 0:8b94afcb61eb 369 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:8b94afcb61eb 370 *
mustwillza 0:8b94afcb61eb 371 * @param reg The register to write to. One of the PCD_Register enums.
mustwillza 0:8b94afcb61eb 372 * @param value The value to write.
mustwillza 0:8b94afcb61eb 373 */
mustwillza 0:8b94afcb61eb 374 void PCD_WriteRegister (uint8_t reg, uint8_t value);
mustwillza 0:8b94afcb61eb 375
mustwillza 0:8b94afcb61eb 376 /**
mustwillza 0:8b94afcb61eb 377 * Writes a number of bytes to the specified register in the MFRC522 chip.
mustwillza 0:8b94afcb61eb 378 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:8b94afcb61eb 379 *
mustwillza 0:8b94afcb61eb 380 * @param reg The register to write to. One of the PCD_Register enums.
mustwillza 0:8b94afcb61eb 381 * @param count The number of bytes to write to the register
mustwillza 0:8b94afcb61eb 382 * @param values The values to write. Byte array.
mustwillza 0:8b94afcb61eb 383 */
mustwillza 0:8b94afcb61eb 384 void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
mustwillza 0:8b94afcb61eb 385
mustwillza 0:8b94afcb61eb 386 /**
mustwillza 0:8b94afcb61eb 387 * Reads a byte from the specified register in the MFRC522 chip.
mustwillza 0:8b94afcb61eb 388 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:8b94afcb61eb 389 *
mustwillza 0:8b94afcb61eb 390 * @param reg The register to read from. One of the PCD_Register enums.
mustwillza 0:8b94afcb61eb 391 * @returns Register value
mustwillza 0:8b94afcb61eb 392 */
mustwillza 0:8b94afcb61eb 393 uint8_t PCD_ReadRegister (uint8_t reg);
mustwillza 0:8b94afcb61eb 394
mustwillza 0:8b94afcb61eb 395 /**
mustwillza 0:8b94afcb61eb 396 * Reads a number of bytes from the specified register in the MFRC522 chip.
mustwillza 0:8b94afcb61eb 397 * The interface is described in the datasheet section 8.1.2.
mustwillza 0:8b94afcb61eb 398 *
mustwillza 0:8b94afcb61eb 399 * @param reg The register to read from. One of the PCD_Register enums.
mustwillza 0:8b94afcb61eb 400 * @param count The number of bytes to read.
mustwillza 0:8b94afcb61eb 401 * @param values Byte array to store the values in.
mustwillza 0:8b94afcb61eb 402 * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
mustwillza 0:8b94afcb61eb 403 */
mustwillza 0:8b94afcb61eb 404 void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
mustwillza 0:8b94afcb61eb 405
mustwillza 0:8b94afcb61eb 406 /**
mustwillza 0:8b94afcb61eb 407 * Sets the bits given in mask in register reg.
mustwillza 0:8b94afcb61eb 408 *
mustwillza 0:8b94afcb61eb 409 * @param reg The register to update. One of the PCD_Register enums.
mustwillza 0:8b94afcb61eb 410 * @param mask The bits to set.
mustwillza 0:8b94afcb61eb 411 */
mustwillza 0:8b94afcb61eb 412 void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
mustwillza 0:8b94afcb61eb 413
mustwillza 0:8b94afcb61eb 414 /**
mustwillza 0:8b94afcb61eb 415 * Clears the bits given in mask from register reg.
mustwillza 0:8b94afcb61eb 416 *
mustwillza 0:8b94afcb61eb 417 * @param reg The register to update. One of the PCD_Register enums.
mustwillza 0:8b94afcb61eb 418 * @param mask The bits to clear.
mustwillza 0:8b94afcb61eb 419 */
mustwillza 0:8b94afcb61eb 420 void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
mustwillza 0:8b94afcb61eb 421
mustwillza 0:8b94afcb61eb 422 /**
mustwillza 0:8b94afcb61eb 423 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
mustwillza 0:8b94afcb61eb 424 *
mustwillza 0:8b94afcb61eb 425 * @param data Pointer to the data to transfer to the FIFO for CRC calculation.
mustwillza 0:8b94afcb61eb 426 * @param length The number of bytes to transfer.
mustwillza 0:8b94afcb61eb 427 * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
mustwillza 0:8b94afcb61eb 428 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 429 */
mustwillza 0:8b94afcb61eb 430 uint8_t PCD_CalculateCRC (uint8_t *data, uint8_t length, uint8_t *result);
mustwillza 0:8b94afcb61eb 431
mustwillza 0:8b94afcb61eb 432 /**
mustwillza 0:8b94afcb61eb 433 * Executes the Transceive command.
mustwillza 0:8b94afcb61eb 434 * CRC validation can only be done if backData and backLen are specified.
mustwillza 0:8b94afcb61eb 435 *
mustwillza 0:8b94afcb61eb 436 * @param sendData Pointer to the data to transfer to the FIFO.
mustwillza 0:8b94afcb61eb 437 * @param sendLen Number of bytes to transfer to the FIFO.
mustwillza 0:8b94afcb61eb 438 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
mustwillza 0:8b94afcb61eb 439 * @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
mustwillza 0:8b94afcb61eb 440 * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
mustwillza 0:8b94afcb61eb 441 * @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
mustwillza 0:8b94afcb61eb 442 * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
mustwillza 0:8b94afcb61eb 443 *
mustwillza 0:8b94afcb61eb 444 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 445 */
mustwillza 0:8b94afcb61eb 446 uint8_t PCD_TransceiveData (uint8_t *sendData,
mustwillza 0:8b94afcb61eb 447 uint8_t sendLen,
mustwillza 0:8b94afcb61eb 448 uint8_t *backData,
mustwillza 0:8b94afcb61eb 449 uint8_t *backLen,
mustwillza 0:8b94afcb61eb 450 uint8_t *validBits = NULL,
mustwillza 0:8b94afcb61eb 451 uint8_t rxAlign = 0,
mustwillza 0:8b94afcb61eb 452 bool checkCRC = false);
mustwillza 0:8b94afcb61eb 453
mustwillza 0:8b94afcb61eb 454
mustwillza 0:8b94afcb61eb 455 /**
mustwillza 0:8b94afcb61eb 456 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
mustwillza 0:8b94afcb61eb 457 * CRC validation can only be done if backData and backLen are specified.
mustwillza 0:8b94afcb61eb 458 *
mustwillza 0:8b94afcb61eb 459 * @param command The command to execute. One of the PCD_Command enums.
mustwillza 0:8b94afcb61eb 460 * @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
mustwillza 0:8b94afcb61eb 461 * @param sendData Pointer to the data to transfer to the FIFO.
mustwillza 0:8b94afcb61eb 462 * @param sendLen Number of bytes to transfer to the FIFO.
mustwillza 0:8b94afcb61eb 463 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
mustwillza 0:8b94afcb61eb 464 * @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
mustwillza 0:8b94afcb61eb 465 * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
mustwillza 0:8b94afcb61eb 466 * @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
mustwillza 0:8b94afcb61eb 467 * @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
mustwillza 0:8b94afcb61eb 468 *
mustwillza 0:8b94afcb61eb 469 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 470 */
mustwillza 0:8b94afcb61eb 471 uint8_t PCD_CommunicateWithPICC(uint8_t command,
mustwillza 0:8b94afcb61eb 472 uint8_t waitIRq,
mustwillza 0:8b94afcb61eb 473 uint8_t *sendData,
mustwillza 0:8b94afcb61eb 474 uint8_t sendLen,
mustwillza 0:8b94afcb61eb 475 uint8_t *backData = NULL,
mustwillza 0:8b94afcb61eb 476 uint8_t *backLen = NULL,
mustwillza 0:8b94afcb61eb 477 uint8_t *validBits = NULL,
mustwillza 0:8b94afcb61eb 478 uint8_t rxAlign = 0,
mustwillza 0:8b94afcb61eb 479 bool checkCRC = false);
mustwillza 0:8b94afcb61eb 480
mustwillza 0:8b94afcb61eb 481 /**
mustwillza 0:8b94afcb61eb 482 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:8b94afcb61eb 483 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mustwillza 0:8b94afcb61eb 484 *
mustwillza 0:8b94afcb61eb 485 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
mustwillza 0:8b94afcb61eb 486 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
mustwillza 0:8b94afcb61eb 487 *
mustwillza 0:8b94afcb61eb 488 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 489 */
mustwillza 0:8b94afcb61eb 490 uint8_t PICC_RequestA (uint8_t *bufferATQA, uint8_t *bufferSize);
mustwillza 0:8b94afcb61eb 491
mustwillza 0:8b94afcb61eb 492 /**
mustwillza 0:8b94afcb61eb 493 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
mustwillza 0:8b94afcb61eb 494 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mustwillza 0:8b94afcb61eb 495 *
mustwillza 0:8b94afcb61eb 496 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
mustwillza 0:8b94afcb61eb 497 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
mustwillza 0:8b94afcb61eb 498 *
mustwillza 0:8b94afcb61eb 499 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 500 */
mustwillza 0:8b94afcb61eb 501 uint8_t PICC_WakeupA (uint8_t *bufferATQA, uint8_t *bufferSize);
mustwillza 0:8b94afcb61eb 502
mustwillza 0:8b94afcb61eb 503 /**
mustwillza 0:8b94afcb61eb 504 * Transmits REQA or WUPA commands.
mustwillza 0:8b94afcb61eb 505 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
mustwillza 0:8b94afcb61eb 506 *
mustwillza 0:8b94afcb61eb 507 * @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
mustwillza 0:8b94afcb61eb 508 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
mustwillza 0:8b94afcb61eb 509 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
mustwillza 0:8b94afcb61eb 510 *
mustwillza 0:8b94afcb61eb 511 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 512 */
mustwillza 0:8b94afcb61eb 513 uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
mustwillza 0:8b94afcb61eb 514
mustwillza 0:8b94afcb61eb 515 /**
mustwillza 0:8b94afcb61eb 516 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
mustwillza 0:8b94afcb61eb 517 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
mustwillza 0:8b94afcb61eb 518 * On success:
mustwillza 0:8b94afcb61eb 519 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
mustwillza 0:8b94afcb61eb 520 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
mustwillza 0:8b94afcb61eb 521 *
mustwillza 0:8b94afcb61eb 522 * A PICC UID consists of 4, 7 or 10 bytes.
mustwillza 0:8b94afcb61eb 523 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
mustwillza 0:8b94afcb61eb 524 *
mustwillza 0:8b94afcb61eb 525 * UID size Number of UID bytes Cascade levels Example of PICC
mustwillza 0:8b94afcb61eb 526 * ======== =================== ============== ===============
mustwillza 0:8b94afcb61eb 527 * single 4 1 MIFARE Classic
mustwillza 0:8b94afcb61eb 528 * double 7 2 MIFARE Ultralight
mustwillza 0:8b94afcb61eb 529 * triple 10 3 Not currently in use?
mustwillza 0:8b94afcb61eb 530 *
mustwillza 0:8b94afcb61eb 531 *
mustwillza 0:8b94afcb61eb 532 * @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
mustwillza 0:8b94afcb61eb 533 * @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
mustwillza 0:8b94afcb61eb 534 *
mustwillza 0:8b94afcb61eb 535 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 536 */
mustwillza 0:8b94afcb61eb 537 uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
mustwillza 0:8b94afcb61eb 538
mustwillza 0:8b94afcb61eb 539 /**
mustwillza 0:8b94afcb61eb 540 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
mustwillza 0:8b94afcb61eb 541 *
mustwillza 0:8b94afcb61eb 542 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 543 */
mustwillza 0:8b94afcb61eb 544 uint8_t PICC_HaltA (void);
mustwillza 0:8b94afcb61eb 545
mustwillza 0:8b94afcb61eb 546 // ************************************************************************************
mustwillza 0:8b94afcb61eb 547 //@}
mustwillza 0:8b94afcb61eb 548
mustwillza 0:8b94afcb61eb 549
mustwillza 0:8b94afcb61eb 550 // ************************************************************************************
mustwillza 0:8b94afcb61eb 551 //! @name Functions for communicating with MIFARE PICCs
mustwillza 0:8b94afcb61eb 552 // ************************************************************************************
mustwillza 0:8b94afcb61eb 553 //@{
mustwillza 0:8b94afcb61eb 554
mustwillza 0:8b94afcb61eb 555 /**
mustwillza 0:8b94afcb61eb 556 * Executes the MFRC522 MFAuthent command.
mustwillza 0:8b94afcb61eb 557 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
mustwillza 0:8b94afcb61eb 558 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
mustwillza 0:8b94afcb61eb 559 * For use with MIFARE Classic PICCs.
mustwillza 0:8b94afcb61eb 560 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
mustwillza 0:8b94afcb61eb 561 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
mustwillza 0:8b94afcb61eb 562 *
mustwillza 0:8b94afcb61eb 563 * All keys are set to FFFFFFFFFFFFh at chip delivery.
mustwillza 0:8b94afcb61eb 564 *
mustwillza 0:8b94afcb61eb 565 * @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
mustwillza 0:8b94afcb61eb 566 * @param blockAddr The block number. See numbering in the comments in the .h file.
mustwillza 0:8b94afcb61eb 567 * @param key Pointer to the Crypteo1 key to use (6 bytes)
mustwillza 0:8b94afcb61eb 568 * @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
mustwillza 0:8b94afcb61eb 569 *
mustwillza 0:8b94afcb61eb 570 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
mustwillza 0:8b94afcb61eb 571 */
mustwillza 0:8b94afcb61eb 572 uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
mustwillza 0:8b94afcb61eb 573
mustwillza 0:8b94afcb61eb 574 /**
mustwillza 0:8b94afcb61eb 575 * Used to exit the PCD from its authenticated state.
mustwillza 0:8b94afcb61eb 576 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
mustwillza 0:8b94afcb61eb 577 */
mustwillza 0:8b94afcb61eb 578 void PCD_StopCrypto1 (void);
mustwillza 0:8b94afcb61eb 579
mustwillza 0:8b94afcb61eb 580 /**
mustwillza 0:8b94afcb61eb 581 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
mustwillza 0:8b94afcb61eb 582 *
mustwillza 0:8b94afcb61eb 583 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
mustwillza 0:8b94afcb61eb 584 *
mustwillza 0:8b94afcb61eb 585 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
mustwillza 0:8b94afcb61eb 586 * The MF0ICU1 returns a NAK for higher addresses.
mustwillza 0:8b94afcb61eb 587 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
mustwillza 0:8b94afcb61eb 588 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
mustwillza 0:8b94afcb61eb 589 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
mustwillza 0:8b94afcb61eb 590 *
mustwillza 0:8b94afcb61eb 591 * The buffer must be at least 18 bytes because a CRC_A is also returned.
mustwillza 0:8b94afcb61eb 592 * Checks the CRC_A before returning STATUS_OK.
mustwillza 0:8b94afcb61eb 593 *
mustwillza 0:8b94afcb61eb 594 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
mustwillza 0:8b94afcb61eb 595 * @param buffer The buffer to store the data in
mustwillza 0:8b94afcb61eb 596 * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
mustwillza 0:8b94afcb61eb 597 *
mustwillza 0:8b94afcb61eb 598 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 599 */
mustwillza 0:8b94afcb61eb 600 uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
mustwillza 0:8b94afcb61eb 601
mustwillza 0:8b94afcb61eb 602 /**
mustwillza 0:8b94afcb61eb 603 * Writes 16 bytes to the active PICC.
mustwillza 0:8b94afcb61eb 604 *
mustwillza 0:8b94afcb61eb 605 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
mustwillza 0:8b94afcb61eb 606 *
mustwillza 0:8b94afcb61eb 607 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
mustwillza 0:8b94afcb61eb 608 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
mustwillza 0:8b94afcb61eb 609 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
mustwillza 0:8b94afcb61eb 610 *
mustwillza 0:8b94afcb61eb 611 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
mustwillza 0:8b94afcb61eb 612 * @param buffer The 16 bytes to write to the PICC
mustwillza 0:8b94afcb61eb 613 * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
mustwillza 0:8b94afcb61eb 614 *
mustwillza 0:8b94afcb61eb 615 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 616 */
mustwillza 0:8b94afcb61eb 617 uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
mustwillza 0:8b94afcb61eb 618
mustwillza 0:8b94afcb61eb 619 /**
mustwillza 0:8b94afcb61eb 620 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
mustwillza 0:8b94afcb61eb 621 *
mustwillza 0:8b94afcb61eb 622 * @param page The page (2-15) to write to.
mustwillza 0:8b94afcb61eb 623 * @param buffer The 4 bytes to write to the PICC
mustwillza 0:8b94afcb61eb 624 * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
mustwillza 0:8b94afcb61eb 625 *
mustwillza 0:8b94afcb61eb 626 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 627 */
mustwillza 0:8b94afcb61eb 628 uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
mustwillza 0:8b94afcb61eb 629
mustwillza 0:8b94afcb61eb 630 /**
mustwillza 0:8b94afcb61eb 631 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
mustwillza 0:8b94afcb61eb 632 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mustwillza 0:8b94afcb61eb 633 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mustwillza 0:8b94afcb61eb 634 * Use MIFARE_Transfer() to store the result in a block.
mustwillza 0:8b94afcb61eb 635 *
mustwillza 0:8b94afcb61eb 636 * @param blockAddr The block (0-0xff) number.
mustwillza 0:8b94afcb61eb 637 * @param delta This number is subtracted from the value of block blockAddr.
mustwillza 0:8b94afcb61eb 638 *
mustwillza 0:8b94afcb61eb 639 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 640 */
mustwillza 0:8b94afcb61eb 641 uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
mustwillza 0:8b94afcb61eb 642
mustwillza 0:8b94afcb61eb 643 /**
mustwillza 0:8b94afcb61eb 644 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
mustwillza 0:8b94afcb61eb 645 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mustwillza 0:8b94afcb61eb 646 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mustwillza 0:8b94afcb61eb 647 * Use MIFARE_Transfer() to store the result in a block.
mustwillza 0:8b94afcb61eb 648 *
mustwillza 0:8b94afcb61eb 649 * @param blockAddr The block (0-0xff) number.
mustwillza 0:8b94afcb61eb 650 * @param delta This number is added to the value of block blockAddr.
mustwillza 0:8b94afcb61eb 651 *
mustwillza 0:8b94afcb61eb 652 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 653 */
mustwillza 0:8b94afcb61eb 654 uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
mustwillza 0:8b94afcb61eb 655
mustwillza 0:8b94afcb61eb 656 /**
mustwillza 0:8b94afcb61eb 657 * MIFARE Restore copies the value of the addressed block into a volatile memory.
mustwillza 0:8b94afcb61eb 658 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mustwillza 0:8b94afcb61eb 659 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mustwillza 0:8b94afcb61eb 660 * Use MIFARE_Transfer() to store the result in a block.
mustwillza 0:8b94afcb61eb 661 *
mustwillza 0:8b94afcb61eb 662 * @param blockAddr The block (0-0xff) number.
mustwillza 0:8b94afcb61eb 663 *
mustwillza 0:8b94afcb61eb 664 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 665 */
mustwillza 0:8b94afcb61eb 666 uint8_t MIFARE_Restore (uint8_t blockAddr);
mustwillza 0:8b94afcb61eb 667
mustwillza 0:8b94afcb61eb 668 /**
mustwillza 0:8b94afcb61eb 669 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
mustwillza 0:8b94afcb61eb 670 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
mustwillza 0:8b94afcb61eb 671 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
mustwillza 0:8b94afcb61eb 672 *
mustwillza 0:8b94afcb61eb 673 * @param blockAddr The block (0-0xff) number.
mustwillza 0:8b94afcb61eb 674 *
mustwillza 0:8b94afcb61eb 675 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 676 */
mustwillza 0:8b94afcb61eb 677 uint8_t MIFARE_Transfer (uint8_t blockAddr);
mustwillza 0:8b94afcb61eb 678
mustwillza 0:8b94afcb61eb 679 // ************************************************************************************
mustwillza 0:8b94afcb61eb 680 //@}
mustwillza 0:8b94afcb61eb 681
mustwillza 0:8b94afcb61eb 682
mustwillza 0:8b94afcb61eb 683 // ************************************************************************************
mustwillza 0:8b94afcb61eb 684 //! @name Support functions
mustwillza 0:8b94afcb61eb 685 // ************************************************************************************
mustwillza 0:8b94afcb61eb 686 //@{
mustwillza 0:8b94afcb61eb 687
mustwillza 0:8b94afcb61eb 688 /**
mustwillza 0:8b94afcb61eb 689 * Wrapper for MIFARE protocol communication.
mustwillza 0:8b94afcb61eb 690 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
mustwillza 0:8b94afcb61eb 691 *
mustwillza 0:8b94afcb61eb 692 * @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
mustwillza 0:8b94afcb61eb 693 * @param sendLen Number of bytes in sendData.
mustwillza 0:8b94afcb61eb 694 * @param acceptTimeout True => A timeout is also success
mustwillza 0:8b94afcb61eb 695 *
mustwillza 0:8b94afcb61eb 696 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 697 */
mustwillza 0:8b94afcb61eb 698 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
mustwillza 0:8b94afcb61eb 699
mustwillza 0:8b94afcb61eb 700 /**
mustwillza 0:8b94afcb61eb 701 * Translates the SAK (Select Acknowledge) to a PICC type.
mustwillza 0:8b94afcb61eb 702 *
mustwillza 0:8b94afcb61eb 703 * @param sak The SAK byte returned from PICC_Select().
mustwillza 0:8b94afcb61eb 704 *
mustwillza 0:8b94afcb61eb 705 * @return PICC_Type
mustwillza 0:8b94afcb61eb 706 */
mustwillza 0:8b94afcb61eb 707 uint8_t PICC_GetType (uint8_t sak);
mustwillza 0:8b94afcb61eb 708
mustwillza 0:8b94afcb61eb 709 /**
mustwillza 0:8b94afcb61eb 710 * Returns a string pointer to the PICC type name.
mustwillza 0:8b94afcb61eb 711 *
mustwillza 0:8b94afcb61eb 712 * @param type One of the PICC_Type enums.
mustwillza 0:8b94afcb61eb 713 *
mustwillza 0:8b94afcb61eb 714 * @return A string pointer to the PICC type name.
mustwillza 0:8b94afcb61eb 715 */
mustwillza 0:8b94afcb61eb 716 char* PICC_GetTypeName (uint8_t type);
mustwillza 0:8b94afcb61eb 717
mustwillza 0:8b94afcb61eb 718 /**
mustwillza 0:8b94afcb61eb 719 * Returns a string pointer to a status code name.
mustwillza 0:8b94afcb61eb 720 *
mustwillza 0:8b94afcb61eb 721 * @param code One of the StatusCode enums.
mustwillza 0:8b94afcb61eb 722 *
mustwillza 0:8b94afcb61eb 723 * @return A string pointer to a status code name.
mustwillza 0:8b94afcb61eb 724 */
mustwillza 0:8b94afcb61eb 725 char* GetStatusCodeName (uint8_t code);
mustwillza 0:8b94afcb61eb 726
mustwillza 0:8b94afcb61eb 727 /**
mustwillza 0:8b94afcb61eb 728 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
mustwillza 0:8b94afcb61eb 729 *
mustwillza 0:8b94afcb61eb 730 * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
mustwillza 0:8b94afcb61eb 731 * @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
mustwillza 0:8b94afcb61eb 732 * @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
mustwillza 0:8b94afcb61eb 733 * @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
mustwillza 0:8b94afcb61eb 734 * @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
mustwillza 0:8b94afcb61eb 735 */
mustwillza 0:8b94afcb61eb 736 void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
mustwillza 0:8b94afcb61eb 737 uint8_t g0,
mustwillza 0:8b94afcb61eb 738 uint8_t g1,
mustwillza 0:8b94afcb61eb 739 uint8_t g2,
mustwillza 0:8b94afcb61eb 740 uint8_t g3);
mustwillza 0:8b94afcb61eb 741
mustwillza 0:8b94afcb61eb 742 // ************************************************************************************
mustwillza 0:8b94afcb61eb 743 //@}
mustwillza 0:8b94afcb61eb 744
mustwillza 0:8b94afcb61eb 745
mustwillza 0:8b94afcb61eb 746 // ************************************************************************************
mustwillza 0:8b94afcb61eb 747 //! @name Convenience functions - does not add extra functionality
mustwillza 0:8b94afcb61eb 748 // ************************************************************************************
mustwillza 0:8b94afcb61eb 749 //@{
mustwillza 0:8b94afcb61eb 750
mustwillza 0:8b94afcb61eb 751 /**
mustwillza 0:8b94afcb61eb 752 * Returns true if a PICC responds to PICC_CMD_REQA.
mustwillza 0:8b94afcb61eb 753 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
mustwillza 0:8b94afcb61eb 754 *
mustwillza 0:8b94afcb61eb 755 * @return bool
mustwillza 0:8b94afcb61eb 756 */
mustwillza 0:8b94afcb61eb 757 bool PICC_IsNewCardPresent(void);
mustwillza 0:8b94afcb61eb 758
mustwillza 0:8b94afcb61eb 759 /**
mustwillza 0:8b94afcb61eb 760 * Simple wrapper around PICC_Select.
mustwillza 0:8b94afcb61eb 761 * Returns true if a UID could be read.
mustwillza 0:8b94afcb61eb 762 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
mustwillza 0:8b94afcb61eb 763 * The read UID is available in the class variable uid.
mustwillza 0:8b94afcb61eb 764 *
mustwillza 0:8b94afcb61eb 765 * @return bool
mustwillza 0:8b94afcb61eb 766 */
mustwillza 0:8b94afcb61eb 767 bool PICC_ReadCardSerial (void);
mustwillza 0:8b94afcb61eb 768
mustwillza 0:8b94afcb61eb 769 // ************************************************************************************
mustwillza 0:8b94afcb61eb 770 //@}
kantapon501 1:568e35232180 771 uint8_t getRFid(uint8_t);
mustwillza 0:8b94afcb61eb 772
mustwillza 0:8b94afcb61eb 773 private:
mustwillza 0:8b94afcb61eb 774 SPI m_SPI;
mustwillza 0:8b94afcb61eb 775 DigitalOut m_CS;
mustwillza 0:8b94afcb61eb 776 DigitalOut m_RESET;
mustwillza 0:8b94afcb61eb 777
mustwillza 0:8b94afcb61eb 778 /**
mustwillza 0:8b94afcb61eb 779 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
mustwillza 0:8b94afcb61eb 780 *
mustwillza 0:8b94afcb61eb 781 * @param command The command to use
mustwillza 0:8b94afcb61eb 782 * @param blockAddr The block (0-0xff) number.
mustwillza 0:8b94afcb61eb 783 * @param data The data to transfer in step 2
mustwillza 0:8b94afcb61eb 784 *
mustwillza 0:8b94afcb61eb 785 * @return STATUS_OK on success, STATUS_??? otherwise.
mustwillza 0:8b94afcb61eb 786 */
mustwillza 0:8b94afcb61eb 787 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
mustwillza 0:8b94afcb61eb 788 };
mustwillza 0:8b94afcb61eb 789
mustwillza 0:8b94afcb61eb 790 #endif