E&R S3 prime
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BSP_DISCO_L476VG
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n25q128a.h
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00001 /** 00002 ****************************************************************************** 00003 * @file n25q128a.h 00004 * @author MCD Application Team 00005 * @brief This file contains all the description of the N25Q128A QSPI memory. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2015 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __N25Q128A_H 00022 #define __N25Q128A_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 00030 /** @addtogroup BSP 00031 * @{ 00032 */ 00033 00034 /** @addtogroup Components 00035 * @{ 00036 */ 00037 00038 /** @addtogroup n25q128a 00039 * @{ 00040 */ 00041 00042 /** @defgroup N25Q128A_Exported_Types 00043 * @{ 00044 */ 00045 00046 /** 00047 * @} 00048 */ 00049 00050 /** @defgroup N25Q128A_Exported_Constants 00051 * @{ 00052 */ 00053 00054 /** 00055 * @brief N25Q128A Configuration 00056 */ 00057 #define N25Q128A_FLASH_SIZE 0x1000000 /* 128 MBits => 16MBytes */ 00058 #define N25Q128A_SECTOR_SIZE 0x10000 /* 256 sectors of 64KBytes */ 00059 #define N25Q128A_SUBSECTOR_SIZE 0x1000 /* 4096 subsectors of 4kBytes */ 00060 #define N25Q128A_PAGE_SIZE 0x100 /* 65536 pages of 256 bytes */ 00061 00062 #define N25Q128A_DUMMY_CYCLES_READ 8 00063 #define N25Q128A_DUMMY_CYCLES_READ_QUAD 10 00064 00065 #define N25Q128A_BULK_ERASE_MAX_TIME 250000 00066 #define N25Q128A_SECTOR_ERASE_MAX_TIME 3000 00067 #define N25Q128A_SUBSECTOR_ERASE_MAX_TIME 800 00068 00069 /** 00070 * @brief N25Q128A Commands 00071 */ 00072 /* Reset Operations */ 00073 #define RESET_ENABLE_CMD 0x66 00074 #define RESET_MEMORY_CMD 0x99 00075 00076 /* Identification Operations */ 00077 #define READ_ID_CMD 0x9E 00078 #define READ_ID_CMD2 0x9F 00079 #define MULTIPLE_IO_READ_ID_CMD 0xAF 00080 #define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A 00081 00082 /* Read Operations */ 00083 #define READ_CMD 0x03 00084 #define FAST_READ_CMD 0x0B 00085 #define DUAL_OUT_FAST_READ_CMD 0x3B 00086 #define DUAL_INOUT_FAST_READ_CMD 0xBB 00087 #define QUAD_OUT_FAST_READ_CMD 0x6B 00088 #define QUAD_INOUT_FAST_READ_CMD 0xEB 00089 00090 /* Write Operations */ 00091 #define WRITE_ENABLE_CMD 0x06 00092 #define WRITE_DISABLE_CMD 0x04 00093 00094 /* Register Operations */ 00095 #define READ_STATUS_REG_CMD 0x05 00096 #define WRITE_STATUS_REG_CMD 0x01 00097 00098 #define READ_LOCK_REG_CMD 0xE8 00099 #define WRITE_LOCK_REG_CMD 0xE5 00100 00101 #define READ_FLAG_STATUS_REG_CMD 0x70 00102 #define CLEAR_FLAG_STATUS_REG_CMD 0x50 00103 00104 #define READ_NONVOL_CFG_REG_CMD 0xB5 00105 #define WRITE_NONVOL_CFG_REG_CMD 0xB1 00106 00107 #define READ_VOL_CFG_REG_CMD 0x85 00108 #define WRITE_VOL_CFG_REG_CMD 0x81 00109 00110 #define READ_ENHANCED_VOL_CFG_REG_CMD 0x65 00111 #define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61 00112 00113 /* Program Operations */ 00114 #define PAGE_PROG_CMD 0x02 00115 #define DUAL_IN_FAST_PROG_CMD 0xA2 00116 #define EXT_DUAL_IN_FAST_PROG_CMD 0xD2 00117 #define QUAD_IN_FAST_PROG_CMD 0x32 00118 #define EXT_QUAD_IN_FAST_PROG_CMD 0x12 00119 00120 /* Erase Operations */ 00121 #define SUBSECTOR_ERASE_CMD 0x20 00122 #define SECTOR_ERASE_CMD 0xD8 00123 #define BULK_ERASE_CMD 0xC7 00124 00125 #define PROG_ERASE_RESUME_CMD 0x7A 00126 #define PROG_ERASE_SUSPEND_CMD 0x75 00127 00128 /* One-Time Programmable Operations */ 00129 #define READ_OTP_ARRAY_CMD 0x4B 00130 #define PROG_OTP_ARRAY_CMD 0x42 00131 00132 /** 00133 * @brief N25Q128A Registers 00134 */ 00135 /* Status Register */ 00136 #define N25Q128A_SR_WIP ((uint8_t)0x01) /*!< Write in progress */ 00137 #define N25Q128A_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */ 00138 #define N25Q128A_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */ 00139 #define N25Q128A_SR_PRBOTTOM ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom */ 00140 #define N25Q128A_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */ 00141 00142 /* Nonvolatile Configuration Register */ 00143 #define N25Q128A_NVCR_LOCK ((uint16_t)0x0001) /*!< Lock nonvolatile configuration register */ 00144 #define N25Q128A_NVCR_DUAL ((uint16_t)0x0004) /*!< Dual I/O protocol */ 00145 #define N25Q128A_NVCR_QUAB ((uint16_t)0x0008) /*!< Quad I/O protocol */ 00146 #define N25Q128A_NVCR_RH ((uint16_t)0x0010) /*!< Reset/hold */ 00147 #define N25Q128A_NVCR_ODS ((uint16_t)0x01C0) /*!< Output driver strength */ 00148 #define N25Q128A_NVCR_XIP ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */ 00149 #define N25Q128A_NVCR_NB_DUMMY ((uint16_t)0xF000) /*!< Number of dummy clock cycles */ 00150 00151 /* Volatile Configuration Register */ 00152 #define N25Q128A_VCR_WRAP ((uint8_t)0x03) /*!< Wrap */ 00153 #define N25Q128A_VCR_XIP ((uint8_t)0x08) /*!< XIP */ 00154 #define N25Q128A_VCR_NB_DUMMY ((uint8_t)0xF0) /*!< Number of dummy clock cycles */ 00155 00156 /* Enhanced Volatile Configuration Register */ 00157 #define N25Q128A_EVCR_ODS ((uint8_t)0x07) /*!< Output driver strength */ 00158 #define N25Q128A_EVCR_VPPA ((uint8_t)0x08) /*!< Vpp accelerator */ 00159 #define N25Q128A_EVCR_RH ((uint8_t)0x10) /*!< Reset/hold */ 00160 #define N25Q128A_EVCR_DUAL ((uint8_t)0x40) /*!< Dual I/O protocol */ 00161 #define N25Q128A_EVCR_QUAD ((uint8_t)0x80) /*!< Quad I/O protocol */ 00162 00163 /* Flag Status Register */ 00164 #define N25Q128A_FSR_PRERR ((uint8_t)0x02) /*!< Protection error */ 00165 #define N25Q128A_FSR_PGSUS ((uint8_t)0x04) /*!< Program operation suspended */ 00166 #define N25Q128A_FSR_VPPERR ((uint8_t)0x08) /*!< Invalid voltage during program or erase */ 00167 #define N25Q128A_FSR_PGERR ((uint8_t)0x10) /*!< Program error */ 00168 #define N25Q128A_FSR_ERERR ((uint8_t)0x20) /*!< Erase error */ 00169 #define N25Q128A_FSR_ERSUS ((uint8_t)0x40) /*!< Erase operation suspended */ 00170 #define N25Q128A_FSR_READY ((uint8_t)0x80) /*!< Ready or command in progress */ 00171 00172 /** 00173 * @} 00174 */ 00175 00176 /** @defgroup N25Q128A_Exported_Functions 00177 * @{ 00178 */ 00179 /** 00180 * @} 00181 */ 00182 00183 /** 00184 * @} 00185 */ 00186 00187 /** 00188 * @} 00189 */ 00190 00191 /** 00192 * @} 00193 */ 00194 00195 #ifdef __cplusplus 00196 } 00197 #endif 00198 00199 #endif /* __N25Q128A_H */ 00200 00201 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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