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targets/TARGET_Maxim/TARGET_MAX32630/mxc/uart.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /**
be_bryan 0:b74591d5ab33 2 * @file
be_bryan 0:b74591d5ab33 3 * @brief This file contains the function implementations for the UART
be_bryan 0:b74591d5ab33 4 * serial communications peripheral module.
be_bryan 0:b74591d5ab33 5 */
be_bryan 0:b74591d5ab33 6 /* *****************************************************************************
be_bryan 0:b74591d5ab33 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
be_bryan 0:b74591d5ab33 8 *
be_bryan 0:b74591d5ab33 9 * Permission is hereby granted, free of charge, to any person obtaining a
be_bryan 0:b74591d5ab33 10 * copy of this software and associated documentation files (the "Software"),
be_bryan 0:b74591d5ab33 11 * to deal in the Software without restriction, including without limitation
be_bryan 0:b74591d5ab33 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
be_bryan 0:b74591d5ab33 13 * and/or sell copies of the Software, and to permit persons to whom the
be_bryan 0:b74591d5ab33 14 * Software is furnished to do so, subject to the following conditions:
be_bryan 0:b74591d5ab33 15 *
be_bryan 0:b74591d5ab33 16 * The above copyright notice and this permission notice shall be included
be_bryan 0:b74591d5ab33 17 * in all copies or substantial portions of the Software.
be_bryan 0:b74591d5ab33 18 *
be_bryan 0:b74591d5ab33 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
be_bryan 0:b74591d5ab33 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
be_bryan 0:b74591d5ab33 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
be_bryan 0:b74591d5ab33 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
be_bryan 0:b74591d5ab33 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
be_bryan 0:b74591d5ab33 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
be_bryan 0:b74591d5ab33 25 * OTHER DEALINGS IN THE SOFTWARE.
be_bryan 0:b74591d5ab33 26 *
be_bryan 0:b74591d5ab33 27 * Except as contained in this notice, the name of Maxim Integrated
be_bryan 0:b74591d5ab33 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
be_bryan 0:b74591d5ab33 29 * Products, Inc. Branding Policy.
be_bryan 0:b74591d5ab33 30 *
be_bryan 0:b74591d5ab33 31 * The mere transfer of this software does not imply any licenses
be_bryan 0:b74591d5ab33 32 * of trade secrets, proprietary technology, copyrights, patents,
be_bryan 0:b74591d5ab33 33 * trademarks, maskwork rights, or any other form of intellectual
be_bryan 0:b74591d5ab33 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
be_bryan 0:b74591d5ab33 35 * ownership rights.
be_bryan 0:b74591d5ab33 36 *
be_bryan 0:b74591d5ab33 37 * $Date: 2016-09-08 17:00:36 -0500 (Thu, 08 Sep 2016) $
be_bryan 0:b74591d5ab33 38 * $Revision: 24319 $
be_bryan 0:b74591d5ab33 39 *
be_bryan 0:b74591d5ab33 40 **************************************************************************** */
be_bryan 0:b74591d5ab33 41
be_bryan 0:b74591d5ab33 42 /* **** Includes **** */
be_bryan 0:b74591d5ab33 43 #include <string.h>
be_bryan 0:b74591d5ab33 44 #include "mxc_config.h"
be_bryan 0:b74591d5ab33 45 #include "mxc_assert.h"
be_bryan 0:b74591d5ab33 46 #include "mxc_lock.h"
be_bryan 0:b74591d5ab33 47 #include "mxc_sys.h"
be_bryan 0:b74591d5ab33 48 #include "uart.h"
be_bryan 0:b74591d5ab33 49
be_bryan 0:b74591d5ab33 50 /**
be_bryan 0:b74591d5ab33 51 * @ingroup uart_comm
be_bryan 0:b74591d5ab33 52 * @{
be_bryan 0:b74591d5ab33 53 */
be_bryan 0:b74591d5ab33 54 /* **** Definitions **** */
be_bryan 0:b74591d5ab33 55 ///@cond
be_bryan 0:b74591d5ab33 56 #define UART_ERRORS (MXC_F_UART_INTEN_RX_FIFO_OVERFLOW | \
be_bryan 0:b74591d5ab33 57 MXC_F_UART_INTEN_RX_FRAMING_ERR | \
be_bryan 0:b74591d5ab33 58 MXC_F_UART_INTEN_RX_PARITY_ERR)
be_bryan 0:b74591d5ab33 59
be_bryan 0:b74591d5ab33 60 #define UART_READ_INTS (MXC_F_UART_INTEN_RX_FIFO_AF | \
be_bryan 0:b74591d5ab33 61 MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | \
be_bryan 0:b74591d5ab33 62 MXC_F_UART_INTEN_RX_STALLED | \
be_bryan 0:b74591d5ab33 63 UART_ERRORS)
be_bryan 0:b74591d5ab33 64
be_bryan 0:b74591d5ab33 65 #define UART_WRITE_INTS (MXC_F_UART_INTEN_TX_UNSTALLED | \
be_bryan 0:b74591d5ab33 66 MXC_F_UART_INTEN_TX_FIFO_AE)
be_bryan 0:b74591d5ab33 67
be_bryan 0:b74591d5ab33 68 #define UART_RXFIFO_USABLE (MXC_UART_FIFO_DEPTH-3)
be_bryan 0:b74591d5ab33 69 ///@endcond
be_bryan 0:b74591d5ab33 70 //
be_bryan 0:b74591d5ab33 71 /* **** Globals **** */
be_bryan 0:b74591d5ab33 72
be_bryan 0:b74591d5ab33 73 // Saves the state of the non-blocking read requests
be_bryan 0:b74591d5ab33 74 static uart_req_t *rx_states[MXC_CFG_UART_INSTANCES];
be_bryan 0:b74591d5ab33 75
be_bryan 0:b74591d5ab33 76 // Saves the state of the non-blocking write requests
be_bryan 0:b74591d5ab33 77 static uart_req_t *tx_states[MXC_CFG_UART_INSTANCES];
be_bryan 0:b74591d5ab33 78
be_bryan 0:b74591d5ab33 79 /* **** Functions **** */
be_bryan 0:b74591d5ab33 80 static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num);
be_bryan 0:b74591d5ab33 81 static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
be_bryan 0:b74591d5ab33 82 uint32_t flags);
be_bryan 0:b74591d5ab33 83
be_bryan 0:b74591d5ab33 84 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 85 int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t *sys_cfg)
be_bryan 0:b74591d5ab33 86 {
be_bryan 0:b74591d5ab33 87 int err;
be_bryan 0:b74591d5ab33 88 int uart_num;
be_bryan 0:b74591d5ab33 89 uint32_t uart_clk;
be_bryan 0:b74591d5ab33 90 uint8_t baud_shift;
be_bryan 0:b74591d5ab33 91 uint16_t baud_div;
be_bryan 0:b74591d5ab33 92 uint32_t baud, diff_baud;
be_bryan 0:b74591d5ab33 93 uint32_t baud_1, diff_baud_1;
be_bryan 0:b74591d5ab33 94
be_bryan 0:b74591d5ab33 95 // Check the input parameters
be_bryan 0:b74591d5ab33 96 uart_num = MXC_UART_GET_IDX(uart);
be_bryan 0:b74591d5ab33 97 MXC_ASSERT(uart_num >= 0);
be_bryan 0:b74591d5ab33 98
be_bryan 0:b74591d5ab33 99 // Set system level configurations
be_bryan 0:b74591d5ab33 100 if(sys_cfg != NULL) {
be_bryan 0:b74591d5ab33 101 if ((err = SYS_UART_Init(uart, cfg, sys_cfg)) != E_NO_ERROR) {
be_bryan 0:b74591d5ab33 102 return err;
be_bryan 0:b74591d5ab33 103 }
be_bryan 0:b74591d5ab33 104 }
be_bryan 0:b74591d5ab33 105
be_bryan 0:b74591d5ab33 106 // Initialize state pointers
be_bryan 0:b74591d5ab33 107 rx_states[uart_num] = NULL;
be_bryan 0:b74591d5ab33 108 tx_states[uart_num] = NULL;
be_bryan 0:b74591d5ab33 109
be_bryan 0:b74591d5ab33 110 // Drain FIFOs and enable UART
be_bryan 0:b74591d5ab33 111 uart->ctrl = 0;
be_bryan 0:b74591d5ab33 112 uart->ctrl = (MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN |
be_bryan 0:b74591d5ab33 113 MXC_F_UART_CTRL_RX_FIFO_EN |
be_bryan 0:b74591d5ab33 114 (UART_RXFIFO_USABLE << MXC_F_UART_CTRL_RTS_LEVEL_POS));
be_bryan 0:b74591d5ab33 115
be_bryan 0:b74591d5ab33 116 // Configure data size, stop bit, parity, cts, and rts
be_bryan 0:b74591d5ab33 117 uart->ctrl |= ((cfg->size << MXC_F_UART_CTRL_DATA_SIZE_POS) |
be_bryan 0:b74591d5ab33 118 (cfg->extra_stop << MXC_F_UART_CTRL_EXTRA_STOP_POS) |
be_bryan 0:b74591d5ab33 119 (cfg->parity << MXC_F_UART_CTRL_PARITY_POS) |
be_bryan 0:b74591d5ab33 120 (cfg->cts << MXC_F_UART_CTRL_CTS_EN_POS) |
be_bryan 0:b74591d5ab33 121 (cfg->rts << MXC_F_UART_CTRL_RTS_EN_POS));
be_bryan 0:b74591d5ab33 122
be_bryan 0:b74591d5ab33 123 // Configure the baud rate and divisor
be_bryan 0:b74591d5ab33 124 uart_clk = SYS_UART_GetFreq(uart);
be_bryan 0:b74591d5ab33 125 MXC_ASSERT(uart_clk > 0);
be_bryan 0:b74591d5ab33 126
be_bryan 0:b74591d5ab33 127 baud_shift = 2;
be_bryan 0:b74591d5ab33 128 baud_div = (uart_clk / (cfg->baud * 4));
be_bryan 0:b74591d5ab33 129
be_bryan 0:b74591d5ab33 130 // Can not support higher frequencies
be_bryan 0:b74591d5ab33 131 if(!baud_div) {
be_bryan 0:b74591d5ab33 132 return E_NOT_SUPPORTED;
be_bryan 0:b74591d5ab33 133 }
be_bryan 0:b74591d5ab33 134
be_bryan 0:b74591d5ab33 135 // Decrease the divisor if baud_div is overflowing
be_bryan 0:b74591d5ab33 136 while(baud_div > 0xFF) {
be_bryan 0:b74591d5ab33 137 if(baud_shift == 0) {
be_bryan 0:b74591d5ab33 138 return E_NOT_SUPPORTED;
be_bryan 0:b74591d5ab33 139 }
be_bryan 0:b74591d5ab33 140 baud_shift--;
be_bryan 0:b74591d5ab33 141 baud_div = (uart_clk / (cfg->baud * (16 >> baud_shift)));
be_bryan 0:b74591d5ab33 142 }
be_bryan 0:b74591d5ab33 143
be_bryan 0:b74591d5ab33 144 // Adjust baud_div so we don't overflow with the calculations below
be_bryan 0:b74591d5ab33 145 if(baud_div == 0xFF) {
be_bryan 0:b74591d5ab33 146 baud_div = 0xFE;
be_bryan 0:b74591d5ab33 147 }
be_bryan 0:b74591d5ab33 148 if(baud_div == 0) {
be_bryan 0:b74591d5ab33 149 baud_div = 1;
be_bryan 0:b74591d5ab33 150 }
be_bryan 0:b74591d5ab33 151
be_bryan 0:b74591d5ab33 152 // Figure out if the truncation increased the error
be_bryan 0:b74591d5ab33 153 baud = (uart_clk / (baud_div * (16 >> baud_shift)));
be_bryan 0:b74591d5ab33 154 baud_1 = (uart_clk / ((baud_div+1) * (16 >> baud_shift)));
be_bryan 0:b74591d5ab33 155
be_bryan 0:b74591d5ab33 156 if(cfg->baud > baud) {
be_bryan 0:b74591d5ab33 157 diff_baud = cfg->baud - baud;
be_bryan 0:b74591d5ab33 158 } else {
be_bryan 0:b74591d5ab33 159 diff_baud = baud - cfg->baud;
be_bryan 0:b74591d5ab33 160 }
be_bryan 0:b74591d5ab33 161
be_bryan 0:b74591d5ab33 162 if(cfg->baud > baud_1) {
be_bryan 0:b74591d5ab33 163 diff_baud_1 = cfg->baud - baud_1;
be_bryan 0:b74591d5ab33 164 } else {
be_bryan 0:b74591d5ab33 165 diff_baud_1 = baud_1 - cfg->baud;
be_bryan 0:b74591d5ab33 166 }
be_bryan 0:b74591d5ab33 167
be_bryan 0:b74591d5ab33 168 if(diff_baud < diff_baud_1) {
be_bryan 0:b74591d5ab33 169 uart->baud = ((baud_div & MXC_F_UART_BAUD_BAUD_DIVISOR) |
be_bryan 0:b74591d5ab33 170 (baud_shift << MXC_F_UART_BAUD_BAUD_MODE_POS));
be_bryan 0:b74591d5ab33 171 } else {
be_bryan 0:b74591d5ab33 172 uart->baud = (((baud_div+1) & MXC_F_UART_BAUD_BAUD_DIVISOR) |
be_bryan 0:b74591d5ab33 173 (baud_shift << MXC_F_UART_BAUD_BAUD_MODE_POS));
be_bryan 0:b74591d5ab33 174 }
be_bryan 0:b74591d5ab33 175
be_bryan 0:b74591d5ab33 176 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 177 }
be_bryan 0:b74591d5ab33 178
be_bryan 0:b74591d5ab33 179 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 180 int UART_Shutdown(mxc_uart_regs_t *uart)
be_bryan 0:b74591d5ab33 181 {
be_bryan 0:b74591d5ab33 182 int uart_num, err;
be_bryan 0:b74591d5ab33 183 uart_req_t *temp_req;
be_bryan 0:b74591d5ab33 184
be_bryan 0:b74591d5ab33 185 uart_num = MXC_UART_GET_IDX(uart);
be_bryan 0:b74591d5ab33 186 MXC_ASSERT(uart_num >= 0);
be_bryan 0:b74591d5ab33 187
be_bryan 0:b74591d5ab33 188 // Disable and clear interrupts
be_bryan 0:b74591d5ab33 189 uart->inten = 0;
be_bryan 0:b74591d5ab33 190 uart->intfl = uart->intfl;
be_bryan 0:b74591d5ab33 191
be_bryan 0:b74591d5ab33 192 // Disable UART and FIFOS
be_bryan 0:b74591d5ab33 193 uart->ctrl &= ~(MXC_F_UART_CTRL_UART_EN | MXC_F_UART_CTRL_TX_FIFO_EN |
be_bryan 0:b74591d5ab33 194 MXC_F_UART_CTRL_RX_FIFO_EN);
be_bryan 0:b74591d5ab33 195
be_bryan 0:b74591d5ab33 196 // Call all of the pending callbacks for this UART
be_bryan 0:b74591d5ab33 197 if(rx_states[uart_num] != NULL) {
be_bryan 0:b74591d5ab33 198
be_bryan 0:b74591d5ab33 199 // Save the request
be_bryan 0:b74591d5ab33 200 temp_req = rx_states[uart_num];
be_bryan 0:b74591d5ab33 201
be_bryan 0:b74591d5ab33 202 // Unlock this UART to read
be_bryan 0:b74591d5ab33 203 mxc_free_lock((uint32_t*)&rx_states[uart_num]);
be_bryan 0:b74591d5ab33 204
be_bryan 0:b74591d5ab33 205 // Callback if not NULL
be_bryan 0:b74591d5ab33 206 if(temp_req->callback != NULL) {
be_bryan 0:b74591d5ab33 207 temp_req->callback(temp_req, E_SHUTDOWN);
be_bryan 0:b74591d5ab33 208 }
be_bryan 0:b74591d5ab33 209 }
be_bryan 0:b74591d5ab33 210
be_bryan 0:b74591d5ab33 211 if(tx_states[uart_num] != NULL) {
be_bryan 0:b74591d5ab33 212
be_bryan 0:b74591d5ab33 213 // Save the request
be_bryan 0:b74591d5ab33 214 temp_req = tx_states[uart_num];
be_bryan 0:b74591d5ab33 215
be_bryan 0:b74591d5ab33 216 // Unlock this UART to write
be_bryan 0:b74591d5ab33 217 mxc_free_lock((uint32_t*)&tx_states[uart_num]);
be_bryan 0:b74591d5ab33 218
be_bryan 0:b74591d5ab33 219 // Callback if not NULL
be_bryan 0:b74591d5ab33 220 if(temp_req->callback != NULL) {
be_bryan 0:b74591d5ab33 221 temp_req->callback(temp_req, E_SHUTDOWN);
be_bryan 0:b74591d5ab33 222 }
be_bryan 0:b74591d5ab33 223 }
be_bryan 0:b74591d5ab33 224
be_bryan 0:b74591d5ab33 225 // Clears system level configurations
be_bryan 0:b74591d5ab33 226 if ((err = SYS_UART_Shutdown(uart)) != E_NO_ERROR) {
be_bryan 0:b74591d5ab33 227 return err;
be_bryan 0:b74591d5ab33 228 }
be_bryan 0:b74591d5ab33 229
be_bryan 0:b74591d5ab33 230 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 231 }
be_bryan 0:b74591d5ab33 232
be_bryan 0:b74591d5ab33 233 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 234 int UART_Write(mxc_uart_regs_t *uart, uint8_t* data, int len)
be_bryan 0:b74591d5ab33 235 {
be_bryan 0:b74591d5ab33 236 int num, uart_num;
be_bryan 0:b74591d5ab33 237 mxc_uart_fifo_regs_t *fifo;
be_bryan 0:b74591d5ab33 238
be_bryan 0:b74591d5ab33 239 uart_num = MXC_UART_GET_IDX(uart);
be_bryan 0:b74591d5ab33 240 MXC_ASSERT(uart_num >= 0);
be_bryan 0:b74591d5ab33 241
be_bryan 0:b74591d5ab33 242 if(data == NULL) {
be_bryan 0:b74591d5ab33 243 return E_NULL_PTR;
be_bryan 0:b74591d5ab33 244 }
be_bryan 0:b74591d5ab33 245
be_bryan 0:b74591d5ab33 246 // Make sure the UART has been initialized
be_bryan 0:b74591d5ab33 247 if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
be_bryan 0:b74591d5ab33 248 return E_UNINITIALIZED;
be_bryan 0:b74591d5ab33 249 }
be_bryan 0:b74591d5ab33 250
be_bryan 0:b74591d5ab33 251 if(!(len > 0)) {
be_bryan 0:b74591d5ab33 252 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 253 }
be_bryan 0:b74591d5ab33 254
be_bryan 0:b74591d5ab33 255 // Lock this UART from writing
be_bryan 0:b74591d5ab33 256 while(mxc_get_lock((uint32_t*)&tx_states[uart_num], 1) != E_NO_ERROR) {}
be_bryan 0:b74591d5ab33 257
be_bryan 0:b74591d5ab33 258 // Get the FIFO for this UART
be_bryan 0:b74591d5ab33 259 fifo = MXC_UART_GET_FIFO(uart_num);
be_bryan 0:b74591d5ab33 260
be_bryan 0:b74591d5ab33 261 num = 0;
be_bryan 0:b74591d5ab33 262
be_bryan 0:b74591d5ab33 263 while(num < len) {
be_bryan 0:b74591d5ab33 264
be_bryan 0:b74591d5ab33 265 // Wait for TXFIFO to not be full
be_bryan 0:b74591d5ab33 266 while((uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) ==
be_bryan 0:b74591d5ab33 267 MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) {}
be_bryan 0:b74591d5ab33 268
be_bryan 0:b74591d5ab33 269 // Write the data to the FIFO
be_bryan 0:b74591d5ab33 270 #if(MXC_UART_REV == 0)
be_bryan 0:b74591d5ab33 271 uart->intfl = MXC_F_UART_INTFL_TX_DONE;
be_bryan 0:b74591d5ab33 272 #endif
be_bryan 0:b74591d5ab33 273 fifo->tx = data[num++];
be_bryan 0:b74591d5ab33 274 }
be_bryan 0:b74591d5ab33 275
be_bryan 0:b74591d5ab33 276 // Unlock this UART to write
be_bryan 0:b74591d5ab33 277 mxc_free_lock((uint32_t*)&tx_states[uart_num]);
be_bryan 0:b74591d5ab33 278
be_bryan 0:b74591d5ab33 279 return num;
be_bryan 0:b74591d5ab33 280 }
be_bryan 0:b74591d5ab33 281
be_bryan 0:b74591d5ab33 282 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 283 int UART_Read(mxc_uart_regs_t *uart, uint8_t* data, int len, int *num)
be_bryan 0:b74591d5ab33 284 {
be_bryan 0:b74591d5ab33 285 int num_local, remain, uart_num;
be_bryan 0:b74591d5ab33 286 mxc_uart_fifo_regs_t *fifo;
be_bryan 0:b74591d5ab33 287
be_bryan 0:b74591d5ab33 288 uart_num = MXC_UART_GET_IDX(uart);
be_bryan 0:b74591d5ab33 289 MXC_ASSERT(uart_num >= 0);
be_bryan 0:b74591d5ab33 290
be_bryan 0:b74591d5ab33 291 if(data == NULL) {
be_bryan 0:b74591d5ab33 292 return E_NULL_PTR;
be_bryan 0:b74591d5ab33 293 }
be_bryan 0:b74591d5ab33 294
be_bryan 0:b74591d5ab33 295 // Make sure the UART has been initialized
be_bryan 0:b74591d5ab33 296 if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
be_bryan 0:b74591d5ab33 297 return E_UNINITIALIZED;
be_bryan 0:b74591d5ab33 298 }
be_bryan 0:b74591d5ab33 299
be_bryan 0:b74591d5ab33 300 if(!(len > 0)) {
be_bryan 0:b74591d5ab33 301 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 302 }
be_bryan 0:b74591d5ab33 303
be_bryan 0:b74591d5ab33 304 // Lock this UART from reading
be_bryan 0:b74591d5ab33 305 while(mxc_get_lock((uint32_t*)&rx_states[uart_num], 1) != E_NO_ERROR) {}
be_bryan 0:b74591d5ab33 306
be_bryan 0:b74591d5ab33 307 // Get the FIFO for this UART
be_bryan 0:b74591d5ab33 308 fifo = MXC_UART_GET_FIFO(uart_num);
be_bryan 0:b74591d5ab33 309
be_bryan 0:b74591d5ab33 310 num_local = 0;
be_bryan 0:b74591d5ab33 311 remain = len;
be_bryan 0:b74591d5ab33 312 while(remain) {
be_bryan 0:b74591d5ab33 313
be_bryan 0:b74591d5ab33 314 // Save the data in the FIFO
be_bryan 0:b74591d5ab33 315 while((uart->rx_fifo_ctrl & MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY) && remain) {
be_bryan 0:b74591d5ab33 316 data[num_local] = fifo->rx;
be_bryan 0:b74591d5ab33 317 num_local++;
be_bryan 0:b74591d5ab33 318 remain--;
be_bryan 0:b74591d5ab33 319 }
be_bryan 0:b74591d5ab33 320
be_bryan 0:b74591d5ab33 321 // Break if there is an error
be_bryan 0:b74591d5ab33 322 if(uart->intfl & UART_ERRORS) {
be_bryan 0:b74591d5ab33 323 break;
be_bryan 0:b74591d5ab33 324 }
be_bryan 0:b74591d5ab33 325 }
be_bryan 0:b74591d5ab33 326
be_bryan 0:b74591d5ab33 327 // Save the number of bytes read if pointer is valid
be_bryan 0:b74591d5ab33 328 if(num != NULL) {
be_bryan 0:b74591d5ab33 329 *num = num_local;
be_bryan 0:b74591d5ab33 330 }
be_bryan 0:b74591d5ab33 331
be_bryan 0:b74591d5ab33 332 // Check for errors
be_bryan 0:b74591d5ab33 333 if(uart->intfl & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
be_bryan 0:b74591d5ab33 334
be_bryan 0:b74591d5ab33 335 // Clear errors and return error code
be_bryan 0:b74591d5ab33 336 uart->intfl = UART_ERRORS;
be_bryan 0:b74591d5ab33 337
be_bryan 0:b74591d5ab33 338
be_bryan 0:b74591d5ab33 339 // Unlock this UART to read
be_bryan 0:b74591d5ab33 340 mxc_free_lock((uint32_t*)&rx_states[uart_num]);
be_bryan 0:b74591d5ab33 341
be_bryan 0:b74591d5ab33 342 return E_OVERFLOW;
be_bryan 0:b74591d5ab33 343
be_bryan 0:b74591d5ab33 344 } else if(uart->intfl & (MXC_F_UART_INTFL_RX_FRAMING_ERR |
be_bryan 0:b74591d5ab33 345 MXC_F_UART_INTFL_RX_PARITY_ERR)) {
be_bryan 0:b74591d5ab33 346
be_bryan 0:b74591d5ab33 347 // Clear errors and return error code
be_bryan 0:b74591d5ab33 348 uart->intfl = UART_ERRORS;
be_bryan 0:b74591d5ab33 349
be_bryan 0:b74591d5ab33 350
be_bryan 0:b74591d5ab33 351 // Unlock this UART to read
be_bryan 0:b74591d5ab33 352 mxc_free_lock((uint32_t*)&rx_states[uart_num]);
be_bryan 0:b74591d5ab33 353
be_bryan 0:b74591d5ab33 354 return E_COMM_ERR;
be_bryan 0:b74591d5ab33 355 }
be_bryan 0:b74591d5ab33 356
be_bryan 0:b74591d5ab33 357 // Unlock this UART to read
be_bryan 0:b74591d5ab33 358 mxc_free_lock((uint32_t*)&rx_states[uart_num]);
be_bryan 0:b74591d5ab33 359
be_bryan 0:b74591d5ab33 360 return num_local;
be_bryan 0:b74591d5ab33 361 }
be_bryan 0:b74591d5ab33 362
be_bryan 0:b74591d5ab33 363 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 364 int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req)
be_bryan 0:b74591d5ab33 365 {
be_bryan 0:b74591d5ab33 366 int uart_num = MXC_UART_GET_IDX(uart);
be_bryan 0:b74591d5ab33 367 MXC_ASSERT(uart_num >= 0);
be_bryan 0:b74591d5ab33 368
be_bryan 0:b74591d5ab33 369 // Check the input parameters
be_bryan 0:b74591d5ab33 370 if(req->data == NULL) {
be_bryan 0:b74591d5ab33 371 return E_NULL_PTR;
be_bryan 0:b74591d5ab33 372 }
be_bryan 0:b74591d5ab33 373
be_bryan 0:b74591d5ab33 374 // Make sure the UART has been initialized
be_bryan 0:b74591d5ab33 375 if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
be_bryan 0:b74591d5ab33 376 return E_UNINITIALIZED;
be_bryan 0:b74591d5ab33 377 }
be_bryan 0:b74591d5ab33 378
be_bryan 0:b74591d5ab33 379 if(!(req->len > 0)) {
be_bryan 0:b74591d5ab33 380 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 381 }
be_bryan 0:b74591d5ab33 382
be_bryan 0:b74591d5ab33 383 // Attempt to register this write request
be_bryan 0:b74591d5ab33 384 if(mxc_get_lock((uint32_t*)&tx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
be_bryan 0:b74591d5ab33 385 return E_BUSY;
be_bryan 0:b74591d5ab33 386 }
be_bryan 0:b74591d5ab33 387
be_bryan 0:b74591d5ab33 388 // Clear the number of bytes counter
be_bryan 0:b74591d5ab33 389 req->num = 0;
be_bryan 0:b74591d5ab33 390
be_bryan 0:b74591d5ab33 391 // Start the write
be_bryan 0:b74591d5ab33 392 UART_WriteHandler(uart, req, uart_num);
be_bryan 0:b74591d5ab33 393
be_bryan 0:b74591d5ab33 394 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 395 }
be_bryan 0:b74591d5ab33 396
be_bryan 0:b74591d5ab33 397 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 398 int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req)
be_bryan 0:b74591d5ab33 399 {
be_bryan 0:b74591d5ab33 400 int uart_num;
be_bryan 0:b74591d5ab33 401 uint32_t flags;
be_bryan 0:b74591d5ab33 402
be_bryan 0:b74591d5ab33 403 uart_num = MXC_UART_GET_IDX(uart);
be_bryan 0:b74591d5ab33 404 MXC_ASSERT(uart_num >= 0);
be_bryan 0:b74591d5ab33 405
be_bryan 0:b74591d5ab33 406 if(req->data == NULL) {
be_bryan 0:b74591d5ab33 407 return E_NULL_PTR;
be_bryan 0:b74591d5ab33 408 }
be_bryan 0:b74591d5ab33 409
be_bryan 0:b74591d5ab33 410 // Make sure the UART has been initialized
be_bryan 0:b74591d5ab33 411 if(!(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
be_bryan 0:b74591d5ab33 412 return E_UNINITIALIZED;
be_bryan 0:b74591d5ab33 413 }
be_bryan 0:b74591d5ab33 414
be_bryan 0:b74591d5ab33 415 if(!(req->len > 0)) {
be_bryan 0:b74591d5ab33 416 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 417 }
be_bryan 0:b74591d5ab33 418
be_bryan 0:b74591d5ab33 419 // Attempt to register this write request
be_bryan 0:b74591d5ab33 420 if(mxc_get_lock((uint32_t*)&rx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
be_bryan 0:b74591d5ab33 421 return E_BUSY;
be_bryan 0:b74591d5ab33 422 }
be_bryan 0:b74591d5ab33 423
be_bryan 0:b74591d5ab33 424 // Clear the number of bytes counter
be_bryan 0:b74591d5ab33 425 req->num = 0;
be_bryan 0:b74591d5ab33 426
be_bryan 0:b74591d5ab33 427 // Start the read
be_bryan 0:b74591d5ab33 428 flags = uart->intfl;
be_bryan 0:b74591d5ab33 429 uart->intfl = flags;
be_bryan 0:b74591d5ab33 430 UART_ReadHandler(uart, req, uart_num, flags);
be_bryan 0:b74591d5ab33 431
be_bryan 0:b74591d5ab33 432 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 433 }
be_bryan 0:b74591d5ab33 434
be_bryan 0:b74591d5ab33 435 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 436 int UART_AbortAsync(uart_req_t *req)
be_bryan 0:b74591d5ab33 437 {
be_bryan 0:b74591d5ab33 438 int uart_num;
be_bryan 0:b74591d5ab33 439
be_bryan 0:b74591d5ab33 440 // Figure out if this was a read or write request, find the request, set to NULL
be_bryan 0:b74591d5ab33 441 for(uart_num = 0; uart_num < MXC_CFG_UART_INSTANCES; uart_num++) {
be_bryan 0:b74591d5ab33 442 if(req == rx_states[uart_num]) {
be_bryan 0:b74591d5ab33 443
be_bryan 0:b74591d5ab33 444 // Disable read interrupts, clear flags.
be_bryan 0:b74591d5ab33 445 MXC_UART_GET_UART(uart_num)->inten &= ~UART_READ_INTS;
be_bryan 0:b74591d5ab33 446 MXC_UART_GET_UART(uart_num)->intfl = UART_READ_INTS;
be_bryan 0:b74591d5ab33 447
be_bryan 0:b74591d5ab33 448 // Unlock this UART to read
be_bryan 0:b74591d5ab33 449 mxc_free_lock((uint32_t*)&rx_states[uart_num]);
be_bryan 0:b74591d5ab33 450
be_bryan 0:b74591d5ab33 451 // Callback if not NULL
be_bryan 0:b74591d5ab33 452 if(req->callback != NULL) {
be_bryan 0:b74591d5ab33 453 req->callback(req, E_ABORT);
be_bryan 0:b74591d5ab33 454 }
be_bryan 0:b74591d5ab33 455
be_bryan 0:b74591d5ab33 456 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 457 }
be_bryan 0:b74591d5ab33 458
be_bryan 0:b74591d5ab33 459 if(req == tx_states[uart_num]) {
be_bryan 0:b74591d5ab33 460
be_bryan 0:b74591d5ab33 461 // Disable write interrupts, clear flags.
be_bryan 0:b74591d5ab33 462 MXC_UART_GET_UART(uart_num)->inten &= ~(UART_WRITE_INTS);
be_bryan 0:b74591d5ab33 463 MXC_UART_GET_UART(uart_num)->intfl = UART_WRITE_INTS;
be_bryan 0:b74591d5ab33 464
be_bryan 0:b74591d5ab33 465 // Unlock this UART to write
be_bryan 0:b74591d5ab33 466 mxc_free_lock((uint32_t*)&tx_states[uart_num]);
be_bryan 0:b74591d5ab33 467
be_bryan 0:b74591d5ab33 468 // Callback if not NULL
be_bryan 0:b74591d5ab33 469 if(req->callback != NULL) {
be_bryan 0:b74591d5ab33 470 req->callback(req, E_ABORT);
be_bryan 0:b74591d5ab33 471 }
be_bryan 0:b74591d5ab33 472
be_bryan 0:b74591d5ab33 473 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 474 }
be_bryan 0:b74591d5ab33 475 }
be_bryan 0:b74591d5ab33 476
be_bryan 0:b74591d5ab33 477 return E_BAD_PARAM;
be_bryan 0:b74591d5ab33 478 }
be_bryan 0:b74591d5ab33 479
be_bryan 0:b74591d5ab33 480 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 481 void UART_Handler(mxc_uart_regs_t *uart)
be_bryan 0:b74591d5ab33 482 {
be_bryan 0:b74591d5ab33 483 int uart_num;
be_bryan 0:b74591d5ab33 484 uint32_t flags;
be_bryan 0:b74591d5ab33 485
be_bryan 0:b74591d5ab33 486 uart_num = MXC_UART_GET_IDX(uart);
be_bryan 0:b74591d5ab33 487 MXC_ASSERT(uart_num >= 0);
be_bryan 0:b74591d5ab33 488
be_bryan 0:b74591d5ab33 489 flags = uart->intfl;
be_bryan 0:b74591d5ab33 490 uart->intfl = flags;
be_bryan 0:b74591d5ab33 491
be_bryan 0:b74591d5ab33 492 // Figure out if this UART has an active Read request
be_bryan 0:b74591d5ab33 493 if((rx_states[uart_num] != NULL) && (flags & UART_READ_INTS)) {
be_bryan 0:b74591d5ab33 494 UART_ReadHandler(uart, rx_states[uart_num], uart_num, flags);
be_bryan 0:b74591d5ab33 495 }
be_bryan 0:b74591d5ab33 496
be_bryan 0:b74591d5ab33 497 // Figure out if this UART has an active Write request
be_bryan 0:b74591d5ab33 498 if((tx_states[uart_num] != NULL) && (flags & (UART_WRITE_INTS))) {
be_bryan 0:b74591d5ab33 499
be_bryan 0:b74591d5ab33 500 UART_WriteHandler(uart, tx_states[uart_num], uart_num);
be_bryan 0:b74591d5ab33 501 }
be_bryan 0:b74591d5ab33 502 }
be_bryan 0:b74591d5ab33 503 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 504 int UART_Busy(mxc_uart_regs_t *uart)
be_bryan 0:b74591d5ab33 505 {
be_bryan 0:b74591d5ab33 506 int uart_num = MXC_UART_GET_IDX(uart);
be_bryan 0:b74591d5ab33 507 MXC_ASSERT(uart_num >= 0);
be_bryan 0:b74591d5ab33 508
be_bryan 0:b74591d5ab33 509 // Check to see if there are any ongoing transactions or if the UART is disabled
be_bryan 0:b74591d5ab33 510 if(((tx_states[uart_num] == NULL) &&
be_bryan 0:b74591d5ab33 511 !(uart->tx_fifo_ctrl & MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY) &&
be_bryan 0:b74591d5ab33 512 #if(MXC_UART_REV == 0)
be_bryan 0:b74591d5ab33 513 (uart->intfl & MXC_F_UART_INTFL_TX_DONE)) ||
be_bryan 0:b74591d5ab33 514 #else
be_bryan 0:b74591d5ab33 515 (uart->idle & MXC_F_UART_IDLE_TX_RX_IDLE)) ||
be_bryan 0:b74591d5ab33 516 #endif
be_bryan 0:b74591d5ab33 517 !(uart->ctrl & MXC_F_UART_CTRL_UART_EN)) {
be_bryan 0:b74591d5ab33 518
be_bryan 0:b74591d5ab33 519 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 520 }
be_bryan 0:b74591d5ab33 521
be_bryan 0:b74591d5ab33 522 return E_BUSY;
be_bryan 0:b74591d5ab33 523 }
be_bryan 0:b74591d5ab33 524
be_bryan 0:b74591d5ab33 525 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 526 int UART_PrepForSleep(mxc_uart_regs_t *uart)
be_bryan 0:b74591d5ab33 527 {
be_bryan 0:b74591d5ab33 528 if(UART_Busy(uart) != E_NO_ERROR) {
be_bryan 0:b74591d5ab33 529 return E_BUSY;
be_bryan 0:b74591d5ab33 530 }
be_bryan 0:b74591d5ab33 531
be_bryan 0:b74591d5ab33 532 // Leave read interrupts enabled, if already enabled
be_bryan 0:b74591d5ab33 533 uart->inten &= UART_READ_INTS;
be_bryan 0:b74591d5ab33 534
be_bryan 0:b74591d5ab33 535 return E_NO_ERROR;
be_bryan 0:b74591d5ab33 536 }
be_bryan 0:b74591d5ab33 537
be_bryan 0:b74591d5ab33 538 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 539 static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num)
be_bryan 0:b74591d5ab33 540 {
be_bryan 0:b74591d5ab33 541 int avail, remain;
be_bryan 0:b74591d5ab33 542 mxc_uart_fifo_regs_t *fifo;
be_bryan 0:b74591d5ab33 543
be_bryan 0:b74591d5ab33 544 // Disable write interrupts
be_bryan 0:b74591d5ab33 545 uart->inten &= ~(UART_WRITE_INTS);
be_bryan 0:b74591d5ab33 546
be_bryan 0:b74591d5ab33 547 // Get the FIFO for this UART
be_bryan 0:b74591d5ab33 548 fifo = MXC_UART_GET_FIFO(uart_num);
be_bryan 0:b74591d5ab33 549
be_bryan 0:b74591d5ab33 550 // Refill the TX FIFO
be_bryan 0:b74591d5ab33 551 avail = UART_NumWriteAvail(uart);
be_bryan 0:b74591d5ab33 552 remain = req->len - req->num;
be_bryan 0:b74591d5ab33 553
be_bryan 0:b74591d5ab33 554 while(avail && remain) {
be_bryan 0:b74591d5ab33 555
be_bryan 0:b74591d5ab33 556 // Write the data to the FIFO
be_bryan 0:b74591d5ab33 557 #if(MXC_UART_REV == 0)
be_bryan 0:b74591d5ab33 558 uart->intfl = MXC_F_UART_INTFL_TX_DONE;
be_bryan 0:b74591d5ab33 559 #endif
be_bryan 0:b74591d5ab33 560 fifo->tx = req->data[req->num++];
be_bryan 0:b74591d5ab33 561 remain--;
be_bryan 0:b74591d5ab33 562 avail--;
be_bryan 0:b74591d5ab33 563 }
be_bryan 0:b74591d5ab33 564
be_bryan 0:b74591d5ab33 565 // All of the bytes have been written to the FIFO
be_bryan 0:b74591d5ab33 566 if(!remain) {
be_bryan 0:b74591d5ab33 567
be_bryan 0:b74591d5ab33 568 // Unlock this UART to write
be_bryan 0:b74591d5ab33 569 mxc_free_lock((uint32_t*)&tx_states[uart_num]);
be_bryan 0:b74591d5ab33 570
be_bryan 0:b74591d5ab33 571 if(req->callback != NULL) {
be_bryan 0:b74591d5ab33 572 req->callback(req, E_NO_ERROR);
be_bryan 0:b74591d5ab33 573 }
be_bryan 0:b74591d5ab33 574
be_bryan 0:b74591d5ab33 575 } else {
be_bryan 0:b74591d5ab33 576
be_bryan 0:b74591d5ab33 577 // Interrupt when there is one byte left in the TXFIFO
be_bryan 0:b74591d5ab33 578 uart->tx_fifo_ctrl = ((MXC_UART_FIFO_DEPTH - 1) << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS);
be_bryan 0:b74591d5ab33 579
be_bryan 0:b74591d5ab33 580 // Enable almost empty interrupt
be_bryan 0:b74591d5ab33 581 uart->inten |= (MXC_F_UART_INTEN_TX_FIFO_AE);
be_bryan 0:b74591d5ab33 582 }
be_bryan 0:b74591d5ab33 583 }
be_bryan 0:b74591d5ab33 584
be_bryan 0:b74591d5ab33 585 /* ************************************************************************* */
be_bryan 0:b74591d5ab33 586 static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
be_bryan 0:b74591d5ab33 587 uint32_t flags)
be_bryan 0:b74591d5ab33 588 {
be_bryan 0:b74591d5ab33 589 int avail, remain;
be_bryan 0:b74591d5ab33 590 mxc_uart_fifo_regs_t *fifo;
be_bryan 0:b74591d5ab33 591
be_bryan 0:b74591d5ab33 592 // Disable interrupts
be_bryan 0:b74591d5ab33 593 uart->inten &= ~UART_READ_INTS;
be_bryan 0:b74591d5ab33 594
be_bryan 0:b74591d5ab33 595 // Get the FIFO for this UART, uart_num
be_bryan 0:b74591d5ab33 596 fifo = MXC_UART_GET_FIFO(uart_num);
be_bryan 0:b74591d5ab33 597
be_bryan 0:b74591d5ab33 598 // Save the data in the FIFO while we still need data
be_bryan 0:b74591d5ab33 599 avail = UART_NumReadAvail(uart);
be_bryan 0:b74591d5ab33 600 remain = req->len - req->num;
be_bryan 0:b74591d5ab33 601 while(avail && remain) {
be_bryan 0:b74591d5ab33 602 req->data[req->num++] = fifo->rx;
be_bryan 0:b74591d5ab33 603 remain--;
be_bryan 0:b74591d5ab33 604 avail--;
be_bryan 0:b74591d5ab33 605 }
be_bryan 0:b74591d5ab33 606
be_bryan 0:b74591d5ab33 607 // Check for errors
be_bryan 0:b74591d5ab33 608 if(flags & MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) {
be_bryan 0:b74591d5ab33 609
be_bryan 0:b74591d5ab33 610 // Unlock this UART to read
be_bryan 0:b74591d5ab33 611 mxc_free_lock((uint32_t*)&rx_states[uart_num]);
be_bryan 0:b74591d5ab33 612
be_bryan 0:b74591d5ab33 613 if(req->callback != NULL) {
be_bryan 0:b74591d5ab33 614 req->callback(req, E_OVERFLOW);
be_bryan 0:b74591d5ab33 615 }
be_bryan 0:b74591d5ab33 616
be_bryan 0:b74591d5ab33 617 return;
be_bryan 0:b74591d5ab33 618 }
be_bryan 0:b74591d5ab33 619
be_bryan 0:b74591d5ab33 620 if(flags & (MXC_F_UART_INTFL_RX_FRAMING_ERR |
be_bryan 0:b74591d5ab33 621 MXC_F_UART_INTFL_RX_PARITY_ERR)) {
be_bryan 0:b74591d5ab33 622
be_bryan 0:b74591d5ab33 623 // Unlock this UART to read
be_bryan 0:b74591d5ab33 624 mxc_free_lock((uint32_t*)&rx_states[uart_num]);
be_bryan 0:b74591d5ab33 625
be_bryan 0:b74591d5ab33 626 if(req->callback != NULL) {
be_bryan 0:b74591d5ab33 627 req->callback(req, E_COMM_ERR);
be_bryan 0:b74591d5ab33 628 }
be_bryan 0:b74591d5ab33 629
be_bryan 0:b74591d5ab33 630 return;
be_bryan 0:b74591d5ab33 631 }
be_bryan 0:b74591d5ab33 632
be_bryan 0:b74591d5ab33 633 // Check to see if we're done receiving
be_bryan 0:b74591d5ab33 634 if(remain == 0) {
be_bryan 0:b74591d5ab33 635
be_bryan 0:b74591d5ab33 636 // Unlock this UART to read
be_bryan 0:b74591d5ab33 637 mxc_free_lock((uint32_t*)&rx_states[uart_num]);
be_bryan 0:b74591d5ab33 638
be_bryan 0:b74591d5ab33 639 if(req->callback != NULL) {
be_bryan 0:b74591d5ab33 640 req->callback(req, E_NO_ERROR);
be_bryan 0:b74591d5ab33 641 }
be_bryan 0:b74591d5ab33 642
be_bryan 0:b74591d5ab33 643 return;
be_bryan 0:b74591d5ab33 644 }
be_bryan 0:b74591d5ab33 645
be_bryan 0:b74591d5ab33 646 if(remain == 1) {
be_bryan 0:b74591d5ab33 647 uart->inten |= (MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY | UART_ERRORS);
be_bryan 0:b74591d5ab33 648
be_bryan 0:b74591d5ab33 649 } else {
be_bryan 0:b74591d5ab33 650 // Set the RX FIFO AF threshold
be_bryan 0:b74591d5ab33 651 if(remain < UART_RXFIFO_USABLE) {
be_bryan 0:b74591d5ab33 652 uart->rx_fifo_ctrl = ((remain - 1) <<
be_bryan 0:b74591d5ab33 653 MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
be_bryan 0:b74591d5ab33 654 } else {
be_bryan 0:b74591d5ab33 655 uart->rx_fifo_ctrl = (UART_RXFIFO_USABLE <<
be_bryan 0:b74591d5ab33 656 MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS);
be_bryan 0:b74591d5ab33 657 }
be_bryan 0:b74591d5ab33 658 uart->inten |= (MXC_F_UART_INTEN_RX_FIFO_AF | UART_ERRORS);
be_bryan 0:b74591d5ab33 659 }
be_bryan 0:b74591d5ab33 660 }
be_bryan 0:b74591d5ab33 661 /**@} end of ingroup uart_comm */