EL4121 Embedded System / mbed-os

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_Maxim/TARGET_MAX32630/device/clkman_regs.h@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /**
be_bryan 0:b74591d5ab33 2 * @file
be_bryan 0:b74591d5ab33 3 * @brief Type definitions for the Clock Management Interface
be_bryan 0:b74591d5ab33 4 *
be_bryan 0:b74591d5ab33 5 */
be_bryan 0:b74591d5ab33 6 /* ****************************************************************************
be_bryan 0:b74591d5ab33 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
be_bryan 0:b74591d5ab33 8 *
be_bryan 0:b74591d5ab33 9 * Permission is hereby granted, free of charge, to any person obtaining a
be_bryan 0:b74591d5ab33 10 * copy of this software and associated documentation files (the "Software"),
be_bryan 0:b74591d5ab33 11 * to deal in the Software without restriction, including without limitation
be_bryan 0:b74591d5ab33 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
be_bryan 0:b74591d5ab33 13 * and/or sell copies of the Software, and to permit persons to whom the
be_bryan 0:b74591d5ab33 14 * Software is furnished to do so, subject to the following conditions:
be_bryan 0:b74591d5ab33 15 *
be_bryan 0:b74591d5ab33 16 * The above copyright notice and this permission notice shall be included
be_bryan 0:b74591d5ab33 17 * in all copies or substantial portions of the Software.
be_bryan 0:b74591d5ab33 18 *
be_bryan 0:b74591d5ab33 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
be_bryan 0:b74591d5ab33 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
be_bryan 0:b74591d5ab33 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
be_bryan 0:b74591d5ab33 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
be_bryan 0:b74591d5ab33 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
be_bryan 0:b74591d5ab33 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
be_bryan 0:b74591d5ab33 25 * OTHER DEALINGS IN THE SOFTWARE.
be_bryan 0:b74591d5ab33 26 *
be_bryan 0:b74591d5ab33 27 * Except as contained in this notice, the name of Maxim Integrated
be_bryan 0:b74591d5ab33 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
be_bryan 0:b74591d5ab33 29 * Products, Inc. Branding Policy.
be_bryan 0:b74591d5ab33 30 *
be_bryan 0:b74591d5ab33 31 * The mere transfer of this software does not imply any licenses
be_bryan 0:b74591d5ab33 32 * of trade secrets, proprietary technology, copyrights, patents,
be_bryan 0:b74591d5ab33 33 * trademarks, maskwork rights, or any other form of intellectual
be_bryan 0:b74591d5ab33 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
be_bryan 0:b74591d5ab33 35 * ownership rights.
be_bryan 0:b74591d5ab33 36 *
be_bryan 0:b74591d5ab33 37 * $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $
be_bryan 0:b74591d5ab33 38 * $Revision: 24058 $
be_bryan 0:b74591d5ab33 39 *
be_bryan 0:b74591d5ab33 40 **************************************************************************** */
be_bryan 0:b74591d5ab33 41
be_bryan 0:b74591d5ab33 42 /* Define to prevent redundant inclusion */
be_bryan 0:b74591d5ab33 43 #ifndef _MXC_CLKMAN_REGS_H_
be_bryan 0:b74591d5ab33 44 #define _MXC_CLKMAN_REGS_H_
be_bryan 0:b74591d5ab33 45
be_bryan 0:b74591d5ab33 46 /* **** Includes **** */
be_bryan 0:b74591d5ab33 47 #include <stdint.h>
be_bryan 0:b74591d5ab33 48
be_bryan 0:b74591d5ab33 49 #ifdef __cplusplus
be_bryan 0:b74591d5ab33 50 extern "C" {
be_bryan 0:b74591d5ab33 51 #endif
be_bryan 0:b74591d5ab33 52
be_bryan 0:b74591d5ab33 53 /// @cond
be_bryan 0:b74591d5ab33 54 /*
be_bryan 0:b74591d5ab33 55 If types are not defined elsewhere (CMSIS) define them here
be_bryan 0:b74591d5ab33 56 */
be_bryan 0:b74591d5ab33 57 #ifndef __IO
be_bryan 0:b74591d5ab33 58 #define __IO volatile
be_bryan 0:b74591d5ab33 59 #endif
be_bryan 0:b74591d5ab33 60 #ifndef __I
be_bryan 0:b74591d5ab33 61 #define __I volatile const
be_bryan 0:b74591d5ab33 62 #endif
be_bryan 0:b74591d5ab33 63 #ifndef __O
be_bryan 0:b74591d5ab33 64 #define __O volatile
be_bryan 0:b74591d5ab33 65 #endif
be_bryan 0:b74591d5ab33 66 #ifndef __RO
be_bryan 0:b74591d5ab33 67 #define __RO volatile const
be_bryan 0:b74591d5ab33 68 #endif
be_bryan 0:b74591d5ab33 69 /// @endcond
be_bryan 0:b74591d5ab33 70
be_bryan 0:b74591d5ab33 71 /**
be_bryan 0:b74591d5ab33 72 * @ingroup clkman
be_bryan 0:b74591d5ab33 73 * @defgroup clkman_registers Registers
be_bryan 0:b74591d5ab33 74 * @brief Registers, Bit Masks and Bit Positions
be_bryan 0:b74591d5ab33 75 * @{
be_bryan 0:b74591d5ab33 76 */
be_bryan 0:b74591d5ab33 77
be_bryan 0:b74591d5ab33 78 /**
be_bryan 0:b74591d5ab33 79 * Structure type for the Clock Management module registers allowing direct 32-bit access to each register.
be_bryan 0:b74591d5ab33 80 */
be_bryan 0:b74591d5ab33 81 typedef struct {
be_bryan 0:b74591d5ab33 82 __IO uint32_t clk_config; /**< <tt>\b 0x0000: </tt> CLKMAN_CLK_CONFIG Register - System Clock Configuration */
be_bryan 0:b74591d5ab33 83 __IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> CLKMAN_CLK_CTRL Register - System Clock Controls */
be_bryan 0:b74591d5ab33 84 __IO uint32_t intfl; /**< <tt>\b 0x0008: </tt> CLKMAN_INTFL Register - Interrupt Flags */
be_bryan 0:b74591d5ab33 85 __IO uint32_t inten; /**< <tt>\b 0x000C: </tt> CLKMAN_INTEN Register - Interrupt Enable/Disable Controls */
be_bryan 0:b74591d5ab33 86 __IO uint32_t trim_calc; /**< <tt>\b 0x0010: </tt> CLKMAN_TRIM_CALC Register - Trim Calculation Controls */
be_bryan 0:b74591d5ab33 87 __IO uint32_t i2c_timer_ctrl; /**< <tt>\b 0x0014: </tt> CLKMAN_I2C_TIMER_CTRL Register - I2C Timer Control */
be_bryan 0:b74591d5ab33 88 __IO uint32_t cm4_start_clk_en0; /**< <tt>\b 0x0018: </tt> CLKMAN_CM4_START_CLK_EN0 Register - CM4 Start Clock on Interrupt Enable 0 */
be_bryan 0:b74591d5ab33 89 __IO uint32_t cm4_start_clk_en1; /**< <tt>\b 0x001C: </tt> CLKMAN_CM4_START_CLK_EN1 Register - CM4 Start Clock on Interrupt Enable 1 */
be_bryan 0:b74591d5ab33 90 __IO uint32_t cm4_start_clk_en2; /**< <tt>\b 0x0020: </tt> CLKMAN_CM4_START_CLK_EN2 Register - CM4 Start Clock on Interrupt Enable 2 */
be_bryan 0:b74591d5ab33 91 __RO uint32_t rsv024[7]; /**< <tt>\b 0x0024-0x003C:</tt> RESERVED */
be_bryan 0:b74591d5ab33 92 __IO uint32_t sys_clk_ctrl_0_cm4; /**< <tt>\b 0x0040: </tt> CLKMAN_SYS_CLK_CTRL_0_CM4 Register - Cortex M4 Clock */
be_bryan 0:b74591d5ab33 93 __IO uint32_t sys_clk_ctrl_1_sync; /**< <tt>\b 0x0044: </tt> CLKMAN_SYS_CLK_CTRL_1_SYNC Register - Synchronizer Clock */
be_bryan 0:b74591d5ab33 94 __IO uint32_t sys_clk_ctrl_2_spix; /**< <tt>\b 0x0048: </tt> CLKMAN_SYS_CLK_CTRL_2_SPIX Register - SPI XIP Clock */
be_bryan 0:b74591d5ab33 95 __IO uint32_t sys_clk_ctrl_3_prng; /**< <tt>\b 0x004C: </tt> CLKMAN_SYS_CLK_CTRL_3_PRNG Register - PRNG Clock */
be_bryan 0:b74591d5ab33 96 __IO uint32_t sys_clk_ctrl_4_wdt0; /**< <tt>\b 0x0050: </tt> CLKMAN_SYS_CLK_CTRL_4_WDT0 Register - Watchdog Timer 0 */
be_bryan 0:b74591d5ab33 97 __IO uint32_t sys_clk_ctrl_5_wdt1; /**< <tt>\b 0x0054: </tt> CLKMAN_SYS_CLK_CTRL_5_WDT1 Register - Watchdog Timer 1 */
be_bryan 0:b74591d5ab33 98 __IO uint32_t sys_clk_ctrl_6_gpio; /**< <tt>\b 0x0058: </tt> CLKMAN_SYS_CLK_CTRL_6_GPIO Register - Clock for GPIO Ports */
be_bryan 0:b74591d5ab33 99 __IO uint32_t sys_clk_ctrl_7_pt; /**< <tt>\b 0x005C: </tt> CLKMAN_SYS_CLK_CTRL_7_PT Register - Source Clock for All Pulse Trains */
be_bryan 0:b74591d5ab33 100 __IO uint32_t sys_clk_ctrl_8_uart; /**< <tt>\b 0x0060: </tt> CLKMAN_SYS_CLK_CTRL_8_UART Register - Source Clock for All UARTs */
be_bryan 0:b74591d5ab33 101 __IO uint32_t sys_clk_ctrl_9_i2cm; /**< <tt>\b 0x0064: </tt> CLKMAN_SYS_CLK_CTRL_9_I2CM Register - Source Clock for All I2C Masters */
be_bryan 0:b74591d5ab33 102 __IO uint32_t sys_clk_ctrl_10_i2cs; /**< <tt>\b 0x0068: </tt> CLKMAN_SYS_CLK_CTRL_10_I2CS Register - Source Clock for I2C Slave */
be_bryan 0:b74591d5ab33 103 __IO uint32_t sys_clk_ctrl_11_spi0; /**< <tt>\b 0x006C: </tt> CLKMAN_SYS_CLK_CTRL_11_SPI0 Register - SPI Master 0 */
be_bryan 0:b74591d5ab33 104 __IO uint32_t sys_clk_ctrl_12_spi1; /**< <tt>\b 0x0070: </tt> CLKMAN_SYS_CLK_CTRL_12_SPI1 Register - SPI Master 1 */
be_bryan 0:b74591d5ab33 105 __IO uint32_t sys_clk_ctrl_13_spi2; /**< <tt>\b 0x0074: </tt> CLKMAN_SYS_CLK_CTRL_13_SPI2 Register - SPI Master 2 */
be_bryan 0:b74591d5ab33 106 __IO uint32_t sys_clk_ctrl_14_spib; /**< <tt>\b 0x0078: </tt> CLKMAN_SYS_CLK_CTRL_14_SPIB Register - SPI Bridge Clock */
be_bryan 0:b74591d5ab33 107 __IO uint32_t sys_clk_ctrl_15_owm; /**< <tt>\b 0x007C: </tt> CLKMAN_SYS_CLK_CTRL_15_OWM Register - 1-Wire Master Clock */
be_bryan 0:b74591d5ab33 108 __IO uint32_t sys_clk_ctrl_16_spis; /**< <tt>\b 0x0080: </tt> CLKMAN_SYS_CLK_CTRL_16_SPIS Register - SPI Slave Clock */
be_bryan 0:b74591d5ab33 109 __RO uint32_t rsv084[31]; /**< <tt>\b 0x0084-0x00FC:</tt> RESERVED: */
be_bryan 0:b74591d5ab33 110 __IO uint32_t crypt_clk_ctrl_0_aes; /**< <tt>\b 0x0100: </tt> CLKMAN_CRYPT_CLK_CTRL_0_AES Register - AES */
be_bryan 0:b74591d5ab33 111 __IO uint32_t crypt_clk_ctrl_1_maa; /**< <tt>\b 0x0104: </tt> CLKMAN_CRYPT_CLK_CTRL_1_MAA Register - MAA */
be_bryan 0:b74591d5ab33 112 __IO uint32_t crypt_clk_ctrl_2_prng; /**< <tt>\b 0x0108: </tt> CLKMAN_CRYPT_CLK_CTRL_2_PRNG Register - PRNG */
be_bryan 0:b74591d5ab33 113 __RO uint32_t rsv10C[13]; /**< <tt>\b 0x010C-0x013C:</tt> RESERVED */
be_bryan 0:b74591d5ab33 114 __IO uint32_t clk_gate_ctrl0; /**< <tt>\b 0x0140: </tt> CLKMAN_CLK_GATE_CTRL0 Register - Dynamic Clock Gating Control Register 0 */
be_bryan 0:b74591d5ab33 115 __IO uint32_t clk_gate_ctrl1; /**< <tt>\b 0x0144: </tt> CLKMAN_CLK_GATE_CTRL1 Register - Dynamic Clock Gating Control Register 1 */
be_bryan 0:b74591d5ab33 116 __IO uint32_t clk_gate_ctrl2; /**< <tt>\b 0x0148: </tt> CLKMAN_CLK_GATE_CTRL2 Register - Dynamic Clock Gating Control Register 2 */
be_bryan 0:b74591d5ab33 117 } mxc_clkman_regs_t;
be_bryan 0:b74591d5ab33 118 /**@} end of clkman_registers */
be_bryan 0:b74591d5ab33 119
be_bryan 0:b74591d5ab33 120 /*
be_bryan 0:b74591d5ab33 121 Register offsets for module CLKMAN.
be_bryan 0:b74591d5ab33 122 */
be_bryan 0:b74591d5ab33 123 /**
be_bryan 0:b74591d5ab33 124 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 125 * @defgroup CLKMAN_Register_Offsets Register Offsets
be_bryan 0:b74591d5ab33 126 * @brief Clock Management Controller Register Offsets from the CLKMAN Base Peripheral Address.
be_bryan 0:b74591d5ab33 127 * @{
be_bryan 0:b74591d5ab33 128 */
be_bryan 0:b74591d5ab33 129 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0000</tt> */
be_bryan 0:b74591d5ab33 130 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0004</tt> */
be_bryan 0:b74591d5ab33 131 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0008</tt> */
be_bryan 0:b74591d5ab33 132 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x000C</tt> */
be_bryan 0:b74591d5ab33 133 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0010</tt> */
be_bryan 0:b74591d5ab33 134 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0014</tt> */
be_bryan 0:b74591d5ab33 135 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0018</tt> */
be_bryan 0:b74591d5ab33 136 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x001C</tt> */
be_bryan 0:b74591d5ab33 137 #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0020</tt> */
be_bryan 0:b74591d5ab33 138 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0040</tt> */
be_bryan 0:b74591d5ab33 139 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0044</tt> */
be_bryan 0:b74591d5ab33 140 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0048</tt> */
be_bryan 0:b74591d5ab33 141 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x004C</tt> */
be_bryan 0:b74591d5ab33 142 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0050</tt> */
be_bryan 0:b74591d5ab33 143 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0054</tt> */
be_bryan 0:b74591d5ab33 144 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0058</tt> */
be_bryan 0:b74591d5ab33 145 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x005C</tt> */
be_bryan 0:b74591d5ab33 146 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0060</tt> */
be_bryan 0:b74591d5ab33 147 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0064</tt> */
be_bryan 0:b74591d5ab33 148 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0068</tt> */
be_bryan 0:b74591d5ab33 149 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x006C</tt> */
be_bryan 0:b74591d5ab33 150 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0070</tt> */
be_bryan 0:b74591d5ab33 151 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0074</tt> */
be_bryan 0:b74591d5ab33 152 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0078</tt> */
be_bryan 0:b74591d5ab33 153 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x007C</tt> */
be_bryan 0:b74591d5ab33 154 #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0080</tt> */
be_bryan 0:b74591d5ab33 155 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0100</tt> */
be_bryan 0:b74591d5ab33 156 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0104</tt> */
be_bryan 0:b74591d5ab33 157 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0108</tt> */
be_bryan 0:b74591d5ab33 158 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0140</tt> */
be_bryan 0:b74591d5ab33 159 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0144</tt> */
be_bryan 0:b74591d5ab33 160 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0148</tt> */
be_bryan 0:b74591d5ab33 161 /**@} end of CLKMAN_Register_Offsets */
be_bryan 0:b74591d5ab33 162 /**
be_bryan 0:b74591d5ab33 163 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 164 * @defgroup clkman_clk_config CLKMAN_CLK_CONFIG Register
be_bryan 0:b74591d5ab33 165 * @brief Field Positions and Masks
be_bryan 0:b74591d5ab33 166 */
be_bryan 0:b74591d5ab33 167 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0 /**< CRYPTO_ENABLE Position */
be_bryan 0:b74591d5ab33 168 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) /**< CRYPTO_ENABLE Mask */
be_bryan 0:b74591d5ab33 169 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4 /**< CRYPTO_STABILITY_COUNT Position */
be_bryan 0:b74591d5ab33 170 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Mask */
be_bryan 0:b74591d5ab33 171 /**@}*/
be_bryan 0:b74591d5ab33 172 /**
be_bryan 0:b74591d5ab33 173 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 174 * @defgroup clkman_clk_ctrl CLKMAN_CLK_CTRL Register
be_bryan 0:b74591d5ab33 175 * @brief Field Positions and Masks
be_bryan 0:b74591d5ab33 176 */
be_bryan 0:b74591d5ab33 177 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0 /**< SYSTEM_SOURCE_SELECT Position */
be_bryan 0:b74591d5ab33 178 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< SYSTEM_SOURCE_SELECT Mask */
be_bryan 0:b74591d5ab33 179 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4 /**< USB_CLOCK_ENABLE Position */
be_bryan 0:b74591d5ab33 180 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS)) /**< USB_CLOCK_ENABLE Mask */
be_bryan 0:b74591d5ab33 181 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5 /**< USB_CLOCK_SELECT Position */
be_bryan 0:b74591d5ab33 182 #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS)) /**< USB_CLOCK_SELECT Mask */
be_bryan 0:b74591d5ab33 183 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8 /**< CRYPTO_CLOCK_ENABLE Position */
be_bryan 0:b74591d5ab33 184 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS)) /**< CRYPTO_CLOCK_ENABLE Mask */
be_bryan 0:b74591d5ab33 185 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12 /**< RTOS_MODE Field Position */
be_bryan 0:b74591d5ab33 186 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) /**< RTOS_MODE Field Mask */
be_bryan 0:b74591d5ab33 187 #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13 /**< CPU_DYNAMIC_CLOCK Field Position */
be_bryan 0:b74591d5ab33 188 #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS)) /**< CPU_DYNAMIC_CLOCK Field Mask */
be_bryan 0:b74591d5ab33 189 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16 /**< WDT0_CLOCK_ENABLE Field Position */
be_bryan 0:b74591d5ab33 190 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS)) /**< WDT0_CLOCK_ENABLE Field Mask */
be_bryan 0:b74591d5ab33 191 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17 /**< WDT0_CLOCK_SELECT Field Position */
be_bryan 0:b74591d5ab33 192 #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) /**< WDT0_CLOCK_SELECT Field Mask */
be_bryan 0:b74591d5ab33 193 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20 /**< WDT1_CLOCK_ENABLE Field Position */
be_bryan 0:b74591d5ab33 194 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS)) /**< WDT1_CLOCK_ENABLE Field Mask */
be_bryan 0:b74591d5ab33 195 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21 /**< WDT1_CLOCK_SELECT Field Position */
be_bryan 0:b74591d5ab33 196 #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) /**< WDT1_CLOCK_SELECT Field Mask */
be_bryan 0:b74591d5ab33 197 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24 /**< ADC_CLOCK_ENABLE Field Position */
be_bryan 0:b74591d5ab33 198 #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS)) /**< ADC_CLOCK_ENABLE Field Mask */
be_bryan 0:b74591d5ab33 199 /**@}*/
be_bryan 0:b74591d5ab33 200 /**
be_bryan 0:b74591d5ab33 201 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 202 * @defgroup clkman_int_flags CLKMAN_INTFL Register
be_bryan 0:b74591d5ab33 203 * @brief Interrupt Flag Positions and Masks
be_bryan 0:b74591d5ab33 204 */
be_bryan 0:b74591d5ab33 205 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Interrupt Flag Position */
be_bryan 0:b74591d5ab33 206 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Interrupt Flag Mask */
be_bryan 0:b74591d5ab33 207 #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Interrupt Flag Position */
be_bryan 0:b74591d5ab33 208 #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Interrupt Flag Mask */
be_bryan 0:b74591d5ab33 209 /**@}*/
be_bryan 0:b74591d5ab33 210 /**
be_bryan 0:b74591d5ab33 211 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 212 * @defgroup clkman_int_enable CLKMAN_INTEN Register
be_bryan 0:b74591d5ab33 213 * @brief Interrupt Enable Positions and Masks
be_bryan 0:b74591d5ab33 214 */
be_bryan 0:b74591d5ab33 215 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Field Position */
be_bryan 0:b74591d5ab33 216 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Field Mask */
be_bryan 0:b74591d5ab33 217 #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Field Position */
be_bryan 0:b74591d5ab33 218 #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Field Mask */
be_bryan 0:b74591d5ab33 219 /**@}*/
be_bryan 0:b74591d5ab33 220 /**
be_bryan 0:b74591d5ab33 221 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 222 * @defgroup clkman_trim_calc CLKMAN_TRIM_CALC Register
be_bryan 0:b74591d5ab33 223 * @brief Field Positions and Masks
be_bryan 0:b74591d5ab33 224 */
be_bryan 0:b74591d5ab33 225 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 /**< TRIM_CLK_SEL Field Position */
be_bryan 0:b74591d5ab33 226 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) /**< TRIM_CLK_SEL Field Mask */
be_bryan 0:b74591d5ab33 227 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 /**< TRIM_CALC_START Field Position */
be_bryan 0:b74591d5ab33 228 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) /**< TRIM_CALC_START Field Mask */
be_bryan 0:b74591d5ab33 229 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 /**< TRIM_CALC_COMPLETED Field Position */
be_bryan 0:b74591d5ab33 230 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) /**< TRIM_CALC_COMPLETED Field Mask */
be_bryan 0:b74591d5ab33 231 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 /**< TRIM_ENABLE Field Position */
be_bryan 0:b74591d5ab33 232 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) /**< TRIM_ENABLE Field Mask */
be_bryan 0:b74591d5ab33 233 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 /**< TRIM_CALC_RESULTS Field Position */
be_bryan 0:b74591d5ab33 234 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) /**< TRIM_CALC_RESULTS Field Mask */
be_bryan 0:b74591d5ab33 235 /**@}*/
be_bryan 0:b74591d5ab33 236 /**
be_bryan 0:b74591d5ab33 237 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 238 * @defgroup clkman_i2c_1ms CLKMAN_I2C_TIMER_CTRL Register
be_bryan 0:b74591d5ab33 239 * @brief Field Positions and Masks
be_bryan 0:b74591d5ab33 240 */
be_bryan 0:b74591d5ab33 241 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 /**< I2C_1MS_TIMER_EN Position */
be_bryan 0:b74591d5ab33 242 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) /**< I2C_1MS_TIMER_EN Mask */
be_bryan 0:b74591d5ab33 243 /**@}*/
be_bryan 0:b74591d5ab33 244 /**
be_bryan 0:b74591d5ab33 245 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 246 * @defgroup clkman_cm4 CLKMAN_CM4 Register
be_bryan 0:b74591d5ab33 247 * @brief Field Positions and Masks
be_bryan 0:b74591d5ab33 248 */
be_bryan 0:b74591d5ab33 249 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0 /**< CLK_EN0_INTS Position */
be_bryan 0:b74591d5ab33 250 #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS)) /**< CLK_EN0_INTS Mask */
be_bryan 0:b74591d5ab33 251
be_bryan 0:b74591d5ab33 252 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0 /**< CLK_EN1_INTS Position */
be_bryan 0:b74591d5ab33 253 #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS)) /**< CLK_EN1_INTS Mask */
be_bryan 0:b74591d5ab33 254
be_bryan 0:b74591d5ab33 255 #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0 /**< CLK_EN2_INTS Position */
be_bryan 0:b74591d5ab33 256 #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS)) /**< CLK_EN2_INTS Mask */
be_bryan 0:b74591d5ab33 257 /**@}*/
be_bryan 0:b74591d5ab33 258 /**
be_bryan 0:b74591d5ab33 259 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 260 * @defgroup clkman_sysclk_ctrl CLKMAN_SYS_CLK_CTRL Register
be_bryan 0:b74591d5ab33 261 * @brief Field Positions and Masks
be_bryan 0:b74591d5ab33 262 */
be_bryan 0:b74591d5ab33 263 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0 /**< CM4_CM4_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 264 #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) /**< CM4_CM4_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 265 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0 /**< SYNC_SYNC_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 266 #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS)) /**< SYNC_SYNC_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 267 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0 /**< SPIX_SPIX_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 268 #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS)) /**< SPIX_SPIX_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 269 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 270 #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 271 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0 /**< WDT0_WATCHDOG0_CLK_ Position */
be_bryan 0:b74591d5ab33 272 #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS)) /**< WDT0_WATCHDOG0_CLK_ Mask */
be_bryan 0:b74591d5ab33 273 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0 /**< WDT1_WATCHDOG1_CLK_ Position */
be_bryan 0:b74591d5ab33 274 #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS)) /**< WDT1_WATCHDOG1_CLK_ Mask */
be_bryan 0:b74591d5ab33 275 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0 /**< GPIO_GPIO_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 276 #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS)) /**< GPIO_GPIO_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 277 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0 /**< PT_PULSE_TRAIN_CLK_ Position */
be_bryan 0:b74591d5ab33 278 #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS)) /**< PT_PULSE_TRAIN_CLK_ Mask */
be_bryan 0:b74591d5ab33 279 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0 /**< UART_UART_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 280 #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS)) /**< UART_UART_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 281 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0 /**< I2CM_I2CM_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 282 #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS)) /**< I2CM_I2CM_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 283 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0 /**< I2CS_I2CS_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 284 #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS)) /**< I2CS_I2CS_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 285 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0 /**< PI0_SPI0_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 286 #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS)) /**< SPI0_SPI0_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 287 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0 /**< SPI1_SPI1_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 288 #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS)) /**< SPI1_SPI1_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 289 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0 /**< SPI2_SPI2_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 290 #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS)) /**< SPI2_SPI2_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 291 #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0 /**< SPIB_SPIB_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 292 #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS)) /**< SPIB_SPIB_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 293 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0 /**< OWM_OWM_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 294 #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS)) /**< OWM_OWM_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 295 #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0 /**< PIS_SPIS_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 296 #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS)) /**< SPIS_SPIS_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 297 /**@}*/
be_bryan 0:b74591d5ab33 298 /**
be_bryan 0:b74591d5ab33 299 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 300 * @defgroup clkman_crypt_clk_ctrl CLKMAN_CRYPT_CLK_CTRL Register
be_bryan 0:b74591d5ab33 301 * @brief Field Positions and Masks
be_bryan 0:b74591d5ab33 302 */
be_bryan 0:b74591d5ab33 303 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 /**< AES_AES_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 304 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) /**< AES_AES_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 305 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0 /**< MAA_MAA_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 306 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS)) /**< MAA_MAA_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 307 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */
be_bryan 0:b74591d5ab33 308 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */
be_bryan 0:b74591d5ab33 309 /**@}*/
be_bryan 0:b74591d5ab33 310 /**
be_bryan 0:b74591d5ab33 311 * @ingroup clkman_registers
be_bryan 0:b74591d5ab33 312 * @defgroup clkman_clk_gate_ctrl CLKMAN_CLK_GATE_CTRL Register
be_bryan 0:b74591d5ab33 313 * @brief Peripheral Clock Gating Field Positions and Masks
be_bryan 0:b74591d5ab33 314 */
be_bryan 0:b74591d5ab33 315 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0 /**< CM4_CLK_GATER Position */
be_bryan 0:b74591d5ab33 316 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS)) /**< CM4_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 317 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2 /**< AHB32_CLK_GATER Position */
be_bryan 0:b74591d5ab33 318 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS)) /**< AHB32_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 319 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 /**< ICACHE_CLK_GATER Position */
be_bryan 0:b74591d5ab33 320 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) /**< ICACHE_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 321 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 /**< FLASH_CLK_GATER Position */
be_bryan 0:b74591d5ab33 322 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) /**< FLASH_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 323 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 /**< SRAM_CLK_GATER Position */
be_bryan 0:b74591d5ab33 324 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) /**< SRAM_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 325 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 /**< APB_BRIDGE_CLK_GATER Position */
be_bryan 0:b74591d5ab33 326 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) /**< APB_BRIDGE_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 327 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 /**< SYSMAN_CLK_GATER Position */
be_bryan 0:b74591d5ab33 328 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) /**< SYSMAN_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 329 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14 /**< PTP_CLK_GATER Position */
be_bryan 0:b74591d5ab33 330 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS)) /**< PTP_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 331 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16 /**< SSB_MUX_CLK_GATER Position */
be_bryan 0:b74591d5ab33 332 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS)) /**< SSB_MUX_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 333 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18 /**< PAD_CLK_GATER Position */
be_bryan 0:b74591d5ab33 334 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS)) /**< PAD_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 335 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20 /**< SPIX_CLK_GATER Position */
be_bryan 0:b74591d5ab33 336 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS)) /**< SPIX_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 337 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22 /**< PMU_CLK_GATER Position */
be_bryan 0:b74591d5ab33 338 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS)) /**< PMU_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 339 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24 /**< USB_CLK_GATER Position */
be_bryan 0:b74591d5ab33 340 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) /**< USB_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 341 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26 /**< CRC_CLK_GATER Position */
be_bryan 0:b74591d5ab33 342 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS)) /**< CRC_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 343 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28 /**< TPU_CLK_GATER Position */
be_bryan 0:b74591d5ab33 344 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS)) /**< TPU_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 345 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30 /**< WATCHDOG0_CLK_GATER Position */
be_bryan 0:b74591d5ab33 346 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) /**< WATCHDOG0_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 347 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0 /**< WATCHDOG1_CLK_GATER Position */
be_bryan 0:b74591d5ab33 348 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS)) /**< WATCHDOG1_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 349 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2 /**< GPIO_CLK_GATER Position */
be_bryan 0:b74591d5ab33 350 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) /**< GPIO_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 351 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4 /**< TIMER0_CLK_GATER Position */
be_bryan 0:b74591d5ab33 352 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS)) /**< TIMER0_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 353 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6 /**< TIMER1_CLK_GATER Position */
be_bryan 0:b74591d5ab33 354 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS)) /**< TIMER1_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 355 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8 /**< TIMER2_CLK_GATER Position */
be_bryan 0:b74591d5ab33 356 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS)) /**< TIMER2_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 357 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10 /**< TIMER3_CLK_GATER Position */
be_bryan 0:b74591d5ab33 358 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS)) /**< TIMER3_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 359 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12 /**< TIMER4_CLK_GATER Position */
be_bryan 0:b74591d5ab33 360 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS)) /**< TIMER4_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 361 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14 /**< TIMER5_CLK_GATER Position */
be_bryan 0:b74591d5ab33 362 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS)) /**< TIMER5_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 363 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16 /**< PULSETRAIN_CLK_GATER Position */
be_bryan 0:b74591d5ab33 364 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) /**< PULSETRAIN_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 365 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18 /**< UART0_CLK_GATER Position */
be_bryan 0:b74591d5ab33 366 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS)) /**< UART0_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 367 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20 /**< UART1_CLK_GATER Position */
be_bryan 0:b74591d5ab33 368 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS)) /**< UART1_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 369 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22 /**< UART2_CLK_GATER Position */
be_bryan 0:b74591d5ab33 370 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS)) /**< UART2_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 371 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24 /**< UART3_CLK_GATER Position */
be_bryan 0:b74591d5ab33 372 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS)) /**< UART3_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 373 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 /**< I2CM0_CLK_GATER Position */
be_bryan 0:b74591d5ab33 374 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) /**< I2CM0_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 375 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 /**< I2CM1_CLK_GATER Position */
be_bryan 0:b74591d5ab33 376 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) /**< I2CM1_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 377 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30 /**< I2CM2_CLK_GATER Position */
be_bryan 0:b74591d5ab33 378 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS)) /**< I2CM2_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 379 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0 /**< I2CS_CLK_GATER Position */
be_bryan 0:b74591d5ab33 380 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS)) /**< I2CS_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 381 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2 /**< SPI0_CLK_GATER Position */
be_bryan 0:b74591d5ab33 382 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS)) /**< SPI0_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 383 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4 /**< SPI1_CLK_GATER Position */
be_bryan 0:b74591d5ab33 384 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS)) /**< SPI1_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 385 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6 /**< SPI2_CLK_GATER Position */
be_bryan 0:b74591d5ab33 386 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS)) /**< SPI2_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 387 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8 /**< SPI_BRIDGE_CLK_GATER Position */
be_bryan 0:b74591d5ab33 388 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS)) /**< SPI_BRIDGE_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 389 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10 /**< OWM_CLK_GATER Position */
be_bryan 0:b74591d5ab33 390 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS)) /**< OWM_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 391 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12 /**< ADC_CLK_GATER Position */
be_bryan 0:b74591d5ab33 392 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS)) /**< ADC_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 393 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14 /**< SPIS_CLK_GATER Position */
be_bryan 0:b74591d5ab33 394 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS)) /**< SPIS_CLK_GATER Mask */
be_bryan 0:b74591d5ab33 395 /**@}*/
be_bryan 0:b74591d5ab33 396 /**
be_bryan 0:b74591d5ab33 397 * @ingroup clkman_clk_config
be_bryan 0:b74591d5ab33 398 * @defgroup clkman_crypto_stability_count CRYPTO_STABILITY_COUNT Value Settings and Shifted Value Settings
be_bryan 0:b74591d5ab33 399 * @brief Crypto Clock Stability Count Setting Values and Shifted Values
be_bryan 0:b74591d5ab33 400 */
be_bryan 0:b74591d5ab33 401 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>8</SUP> */
be_bryan 0:b74591d5ab33 402 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>9</SUP> */
be_bryan 0:b74591d5ab33 403 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>10</SUP> */
be_bryan 0:b74591d5ab33 404 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>11</SUP> */
be_bryan 0:b74591d5ab33 405 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>12</SUP> */
be_bryan 0:b74591d5ab33 406 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>13</SUP> */
be_bryan 0:b74591d5ab33 407 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>14</SUP> */
be_bryan 0:b74591d5ab33 408 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>15</SUP> */
be_bryan 0:b74591d5ab33 409 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>16</SUP> */
be_bryan 0:b74591d5ab33 410 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>17</SUP> */
be_bryan 0:b74591d5ab33 411 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>18</SUP> */
be_bryan 0:b74591d5ab33 412 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>19</SUP> */
be_bryan 0:b74591d5ab33 413 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>20</SUP> */
be_bryan 0:b74591d5ab33 414 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>21</SUP> */
be_bryan 0:b74591d5ab33 415 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>22</SUP> */
be_bryan 0:b74591d5ab33 416 #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>23</SUP> */
be_bryan 0:b74591d5ab33 417
be_bryan 0:b74591d5ab33 418 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>8</SUP> */
be_bryan 0:b74591d5ab33 419 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>9</SUP> */
be_bryan 0:b74591d5ab33 420 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>10</SUP> */
be_bryan 0:b74591d5ab33 421 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>11</SUP> */
be_bryan 0:b74591d5ab33 422 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>12</SUP> */
be_bryan 0:b74591d5ab33 423 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>13</SUP> */
be_bryan 0:b74591d5ab33 424 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>14</SUP> */
be_bryan 0:b74591d5ab33 425 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>15</SUP> */
be_bryan 0:b74591d5ab33 426 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>16</SUP> */
be_bryan 0:b74591d5ab33 427 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>17</SUP> */
be_bryan 0:b74591d5ab33 428 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>18</SUP> */
be_bryan 0:b74591d5ab33 429 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>19</SUP> */
be_bryan 0:b74591d5ab33 430 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>20</SUP> */
be_bryan 0:b74591d5ab33 431 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>21</SUP> */
be_bryan 0:b74591d5ab33 432 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>22</SUP> */
be_bryan 0:b74591d5ab33 433 #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>23</SUP> */
be_bryan 0:b74591d5ab33 434
be_bryan 0:b74591d5ab33 435 /**@} clkman_crypto_stability_count */
be_bryan 0:b74591d5ab33 436
be_bryan 0:b74591d5ab33 437 /**
be_bryan 0:b74591d5ab33 438 * @ingroup clkman_clk_ctrl
be_bryan 0:b74591d5ab33 439 * @defgroup clkman_sysclock_select System Clock Select Values
be_bryan 0:b74591d5ab33 440 * @brief System Clock Selection Values and Shifted Values for selecting the system clock source
be_bryan 0:b74591d5ab33 441 * @{
be_bryan 0:b74591d5ab33 442 */
be_bryan 0:b74591d5ab33 443 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */
be_bryan 0:b74591d5ab33 444 #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO */
be_bryan 0:b74591d5ab33 445 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */
be_bryan 0:b74591d5ab33 446 #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO */
be_bryan 0:b74591d5ab33 447 /**@} end of clkman_sysclock_select group */
be_bryan 0:b74591d5ab33 448 ///@cond
be_bryan 0:b74591d5ab33 449
be_bryan 0:b74591d5ab33 450 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL))
be_bryan 0:b74591d5ab33 451 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
be_bryan 0:b74591d5ab33 452 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
be_bryan 0:b74591d5ab33 453 #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
be_bryan 0:b74591d5ab33 454 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
be_bryan 0:b74591d5ab33 455 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
be_bryan 0:b74591d5ab33 456 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
be_bryan 0:b74591d5ab33 457 #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS))
be_bryan 0:b74591d5ab33 458 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL))
be_bryan 0:b74591d5ab33 459 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL))
be_bryan 0:b74591d5ab33 460 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL))
be_bryan 0:b74591d5ab33 461 #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL))
be_bryan 0:b74591d5ab33 462 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
be_bryan 0:b74591d5ab33 463 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
be_bryan 0:b74591d5ab33 464 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
be_bryan 0:b74591d5ab33 465 #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS))
be_bryan 0:b74591d5ab33 466 #define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL))
be_bryan 0:b74591d5ab33 467 #define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL))
be_bryan 0:b74591d5ab33 468 #define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL))
be_bryan 0:b74591d5ab33 469 #define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL))
be_bryan 0:b74591d5ab33 470 #define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL))
be_bryan 0:b74591d5ab33 471 #define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL))
be_bryan 0:b74591d5ab33 472 #define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL))
be_bryan 0:b74591d5ab33 473 #define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL))
be_bryan 0:b74591d5ab33 474 #define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL))
be_bryan 0:b74591d5ab33 475 #define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL))
be_bryan 0:b74591d5ab33 476 #define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 477 #define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 478 #define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 479 #define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 480 #define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 481 #define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 482 #define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 483 #define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 484 #define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 485 #define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS))
be_bryan 0:b74591d5ab33 486 ///@endcond
be_bryan 0:b74591d5ab33 487
be_bryan 0:b74591d5ab33 488 #ifdef __cplusplus
be_bryan 0:b74591d5ab33 489 }
be_bryan 0:b74591d5ab33 490 #endif
be_bryan 0:b74591d5ab33 491
be_bryan 0:b74591d5ab33 492 #endif /* _MXC_CLKMAN_REGS_H_ */
be_bryan 0:b74591d5ab33 493