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cmsis/TARGET_CORTEX_M/cmsis_armclang.h@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:: be_bryan
Date:: Mon Dec 11 17:54:04 2017 +0000
Revision:: 0:b74591d5ab33

motor ++

Who changed what in which revision?

User	Revision	Line number	New contents of line
be_bryan	0:b74591d5ab33	1	/************************************************************************//
be_bryan	0:b74591d5ab33	2	* @file cmsis_armclang.h
be_bryan	0:b74591d5ab33	3	* @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
be_bryan	0:b74591d5ab33	4	* @version V5.0.3
be_bryan	0:b74591d5ab33	5	* @date 27. March 2017
be_bryan	0:b74591d5ab33	6	******************************************************************************/
be_bryan	0:b74591d5ab33	7	/*
be_bryan	0:b74591d5ab33	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
be_bryan	0:b74591d5ab33	9	*
be_bryan	0:b74591d5ab33	10	* SPDX-License-Identifier: Apache-2.0
be_bryan	0:b74591d5ab33	11	*
be_bryan	0:b74591d5ab33	12	* Licensed under the Apache License, Version 2.0 (the License); you may
be_bryan	0:b74591d5ab33	13	* not use this file except in compliance with the License.
be_bryan	0:b74591d5ab33	14	* You may obtain a copy of the License at
be_bryan	0:b74591d5ab33	15	*
be_bryan	0:b74591d5ab33	16	* www.apache.org/licenses/LICENSE-2.0
be_bryan	0:b74591d5ab33	17	*
be_bryan	0:b74591d5ab33	18	* Unless required by applicable law or agreed to in writing, software
be_bryan	0:b74591d5ab33	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
be_bryan	0:b74591d5ab33	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan	0:b74591d5ab33	21	* See the License for the specific language governing permissions and
be_bryan	0:b74591d5ab33	22	* limitations under the License.
be_bryan	0:b74591d5ab33	23	*/
be_bryan	0:b74591d5ab33	24
be_bryan	0:b74591d5ab33	25	/lint -esym(9058, IRQn)/ /* disable MISRA 2012 Rule 2.4 for IRQn */
be_bryan	0:b74591d5ab33	26
be_bryan	0:b74591d5ab33	27	#ifndef __CMSIS_ARMCLANG_H
be_bryan	0:b74591d5ab33	28	#define __CMSIS_ARMCLANG_H
be_bryan	0:b74591d5ab33	29
be_bryan	0:b74591d5ab33	30	#ifndef __ARM_COMPAT_H
be_bryan	0:b74591d5ab33	31	#include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
be_bryan	0:b74591d5ab33	32	#endif
be_bryan	0:b74591d5ab33	33
be_bryan	0:b74591d5ab33	34	/* CMSIS compiler specific defines */
be_bryan	0:b74591d5ab33	35	#ifndef __ASM
be_bryan	0:b74591d5ab33	36	#define __ASM __asm
be_bryan	0:b74591d5ab33	37	#endif
be_bryan	0:b74591d5ab33	38	#ifndef __INLINE
be_bryan	0:b74591d5ab33	39	#define __INLINE __inline
be_bryan	0:b74591d5ab33	40	#endif
be_bryan	0:b74591d5ab33	41	#ifndef __STATIC_INLINE
be_bryan	0:b74591d5ab33	42	#define __STATIC_INLINE static __inline
be_bryan	0:b74591d5ab33	43	#endif
be_bryan	0:b74591d5ab33	44	#ifndef __NO_RETURN
be_bryan	0:b74591d5ab33	45	#define __NO_RETURN __attribute__((noreturn))
be_bryan	0:b74591d5ab33	46	#endif
be_bryan	0:b74591d5ab33	47	#ifndef __USED
be_bryan	0:b74591d5ab33	48	#define __USED __attribute__((used))
be_bryan	0:b74591d5ab33	49	#endif
be_bryan	0:b74591d5ab33	50	#ifndef __WEAK
be_bryan	0:b74591d5ab33	51	#define __WEAK __attribute__((weak))
be_bryan	0:b74591d5ab33	52	#endif
be_bryan	0:b74591d5ab33	53	#ifndef __PACKED
be_bryan	0:b74591d5ab33	54	#define __PACKED __attribute__((packed, aligned(1)))
be_bryan	0:b74591d5ab33	55	#endif
be_bryan	0:b74591d5ab33	56	#ifndef __PACKED_STRUCT
be_bryan	0:b74591d5ab33	57	#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
be_bryan	0:b74591d5ab33	58	#endif
be_bryan	0:b74591d5ab33	59	#ifndef __PACKED_UNION
be_bryan	0:b74591d5ab33	60	#define __PACKED_UNION union __attribute__((packed, aligned(1)))
be_bryan	0:b74591d5ab33	61	#endif
be_bryan	0:b74591d5ab33	62	#ifndef __UNALIGNED_UINT32 /* deprecated */
be_bryan	0:b74591d5ab33	63	#pragma clang diagnostic push
be_bryan	0:b74591d5ab33	64	#pragma clang diagnostic ignored "-Wpacked"
be_bryan	0:b74591d5ab33	65	/lint -esym(9058, T_UINT32)/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
be_bryan	0:b74591d5ab33	66	struct __attribute__((packed)) T_UINT32 { uint32_t v; };
be_bryan	0:b74591d5ab33	67	#pragma clang diagnostic pop
be_bryan	0:b74591d5ab33	68	#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
be_bryan	0:b74591d5ab33	69	#endif
be_bryan	0:b74591d5ab33	70	#ifndef __UNALIGNED_UINT16_WRITE
be_bryan	0:b74591d5ab33	71	#pragma clang diagnostic push
be_bryan	0:b74591d5ab33	72	#pragma clang diagnostic ignored "-Wpacked"
be_bryan	0:b74591d5ab33	73	/lint -esym(9058, T_UINT16_WRITE)/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
be_bryan	0:b74591d5ab33	74	__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
be_bryan	0:b74591d5ab33	75	#pragma clang diagnostic pop
be_bryan	0:b74591d5ab33	76	#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE )(void )(addr))->v) = (val))
be_bryan	0:b74591d5ab33	77	#endif
be_bryan	0:b74591d5ab33	78	#ifndef __UNALIGNED_UINT16_READ
be_bryan	0:b74591d5ab33	79	#pragma clang diagnostic push
be_bryan	0:b74591d5ab33	80	#pragma clang diagnostic ignored "-Wpacked"
be_bryan	0:b74591d5ab33	81	/lint -esym(9058, T_UINT16_READ)/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
be_bryan	0:b74591d5ab33	82	__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
be_bryan	0:b74591d5ab33	83	#pragma clang diagnostic pop
be_bryan	0:b74591d5ab33	84	#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ )(const void )(addr))->v)
be_bryan	0:b74591d5ab33	85	#endif
be_bryan	0:b74591d5ab33	86	#ifndef __UNALIGNED_UINT32_WRITE
be_bryan	0:b74591d5ab33	87	#pragma clang diagnostic push
be_bryan	0:b74591d5ab33	88	#pragma clang diagnostic ignored "-Wpacked"
be_bryan	0:b74591d5ab33	89	/lint -esym(9058, T_UINT32_WRITE)/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
be_bryan	0:b74591d5ab33	90	__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
be_bryan	0:b74591d5ab33	91	#pragma clang diagnostic pop
be_bryan	0:b74591d5ab33	92	#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE )(void )(addr))->v) = (val))
be_bryan	0:b74591d5ab33	93	#endif
be_bryan	0:b74591d5ab33	94	#ifndef __UNALIGNED_UINT32_READ
be_bryan	0:b74591d5ab33	95	#pragma clang diagnostic push
be_bryan	0:b74591d5ab33	96	#pragma clang diagnostic ignored "-Wpacked"
be_bryan	0:b74591d5ab33	97	/lint -esym(9058, T_UINT32_READ)/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
be_bryan	0:b74591d5ab33	98	__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
be_bryan	0:b74591d5ab33	99	#pragma clang diagnostic pop
be_bryan	0:b74591d5ab33	100	#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ )(const void )(addr))->v)
be_bryan	0:b74591d5ab33	101	#endif
be_bryan	0:b74591d5ab33	102	#ifndef __ALIGNED
be_bryan	0:b74591d5ab33	103	#define __ALIGNED(x) __attribute__((aligned(x)))
be_bryan	0:b74591d5ab33	104	#endif
be_bryan	0:b74591d5ab33	105	#ifndef __RESTRICT
be_bryan	0:b74591d5ab33	106	#define __RESTRICT __restrict
be_bryan	0:b74591d5ab33	107	#endif
be_bryan	0:b74591d5ab33	108
be_bryan	0:b74591d5ab33	109
be_bryan	0:b74591d5ab33	110	/* ########################### Core Function Access ########################### */
be_bryan	0:b74591d5ab33	111	/** \ingroup CMSIS_Core_FunctionInterface
be_bryan	0:b74591d5ab33	112	\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
be_bryan	0:b74591d5ab33	113	@{
be_bryan	0:b74591d5ab33	114	*/
be_bryan	0:b74591d5ab33	115
be_bryan	0:b74591d5ab33	116	/**
be_bryan	0:b74591d5ab33	117	\brief Enable IRQ Interrupts
be_bryan	0:b74591d5ab33	118	\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
be_bryan	0:b74591d5ab33	119	Can only be executed in Privileged modes.
be_bryan	0:b74591d5ab33	120	*/
be_bryan	0:b74591d5ab33	121	/* intrinsic void __enable_irq(); see arm_compat.h */
be_bryan	0:b74591d5ab33	122
be_bryan	0:b74591d5ab33	123
be_bryan	0:b74591d5ab33	124	/**
be_bryan	0:b74591d5ab33	125	\brief Disable IRQ Interrupts
be_bryan	0:b74591d5ab33	126	\details Disables IRQ interrupts by setting the I-bit in the CPSR.
be_bryan	0:b74591d5ab33	127	Can only be executed in Privileged modes.
be_bryan	0:b74591d5ab33	128	*/
be_bryan	0:b74591d5ab33	129	/* intrinsic void __disable_irq(); see arm_compat.h */
be_bryan	0:b74591d5ab33	130
be_bryan	0:b74591d5ab33	131
be_bryan	0:b74591d5ab33	132	/**
be_bryan	0:b74591d5ab33	133	\brief Get Control Register
be_bryan	0:b74591d5ab33	134	\details Returns the content of the Control Register.
be_bryan	0:b74591d5ab33	135	\return Control Register value
be_bryan	0:b74591d5ab33	136	*/
be_bryan	0:b74591d5ab33	137	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
be_bryan	0:b74591d5ab33	138	{
be_bryan	0:b74591d5ab33	139	uint32_t result;
be_bryan	0:b74591d5ab33	140
be_bryan	0:b74591d5ab33	141	__ASM volatile ("MRS %0, control" : "=r" (result) );
be_bryan	0:b74591d5ab33	142	return(result);
be_bryan	0:b74591d5ab33	143	}
be_bryan	0:b74591d5ab33	144
be_bryan	0:b74591d5ab33	145
be_bryan	0:b74591d5ab33	146	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	147	/**
be_bryan	0:b74591d5ab33	148	\brief Get Control Register (non-secure)
be_bryan	0:b74591d5ab33	149	\details Returns the content of the non-secure Control Register when in secure mode.
be_bryan	0:b74591d5ab33	150	\return non-secure Control Register value
be_bryan	0:b74591d5ab33	151	*/
be_bryan	0:b74591d5ab33	152	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
be_bryan	0:b74591d5ab33	153	{
be_bryan	0:b74591d5ab33	154	uint32_t result;
be_bryan	0:b74591d5ab33	155
be_bryan	0:b74591d5ab33	156	__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
be_bryan	0:b74591d5ab33	157	return(result);
be_bryan	0:b74591d5ab33	158	}
be_bryan	0:b74591d5ab33	159	#endif
be_bryan	0:b74591d5ab33	160
be_bryan	0:b74591d5ab33	161
be_bryan	0:b74591d5ab33	162	/**
be_bryan	0:b74591d5ab33	163	\brief Set Control Register
be_bryan	0:b74591d5ab33	164	\details Writes the given value to the Control Register.
be_bryan	0:b74591d5ab33	165	\param [in] control Control Register value to set
be_bryan	0:b74591d5ab33	166	*/
be_bryan	0:b74591d5ab33	167	__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
be_bryan	0:b74591d5ab33	168	{
be_bryan	0:b74591d5ab33	169	__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
be_bryan	0:b74591d5ab33	170	}
be_bryan	0:b74591d5ab33	171
be_bryan	0:b74591d5ab33	172
be_bryan	0:b74591d5ab33	173	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	174	/**
be_bryan	0:b74591d5ab33	175	\brief Set Control Register (non-secure)
be_bryan	0:b74591d5ab33	176	\details Writes the given value to the non-secure Control Register when in secure state.
be_bryan	0:b74591d5ab33	177	\param [in] control Control Register value to set
be_bryan	0:b74591d5ab33	178	*/
be_bryan	0:b74591d5ab33	179	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
be_bryan	0:b74591d5ab33	180	{
be_bryan	0:b74591d5ab33	181	__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
be_bryan	0:b74591d5ab33	182	}
be_bryan	0:b74591d5ab33	183	#endif
be_bryan	0:b74591d5ab33	184
be_bryan	0:b74591d5ab33	185
be_bryan	0:b74591d5ab33	186	/**
be_bryan	0:b74591d5ab33	187	\brief Get IPSR Register
be_bryan	0:b74591d5ab33	188	\details Returns the content of the IPSR Register.
be_bryan	0:b74591d5ab33	189	\return IPSR Register value
be_bryan	0:b74591d5ab33	190	*/
be_bryan	0:b74591d5ab33	191	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
be_bryan	0:b74591d5ab33	192	{
be_bryan	0:b74591d5ab33	193	uint32_t result;
be_bryan	0:b74591d5ab33	194
be_bryan	0:b74591d5ab33	195	__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
be_bryan	0:b74591d5ab33	196	return(result);
be_bryan	0:b74591d5ab33	197	}
be_bryan	0:b74591d5ab33	198
be_bryan	0:b74591d5ab33	199
be_bryan	0:b74591d5ab33	200	/**
be_bryan	0:b74591d5ab33	201	\brief Get APSR Register
be_bryan	0:b74591d5ab33	202	\details Returns the content of the APSR Register.
be_bryan	0:b74591d5ab33	203	\return APSR Register value
be_bryan	0:b74591d5ab33	204	*/
be_bryan	0:b74591d5ab33	205	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
be_bryan	0:b74591d5ab33	206	{
be_bryan	0:b74591d5ab33	207	uint32_t result;
be_bryan	0:b74591d5ab33	208
be_bryan	0:b74591d5ab33	209	__ASM volatile ("MRS %0, apsr" : "=r" (result) );
be_bryan	0:b74591d5ab33	210	return(result);
be_bryan	0:b74591d5ab33	211	}
be_bryan	0:b74591d5ab33	212
be_bryan	0:b74591d5ab33	213
be_bryan	0:b74591d5ab33	214	/**
be_bryan	0:b74591d5ab33	215	\brief Get xPSR Register
be_bryan	0:b74591d5ab33	216	\details Returns the content of the xPSR Register.
be_bryan	0:b74591d5ab33	217	\return xPSR Register value
be_bryan	0:b74591d5ab33	218	*/
be_bryan	0:b74591d5ab33	219	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
be_bryan	0:b74591d5ab33	220	{
be_bryan	0:b74591d5ab33	221	uint32_t result;
be_bryan	0:b74591d5ab33	222
be_bryan	0:b74591d5ab33	223	__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
be_bryan	0:b74591d5ab33	224	return(result);
be_bryan	0:b74591d5ab33	225	}
be_bryan	0:b74591d5ab33	226
be_bryan	0:b74591d5ab33	227
be_bryan	0:b74591d5ab33	228	/**
be_bryan	0:b74591d5ab33	229	\brief Get Process Stack Pointer
be_bryan	0:b74591d5ab33	230	\details Returns the current value of the Process Stack Pointer (PSP).
be_bryan	0:b74591d5ab33	231	\return PSP Register value
be_bryan	0:b74591d5ab33	232	*/
be_bryan	0:b74591d5ab33	233	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
be_bryan	0:b74591d5ab33	234	{
be_bryan	0:b74591d5ab33	235	register uint32_t result;
be_bryan	0:b74591d5ab33	236
be_bryan	0:b74591d5ab33	237	__ASM volatile ("MRS %0, psp" : "=r" (result) );
be_bryan	0:b74591d5ab33	238	return(result);
be_bryan	0:b74591d5ab33	239	}
be_bryan	0:b74591d5ab33	240
be_bryan	0:b74591d5ab33	241
be_bryan	0:b74591d5ab33	242	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	243	/**
be_bryan	0:b74591d5ab33	244	\brief Get Process Stack Pointer (non-secure)
be_bryan	0:b74591d5ab33	245	\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
be_bryan	0:b74591d5ab33	246	\return PSP Register value
be_bryan	0:b74591d5ab33	247	*/
be_bryan	0:b74591d5ab33	248	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
be_bryan	0:b74591d5ab33	249	{
be_bryan	0:b74591d5ab33	250	register uint32_t result;
be_bryan	0:b74591d5ab33	251
be_bryan	0:b74591d5ab33	252	__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
be_bryan	0:b74591d5ab33	253	return(result);
be_bryan	0:b74591d5ab33	254	}
be_bryan	0:b74591d5ab33	255	#endif
be_bryan	0:b74591d5ab33	256
be_bryan	0:b74591d5ab33	257
be_bryan	0:b74591d5ab33	258	/**
be_bryan	0:b74591d5ab33	259	\brief Set Process Stack Pointer
be_bryan	0:b74591d5ab33	260	\details Assigns the given value to the Process Stack Pointer (PSP).
be_bryan	0:b74591d5ab33	261	\param [in] topOfProcStack Process Stack Pointer value to set
be_bryan	0:b74591d5ab33	262	*/
be_bryan	0:b74591d5ab33	263	__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
be_bryan	0:b74591d5ab33	264	{
be_bryan	0:b74591d5ab33	265	__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
be_bryan	0:b74591d5ab33	266	}
be_bryan	0:b74591d5ab33	267
be_bryan	0:b74591d5ab33	268
be_bryan	0:b74591d5ab33	269	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	270	/**
be_bryan	0:b74591d5ab33	271	\brief Set Process Stack Pointer (non-secure)
be_bryan	0:b74591d5ab33	272	\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
be_bryan	0:b74591d5ab33	273	\param [in] topOfProcStack Process Stack Pointer value to set
be_bryan	0:b74591d5ab33	274	*/
be_bryan	0:b74591d5ab33	275	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
be_bryan	0:b74591d5ab33	276	{
be_bryan	0:b74591d5ab33	277	__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
be_bryan	0:b74591d5ab33	278	}
be_bryan	0:b74591d5ab33	279	#endif
be_bryan	0:b74591d5ab33	280
be_bryan	0:b74591d5ab33	281
be_bryan	0:b74591d5ab33	282	/**
be_bryan	0:b74591d5ab33	283	\brief Get Main Stack Pointer
be_bryan	0:b74591d5ab33	284	\details Returns the current value of the Main Stack Pointer (MSP).
be_bryan	0:b74591d5ab33	285	\return MSP Register value
be_bryan	0:b74591d5ab33	286	*/
be_bryan	0:b74591d5ab33	287	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
be_bryan	0:b74591d5ab33	288	{
be_bryan	0:b74591d5ab33	289	register uint32_t result;
be_bryan	0:b74591d5ab33	290
be_bryan	0:b74591d5ab33	291	__ASM volatile ("MRS %0, msp" : "=r" (result) );
be_bryan	0:b74591d5ab33	292	return(result);
be_bryan	0:b74591d5ab33	293	}
be_bryan	0:b74591d5ab33	294
be_bryan	0:b74591d5ab33	295
be_bryan	0:b74591d5ab33	296	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	297	/**
be_bryan	0:b74591d5ab33	298	\brief Get Main Stack Pointer (non-secure)
be_bryan	0:b74591d5ab33	299	\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
be_bryan	0:b74591d5ab33	300	\return MSP Register value
be_bryan	0:b74591d5ab33	301	*/
be_bryan	0:b74591d5ab33	302	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
be_bryan	0:b74591d5ab33	303	{
be_bryan	0:b74591d5ab33	304	register uint32_t result;
be_bryan	0:b74591d5ab33	305
be_bryan	0:b74591d5ab33	306	__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
be_bryan	0:b74591d5ab33	307	return(result);
be_bryan	0:b74591d5ab33	308	}
be_bryan	0:b74591d5ab33	309	#endif
be_bryan	0:b74591d5ab33	310
be_bryan	0:b74591d5ab33	311
be_bryan	0:b74591d5ab33	312	/**
be_bryan	0:b74591d5ab33	313	\brief Set Main Stack Pointer
be_bryan	0:b74591d5ab33	314	\details Assigns the given value to the Main Stack Pointer (MSP).
be_bryan	0:b74591d5ab33	315	\param [in] topOfMainStack Main Stack Pointer value to set
be_bryan	0:b74591d5ab33	316	*/
be_bryan	0:b74591d5ab33	317	__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
be_bryan	0:b74591d5ab33	318	{
be_bryan	0:b74591d5ab33	319	__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
be_bryan	0:b74591d5ab33	320	}
be_bryan	0:b74591d5ab33	321
be_bryan	0:b74591d5ab33	322
be_bryan	0:b74591d5ab33	323	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	324	/**
be_bryan	0:b74591d5ab33	325	\brief Set Main Stack Pointer (non-secure)
be_bryan	0:b74591d5ab33	326	\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
be_bryan	0:b74591d5ab33	327	\param [in] topOfMainStack Main Stack Pointer value to set
be_bryan	0:b74591d5ab33	328	*/
be_bryan	0:b74591d5ab33	329	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
be_bryan	0:b74591d5ab33	330	{
be_bryan	0:b74591d5ab33	331	__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
be_bryan	0:b74591d5ab33	332	}
be_bryan	0:b74591d5ab33	333	#endif
be_bryan	0:b74591d5ab33	334
be_bryan	0:b74591d5ab33	335
be_bryan	0:b74591d5ab33	336	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	337	/**
be_bryan	0:b74591d5ab33	338	\brief Get Stack Pointer (non-secure)
be_bryan	0:b74591d5ab33	339	\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
be_bryan	0:b74591d5ab33	340	\return SP Register value
be_bryan	0:b74591d5ab33	341	*/
be_bryan	0:b74591d5ab33	342	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
be_bryan	0:b74591d5ab33	343	{
be_bryan	0:b74591d5ab33	344	register uint32_t result;
be_bryan	0:b74591d5ab33	345
be_bryan	0:b74591d5ab33	346	__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
be_bryan	0:b74591d5ab33	347	return(result);
be_bryan	0:b74591d5ab33	348	}
be_bryan	0:b74591d5ab33	349
be_bryan	0:b74591d5ab33	350
be_bryan	0:b74591d5ab33	351	/**
be_bryan	0:b74591d5ab33	352	\brief Set Stack Pointer (non-secure)
be_bryan	0:b74591d5ab33	353	\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
be_bryan	0:b74591d5ab33	354	\param [in] topOfStack Stack Pointer value to set
be_bryan	0:b74591d5ab33	355	*/
be_bryan	0:b74591d5ab33	356	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
be_bryan	0:b74591d5ab33	357	{
be_bryan	0:b74591d5ab33	358	__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
be_bryan	0:b74591d5ab33	359	}
be_bryan	0:b74591d5ab33	360	#endif
be_bryan	0:b74591d5ab33	361
be_bryan	0:b74591d5ab33	362
be_bryan	0:b74591d5ab33	363	/**
be_bryan	0:b74591d5ab33	364	\brief Get Priority Mask
be_bryan	0:b74591d5ab33	365	\details Returns the current state of the priority mask bit from the Priority Mask Register.
be_bryan	0:b74591d5ab33	366	\return Priority Mask value
be_bryan	0:b74591d5ab33	367	*/
be_bryan	0:b74591d5ab33	368	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
be_bryan	0:b74591d5ab33	369	{
be_bryan	0:b74591d5ab33	370	uint32_t result;
be_bryan	0:b74591d5ab33	371
be_bryan	0:b74591d5ab33	372	__ASM volatile ("MRS %0, primask" : "=r" (result) );
be_bryan	0:b74591d5ab33	373	return(result);
be_bryan	0:b74591d5ab33	374	}
be_bryan	0:b74591d5ab33	375
be_bryan	0:b74591d5ab33	376
be_bryan	0:b74591d5ab33	377	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	378	/**
be_bryan	0:b74591d5ab33	379	\brief Get Priority Mask (non-secure)
be_bryan	0:b74591d5ab33	380	\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
be_bryan	0:b74591d5ab33	381	\return Priority Mask value
be_bryan	0:b74591d5ab33	382	*/
be_bryan	0:b74591d5ab33	383	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
be_bryan	0:b74591d5ab33	384	{
be_bryan	0:b74591d5ab33	385	uint32_t result;
be_bryan	0:b74591d5ab33	386
be_bryan	0:b74591d5ab33	387	__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
be_bryan	0:b74591d5ab33	388	return(result);
be_bryan	0:b74591d5ab33	389	}
be_bryan	0:b74591d5ab33	390	#endif
be_bryan	0:b74591d5ab33	391
be_bryan	0:b74591d5ab33	392
be_bryan	0:b74591d5ab33	393	/**
be_bryan	0:b74591d5ab33	394	\brief Set Priority Mask
be_bryan	0:b74591d5ab33	395	\details Assigns the given value to the Priority Mask Register.
be_bryan	0:b74591d5ab33	396	\param [in] priMask Priority Mask
be_bryan	0:b74591d5ab33	397	*/
be_bryan	0:b74591d5ab33	398	__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
be_bryan	0:b74591d5ab33	399	{
be_bryan	0:b74591d5ab33	400	__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
be_bryan	0:b74591d5ab33	401	}
be_bryan	0:b74591d5ab33	402
be_bryan	0:b74591d5ab33	403
be_bryan	0:b74591d5ab33	404	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	405	/**
be_bryan	0:b74591d5ab33	406	\brief Set Priority Mask (non-secure)
be_bryan	0:b74591d5ab33	407	\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
be_bryan	0:b74591d5ab33	408	\param [in] priMask Priority Mask
be_bryan	0:b74591d5ab33	409	*/
be_bryan	0:b74591d5ab33	410	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
be_bryan	0:b74591d5ab33	411	{
be_bryan	0:b74591d5ab33	412	__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
be_bryan	0:b74591d5ab33	413	}
be_bryan	0:b74591d5ab33	414	#endif
be_bryan	0:b74591d5ab33	415
be_bryan	0:b74591d5ab33	416
be_bryan	0:b74591d5ab33	417	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	418	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	419	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
be_bryan	0:b74591d5ab33	420	/**
be_bryan	0:b74591d5ab33	421	\brief Enable FIQ
be_bryan	0:b74591d5ab33	422	\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
be_bryan	0:b74591d5ab33	423	Can only be executed in Privileged modes.
be_bryan	0:b74591d5ab33	424	*/
be_bryan	0:b74591d5ab33	425	#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
be_bryan	0:b74591d5ab33	426
be_bryan	0:b74591d5ab33	427
be_bryan	0:b74591d5ab33	428	/**
be_bryan	0:b74591d5ab33	429	\brief Disable FIQ
be_bryan	0:b74591d5ab33	430	\details Disables FIQ interrupts by setting the F-bit in the CPSR.
be_bryan	0:b74591d5ab33	431	Can only be executed in Privileged modes.
be_bryan	0:b74591d5ab33	432	*/
be_bryan	0:b74591d5ab33	433	#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
be_bryan	0:b74591d5ab33	434
be_bryan	0:b74591d5ab33	435
be_bryan	0:b74591d5ab33	436	/**
be_bryan	0:b74591d5ab33	437	\brief Get Base Priority
be_bryan	0:b74591d5ab33	438	\details Returns the current value of the Base Priority register.
be_bryan	0:b74591d5ab33	439	\return Base Priority register value
be_bryan	0:b74591d5ab33	440	*/
be_bryan	0:b74591d5ab33	441	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
be_bryan	0:b74591d5ab33	442	{
be_bryan	0:b74591d5ab33	443	uint32_t result;
be_bryan	0:b74591d5ab33	444
be_bryan	0:b74591d5ab33	445	__ASM volatile ("MRS %0, basepri" : "=r" (result) );
be_bryan	0:b74591d5ab33	446	return(result);
be_bryan	0:b74591d5ab33	447	}
be_bryan	0:b74591d5ab33	448
be_bryan	0:b74591d5ab33	449
be_bryan	0:b74591d5ab33	450	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	451	/**
be_bryan	0:b74591d5ab33	452	\brief Get Base Priority (non-secure)
be_bryan	0:b74591d5ab33	453	\details Returns the current value of the non-secure Base Priority register when in secure state.
be_bryan	0:b74591d5ab33	454	\return Base Priority register value
be_bryan	0:b74591d5ab33	455	*/
be_bryan	0:b74591d5ab33	456	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
be_bryan	0:b74591d5ab33	457	{
be_bryan	0:b74591d5ab33	458	uint32_t result;
be_bryan	0:b74591d5ab33	459
be_bryan	0:b74591d5ab33	460	__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
be_bryan	0:b74591d5ab33	461	return(result);
be_bryan	0:b74591d5ab33	462	}
be_bryan	0:b74591d5ab33	463	#endif
be_bryan	0:b74591d5ab33	464
be_bryan	0:b74591d5ab33	465
be_bryan	0:b74591d5ab33	466	/**
be_bryan	0:b74591d5ab33	467	\brief Set Base Priority
be_bryan	0:b74591d5ab33	468	\details Assigns the given value to the Base Priority register.
be_bryan	0:b74591d5ab33	469	\param [in] basePri Base Priority value to set
be_bryan	0:b74591d5ab33	470	*/
be_bryan	0:b74591d5ab33	471	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
be_bryan	0:b74591d5ab33	472	{
be_bryan	0:b74591d5ab33	473	__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
be_bryan	0:b74591d5ab33	474	}
be_bryan	0:b74591d5ab33	475
be_bryan	0:b74591d5ab33	476
be_bryan	0:b74591d5ab33	477	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	478	/**
be_bryan	0:b74591d5ab33	479	\brief Set Base Priority (non-secure)
be_bryan	0:b74591d5ab33	480	\details Assigns the given value to the non-secure Base Priority register when in secure state.
be_bryan	0:b74591d5ab33	481	\param [in] basePri Base Priority value to set
be_bryan	0:b74591d5ab33	482	*/
be_bryan	0:b74591d5ab33	483	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
be_bryan	0:b74591d5ab33	484	{
be_bryan	0:b74591d5ab33	485	__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
be_bryan	0:b74591d5ab33	486	}
be_bryan	0:b74591d5ab33	487	#endif
be_bryan	0:b74591d5ab33	488
be_bryan	0:b74591d5ab33	489
be_bryan	0:b74591d5ab33	490	/**
be_bryan	0:b74591d5ab33	491	\brief Set Base Priority with condition
be_bryan	0:b74591d5ab33	492	\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
be_bryan	0:b74591d5ab33	493	or the new value increases the BASEPRI priority level.
be_bryan	0:b74591d5ab33	494	\param [in] basePri Base Priority value to set
be_bryan	0:b74591d5ab33	495	*/
be_bryan	0:b74591d5ab33	496	__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
be_bryan	0:b74591d5ab33	497	{
be_bryan	0:b74591d5ab33	498	__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
be_bryan	0:b74591d5ab33	499	}
be_bryan	0:b74591d5ab33	500
be_bryan	0:b74591d5ab33	501
be_bryan	0:b74591d5ab33	502	/**
be_bryan	0:b74591d5ab33	503	\brief Get Fault Mask
be_bryan	0:b74591d5ab33	504	\details Returns the current value of the Fault Mask register.
be_bryan	0:b74591d5ab33	505	\return Fault Mask register value
be_bryan	0:b74591d5ab33	506	*/
be_bryan	0:b74591d5ab33	507	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
be_bryan	0:b74591d5ab33	508	{
be_bryan	0:b74591d5ab33	509	uint32_t result;
be_bryan	0:b74591d5ab33	510
be_bryan	0:b74591d5ab33	511	__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
be_bryan	0:b74591d5ab33	512	return(result);
be_bryan	0:b74591d5ab33	513	}
be_bryan	0:b74591d5ab33	514
be_bryan	0:b74591d5ab33	515
be_bryan	0:b74591d5ab33	516	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	517	/**
be_bryan	0:b74591d5ab33	518	\brief Get Fault Mask (non-secure)
be_bryan	0:b74591d5ab33	519	\details Returns the current value of the non-secure Fault Mask register when in secure state.
be_bryan	0:b74591d5ab33	520	\return Fault Mask register value
be_bryan	0:b74591d5ab33	521	*/
be_bryan	0:b74591d5ab33	522	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
be_bryan	0:b74591d5ab33	523	{
be_bryan	0:b74591d5ab33	524	uint32_t result;
be_bryan	0:b74591d5ab33	525
be_bryan	0:b74591d5ab33	526	__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
be_bryan	0:b74591d5ab33	527	return(result);
be_bryan	0:b74591d5ab33	528	}
be_bryan	0:b74591d5ab33	529	#endif
be_bryan	0:b74591d5ab33	530
be_bryan	0:b74591d5ab33	531
be_bryan	0:b74591d5ab33	532	/**
be_bryan	0:b74591d5ab33	533	\brief Set Fault Mask
be_bryan	0:b74591d5ab33	534	\details Assigns the given value to the Fault Mask register.
be_bryan	0:b74591d5ab33	535	\param [in] faultMask Fault Mask value to set
be_bryan	0:b74591d5ab33	536	*/
be_bryan	0:b74591d5ab33	537	__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
be_bryan	0:b74591d5ab33	538	{
be_bryan	0:b74591d5ab33	539	__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
be_bryan	0:b74591d5ab33	540	}
be_bryan	0:b74591d5ab33	541
be_bryan	0:b74591d5ab33	542
be_bryan	0:b74591d5ab33	543	#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
be_bryan	0:b74591d5ab33	544	/**
be_bryan	0:b74591d5ab33	545	\brief Set Fault Mask (non-secure)
be_bryan	0:b74591d5ab33	546	\details Assigns the given value to the non-secure Fault Mask register when in secure state.
be_bryan	0:b74591d5ab33	547	\param [in] faultMask Fault Mask value to set
be_bryan	0:b74591d5ab33	548	*/
be_bryan	0:b74591d5ab33	549	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
be_bryan	0:b74591d5ab33	550	{
be_bryan	0:b74591d5ab33	551	__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
be_bryan	0:b74591d5ab33	552	}
be_bryan	0:b74591d5ab33	553	#endif
be_bryan	0:b74591d5ab33	554
be_bryan	0:b74591d5ab33	555	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	556	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	557	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
be_bryan	0:b74591d5ab33	558
be_bryan	0:b74591d5ab33	559
be_bryan	0:b74591d5ab33	560	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	561	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
be_bryan	0:b74591d5ab33	562
be_bryan	0:b74591d5ab33	563	/**
be_bryan	0:b74591d5ab33	564	\brief Get Process Stack Pointer Limit
be_bryan	0:b74591d5ab33	565	\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
be_bryan	0:b74591d5ab33	566	\return PSPLIM Register value
be_bryan	0:b74591d5ab33	567	*/
be_bryan	0:b74591d5ab33	568	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
be_bryan	0:b74591d5ab33	569	{
be_bryan	0:b74591d5ab33	570	register uint32_t result;
be_bryan	0:b74591d5ab33	571
be_bryan	0:b74591d5ab33	572	__ASM volatile ("MRS %0, psplim" : "=r" (result) );
be_bryan	0:b74591d5ab33	573	return(result);
be_bryan	0:b74591d5ab33	574	}
be_bryan	0:b74591d5ab33	575
be_bryan	0:b74591d5ab33	576
be_bryan	0:b74591d5ab33	577	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
be_bryan	0:b74591d5ab33	578	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
be_bryan	0:b74591d5ab33	579	/**
be_bryan	0:b74591d5ab33	580	\brief Get Process Stack Pointer Limit (non-secure)
be_bryan	0:b74591d5ab33	581	\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
be_bryan	0:b74591d5ab33	582	\return PSPLIM Register value
be_bryan	0:b74591d5ab33	583	*/
be_bryan	0:b74591d5ab33	584	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
be_bryan	0:b74591d5ab33	585	{
be_bryan	0:b74591d5ab33	586	register uint32_t result;
be_bryan	0:b74591d5ab33	587
be_bryan	0:b74591d5ab33	588	__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
be_bryan	0:b74591d5ab33	589	return(result);
be_bryan	0:b74591d5ab33	590	}
be_bryan	0:b74591d5ab33	591	#endif
be_bryan	0:b74591d5ab33	592
be_bryan	0:b74591d5ab33	593
be_bryan	0:b74591d5ab33	594	/**
be_bryan	0:b74591d5ab33	595	\brief Set Process Stack Pointer Limit
be_bryan	0:b74591d5ab33	596	\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
be_bryan	0:b74591d5ab33	597	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
be_bryan	0:b74591d5ab33	598	*/
be_bryan	0:b74591d5ab33	599	__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
be_bryan	0:b74591d5ab33	600	{
be_bryan	0:b74591d5ab33	601	__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
be_bryan	0:b74591d5ab33	602	}
be_bryan	0:b74591d5ab33	603
be_bryan	0:b74591d5ab33	604
be_bryan	0:b74591d5ab33	605	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
be_bryan	0:b74591d5ab33	606	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
be_bryan	0:b74591d5ab33	607	/**
be_bryan	0:b74591d5ab33	608	\brief Set Process Stack Pointer (non-secure)
be_bryan	0:b74591d5ab33	609	\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
be_bryan	0:b74591d5ab33	610	\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
be_bryan	0:b74591d5ab33	611	*/
be_bryan	0:b74591d5ab33	612	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
be_bryan	0:b74591d5ab33	613	{
be_bryan	0:b74591d5ab33	614	__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
be_bryan	0:b74591d5ab33	615	}
be_bryan	0:b74591d5ab33	616	#endif
be_bryan	0:b74591d5ab33	617
be_bryan	0:b74591d5ab33	618
be_bryan	0:b74591d5ab33	619	/**
be_bryan	0:b74591d5ab33	620	\brief Get Main Stack Pointer Limit
be_bryan	0:b74591d5ab33	621	\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
be_bryan	0:b74591d5ab33	622	\return MSPLIM Register value
be_bryan	0:b74591d5ab33	623	*/
be_bryan	0:b74591d5ab33	624	__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
be_bryan	0:b74591d5ab33	625	{
be_bryan	0:b74591d5ab33	626	register uint32_t result;
be_bryan	0:b74591d5ab33	627
be_bryan	0:b74591d5ab33	628	__ASM volatile ("MRS %0, msplim" : "=r" (result) );
be_bryan	0:b74591d5ab33	629
be_bryan	0:b74591d5ab33	630	return(result);
be_bryan	0:b74591d5ab33	631	}
be_bryan	0:b74591d5ab33	632
be_bryan	0:b74591d5ab33	633
be_bryan	0:b74591d5ab33	634	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
be_bryan	0:b74591d5ab33	635	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
be_bryan	0:b74591d5ab33	636	/**
be_bryan	0:b74591d5ab33	637	\brief Get Main Stack Pointer Limit (non-secure)
be_bryan	0:b74591d5ab33	638	\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
be_bryan	0:b74591d5ab33	639	\return MSPLIM Register value
be_bryan	0:b74591d5ab33	640	*/
be_bryan	0:b74591d5ab33	641	__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
be_bryan	0:b74591d5ab33	642	{
be_bryan	0:b74591d5ab33	643	register uint32_t result;
be_bryan	0:b74591d5ab33	644
be_bryan	0:b74591d5ab33	645	__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
be_bryan	0:b74591d5ab33	646	return(result);
be_bryan	0:b74591d5ab33	647	}
be_bryan	0:b74591d5ab33	648	#endif
be_bryan	0:b74591d5ab33	649
be_bryan	0:b74591d5ab33	650
be_bryan	0:b74591d5ab33	651	/**
be_bryan	0:b74591d5ab33	652	\brief Set Main Stack Pointer Limit
be_bryan	0:b74591d5ab33	653	\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
be_bryan	0:b74591d5ab33	654	\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
be_bryan	0:b74591d5ab33	655	*/
be_bryan	0:b74591d5ab33	656	__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
be_bryan	0:b74591d5ab33	657	{
be_bryan	0:b74591d5ab33	658	__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
be_bryan	0:b74591d5ab33	659	}
be_bryan	0:b74591d5ab33	660
be_bryan	0:b74591d5ab33	661
be_bryan	0:b74591d5ab33	662	#if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
be_bryan	0:b74591d5ab33	663	(defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
be_bryan	0:b74591d5ab33	664	/**
be_bryan	0:b74591d5ab33	665	\brief Set Main Stack Pointer Limit (non-secure)
be_bryan	0:b74591d5ab33	666	\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
be_bryan	0:b74591d5ab33	667	\param [in] MainStackPtrLimit Main Stack Pointer value to set
be_bryan	0:b74591d5ab33	668	*/
be_bryan	0:b74591d5ab33	669	__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
be_bryan	0:b74591d5ab33	670	{
be_bryan	0:b74591d5ab33	671	__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
be_bryan	0:b74591d5ab33	672	}
be_bryan	0:b74591d5ab33	673	#endif
be_bryan	0:b74591d5ab33	674
be_bryan	0:b74591d5ab33	675	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	676	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
be_bryan	0:b74591d5ab33	677
be_bryan	0:b74591d5ab33	678
be_bryan	0:b74591d5ab33	679	#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	680	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
be_bryan	0:b74591d5ab33	681
be_bryan	0:b74591d5ab33	682	/**
be_bryan	0:b74591d5ab33	683	\brief Get FPSCR
be_bryan	0:b74591d5ab33	684	\details Returns the current value of the Floating Point Status/Control register.
be_bryan	0:b74591d5ab33	685	\return Floating Point Status/Control register value
be_bryan	0:b74591d5ab33	686	*/
be_bryan	0:b74591d5ab33	687	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
be_bryan	0:b74591d5ab33	688	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
be_bryan	0:b74591d5ab33	689	#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
be_bryan	0:b74591d5ab33	690	#else
be_bryan	0:b74591d5ab33	691	#define __get_FPSCR() ((uint32_t)0U)
be_bryan	0:b74591d5ab33	692	#endif
be_bryan	0:b74591d5ab33	693
be_bryan	0:b74591d5ab33	694	/**
be_bryan	0:b74591d5ab33	695	\brief Set FPSCR
be_bryan	0:b74591d5ab33	696	\details Assigns the given value to the Floating Point Status/Control register.
be_bryan	0:b74591d5ab33	697	\param [in] fpscr Floating Point Status/Control value to set
be_bryan	0:b74591d5ab33	698	*/
be_bryan	0:b74591d5ab33	699	#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
be_bryan	0:b74591d5ab33	700	(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
be_bryan	0:b74591d5ab33	701	#define __set_FPSCR __builtin_arm_set_fpscr
be_bryan	0:b74591d5ab33	702	#else
be_bryan	0:b74591d5ab33	703	#define __set_FPSCR(x) ((void)(x))
be_bryan	0:b74591d5ab33	704	#endif
be_bryan	0:b74591d5ab33	705
be_bryan	0:b74591d5ab33	706	#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	707	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
be_bryan	0:b74591d5ab33	708
be_bryan	0:b74591d5ab33	709
be_bryan	0:b74591d5ab33	710
be_bryan	0:b74591d5ab33	711	/@} end of CMSIS_Core_RegAccFunctions /
be_bryan	0:b74591d5ab33	712
be_bryan	0:b74591d5ab33	713
be_bryan	0:b74591d5ab33	714	/* ########################## Core Instruction Access ######################### */
be_bryan	0:b74591d5ab33	715	/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
be_bryan	0:b74591d5ab33	716	Access to dedicated instructions
be_bryan	0:b74591d5ab33	717	@{
be_bryan	0:b74591d5ab33	718	*/
be_bryan	0:b74591d5ab33	719
be_bryan	0:b74591d5ab33	720	/* Define macros for porting to both thumb1 and thumb2.
be_bryan	0:b74591d5ab33	721	* For thumb1, use low register (r0-r7), specified by constraint "l"
be_bryan	0:b74591d5ab33	722	* Otherwise, use general registers, specified by constraint "r" */
be_bryan	0:b74591d5ab33	723	#if defined (__thumb__) && !defined (__thumb2__)
be_bryan	0:b74591d5ab33	724	#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
be_bryan	0:b74591d5ab33	725	#define __CMSIS_GCC_USE_REG(r) "l" (r)
be_bryan	0:b74591d5ab33	726	#else
be_bryan	0:b74591d5ab33	727	#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
be_bryan	0:b74591d5ab33	728	#define __CMSIS_GCC_USE_REG(r) "r" (r)
be_bryan	0:b74591d5ab33	729	#endif
be_bryan	0:b74591d5ab33	730
be_bryan	0:b74591d5ab33	731	/**
be_bryan	0:b74591d5ab33	732	\brief No Operation
be_bryan	0:b74591d5ab33	733	\details No Operation does nothing. This instruction can be used for code alignment purposes.
be_bryan	0:b74591d5ab33	734	*/
be_bryan	0:b74591d5ab33	735	#define __NOP __builtin_arm_nop
be_bryan	0:b74591d5ab33	736
be_bryan	0:b74591d5ab33	737	/**
be_bryan	0:b74591d5ab33	738	\brief Wait For Interrupt
be_bryan	0:b74591d5ab33	739	\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
be_bryan	0:b74591d5ab33	740	*/
be_bryan	0:b74591d5ab33	741	#define __WFI __builtin_arm_wfi
be_bryan	0:b74591d5ab33	742
be_bryan	0:b74591d5ab33	743
be_bryan	0:b74591d5ab33	744	/**
be_bryan	0:b74591d5ab33	745	\brief Wait For Event
be_bryan	0:b74591d5ab33	746	\details Wait For Event is a hint instruction that permits the processor to enter
be_bryan	0:b74591d5ab33	747	a low-power state until one of a number of events occurs.
be_bryan	0:b74591d5ab33	748	*/
be_bryan	0:b74591d5ab33	749	#define __WFE __builtin_arm_wfe
be_bryan	0:b74591d5ab33	750
be_bryan	0:b74591d5ab33	751
be_bryan	0:b74591d5ab33	752	/**
be_bryan	0:b74591d5ab33	753	\brief Send Event
be_bryan	0:b74591d5ab33	754	\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
be_bryan	0:b74591d5ab33	755	*/
be_bryan	0:b74591d5ab33	756	#define __SEV __builtin_arm_sev
be_bryan	0:b74591d5ab33	757
be_bryan	0:b74591d5ab33	758
be_bryan	0:b74591d5ab33	759	/**
be_bryan	0:b74591d5ab33	760	\brief Instruction Synchronization Barrier
be_bryan	0:b74591d5ab33	761	\details Instruction Synchronization Barrier flushes the pipeline in the processor,
be_bryan	0:b74591d5ab33	762	so that all instructions following the ISB are fetched from cache or memory,
be_bryan	0:b74591d5ab33	763	after the instruction has been completed.
be_bryan	0:b74591d5ab33	764	*/
be_bryan	0:b74591d5ab33	765	#define __ISB() __builtin_arm_isb(0xF);
be_bryan	0:b74591d5ab33	766
be_bryan	0:b74591d5ab33	767	/**
be_bryan	0:b74591d5ab33	768	\brief Data Synchronization Barrier
be_bryan	0:b74591d5ab33	769	\details Acts as a special kind of Data Memory Barrier.
be_bryan	0:b74591d5ab33	770	It completes when all explicit memory accesses before this instruction complete.
be_bryan	0:b74591d5ab33	771	*/
be_bryan	0:b74591d5ab33	772	#define __DSB() __builtin_arm_dsb(0xF);
be_bryan	0:b74591d5ab33	773
be_bryan	0:b74591d5ab33	774
be_bryan	0:b74591d5ab33	775	/**
be_bryan	0:b74591d5ab33	776	\brief Data Memory Barrier
be_bryan	0:b74591d5ab33	777	\details Ensures the apparent order of the explicit memory operations before
be_bryan	0:b74591d5ab33	778	and after the instruction, without ensuring their completion.
be_bryan	0:b74591d5ab33	779	*/
be_bryan	0:b74591d5ab33	780	#define __DMB() __builtin_arm_dmb(0xF);
be_bryan	0:b74591d5ab33	781
be_bryan	0:b74591d5ab33	782
be_bryan	0:b74591d5ab33	783	/**
be_bryan	0:b74591d5ab33	784	\brief Reverse byte order (32 bit)
be_bryan	0:b74591d5ab33	785	\details Reverses the byte order in integer value.
be_bryan	0:b74591d5ab33	786	\param [in] value Value to reverse
be_bryan	0:b74591d5ab33	787	\return Reversed value
be_bryan	0:b74591d5ab33	788	*/
be_bryan	0:b74591d5ab33	789	#define __REV (uint32_t)__builtin_bswap32
be_bryan	0:b74591d5ab33	790
be_bryan	0:b74591d5ab33	791
be_bryan	0:b74591d5ab33	792	/**
be_bryan	0:b74591d5ab33	793	\brief Reverse byte order (16 bit)
be_bryan	0:b74591d5ab33	794	\details Reverses the byte order in two unsigned short values.
be_bryan	0:b74591d5ab33	795	\param [in] value Value to reverse
be_bryan	0:b74591d5ab33	796	\return Reversed value
be_bryan	0:b74591d5ab33	797	*/
be_bryan	0:b74591d5ab33	798	#define __REV16 (uint16_t)__builtin_bswap16
be_bryan	0:b74591d5ab33	799
be_bryan	0:b74591d5ab33	800
be_bryan	0:b74591d5ab33	801	/**
be_bryan	0:b74591d5ab33	802	\brief Reverse byte order in signed short value
be_bryan	0:b74591d5ab33	803	\details Reverses the byte order in a signed short value with sign extension to integer.
be_bryan	0:b74591d5ab33	804	\param [in] value Value to reverse
be_bryan	0:b74591d5ab33	805	\return Reversed value
be_bryan	0:b74591d5ab33	806	*/
be_bryan	0:b74591d5ab33	807	__attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value)
be_bryan	0:b74591d5ab33	808	{
be_bryan	0:b74591d5ab33	809	int16_t result;
be_bryan	0:b74591d5ab33	810
be_bryan	0:b74591d5ab33	811	__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
be_bryan	0:b74591d5ab33	812
be_bryan	0:b74591d5ab33	813	return result;
be_bryan	0:b74591d5ab33	814	}
be_bryan	0:b74591d5ab33	815
be_bryan	0:b74591d5ab33	816
be_bryan	0:b74591d5ab33	817	/**
be_bryan	0:b74591d5ab33	818	\brief Rotate Right in unsigned value (32 bit)
be_bryan	0:b74591d5ab33	819	\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
be_bryan	0:b74591d5ab33	820	\param [in] op1 Value to rotate
be_bryan	0:b74591d5ab33	821	\param [in] op2 Number of Bits to rotate
be_bryan	0:b74591d5ab33	822	\return Rotated value
be_bryan	0:b74591d5ab33	823	*/
be_bryan	0:b74591d5ab33	824	__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	825	{
be_bryan	0:b74591d5ab33	826	return (op1 >> op2) \| (op1 << (32U - op2));
be_bryan	0:b74591d5ab33	827	}
be_bryan	0:b74591d5ab33	828
be_bryan	0:b74591d5ab33	829
be_bryan	0:b74591d5ab33	830	/**
be_bryan	0:b74591d5ab33	831	\brief Breakpoint
be_bryan	0:b74591d5ab33	832	\details Causes the processor to enter Debug state.
be_bryan	0:b74591d5ab33	833	Debug tools can use this to investigate system state when the instruction at a particular address is reached.
be_bryan	0:b74591d5ab33	834	\param [in] value is ignored by the processor.
be_bryan	0:b74591d5ab33	835	If required, a debugger can use it to store additional information about the breakpoint.
be_bryan	0:b74591d5ab33	836	*/
be_bryan	0:b74591d5ab33	837	#define __BKPT(value) __ASM volatile ("bkpt "#value)
be_bryan	0:b74591d5ab33	838
be_bryan	0:b74591d5ab33	839
be_bryan	0:b74591d5ab33	840	/**
be_bryan	0:b74591d5ab33	841	\brief Reverse bit order of value
be_bryan	0:b74591d5ab33	842	\details Reverses the bit order of the given value.
be_bryan	0:b74591d5ab33	843	\param [in] value Value to reverse
be_bryan	0:b74591d5ab33	844	\return Reversed value
be_bryan	0:b74591d5ab33	845	*/
be_bryan	0:b74591d5ab33	846	#define __RBIT (uint32_t)__builtin_arm_rbit
be_bryan	0:b74591d5ab33	847
be_bryan	0:b74591d5ab33	848	/**
be_bryan	0:b74591d5ab33	849	\brief Count leading zeros
be_bryan	0:b74591d5ab33	850	\details Counts the number of leading zeros of a data value.
be_bryan	0:b74591d5ab33	851	\param [in] value Value to count the leading zeros
be_bryan	0:b74591d5ab33	852	\return number of leading zeros in value
be_bryan	0:b74591d5ab33	853	*/
be_bryan	0:b74591d5ab33	854	#define __CLZ __builtin_clz
be_bryan	0:b74591d5ab33	855
be_bryan	0:b74591d5ab33	856
be_bryan	0:b74591d5ab33	857	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	858	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	859	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	860	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
be_bryan	0:b74591d5ab33	861	/**
be_bryan	0:b74591d5ab33	862	\brief LDR Exclusive (8 bit)
be_bryan	0:b74591d5ab33	863	\details Executes a exclusive LDR instruction for 8 bit value.
be_bryan	0:b74591d5ab33	864	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	865	\return value of type uint8_t at (*ptr)
be_bryan	0:b74591d5ab33	866	*/
be_bryan	0:b74591d5ab33	867	#define __LDREXB (uint8_t)__builtin_arm_ldrex
be_bryan	0:b74591d5ab33	868
be_bryan	0:b74591d5ab33	869
be_bryan	0:b74591d5ab33	870	/**
be_bryan	0:b74591d5ab33	871	\brief LDR Exclusive (16 bit)
be_bryan	0:b74591d5ab33	872	\details Executes a exclusive LDR instruction for 16 bit values.
be_bryan	0:b74591d5ab33	873	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	874	\return value of type uint16_t at (*ptr)
be_bryan	0:b74591d5ab33	875	*/
be_bryan	0:b74591d5ab33	876	#define __LDREXH (uint16_t)__builtin_arm_ldrex
be_bryan	0:b74591d5ab33	877
be_bryan	0:b74591d5ab33	878
be_bryan	0:b74591d5ab33	879	/**
be_bryan	0:b74591d5ab33	880	\brief LDR Exclusive (32 bit)
be_bryan	0:b74591d5ab33	881	\details Executes a exclusive LDR instruction for 32 bit values.
be_bryan	0:b74591d5ab33	882	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	883	\return value of type uint32_t at (*ptr)
be_bryan	0:b74591d5ab33	884	*/
be_bryan	0:b74591d5ab33	885	#define __LDREXW (uint32_t)__builtin_arm_ldrex
be_bryan	0:b74591d5ab33	886
be_bryan	0:b74591d5ab33	887
be_bryan	0:b74591d5ab33	888	/**
be_bryan	0:b74591d5ab33	889	\brief STR Exclusive (8 bit)
be_bryan	0:b74591d5ab33	890	\details Executes a exclusive STR instruction for 8 bit values.
be_bryan	0:b74591d5ab33	891	\param [in] value Value to store
be_bryan	0:b74591d5ab33	892	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	893	\return 0 Function succeeded
be_bryan	0:b74591d5ab33	894	\return 1 Function failed
be_bryan	0:b74591d5ab33	895	*/
be_bryan	0:b74591d5ab33	896	#define __STREXB (uint32_t)__builtin_arm_strex
be_bryan	0:b74591d5ab33	897
be_bryan	0:b74591d5ab33	898
be_bryan	0:b74591d5ab33	899	/**
be_bryan	0:b74591d5ab33	900	\brief STR Exclusive (16 bit)
be_bryan	0:b74591d5ab33	901	\details Executes a exclusive STR instruction for 16 bit values.
be_bryan	0:b74591d5ab33	902	\param [in] value Value to store
be_bryan	0:b74591d5ab33	903	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	904	\return 0 Function succeeded
be_bryan	0:b74591d5ab33	905	\return 1 Function failed
be_bryan	0:b74591d5ab33	906	*/
be_bryan	0:b74591d5ab33	907	#define __STREXH (uint32_t)__builtin_arm_strex
be_bryan	0:b74591d5ab33	908
be_bryan	0:b74591d5ab33	909
be_bryan	0:b74591d5ab33	910	/**
be_bryan	0:b74591d5ab33	911	\brief STR Exclusive (32 bit)
be_bryan	0:b74591d5ab33	912	\details Executes a exclusive STR instruction for 32 bit values.
be_bryan	0:b74591d5ab33	913	\param [in] value Value to store
be_bryan	0:b74591d5ab33	914	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	915	\return 0 Function succeeded
be_bryan	0:b74591d5ab33	916	\return 1 Function failed
be_bryan	0:b74591d5ab33	917	*/
be_bryan	0:b74591d5ab33	918	#define __STREXW (uint32_t)__builtin_arm_strex
be_bryan	0:b74591d5ab33	919
be_bryan	0:b74591d5ab33	920
be_bryan	0:b74591d5ab33	921	/**
be_bryan	0:b74591d5ab33	922	\brief Remove the exclusive lock
be_bryan	0:b74591d5ab33	923	\details Removes the exclusive lock which is created by LDREX.
be_bryan	0:b74591d5ab33	924	*/
be_bryan	0:b74591d5ab33	925	#define __CLREX __builtin_arm_clrex
be_bryan	0:b74591d5ab33	926
be_bryan	0:b74591d5ab33	927	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	928	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	929	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	930	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
be_bryan	0:b74591d5ab33	931
be_bryan	0:b74591d5ab33	932
be_bryan	0:b74591d5ab33	933	#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	934	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	935	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
be_bryan	0:b74591d5ab33	936
be_bryan	0:b74591d5ab33	937	/**
be_bryan	0:b74591d5ab33	938	\brief Signed Saturate
be_bryan	0:b74591d5ab33	939	\details Saturates a signed value.
be_bryan	0:b74591d5ab33	940	\param [in] value Value to be saturated
be_bryan	0:b74591d5ab33	941	\param [in] sat Bit position to saturate to (1..32)
be_bryan	0:b74591d5ab33	942	\return Saturated value
be_bryan	0:b74591d5ab33	943	*/
be_bryan	0:b74591d5ab33	944	#define __SSAT __builtin_arm_ssat
be_bryan	0:b74591d5ab33	945
be_bryan	0:b74591d5ab33	946
be_bryan	0:b74591d5ab33	947	/**
be_bryan	0:b74591d5ab33	948	\brief Unsigned Saturate
be_bryan	0:b74591d5ab33	949	\details Saturates an unsigned value.
be_bryan	0:b74591d5ab33	950	\param [in] value Value to be saturated
be_bryan	0:b74591d5ab33	951	\param [in] sat Bit position to saturate to (0..31)
be_bryan	0:b74591d5ab33	952	\return Saturated value
be_bryan	0:b74591d5ab33	953	*/
be_bryan	0:b74591d5ab33	954	#define __USAT __builtin_arm_usat
be_bryan	0:b74591d5ab33	955
be_bryan	0:b74591d5ab33	956
be_bryan	0:b74591d5ab33	957	/**
be_bryan	0:b74591d5ab33	958	\brief Rotate Right with Extend (32 bit)
be_bryan	0:b74591d5ab33	959	\details Moves each bit of a bitstring right by one bit.
be_bryan	0:b74591d5ab33	960	The carry input is shifted in at the left end of the bitstring.
be_bryan	0:b74591d5ab33	961	\param [in] value Value to rotate
be_bryan	0:b74591d5ab33	962	\return Rotated value
be_bryan	0:b74591d5ab33	963	*/
be_bryan	0:b74591d5ab33	964	__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
be_bryan	0:b74591d5ab33	965	{
be_bryan	0:b74591d5ab33	966	uint32_t result;
be_bryan	0:b74591d5ab33	967
be_bryan	0:b74591d5ab33	968	__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
be_bryan	0:b74591d5ab33	969	return(result);
be_bryan	0:b74591d5ab33	970	}
be_bryan	0:b74591d5ab33	971
be_bryan	0:b74591d5ab33	972
be_bryan	0:b74591d5ab33	973	/**
be_bryan	0:b74591d5ab33	974	\brief LDRT Unprivileged (8 bit)
be_bryan	0:b74591d5ab33	975	\details Executes a Unprivileged LDRT instruction for 8 bit value.
be_bryan	0:b74591d5ab33	976	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	977	\return value of type uint8_t at (*ptr)
be_bryan	0:b74591d5ab33	978	*/
be_bryan	0:b74591d5ab33	979	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
be_bryan	0:b74591d5ab33	980	{
be_bryan	0:b74591d5ab33	981	uint32_t result;
be_bryan	0:b74591d5ab33	982
be_bryan	0:b74591d5ab33	983	__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
be_bryan	0:b74591d5ab33	984	return ((uint8_t) result); /* Add explicit type cast here */
be_bryan	0:b74591d5ab33	985	}
be_bryan	0:b74591d5ab33	986
be_bryan	0:b74591d5ab33	987
be_bryan	0:b74591d5ab33	988	/**
be_bryan	0:b74591d5ab33	989	\brief LDRT Unprivileged (16 bit)
be_bryan	0:b74591d5ab33	990	\details Executes a Unprivileged LDRT instruction for 16 bit values.
be_bryan	0:b74591d5ab33	991	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	992	\return value of type uint16_t at (*ptr)
be_bryan	0:b74591d5ab33	993	*/
be_bryan	0:b74591d5ab33	994	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
be_bryan	0:b74591d5ab33	995	{
be_bryan	0:b74591d5ab33	996	uint32_t result;
be_bryan	0:b74591d5ab33	997
be_bryan	0:b74591d5ab33	998	__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
be_bryan	0:b74591d5ab33	999	return ((uint16_t) result); /* Add explicit type cast here */
be_bryan	0:b74591d5ab33	1000	}
be_bryan	0:b74591d5ab33	1001
be_bryan	0:b74591d5ab33	1002
be_bryan	0:b74591d5ab33	1003	/**
be_bryan	0:b74591d5ab33	1004	\brief LDRT Unprivileged (32 bit)
be_bryan	0:b74591d5ab33	1005	\details Executes a Unprivileged LDRT instruction for 32 bit values.
be_bryan	0:b74591d5ab33	1006	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	1007	\return value of type uint32_t at (*ptr)
be_bryan	0:b74591d5ab33	1008	*/
be_bryan	0:b74591d5ab33	1009	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
be_bryan	0:b74591d5ab33	1010	{
be_bryan	0:b74591d5ab33	1011	uint32_t result;
be_bryan	0:b74591d5ab33	1012
be_bryan	0:b74591d5ab33	1013	__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
be_bryan	0:b74591d5ab33	1014	return(result);
be_bryan	0:b74591d5ab33	1015	}
be_bryan	0:b74591d5ab33	1016
be_bryan	0:b74591d5ab33	1017
be_bryan	0:b74591d5ab33	1018	/**
be_bryan	0:b74591d5ab33	1019	\brief STRT Unprivileged (8 bit)
be_bryan	0:b74591d5ab33	1020	\details Executes a Unprivileged STRT instruction for 8 bit values.
be_bryan	0:b74591d5ab33	1021	\param [in] value Value to store
be_bryan	0:b74591d5ab33	1022	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	1023	*/
be_bryan	0:b74591d5ab33	1024	__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
be_bryan	0:b74591d5ab33	1025	{
be_bryan	0:b74591d5ab33	1026	__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
be_bryan	0:b74591d5ab33	1027	}
be_bryan	0:b74591d5ab33	1028
be_bryan	0:b74591d5ab33	1029
be_bryan	0:b74591d5ab33	1030	/**
be_bryan	0:b74591d5ab33	1031	\brief STRT Unprivileged (16 bit)
be_bryan	0:b74591d5ab33	1032	\details Executes a Unprivileged STRT instruction for 16 bit values.
be_bryan	0:b74591d5ab33	1033	\param [in] value Value to store
be_bryan	0:b74591d5ab33	1034	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	1035	*/
be_bryan	0:b74591d5ab33	1036	__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
be_bryan	0:b74591d5ab33	1037	{
be_bryan	0:b74591d5ab33	1038	__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
be_bryan	0:b74591d5ab33	1039	}
be_bryan	0:b74591d5ab33	1040
be_bryan	0:b74591d5ab33	1041
be_bryan	0:b74591d5ab33	1042	/**
be_bryan	0:b74591d5ab33	1043	\brief STRT Unprivileged (32 bit)
be_bryan	0:b74591d5ab33	1044	\details Executes a Unprivileged STRT instruction for 32 bit values.
be_bryan	0:b74591d5ab33	1045	\param [in] value Value to store
be_bryan	0:b74591d5ab33	1046	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	1047	*/
be_bryan	0:b74591d5ab33	1048	__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
be_bryan	0:b74591d5ab33	1049	{
be_bryan	0:b74591d5ab33	1050	__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
be_bryan	0:b74591d5ab33	1051	}
be_bryan	0:b74591d5ab33	1052
be_bryan	0:b74591d5ab33	1053	#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	1054	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	1055	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
be_bryan	0:b74591d5ab33	1056
be_bryan	0:b74591d5ab33	1057	/**
be_bryan	0:b74591d5ab33	1058	\brief Signed Saturate
be_bryan	0:b74591d5ab33	1059	\details Saturates a signed value.
be_bryan	0:b74591d5ab33	1060	\param [in] value Value to be saturated
be_bryan	0:b74591d5ab33	1061	\param [in] sat Bit position to saturate to (1..32)
be_bryan	0:b74591d5ab33	1062	\return Saturated value
be_bryan	0:b74591d5ab33	1063	*/
be_bryan	0:b74591d5ab33	1064	__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
be_bryan	0:b74591d5ab33	1065	{
be_bryan	0:b74591d5ab33	1066	if ((sat >= 1U) && (sat <= 32U)) {
be_bryan	0:b74591d5ab33	1067	const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
be_bryan	0:b74591d5ab33	1068	const int32_t min = -1 - max ;
be_bryan	0:b74591d5ab33	1069	if (val > max) {
be_bryan	0:b74591d5ab33	1070	return max;
be_bryan	0:b74591d5ab33	1071	} else if (val < min) {
be_bryan	0:b74591d5ab33	1072	return min;
be_bryan	0:b74591d5ab33	1073	}
be_bryan	0:b74591d5ab33	1074	}
be_bryan	0:b74591d5ab33	1075	return val;
be_bryan	0:b74591d5ab33	1076	}
be_bryan	0:b74591d5ab33	1077
be_bryan	0:b74591d5ab33	1078	/**
be_bryan	0:b74591d5ab33	1079	\brief Unsigned Saturate
be_bryan	0:b74591d5ab33	1080	\details Saturates an unsigned value.
be_bryan	0:b74591d5ab33	1081	\param [in] value Value to be saturated
be_bryan	0:b74591d5ab33	1082	\param [in] sat Bit position to saturate to (0..31)
be_bryan	0:b74591d5ab33	1083	\return Saturated value
be_bryan	0:b74591d5ab33	1084	*/
be_bryan	0:b74591d5ab33	1085	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
be_bryan	0:b74591d5ab33	1086	{
be_bryan	0:b74591d5ab33	1087	if (sat <= 31U) {
be_bryan	0:b74591d5ab33	1088	const uint32_t max = ((1U << sat) - 1U);
be_bryan	0:b74591d5ab33	1089	if (val > (int32_t)max) {
be_bryan	0:b74591d5ab33	1090	return max;
be_bryan	0:b74591d5ab33	1091	} else if (val < 0) {
be_bryan	0:b74591d5ab33	1092	return 0U;
be_bryan	0:b74591d5ab33	1093	}
be_bryan	0:b74591d5ab33	1094	}
be_bryan	0:b74591d5ab33	1095	return (uint32_t)val;
be_bryan	0:b74591d5ab33	1096	}
be_bryan	0:b74591d5ab33	1097
be_bryan	0:b74591d5ab33	1098	#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	1099	(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	1100	(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
be_bryan	0:b74591d5ab33	1101
be_bryan	0:b74591d5ab33	1102
be_bryan	0:b74591d5ab33	1103	#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	1104	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
be_bryan	0:b74591d5ab33	1105	/**
be_bryan	0:b74591d5ab33	1106	\brief Load-Acquire (8 bit)
be_bryan	0:b74591d5ab33	1107	\details Executes a LDAB instruction for 8 bit value.
be_bryan	0:b74591d5ab33	1108	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	1109	\return value of type uint8_t at (*ptr)
be_bryan	0:b74591d5ab33	1110	*/
be_bryan	0:b74591d5ab33	1111	__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
be_bryan	0:b74591d5ab33	1112	{
be_bryan	0:b74591d5ab33	1113	uint32_t result;
be_bryan	0:b74591d5ab33	1114
be_bryan	0:b74591d5ab33	1115	__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
be_bryan	0:b74591d5ab33	1116	return ((uint8_t) result);
be_bryan	0:b74591d5ab33	1117	}
be_bryan	0:b74591d5ab33	1118
be_bryan	0:b74591d5ab33	1119
be_bryan	0:b74591d5ab33	1120	/**
be_bryan	0:b74591d5ab33	1121	\brief Load-Acquire (16 bit)
be_bryan	0:b74591d5ab33	1122	\details Executes a LDAH instruction for 16 bit values.
be_bryan	0:b74591d5ab33	1123	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	1124	\return value of type uint16_t at (*ptr)
be_bryan	0:b74591d5ab33	1125	*/
be_bryan	0:b74591d5ab33	1126	__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
be_bryan	0:b74591d5ab33	1127	{
be_bryan	0:b74591d5ab33	1128	uint32_t result;
be_bryan	0:b74591d5ab33	1129
be_bryan	0:b74591d5ab33	1130	__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
be_bryan	0:b74591d5ab33	1131	return ((uint16_t) result);
be_bryan	0:b74591d5ab33	1132	}
be_bryan	0:b74591d5ab33	1133
be_bryan	0:b74591d5ab33	1134
be_bryan	0:b74591d5ab33	1135	/**
be_bryan	0:b74591d5ab33	1136	\brief Load-Acquire (32 bit)
be_bryan	0:b74591d5ab33	1137	\details Executes a LDA instruction for 32 bit values.
be_bryan	0:b74591d5ab33	1138	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	1139	\return value of type uint32_t at (*ptr)
be_bryan	0:b74591d5ab33	1140	*/
be_bryan	0:b74591d5ab33	1141	__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
be_bryan	0:b74591d5ab33	1142	{
be_bryan	0:b74591d5ab33	1143	uint32_t result;
be_bryan	0:b74591d5ab33	1144
be_bryan	0:b74591d5ab33	1145	__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
be_bryan	0:b74591d5ab33	1146	return(result);
be_bryan	0:b74591d5ab33	1147	}
be_bryan	0:b74591d5ab33	1148
be_bryan	0:b74591d5ab33	1149
be_bryan	0:b74591d5ab33	1150	/**
be_bryan	0:b74591d5ab33	1151	\brief Store-Release (8 bit)
be_bryan	0:b74591d5ab33	1152	\details Executes a STLB instruction for 8 bit values.
be_bryan	0:b74591d5ab33	1153	\param [in] value Value to store
be_bryan	0:b74591d5ab33	1154	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	1155	*/
be_bryan	0:b74591d5ab33	1156	__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
be_bryan	0:b74591d5ab33	1157	{
be_bryan	0:b74591d5ab33	1158	__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
be_bryan	0:b74591d5ab33	1159	}
be_bryan	0:b74591d5ab33	1160
be_bryan	0:b74591d5ab33	1161
be_bryan	0:b74591d5ab33	1162	/**
be_bryan	0:b74591d5ab33	1163	\brief Store-Release (16 bit)
be_bryan	0:b74591d5ab33	1164	\details Executes a STLH instruction for 16 bit values.
be_bryan	0:b74591d5ab33	1165	\param [in] value Value to store
be_bryan	0:b74591d5ab33	1166	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	1167	*/
be_bryan	0:b74591d5ab33	1168	__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
be_bryan	0:b74591d5ab33	1169	{
be_bryan	0:b74591d5ab33	1170	__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
be_bryan	0:b74591d5ab33	1171	}
be_bryan	0:b74591d5ab33	1172
be_bryan	0:b74591d5ab33	1173
be_bryan	0:b74591d5ab33	1174	/**
be_bryan	0:b74591d5ab33	1175	\brief Store-Release (32 bit)
be_bryan	0:b74591d5ab33	1176	\details Executes a STL instruction for 32 bit values.
be_bryan	0:b74591d5ab33	1177	\param [in] value Value to store
be_bryan	0:b74591d5ab33	1178	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	1179	*/
be_bryan	0:b74591d5ab33	1180	__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
be_bryan	0:b74591d5ab33	1181	{
be_bryan	0:b74591d5ab33	1182	__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
be_bryan	0:b74591d5ab33	1183	}
be_bryan	0:b74591d5ab33	1184
be_bryan	0:b74591d5ab33	1185
be_bryan	0:b74591d5ab33	1186	/**
be_bryan	0:b74591d5ab33	1187	\brief Load-Acquire Exclusive (8 bit)
be_bryan	0:b74591d5ab33	1188	\details Executes a LDAB exclusive instruction for 8 bit value.
be_bryan	0:b74591d5ab33	1189	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	1190	\return value of type uint8_t at (*ptr)
be_bryan	0:b74591d5ab33	1191	*/
be_bryan	0:b74591d5ab33	1192	#define __LDAEXB (uint8_t)__builtin_arm_ldaex
be_bryan	0:b74591d5ab33	1193
be_bryan	0:b74591d5ab33	1194
be_bryan	0:b74591d5ab33	1195	/**
be_bryan	0:b74591d5ab33	1196	\brief Load-Acquire Exclusive (16 bit)
be_bryan	0:b74591d5ab33	1197	\details Executes a LDAH exclusive instruction for 16 bit values.
be_bryan	0:b74591d5ab33	1198	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	1199	\return value of type uint16_t at (*ptr)
be_bryan	0:b74591d5ab33	1200	*/
be_bryan	0:b74591d5ab33	1201	#define __LDAEXH (uint16_t)__builtin_arm_ldaex
be_bryan	0:b74591d5ab33	1202
be_bryan	0:b74591d5ab33	1203
be_bryan	0:b74591d5ab33	1204	/**
be_bryan	0:b74591d5ab33	1205	\brief Load-Acquire Exclusive (32 bit)
be_bryan	0:b74591d5ab33	1206	\details Executes a LDA exclusive instruction for 32 bit values.
be_bryan	0:b74591d5ab33	1207	\param [in] ptr Pointer to data
be_bryan	0:b74591d5ab33	1208	\return value of type uint32_t at (*ptr)
be_bryan	0:b74591d5ab33	1209	*/
be_bryan	0:b74591d5ab33	1210	#define __LDAEX (uint32_t)__builtin_arm_ldaex
be_bryan	0:b74591d5ab33	1211
be_bryan	0:b74591d5ab33	1212
be_bryan	0:b74591d5ab33	1213	/**
be_bryan	0:b74591d5ab33	1214	\brief Store-Release Exclusive (8 bit)
be_bryan	0:b74591d5ab33	1215	\details Executes a STLB exclusive instruction for 8 bit values.
be_bryan	0:b74591d5ab33	1216	\param [in] value Value to store
be_bryan	0:b74591d5ab33	1217	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	1218	\return 0 Function succeeded
be_bryan	0:b74591d5ab33	1219	\return 1 Function failed
be_bryan	0:b74591d5ab33	1220	*/
be_bryan	0:b74591d5ab33	1221	#define __STLEXB (uint32_t)__builtin_arm_stlex
be_bryan	0:b74591d5ab33	1222
be_bryan	0:b74591d5ab33	1223
be_bryan	0:b74591d5ab33	1224	/**
be_bryan	0:b74591d5ab33	1225	\brief Store-Release Exclusive (16 bit)
be_bryan	0:b74591d5ab33	1226	\details Executes a STLH exclusive instruction for 16 bit values.
be_bryan	0:b74591d5ab33	1227	\param [in] value Value to store
be_bryan	0:b74591d5ab33	1228	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	1229	\return 0 Function succeeded
be_bryan	0:b74591d5ab33	1230	\return 1 Function failed
be_bryan	0:b74591d5ab33	1231	*/
be_bryan	0:b74591d5ab33	1232	#define __STLEXH (uint32_t)__builtin_arm_stlex
be_bryan	0:b74591d5ab33	1233
be_bryan	0:b74591d5ab33	1234
be_bryan	0:b74591d5ab33	1235	/**
be_bryan	0:b74591d5ab33	1236	\brief Store-Release Exclusive (32 bit)
be_bryan	0:b74591d5ab33	1237	\details Executes a STL exclusive instruction for 32 bit values.
be_bryan	0:b74591d5ab33	1238	\param [in] value Value to store
be_bryan	0:b74591d5ab33	1239	\param [in] ptr Pointer to location
be_bryan	0:b74591d5ab33	1240	\return 0 Function succeeded
be_bryan	0:b74591d5ab33	1241	\return 1 Function failed
be_bryan	0:b74591d5ab33	1242	*/
be_bryan	0:b74591d5ab33	1243	#define __STLEX (uint32_t)__builtin_arm_stlex
be_bryan	0:b74591d5ab33	1244
be_bryan	0:b74591d5ab33	1245	#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) \|\| \
be_bryan	0:b74591d5ab33	1246	(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
be_bryan	0:b74591d5ab33	1247
be_bryan	0:b74591d5ab33	1248	/@}/ /* end of group CMSIS_Core_InstructionInterface */
be_bryan	0:b74591d5ab33	1249
be_bryan	0:b74591d5ab33	1250
be_bryan	0:b74591d5ab33	1251	/* ################### Compiler specific Intrinsics ########################### */
be_bryan	0:b74591d5ab33	1252	/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
be_bryan	0:b74591d5ab33	1253	Access to dedicated SIMD instructions
be_bryan	0:b74591d5ab33	1254	@{
be_bryan	0:b74591d5ab33	1255	*/
be_bryan	0:b74591d5ab33	1256
be_bryan	0:b74591d5ab33	1257	#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
be_bryan	0:b74591d5ab33	1258
be_bryan	0:b74591d5ab33	1259	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1260	{
be_bryan	0:b74591d5ab33	1261	uint32_t result;
be_bryan	0:b74591d5ab33	1262
be_bryan	0:b74591d5ab33	1263	__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1264	return(result);
be_bryan	0:b74591d5ab33	1265	}
be_bryan	0:b74591d5ab33	1266
be_bryan	0:b74591d5ab33	1267	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1268	{
be_bryan	0:b74591d5ab33	1269	uint32_t result;
be_bryan	0:b74591d5ab33	1270
be_bryan	0:b74591d5ab33	1271	__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1272	return(result);
be_bryan	0:b74591d5ab33	1273	}
be_bryan	0:b74591d5ab33	1274
be_bryan	0:b74591d5ab33	1275	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1276	{
be_bryan	0:b74591d5ab33	1277	uint32_t result;
be_bryan	0:b74591d5ab33	1278
be_bryan	0:b74591d5ab33	1279	__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1280	return(result);
be_bryan	0:b74591d5ab33	1281	}
be_bryan	0:b74591d5ab33	1282
be_bryan	0:b74591d5ab33	1283	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1284	{
be_bryan	0:b74591d5ab33	1285	uint32_t result;
be_bryan	0:b74591d5ab33	1286
be_bryan	0:b74591d5ab33	1287	__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1288	return(result);
be_bryan	0:b74591d5ab33	1289	}
be_bryan	0:b74591d5ab33	1290
be_bryan	0:b74591d5ab33	1291	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1292	{
be_bryan	0:b74591d5ab33	1293	uint32_t result;
be_bryan	0:b74591d5ab33	1294
be_bryan	0:b74591d5ab33	1295	__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1296	return(result);
be_bryan	0:b74591d5ab33	1297	}
be_bryan	0:b74591d5ab33	1298
be_bryan	0:b74591d5ab33	1299	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1300	{
be_bryan	0:b74591d5ab33	1301	uint32_t result;
be_bryan	0:b74591d5ab33	1302
be_bryan	0:b74591d5ab33	1303	__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1304	return(result);
be_bryan	0:b74591d5ab33	1305	}
be_bryan	0:b74591d5ab33	1306
be_bryan	0:b74591d5ab33	1307
be_bryan	0:b74591d5ab33	1308	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1309	{
be_bryan	0:b74591d5ab33	1310	uint32_t result;
be_bryan	0:b74591d5ab33	1311
be_bryan	0:b74591d5ab33	1312	__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1313	return(result);
be_bryan	0:b74591d5ab33	1314	}
be_bryan	0:b74591d5ab33	1315
be_bryan	0:b74591d5ab33	1316	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1317	{
be_bryan	0:b74591d5ab33	1318	uint32_t result;
be_bryan	0:b74591d5ab33	1319
be_bryan	0:b74591d5ab33	1320	__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1321	return(result);
be_bryan	0:b74591d5ab33	1322	}
be_bryan	0:b74591d5ab33	1323
be_bryan	0:b74591d5ab33	1324	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1325	{
be_bryan	0:b74591d5ab33	1326	uint32_t result;
be_bryan	0:b74591d5ab33	1327
be_bryan	0:b74591d5ab33	1328	__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1329	return(result);
be_bryan	0:b74591d5ab33	1330	}
be_bryan	0:b74591d5ab33	1331
be_bryan	0:b74591d5ab33	1332	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1333	{
be_bryan	0:b74591d5ab33	1334	uint32_t result;
be_bryan	0:b74591d5ab33	1335
be_bryan	0:b74591d5ab33	1336	__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1337	return(result);
be_bryan	0:b74591d5ab33	1338	}
be_bryan	0:b74591d5ab33	1339
be_bryan	0:b74591d5ab33	1340	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1341	{
be_bryan	0:b74591d5ab33	1342	uint32_t result;
be_bryan	0:b74591d5ab33	1343
be_bryan	0:b74591d5ab33	1344	__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1345	return(result);
be_bryan	0:b74591d5ab33	1346	}
be_bryan	0:b74591d5ab33	1347
be_bryan	0:b74591d5ab33	1348	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1349	{
be_bryan	0:b74591d5ab33	1350	uint32_t result;
be_bryan	0:b74591d5ab33	1351
be_bryan	0:b74591d5ab33	1352	__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1353	return(result);
be_bryan	0:b74591d5ab33	1354	}
be_bryan	0:b74591d5ab33	1355
be_bryan	0:b74591d5ab33	1356
be_bryan	0:b74591d5ab33	1357	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1358	{
be_bryan	0:b74591d5ab33	1359	uint32_t result;
be_bryan	0:b74591d5ab33	1360
be_bryan	0:b74591d5ab33	1361	__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1362	return(result);
be_bryan	0:b74591d5ab33	1363	}
be_bryan	0:b74591d5ab33	1364
be_bryan	0:b74591d5ab33	1365	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1366	{
be_bryan	0:b74591d5ab33	1367	uint32_t result;
be_bryan	0:b74591d5ab33	1368
be_bryan	0:b74591d5ab33	1369	__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1370	return(result);
be_bryan	0:b74591d5ab33	1371	}
be_bryan	0:b74591d5ab33	1372
be_bryan	0:b74591d5ab33	1373	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1374	{
be_bryan	0:b74591d5ab33	1375	uint32_t result;
be_bryan	0:b74591d5ab33	1376
be_bryan	0:b74591d5ab33	1377	__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1378	return(result);
be_bryan	0:b74591d5ab33	1379	}
be_bryan	0:b74591d5ab33	1380
be_bryan	0:b74591d5ab33	1381	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1382	{
be_bryan	0:b74591d5ab33	1383	uint32_t result;
be_bryan	0:b74591d5ab33	1384
be_bryan	0:b74591d5ab33	1385	__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1386	return(result);
be_bryan	0:b74591d5ab33	1387	}
be_bryan	0:b74591d5ab33	1388
be_bryan	0:b74591d5ab33	1389	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1390	{
be_bryan	0:b74591d5ab33	1391	uint32_t result;
be_bryan	0:b74591d5ab33	1392
be_bryan	0:b74591d5ab33	1393	__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1394	return(result);
be_bryan	0:b74591d5ab33	1395	}
be_bryan	0:b74591d5ab33	1396
be_bryan	0:b74591d5ab33	1397	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1398	{
be_bryan	0:b74591d5ab33	1399	uint32_t result;
be_bryan	0:b74591d5ab33	1400
be_bryan	0:b74591d5ab33	1401	__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1402	return(result);
be_bryan	0:b74591d5ab33	1403	}
be_bryan	0:b74591d5ab33	1404
be_bryan	0:b74591d5ab33	1405	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1406	{
be_bryan	0:b74591d5ab33	1407	uint32_t result;
be_bryan	0:b74591d5ab33	1408
be_bryan	0:b74591d5ab33	1409	__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1410	return(result);
be_bryan	0:b74591d5ab33	1411	}
be_bryan	0:b74591d5ab33	1412
be_bryan	0:b74591d5ab33	1413	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1414	{
be_bryan	0:b74591d5ab33	1415	uint32_t result;
be_bryan	0:b74591d5ab33	1416
be_bryan	0:b74591d5ab33	1417	__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1418	return(result);
be_bryan	0:b74591d5ab33	1419	}
be_bryan	0:b74591d5ab33	1420
be_bryan	0:b74591d5ab33	1421	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1422	{
be_bryan	0:b74591d5ab33	1423	uint32_t result;
be_bryan	0:b74591d5ab33	1424
be_bryan	0:b74591d5ab33	1425	__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1426	return(result);
be_bryan	0:b74591d5ab33	1427	}
be_bryan	0:b74591d5ab33	1428
be_bryan	0:b74591d5ab33	1429	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1430	{
be_bryan	0:b74591d5ab33	1431	uint32_t result;
be_bryan	0:b74591d5ab33	1432
be_bryan	0:b74591d5ab33	1433	__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1434	return(result);
be_bryan	0:b74591d5ab33	1435	}
be_bryan	0:b74591d5ab33	1436
be_bryan	0:b74591d5ab33	1437	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1438	{
be_bryan	0:b74591d5ab33	1439	uint32_t result;
be_bryan	0:b74591d5ab33	1440
be_bryan	0:b74591d5ab33	1441	__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1442	return(result);
be_bryan	0:b74591d5ab33	1443	}
be_bryan	0:b74591d5ab33	1444
be_bryan	0:b74591d5ab33	1445	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1446	{
be_bryan	0:b74591d5ab33	1447	uint32_t result;
be_bryan	0:b74591d5ab33	1448
be_bryan	0:b74591d5ab33	1449	__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1450	return(result);
be_bryan	0:b74591d5ab33	1451	}
be_bryan	0:b74591d5ab33	1452
be_bryan	0:b74591d5ab33	1453	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1454	{
be_bryan	0:b74591d5ab33	1455	uint32_t result;
be_bryan	0:b74591d5ab33	1456
be_bryan	0:b74591d5ab33	1457	__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1458	return(result);
be_bryan	0:b74591d5ab33	1459	}
be_bryan	0:b74591d5ab33	1460
be_bryan	0:b74591d5ab33	1461	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1462	{
be_bryan	0:b74591d5ab33	1463	uint32_t result;
be_bryan	0:b74591d5ab33	1464
be_bryan	0:b74591d5ab33	1465	__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1466	return(result);
be_bryan	0:b74591d5ab33	1467	}
be_bryan	0:b74591d5ab33	1468
be_bryan	0:b74591d5ab33	1469	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1470	{
be_bryan	0:b74591d5ab33	1471	uint32_t result;
be_bryan	0:b74591d5ab33	1472
be_bryan	0:b74591d5ab33	1473	__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1474	return(result);
be_bryan	0:b74591d5ab33	1475	}
be_bryan	0:b74591d5ab33	1476
be_bryan	0:b74591d5ab33	1477	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1478	{
be_bryan	0:b74591d5ab33	1479	uint32_t result;
be_bryan	0:b74591d5ab33	1480
be_bryan	0:b74591d5ab33	1481	__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1482	return(result);
be_bryan	0:b74591d5ab33	1483	}
be_bryan	0:b74591d5ab33	1484
be_bryan	0:b74591d5ab33	1485	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1486	{
be_bryan	0:b74591d5ab33	1487	uint32_t result;
be_bryan	0:b74591d5ab33	1488
be_bryan	0:b74591d5ab33	1489	__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1490	return(result);
be_bryan	0:b74591d5ab33	1491	}
be_bryan	0:b74591d5ab33	1492
be_bryan	0:b74591d5ab33	1493	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1494	{
be_bryan	0:b74591d5ab33	1495	uint32_t result;
be_bryan	0:b74591d5ab33	1496
be_bryan	0:b74591d5ab33	1497	__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1498	return(result);
be_bryan	0:b74591d5ab33	1499	}
be_bryan	0:b74591d5ab33	1500
be_bryan	0:b74591d5ab33	1501	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1502	{
be_bryan	0:b74591d5ab33	1503	uint32_t result;
be_bryan	0:b74591d5ab33	1504
be_bryan	0:b74591d5ab33	1505	__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1506	return(result);
be_bryan	0:b74591d5ab33	1507	}
be_bryan	0:b74591d5ab33	1508
be_bryan	0:b74591d5ab33	1509	__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1510	{
be_bryan	0:b74591d5ab33	1511	uint32_t result;
be_bryan	0:b74591d5ab33	1512
be_bryan	0:b74591d5ab33	1513	__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1514	return(result);
be_bryan	0:b74591d5ab33	1515	}
be_bryan	0:b74591d5ab33	1516
be_bryan	0:b74591d5ab33	1517	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1518	{
be_bryan	0:b74591d5ab33	1519	uint32_t result;
be_bryan	0:b74591d5ab33	1520
be_bryan	0:b74591d5ab33	1521	__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1522	return(result);
be_bryan	0:b74591d5ab33	1523	}
be_bryan	0:b74591d5ab33	1524
be_bryan	0:b74591d5ab33	1525	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1526	{
be_bryan	0:b74591d5ab33	1527	uint32_t result;
be_bryan	0:b74591d5ab33	1528
be_bryan	0:b74591d5ab33	1529	__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1530	return(result);
be_bryan	0:b74591d5ab33	1531	}
be_bryan	0:b74591d5ab33	1532
be_bryan	0:b74591d5ab33	1533	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1534	{
be_bryan	0:b74591d5ab33	1535	uint32_t result;
be_bryan	0:b74591d5ab33	1536
be_bryan	0:b74591d5ab33	1537	__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1538	return(result);
be_bryan	0:b74591d5ab33	1539	}
be_bryan	0:b74591d5ab33	1540
be_bryan	0:b74591d5ab33	1541	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1542	{
be_bryan	0:b74591d5ab33	1543	uint32_t result;
be_bryan	0:b74591d5ab33	1544
be_bryan	0:b74591d5ab33	1545	__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1546	return(result);
be_bryan	0:b74591d5ab33	1547	}
be_bryan	0:b74591d5ab33	1548
be_bryan	0:b74591d5ab33	1549	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1550	{
be_bryan	0:b74591d5ab33	1551	uint32_t result;
be_bryan	0:b74591d5ab33	1552
be_bryan	0:b74591d5ab33	1553	__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1554	return(result);
be_bryan	0:b74591d5ab33	1555	}
be_bryan	0:b74591d5ab33	1556
be_bryan	0:b74591d5ab33	1557	__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
be_bryan	0:b74591d5ab33	1558	{
be_bryan	0:b74591d5ab33	1559	uint32_t result;
be_bryan	0:b74591d5ab33	1560
be_bryan	0:b74591d5ab33	1561	__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
be_bryan	0:b74591d5ab33	1562	return(result);
be_bryan	0:b74591d5ab33	1563	}
be_bryan	0:b74591d5ab33	1564
be_bryan	0:b74591d5ab33	1565	#define __SSAT16(ARG1,ARG2) \
be_bryan	0:b74591d5ab33	1566	({ \
be_bryan	0:b74591d5ab33	1567	int32_t __RES, __ARG1 = (ARG1); \
be_bryan	0:b74591d5ab33	1568	__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
be_bryan	0:b74591d5ab33	1569	__RES; \
be_bryan	0:b74591d5ab33	1570	})
be_bryan	0:b74591d5ab33	1571
be_bryan	0:b74591d5ab33	1572	#define __USAT16(ARG1,ARG2) \
be_bryan	0:b74591d5ab33	1573	({ \
be_bryan	0:b74591d5ab33	1574	uint32_t __RES, __ARG1 = (ARG1); \
be_bryan	0:b74591d5ab33	1575	__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
be_bryan	0:b74591d5ab33	1576	__RES; \
be_bryan	0:b74591d5ab33	1577	})
be_bryan	0:b74591d5ab33	1578
be_bryan	0:b74591d5ab33	1579	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
be_bryan	0:b74591d5ab33	1580	{
be_bryan	0:b74591d5ab33	1581	uint32_t result;
be_bryan	0:b74591d5ab33	1582
be_bryan	0:b74591d5ab33	1583	__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
be_bryan	0:b74591d5ab33	1584	return(result);
be_bryan	0:b74591d5ab33	1585	}
be_bryan	0:b74591d5ab33	1586
be_bryan	0:b74591d5ab33	1587	__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1588	{
be_bryan	0:b74591d5ab33	1589	uint32_t result;
be_bryan	0:b74591d5ab33	1590
be_bryan	0:b74591d5ab33	1591	__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1592	return(result);
be_bryan	0:b74591d5ab33	1593	}
be_bryan	0:b74591d5ab33	1594
be_bryan	0:b74591d5ab33	1595	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
be_bryan	0:b74591d5ab33	1596	{
be_bryan	0:b74591d5ab33	1597	uint32_t result;
be_bryan	0:b74591d5ab33	1598
be_bryan	0:b74591d5ab33	1599	__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
be_bryan	0:b74591d5ab33	1600	return(result);
be_bryan	0:b74591d5ab33	1601	}
be_bryan	0:b74591d5ab33	1602
be_bryan	0:b74591d5ab33	1603	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1604	{
be_bryan	0:b74591d5ab33	1605	uint32_t result;
be_bryan	0:b74591d5ab33	1606
be_bryan	0:b74591d5ab33	1607	__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1608	return(result);
be_bryan	0:b74591d5ab33	1609	}
be_bryan	0:b74591d5ab33	1610
be_bryan	0:b74591d5ab33	1611	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1612	{
be_bryan	0:b74591d5ab33	1613	uint32_t result;
be_bryan	0:b74591d5ab33	1614
be_bryan	0:b74591d5ab33	1615	__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1616	return(result);
be_bryan	0:b74591d5ab33	1617	}
be_bryan	0:b74591d5ab33	1618
be_bryan	0:b74591d5ab33	1619	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1620	{
be_bryan	0:b74591d5ab33	1621	uint32_t result;
be_bryan	0:b74591d5ab33	1622
be_bryan	0:b74591d5ab33	1623	__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1624	return(result);
be_bryan	0:b74591d5ab33	1625	}
be_bryan	0:b74591d5ab33	1626
be_bryan	0:b74591d5ab33	1627	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
be_bryan	0:b74591d5ab33	1628	{
be_bryan	0:b74591d5ab33	1629	uint32_t result;
be_bryan	0:b74591d5ab33	1630
be_bryan	0:b74591d5ab33	1631	__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
be_bryan	0:b74591d5ab33	1632	return(result);
be_bryan	0:b74591d5ab33	1633	}
be_bryan	0:b74591d5ab33	1634
be_bryan	0:b74591d5ab33	1635	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
be_bryan	0:b74591d5ab33	1636	{
be_bryan	0:b74591d5ab33	1637	uint32_t result;
be_bryan	0:b74591d5ab33	1638
be_bryan	0:b74591d5ab33	1639	__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
be_bryan	0:b74591d5ab33	1640	return(result);
be_bryan	0:b74591d5ab33	1641	}
be_bryan	0:b74591d5ab33	1642
be_bryan	0:b74591d5ab33	1643	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
be_bryan	0:b74591d5ab33	1644	{
be_bryan	0:b74591d5ab33	1645	union llreg_u{
be_bryan	0:b74591d5ab33	1646	uint32_t w32[2];
be_bryan	0:b74591d5ab33	1647	uint64_t w64;
be_bryan	0:b74591d5ab33	1648	} llr;
be_bryan	0:b74591d5ab33	1649	llr.w64 = acc;
be_bryan	0:b74591d5ab33	1650
be_bryan	0:b74591d5ab33	1651	#ifndef __ARMEB__ /* Little endian */
be_bryan	0:b74591d5ab33	1652	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
be_bryan	0:b74591d5ab33	1653	#else /* Big endian */
be_bryan	0:b74591d5ab33	1654	__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
be_bryan	0:b74591d5ab33	1655	#endif
be_bryan	0:b74591d5ab33	1656
be_bryan	0:b74591d5ab33	1657	return(llr.w64);
be_bryan	0:b74591d5ab33	1658	}
be_bryan	0:b74591d5ab33	1659
be_bryan	0:b74591d5ab33	1660	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
be_bryan	0:b74591d5ab33	1661	{
be_bryan	0:b74591d5ab33	1662	union llreg_u{
be_bryan	0:b74591d5ab33	1663	uint32_t w32[2];
be_bryan	0:b74591d5ab33	1664	uint64_t w64;
be_bryan	0:b74591d5ab33	1665	} llr;
be_bryan	0:b74591d5ab33	1666	llr.w64 = acc;
be_bryan	0:b74591d5ab33	1667
be_bryan	0:b74591d5ab33	1668	#ifndef __ARMEB__ /* Little endian */
be_bryan	0:b74591d5ab33	1669	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
be_bryan	0:b74591d5ab33	1670	#else /* Big endian */
be_bryan	0:b74591d5ab33	1671	__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
be_bryan	0:b74591d5ab33	1672	#endif
be_bryan	0:b74591d5ab33	1673
be_bryan	0:b74591d5ab33	1674	return(llr.w64);
be_bryan	0:b74591d5ab33	1675	}
be_bryan	0:b74591d5ab33	1676
be_bryan	0:b74591d5ab33	1677	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1678	{
be_bryan	0:b74591d5ab33	1679	uint32_t result;
be_bryan	0:b74591d5ab33	1680
be_bryan	0:b74591d5ab33	1681	__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1682	return(result);
be_bryan	0:b74591d5ab33	1683	}
be_bryan	0:b74591d5ab33	1684
be_bryan	0:b74591d5ab33	1685	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1686	{
be_bryan	0:b74591d5ab33	1687	uint32_t result;
be_bryan	0:b74591d5ab33	1688
be_bryan	0:b74591d5ab33	1689	__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1690	return(result);
be_bryan	0:b74591d5ab33	1691	}
be_bryan	0:b74591d5ab33	1692
be_bryan	0:b74591d5ab33	1693	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
be_bryan	0:b74591d5ab33	1694	{
be_bryan	0:b74591d5ab33	1695	uint32_t result;
be_bryan	0:b74591d5ab33	1696
be_bryan	0:b74591d5ab33	1697	__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
be_bryan	0:b74591d5ab33	1698	return(result);
be_bryan	0:b74591d5ab33	1699	}
be_bryan	0:b74591d5ab33	1700
be_bryan	0:b74591d5ab33	1701	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
be_bryan	0:b74591d5ab33	1702	{
be_bryan	0:b74591d5ab33	1703	uint32_t result;
be_bryan	0:b74591d5ab33	1704
be_bryan	0:b74591d5ab33	1705	__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
be_bryan	0:b74591d5ab33	1706	return(result);
be_bryan	0:b74591d5ab33	1707	}
be_bryan	0:b74591d5ab33	1708
be_bryan	0:b74591d5ab33	1709	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
be_bryan	0:b74591d5ab33	1710	{
be_bryan	0:b74591d5ab33	1711	union llreg_u{
be_bryan	0:b74591d5ab33	1712	uint32_t w32[2];
be_bryan	0:b74591d5ab33	1713	uint64_t w64;
be_bryan	0:b74591d5ab33	1714	} llr;
be_bryan	0:b74591d5ab33	1715	llr.w64 = acc;
be_bryan	0:b74591d5ab33	1716
be_bryan	0:b74591d5ab33	1717	#ifndef __ARMEB__ /* Little endian */
be_bryan	0:b74591d5ab33	1718	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
be_bryan	0:b74591d5ab33	1719	#else /* Big endian */
be_bryan	0:b74591d5ab33	1720	__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
be_bryan	0:b74591d5ab33	1721	#endif
be_bryan	0:b74591d5ab33	1722
be_bryan	0:b74591d5ab33	1723	return(llr.w64);
be_bryan	0:b74591d5ab33	1724	}
be_bryan	0:b74591d5ab33	1725
be_bryan	0:b74591d5ab33	1726	__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
be_bryan	0:b74591d5ab33	1727	{
be_bryan	0:b74591d5ab33	1728	union llreg_u{
be_bryan	0:b74591d5ab33	1729	uint32_t w32[2];
be_bryan	0:b74591d5ab33	1730	uint64_t w64;
be_bryan	0:b74591d5ab33	1731	} llr;
be_bryan	0:b74591d5ab33	1732	llr.w64 = acc;
be_bryan	0:b74591d5ab33	1733
be_bryan	0:b74591d5ab33	1734	#ifndef __ARMEB__ /* Little endian */
be_bryan	0:b74591d5ab33	1735	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
be_bryan	0:b74591d5ab33	1736	#else /* Big endian */
be_bryan	0:b74591d5ab33	1737	__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
be_bryan	0:b74591d5ab33	1738	#endif
be_bryan	0:b74591d5ab33	1739
be_bryan	0:b74591d5ab33	1740	return(llr.w64);
be_bryan	0:b74591d5ab33	1741	}
be_bryan	0:b74591d5ab33	1742
be_bryan	0:b74591d5ab33	1743	__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
be_bryan	0:b74591d5ab33	1744	{
be_bryan	0:b74591d5ab33	1745	uint32_t result;
be_bryan	0:b74591d5ab33	1746
be_bryan	0:b74591d5ab33	1747	__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1748	return(result);
be_bryan	0:b74591d5ab33	1749	}
be_bryan	0:b74591d5ab33	1750
be_bryan	0:b74591d5ab33	1751	__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
be_bryan	0:b74591d5ab33	1752	{
be_bryan	0:b74591d5ab33	1753	int32_t result;
be_bryan	0:b74591d5ab33	1754
be_bryan	0:b74591d5ab33	1755	__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1756	return(result);
be_bryan	0:b74591d5ab33	1757	}
be_bryan	0:b74591d5ab33	1758
be_bryan	0:b74591d5ab33	1759	__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
be_bryan	0:b74591d5ab33	1760	{
be_bryan	0:b74591d5ab33	1761	int32_t result;
be_bryan	0:b74591d5ab33	1762
be_bryan	0:b74591d5ab33	1763	__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
be_bryan	0:b74591d5ab33	1764	return(result);
be_bryan	0:b74591d5ab33	1765	}
be_bryan	0:b74591d5ab33	1766
be_bryan	0:b74591d5ab33	1767	#if 0
be_bryan	0:b74591d5ab33	1768	#define __PKHBT(ARG1,ARG2,ARG3) \
be_bryan	0:b74591d5ab33	1769	({ \
be_bryan	0:b74591d5ab33	1770	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
be_bryan	0:b74591d5ab33	1771	__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
be_bryan	0:b74591d5ab33	1772	__RES; \
be_bryan	0:b74591d5ab33	1773	})
be_bryan	0:b74591d5ab33	1774
be_bryan	0:b74591d5ab33	1775	#define __PKHTB(ARG1,ARG2,ARG3) \
be_bryan	0:b74591d5ab33	1776	({ \
be_bryan	0:b74591d5ab33	1777	uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
be_bryan	0:b74591d5ab33	1778	if (ARG3 == 0) \
be_bryan	0:b74591d5ab33	1779	__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
be_bryan	0:b74591d5ab33	1780	else \
be_bryan	0:b74591d5ab33	1781	__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
be_bryan	0:b74591d5ab33	1782	__RES; \
be_bryan	0:b74591d5ab33	1783	})
be_bryan	0:b74591d5ab33	1784	#endif
be_bryan	0:b74591d5ab33	1785
be_bryan	0:b74591d5ab33	1786	#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) \| \
be_bryan	0:b74591d5ab33	1787	((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
be_bryan	0:b74591d5ab33	1788
be_bryan	0:b74591d5ab33	1789	#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) \| \
be_bryan	0:b74591d5ab33	1790	((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
be_bryan	0:b74591d5ab33	1791
be_bryan	0:b74591d5ab33	1792	__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
be_bryan	0:b74591d5ab33	1793	{
be_bryan	0:b74591d5ab33	1794	int32_t result;
be_bryan	0:b74591d5ab33	1795
be_bryan	0:b74591d5ab33	1796	__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
be_bryan	0:b74591d5ab33	1797	return(result);
be_bryan	0:b74591d5ab33	1798	}
be_bryan	0:b74591d5ab33	1799
be_bryan	0:b74591d5ab33	1800	#endif /* (__ARM_FEATURE_DSP == 1) */
be_bryan	0:b74591d5ab33	1801	/@} end of group CMSIS_SIMD_intrinsics /
be_bryan	0:b74591d5ab33	1802
be_bryan	0:b74591d5ab33	1803
be_bryan	0:b74591d5ab33	1804	#endif /* __CMSIS_ARMCLANG_H */

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Type:	Library
Created:	12 Dec 2017
Imports:	1018
Forks:	0
Commits:	1
Dependents:	14
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