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Dependents:   cobaLCDJoyMotor_Thread odometry_omni_3roda_v3 odometry_omni_3roda_v1 odometry_omni_3roda_v2 ... more

targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /**
be_bryan 0:b74591d5ab33 2 ******************************************************************************
be_bryan 0:b74591d5ab33 3 * @file startup_stm32l053xx.s
be_bryan 0:b74591d5ab33 4 * @author MCD Application Team
be_bryan 0:b74591d5ab33 5 * @version V1.5.0
be_bryan 0:b74591d5ab33 6 * @date 8-January-2016
be_bryan 0:b74591d5ab33 7 * @brief STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
be_bryan 0:b74591d5ab33 8 * This module performs:
be_bryan 0:b74591d5ab33 9 * - Set the initial SP
be_bryan 0:b74591d5ab33 10 * - Set the initial PC == Reset_Handler,
be_bryan 0:b74591d5ab33 11 * - Set the vector table entries with the exceptions ISR address
be_bryan 0:b74591d5ab33 12 * - Branches to main in the C library (which eventually
be_bryan 0:b74591d5ab33 13 * calls main()).
be_bryan 0:b74591d5ab33 14 * After Reset the Cortex-M0+ processor is in Thread mode,
be_bryan 0:b74591d5ab33 15 * priority is Privileged, and the Stack is set to Main.
be_bryan 0:b74591d5ab33 16 ******************************************************************************
be_bryan 0:b74591d5ab33 17 *
be_bryan 0:b74591d5ab33 18 * Redistribution and use in source and binary forms, with or without modification,
be_bryan 0:b74591d5ab33 19 * are permitted provided that the following conditions are met:
be_bryan 0:b74591d5ab33 20 * 1. Redistributions of source code must retain the above copyright notice,
be_bryan 0:b74591d5ab33 21 * this list of conditions and the following disclaimer.
be_bryan 0:b74591d5ab33 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
be_bryan 0:b74591d5ab33 23 * this list of conditions and the following disclaimer in the documentation
be_bryan 0:b74591d5ab33 24 * and/or other materials provided with the distribution.
be_bryan 0:b74591d5ab33 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
be_bryan 0:b74591d5ab33 26 * may be used to endorse or promote products derived from this software
be_bryan 0:b74591d5ab33 27 * without specific prior written permission.
be_bryan 0:b74591d5ab33 28 *
be_bryan 0:b74591d5ab33 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
be_bryan 0:b74591d5ab33 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
be_bryan 0:b74591d5ab33 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
be_bryan 0:b74591d5ab33 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
be_bryan 0:b74591d5ab33 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
be_bryan 0:b74591d5ab33 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
be_bryan 0:b74591d5ab33 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
be_bryan 0:b74591d5ab33 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
be_bryan 0:b74591d5ab33 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
be_bryan 0:b74591d5ab33 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
be_bryan 0:b74591d5ab33 39 *
be_bryan 0:b74591d5ab33 40 ******************************************************************************
be_bryan 0:b74591d5ab33 41 */
be_bryan 0:b74591d5ab33 42
be_bryan 0:b74591d5ab33 43 .syntax unified
be_bryan 0:b74591d5ab33 44 .cpu cortex-m0plus
be_bryan 0:b74591d5ab33 45 .fpu softvfp
be_bryan 0:b74591d5ab33 46 .thumb
be_bryan 0:b74591d5ab33 47
be_bryan 0:b74591d5ab33 48 .global g_pfnVectors
be_bryan 0:b74591d5ab33 49 .global Default_Handler
be_bryan 0:b74591d5ab33 50
be_bryan 0:b74591d5ab33 51 /* start address for the initialization values of the .data section.
be_bryan 0:b74591d5ab33 52 defined in linker script */
be_bryan 0:b74591d5ab33 53 .word _sidata
be_bryan 0:b74591d5ab33 54 /* start address for the .data section. defined in linker script */
be_bryan 0:b74591d5ab33 55 .word _sdata
be_bryan 0:b74591d5ab33 56 /* end address for the .data section. defined in linker script */
be_bryan 0:b74591d5ab33 57 .word _edata
be_bryan 0:b74591d5ab33 58
be_bryan 0:b74591d5ab33 59 .section .text.Reset_Handler
be_bryan 0:b74591d5ab33 60 .weak Reset_Handler
be_bryan 0:b74591d5ab33 61 .type Reset_Handler, %function
be_bryan 0:b74591d5ab33 62 Reset_Handler:
be_bryan 0:b74591d5ab33 63 ldr r0, =_estack
be_bryan 0:b74591d5ab33 64 mov sp, r0 /* set stack pointer */
be_bryan 0:b74591d5ab33 65
be_bryan 0:b74591d5ab33 66 /* Copy the data segment initializers from flash to SRAM */
be_bryan 0:b74591d5ab33 67 movs r1, #0
be_bryan 0:b74591d5ab33 68 b LoopCopyDataInit
be_bryan 0:b74591d5ab33 69
be_bryan 0:b74591d5ab33 70 CopyDataInit:
be_bryan 0:b74591d5ab33 71 ldr r3, =_sidata
be_bryan 0:b74591d5ab33 72 ldr r3, [r3, r1]
be_bryan 0:b74591d5ab33 73 str r3, [r0, r1]
be_bryan 0:b74591d5ab33 74 adds r1, r1, #4
be_bryan 0:b74591d5ab33 75
be_bryan 0:b74591d5ab33 76 LoopCopyDataInit:
be_bryan 0:b74591d5ab33 77 ldr r0, =_sdata
be_bryan 0:b74591d5ab33 78 ldr r3, =_edata
be_bryan 0:b74591d5ab33 79 adds r2, r0, r1
be_bryan 0:b74591d5ab33 80 cmp r2, r3
be_bryan 0:b74591d5ab33 81 bcc CopyDataInit
be_bryan 0:b74591d5ab33 82
be_bryan 0:b74591d5ab33 83 /* Call the clock system intitialization function.*/
be_bryan 0:b74591d5ab33 84 bl SystemInit
be_bryan 0:b74591d5ab33 85 /* Call static constructors */
be_bryan 0:b74591d5ab33 86 //bl __libc_init_array
be_bryan 0:b74591d5ab33 87 /* Call the application's entry point.*/
be_bryan 0:b74591d5ab33 88 //bl main
be_bryan 0:b74591d5ab33 89 bl _start
be_bryan 0:b74591d5ab33 90
be_bryan 0:b74591d5ab33 91 LoopForever:
be_bryan 0:b74591d5ab33 92 b LoopForever
be_bryan 0:b74591d5ab33 93
be_bryan 0:b74591d5ab33 94
be_bryan 0:b74591d5ab33 95 .size Reset_Handler, .-Reset_Handler
be_bryan 0:b74591d5ab33 96
be_bryan 0:b74591d5ab33 97 /**
be_bryan 0:b74591d5ab33 98 * @brief This is the code that gets called when the processor receives an
be_bryan 0:b74591d5ab33 99 * unexpected interrupt. This simply enters an infinite loop, preserving
be_bryan 0:b74591d5ab33 100 * the system state for examination by a debugger.
be_bryan 0:b74591d5ab33 101 *
be_bryan 0:b74591d5ab33 102 * @param None
be_bryan 0:b74591d5ab33 103 * @retval : None
be_bryan 0:b74591d5ab33 104 */
be_bryan 0:b74591d5ab33 105 .section .text.Default_Handler,"ax",%progbits
be_bryan 0:b74591d5ab33 106 Default_Handler:
be_bryan 0:b74591d5ab33 107 Infinite_Loop:
be_bryan 0:b74591d5ab33 108 b Infinite_Loop
be_bryan 0:b74591d5ab33 109 .size Default_Handler, .-Default_Handler
be_bryan 0:b74591d5ab33 110 /******************************************************************************
be_bryan 0:b74591d5ab33 111 *
be_bryan 0:b74591d5ab33 112 * The minimal vector table for a Cortex M0. Note that the proper constructs
be_bryan 0:b74591d5ab33 113 * must be placed on this to ensure that it ends up at physical address
be_bryan 0:b74591d5ab33 114 * 0x0000.0000.
be_bryan 0:b74591d5ab33 115 *
be_bryan 0:b74591d5ab33 116 ******************************************************************************/
be_bryan 0:b74591d5ab33 117 .section .isr_vector,"a",%progbits
be_bryan 0:b74591d5ab33 118 .type g_pfnVectors, %object
be_bryan 0:b74591d5ab33 119 .size g_pfnVectors, .-g_pfnVectors
be_bryan 0:b74591d5ab33 120
be_bryan 0:b74591d5ab33 121
be_bryan 0:b74591d5ab33 122 g_pfnVectors:
be_bryan 0:b74591d5ab33 123 .word _estack
be_bryan 0:b74591d5ab33 124 .word Reset_Handler
be_bryan 0:b74591d5ab33 125 .word NMI_Handler
be_bryan 0:b74591d5ab33 126 .word HardFault_Handler
be_bryan 0:b74591d5ab33 127 .word 0
be_bryan 0:b74591d5ab33 128 .word 0
be_bryan 0:b74591d5ab33 129 .word 0
be_bryan 0:b74591d5ab33 130 .word 0
be_bryan 0:b74591d5ab33 131 .word 0
be_bryan 0:b74591d5ab33 132 .word 0
be_bryan 0:b74591d5ab33 133 .word 0
be_bryan 0:b74591d5ab33 134 .word SVC_Handler
be_bryan 0:b74591d5ab33 135 .word 0
be_bryan 0:b74591d5ab33 136 .word 0
be_bryan 0:b74591d5ab33 137 .word PendSV_Handler
be_bryan 0:b74591d5ab33 138 .word SysTick_Handler
be_bryan 0:b74591d5ab33 139 .word WWDG_IRQHandler /* Window WatchDog */
be_bryan 0:b74591d5ab33 140 .word PVD_IRQHandler /* PVD through EXTI Line detection */
be_bryan 0:b74591d5ab33 141 .word RTC_IRQHandler /* RTC through the EXTI line */
be_bryan 0:b74591d5ab33 142 .word FLASH_IRQHandler /* FLASH */
be_bryan 0:b74591d5ab33 143 .word RCC_CRS_IRQHandler /* RCC and CRS */
be_bryan 0:b74591d5ab33 144 .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
be_bryan 0:b74591d5ab33 145 .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
be_bryan 0:b74591d5ab33 146 .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
be_bryan 0:b74591d5ab33 147 .word TSC_IRQHandler /* TSC */
be_bryan 0:b74591d5ab33 148 .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
be_bryan 0:b74591d5ab33 149 .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
be_bryan 0:b74591d5ab33 150 .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
be_bryan 0:b74591d5ab33 151 .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
be_bryan 0:b74591d5ab33 152 .word LPTIM1_IRQHandler /* LPTIM1 */
be_bryan 0:b74591d5ab33 153 .word 0 /* Reserved */
be_bryan 0:b74591d5ab33 154 .word TIM2_IRQHandler /* TIM2 */
be_bryan 0:b74591d5ab33 155 .word 0 /* Reserved */
be_bryan 0:b74591d5ab33 156 .word TIM6_DAC_IRQHandler /* TIM6 and DAC */
be_bryan 0:b74591d5ab33 157 .word 0 /* Reserved */
be_bryan 0:b74591d5ab33 158 .word 0 /* Reserved */
be_bryan 0:b74591d5ab33 159 .word TIM21_IRQHandler /* TIM21 */
be_bryan 0:b74591d5ab33 160 .word 0 /* Reserved */
be_bryan 0:b74591d5ab33 161 .word TIM22_IRQHandler /* TIM22 */
be_bryan 0:b74591d5ab33 162 .word I2C1_IRQHandler /* I2C1 */
be_bryan 0:b74591d5ab33 163 .word I2C2_IRQHandler /* I2C2 */
be_bryan 0:b74591d5ab33 164 .word SPI1_IRQHandler /* SPI1 */
be_bryan 0:b74591d5ab33 165 .word SPI2_IRQHandler /* SPI2 */
be_bryan 0:b74591d5ab33 166 .word USART1_IRQHandler /* USART1 */
be_bryan 0:b74591d5ab33 167 .word USART2_IRQHandler /* USART2 */
be_bryan 0:b74591d5ab33 168 .word RNG_LPUART1_IRQHandler /* RNG and LPUART1 */
be_bryan 0:b74591d5ab33 169 .word LCD_IRQHandler /* LCD */
be_bryan 0:b74591d5ab33 170 .word USB_IRQHandler /* USB */
be_bryan 0:b74591d5ab33 171
be_bryan 0:b74591d5ab33 172 /*******************************************************************************
be_bryan 0:b74591d5ab33 173 *
be_bryan 0:b74591d5ab33 174 * Provide weak aliases for each Exception handler to the Default_Handler.
be_bryan 0:b74591d5ab33 175 * As they are weak aliases, any function with the same name will override
be_bryan 0:b74591d5ab33 176 * this definition.
be_bryan 0:b74591d5ab33 177 *
be_bryan 0:b74591d5ab33 178 *******************************************************************************/
be_bryan 0:b74591d5ab33 179
be_bryan 0:b74591d5ab33 180 .weak NMI_Handler
be_bryan 0:b74591d5ab33 181 .thumb_set NMI_Handler,Default_Handler
be_bryan 0:b74591d5ab33 182
be_bryan 0:b74591d5ab33 183 .weak HardFault_Handler
be_bryan 0:b74591d5ab33 184 .thumb_set HardFault_Handler,Default_Handler
be_bryan 0:b74591d5ab33 185
be_bryan 0:b74591d5ab33 186 .weak SVC_Handler
be_bryan 0:b74591d5ab33 187 .thumb_set SVC_Handler,Default_Handler
be_bryan 0:b74591d5ab33 188
be_bryan 0:b74591d5ab33 189 .weak PendSV_Handler
be_bryan 0:b74591d5ab33 190 .thumb_set PendSV_Handler,Default_Handler
be_bryan 0:b74591d5ab33 191
be_bryan 0:b74591d5ab33 192 .weak SysTick_Handler
be_bryan 0:b74591d5ab33 193 .thumb_set SysTick_Handler,Default_Handler
be_bryan 0:b74591d5ab33 194
be_bryan 0:b74591d5ab33 195 .weak WWDG_IRQHandler
be_bryan 0:b74591d5ab33 196 .thumb_set WWDG_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 197
be_bryan 0:b74591d5ab33 198 .weak PVD_IRQHandler
be_bryan 0:b74591d5ab33 199 .thumb_set PVD_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 200
be_bryan 0:b74591d5ab33 201 .weak RTC_IRQHandler
be_bryan 0:b74591d5ab33 202 .thumb_set RTC_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 203
be_bryan 0:b74591d5ab33 204 .weak FLASH_IRQHandler
be_bryan 0:b74591d5ab33 205 .thumb_set FLASH_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 206
be_bryan 0:b74591d5ab33 207 .weak RCC_CRS_IRQHandler
be_bryan 0:b74591d5ab33 208 .thumb_set RCC_CRS_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 209
be_bryan 0:b74591d5ab33 210 .weak EXTI0_1_IRQHandler
be_bryan 0:b74591d5ab33 211 .thumb_set EXTI0_1_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 212
be_bryan 0:b74591d5ab33 213 .weak EXTI2_3_IRQHandler
be_bryan 0:b74591d5ab33 214 .thumb_set EXTI2_3_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 215
be_bryan 0:b74591d5ab33 216 .weak EXTI4_15_IRQHandler
be_bryan 0:b74591d5ab33 217 .thumb_set EXTI4_15_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 218
be_bryan 0:b74591d5ab33 219 .weak TSC_IRQHandler
be_bryan 0:b74591d5ab33 220 .thumb_set TSC_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 221
be_bryan 0:b74591d5ab33 222 .weak DMA1_Channel1_IRQHandler
be_bryan 0:b74591d5ab33 223 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 224
be_bryan 0:b74591d5ab33 225 .weak DMA1_Channel2_3_IRQHandler
be_bryan 0:b74591d5ab33 226 .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 227
be_bryan 0:b74591d5ab33 228 .weak DMA1_Channel4_5_6_7_IRQHandler
be_bryan 0:b74591d5ab33 229 .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 230
be_bryan 0:b74591d5ab33 231 .weak ADC1_COMP_IRQHandler
be_bryan 0:b74591d5ab33 232 .thumb_set ADC1_COMP_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 233
be_bryan 0:b74591d5ab33 234 .weak LPTIM1_IRQHandler
be_bryan 0:b74591d5ab33 235 .thumb_set LPTIM1_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 236
be_bryan 0:b74591d5ab33 237 .weak TIM2_IRQHandler
be_bryan 0:b74591d5ab33 238 .thumb_set TIM2_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 239
be_bryan 0:b74591d5ab33 240 .weak TIM6_DAC_IRQHandler
be_bryan 0:b74591d5ab33 241 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 242
be_bryan 0:b74591d5ab33 243 .weak TIM21_IRQHandler
be_bryan 0:b74591d5ab33 244 .thumb_set TIM21_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 245
be_bryan 0:b74591d5ab33 246 .weak TIM22_IRQHandler
be_bryan 0:b74591d5ab33 247 .thumb_set TIM22_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 248
be_bryan 0:b74591d5ab33 249 .weak I2C1_IRQHandler
be_bryan 0:b74591d5ab33 250 .thumb_set I2C1_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 251
be_bryan 0:b74591d5ab33 252 .weak I2C2_IRQHandler
be_bryan 0:b74591d5ab33 253 .thumb_set I2C2_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 254
be_bryan 0:b74591d5ab33 255 .weak SPI1_IRQHandler
be_bryan 0:b74591d5ab33 256 .thumb_set SPI1_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 257
be_bryan 0:b74591d5ab33 258 .weak SPI2_IRQHandler
be_bryan 0:b74591d5ab33 259 .thumb_set SPI2_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 260
be_bryan 0:b74591d5ab33 261 .weak USART1_IRQHandler
be_bryan 0:b74591d5ab33 262 .thumb_set USART1_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 263
be_bryan 0:b74591d5ab33 264 .weak USART2_IRQHandler
be_bryan 0:b74591d5ab33 265 .thumb_set USART2_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 266
be_bryan 0:b74591d5ab33 267 .weak RNG_LPUART1_IRQHandler
be_bryan 0:b74591d5ab33 268 .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 269
be_bryan 0:b74591d5ab33 270 .weak LCD_IRQHandler
be_bryan 0:b74591d5ab33 271 .thumb_set LCD_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 272
be_bryan 0:b74591d5ab33 273 .weak USB_IRQHandler
be_bryan 0:b74591d5ab33 274 .thumb_set USB_IRQHandler,Default_Handler
be_bryan 0:b74591d5ab33 275
be_bryan 0:b74591d5ab33 276
be_bryan 0:b74591d5ab33 277
be_bryan 0:b74591d5ab33 278 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
be_bryan 0:b74591d5ab33 279