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targets/TARGET_Maxim/TARGET_MAX32610/PeripheralPins.c@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /*******************************************************************************
be_bryan 0:b74591d5ab33 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Permission is hereby granted, free of charge, to any person obtaining a
be_bryan 0:b74591d5ab33 5 * copy of this software and associated documentation files (the "Software"),
be_bryan 0:b74591d5ab33 6 * to deal in the Software without restriction, including without limitation
be_bryan 0:b74591d5ab33 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
be_bryan 0:b74591d5ab33 8 * and/or sell copies of the Software, and to permit persons to whom the
be_bryan 0:b74591d5ab33 9 * Software is furnished to do so, subject to the following conditions:
be_bryan 0:b74591d5ab33 10 *
be_bryan 0:b74591d5ab33 11 * The above copyright notice and this permission notice shall be included
be_bryan 0:b74591d5ab33 12 * in all copies or substantial portions of the Software.
be_bryan 0:b74591d5ab33 13 *
be_bryan 0:b74591d5ab33 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
be_bryan 0:b74591d5ab33 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
be_bryan 0:b74591d5ab33 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
be_bryan 0:b74591d5ab33 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
be_bryan 0:b74591d5ab33 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
be_bryan 0:b74591d5ab33 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
be_bryan 0:b74591d5ab33 20 * OTHER DEALINGS IN THE SOFTWARE.
be_bryan 0:b74591d5ab33 21 *
be_bryan 0:b74591d5ab33 22 * Except as contained in this notice, the name of Maxim Integrated
be_bryan 0:b74591d5ab33 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
be_bryan 0:b74591d5ab33 24 * Products, Inc. Branding Policy.
be_bryan 0:b74591d5ab33 25 *
be_bryan 0:b74591d5ab33 26 * The mere transfer of this software does not imply any licenses
be_bryan 0:b74591d5ab33 27 * of trade secrets, proprietary technology, copyrights, patents,
be_bryan 0:b74591d5ab33 28 * trademarks, maskwork rights, or any other form of intellectual
be_bryan 0:b74591d5ab33 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
be_bryan 0:b74591d5ab33 30 * ownership rights.
be_bryan 0:b74591d5ab33 31 *******************************************************************************
be_bryan 0:b74591d5ab33 32 */
be_bryan 0:b74591d5ab33 33
be_bryan 0:b74591d5ab33 34 #include "device.h"
be_bryan 0:b74591d5ab33 35 #include "PeripheralPins.h"
be_bryan 0:b74591d5ab33 36 #include "ioman_regs.h"
be_bryan 0:b74591d5ab33 37
be_bryan 0:b74591d5ab33 38 /*
be_bryan 0:b74591d5ab33 39 * To select a peripheral function on Maxim microcontrollers, multiple
be_bryan 0:b74591d5ab33 40 * configurations must be made. The mbed PinMap structure only includes one
be_bryan 0:b74591d5ab33 41 * data member to hold this information. To extend the configuration storage,
be_bryan 0:b74591d5ab33 42 * the "function" data member is used as a pointer to a pin_function_t
be_bryan 0:b74591d5ab33 43 * structure. This structure is defined in objects.h. The definitions below
be_bryan 0:b74591d5ab33 44 * include the creation of the pin_function_t structures and the assignment of
be_bryan 0:b74591d5ab33 45 * the pointers to the "function" data members.
be_bryan 0:b74591d5ab33 46 */
be_bryan 0:b74591d5ab33 47
be_bryan 0:b74591d5ab33 48 #ifdef TOOLCHAIN_ARM_STD
be_bryan 0:b74591d5ab33 49 #pragma diag_suppress 1296
be_bryan 0:b74591d5ab33 50 #endif
be_bryan 0:b74591d5ab33 51
be_bryan 0:b74591d5ab33 52 /************I2C***************/
be_bryan 0:b74591d5ab33 53 const PinMap PinMap_I2C_SDA[] = {
be_bryan 0:b74591d5ab33 54 { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
be_bryan 0:b74591d5ab33 55 { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
be_bryan 0:b74591d5ab33 56 { NC, NC, 0 }
be_bryan 0:b74591d5ab33 57 };
be_bryan 0:b74591d5ab33 58
be_bryan 0:b74591d5ab33 59 const PinMap PinMap_I2C_SCL[] = {
be_bryan 0:b74591d5ab33 60 { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
be_bryan 0:b74591d5ab33 61 { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_H | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
be_bryan 0:b74591d5ab33 62 { NC, NC, 0 }
be_bryan 0:b74591d5ab33 63 };
be_bryan 0:b74591d5ab33 64
be_bryan 0:b74591d5ab33 65 /************UART***************/
be_bryan 0:b74591d5ab33 66 const PinMap PinMap_UART_TX[] = {
be_bryan 0:b74591d5ab33 67 { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 68 { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 69 { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 70 { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 71 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 72 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 73 { NC, NC, 0 }
be_bryan 0:b74591d5ab33 74 };
be_bryan 0:b74591d5ab33 75
be_bryan 0:b74591d5ab33 76 const PinMap PinMap_UART_RX[] = {
be_bryan 0:b74591d5ab33 77 { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 78 { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 79 { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 80 { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 81 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 82 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
be_bryan 0:b74591d5ab33 83 { NC, NC, 0 }
be_bryan 0:b74591d5ab33 84 };
be_bryan 0:b74591d5ab33 85
be_bryan 0:b74591d5ab33 86 const PinMap PinMap_UART_CTS[] = {
be_bryan 0:b74591d5ab33 87 { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
be_bryan 0:b74591d5ab33 88 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
be_bryan 0:b74591d5ab33 89 { P2_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
be_bryan 0:b74591d5ab33 90 { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
be_bryan 0:b74591d5ab33 91 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
be_bryan 0:b74591d5ab33 92 { NC, NC, 0 }
be_bryan 0:b74591d5ab33 93 };
be_bryan 0:b74591d5ab33 94
be_bryan 0:b74591d5ab33 95 const PinMap PinMap_UART_RTS[] = {
be_bryan 0:b74591d5ab33 96 { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
be_bryan 0:b74591d5ab33 97 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
be_bryan 0:b74591d5ab33 98 { P2_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
be_bryan 0:b74591d5ab33 99 { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
be_bryan 0:b74591d5ab33 100 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
be_bryan 0:b74591d5ab33 101 { NC, NC, 0 }
be_bryan 0:b74591d5ab33 102 };
be_bryan 0:b74591d5ab33 103
be_bryan 0:b74591d5ab33 104 /************SPI***************/
be_bryan 0:b74591d5ab33 105 const PinMap PinMap_SPI_SCLK[] = {
be_bryan 0:b74591d5ab33 106 { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
be_bryan 0:b74591d5ab33 107 { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
be_bryan 0:b74591d5ab33 108 { NC, NC, 0}
be_bryan 0:b74591d5ab33 109 };
be_bryan 0:b74591d5ab33 110
be_bryan 0:b74591d5ab33 111 const PinMap PinMap_SPI_MOSI[] = {
be_bryan 0:b74591d5ab33 112 { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
be_bryan 0:b74591d5ab33 113 { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
be_bryan 0:b74591d5ab33 114 { NC, NC, 0}
be_bryan 0:b74591d5ab33 115 };
be_bryan 0:b74591d5ab33 116
be_bryan 0:b74591d5ab33 117 const PinMap PinMap_SPI_MISO[] = {
be_bryan 0:b74591d5ab33 118 { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
be_bryan 0:b74591d5ab33 119 { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
be_bryan 0:b74591d5ab33 120 { NC, NC, 0}
be_bryan 0:b74591d5ab33 121 };
be_bryan 0:b74591d5ab33 122
be_bryan 0:b74591d5ab33 123 const PinMap PinMap_SPI_SSEL[] = {
be_bryan 0:b74591d5ab33 124 { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
be_bryan 0:b74591d5ab33 125 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
be_bryan 0:b74591d5ab33 126 { NC, NC, 0}
be_bryan 0:b74591d5ab33 127 };
be_bryan 0:b74591d5ab33 128
be_bryan 0:b74591d5ab33 129 /************PWM***************/
be_bryan 0:b74591d5ab33 130 const PinMap PinMap_PWM[] = {
be_bryan 0:b74591d5ab33 131 {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
be_bryan 0:b74591d5ab33 132 {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, {P0_1, PWM_0, 3},
be_bryan 0:b74591d5ab33 133 {P0_2, PWM_2, 1}, {P0_2, PWM_1, 2}, {P0_2, PWM_5, 3},
be_bryan 0:b74591d5ab33 134 {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, {P0_3, PWM_1, 3},
be_bryan 0:b74591d5ab33 135 {P0_4, PWM_4, 1}, {P0_4, PWM_2, 2}, {P0_4, PWM_6, 3},
be_bryan 0:b74591d5ab33 136 {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, {P0_5, PWM_2, 3},
be_bryan 0:b74591d5ab33 137 {P0_6, PWM_6, 1}, {P0_6, PWM_3, 2}, {P0_6, PWM_7, 3},
be_bryan 0:b74591d5ab33 138 {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, {P0_7, PWM_3, 3},
be_bryan 0:b74591d5ab33 139
be_bryan 0:b74591d5ab33 140 {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
be_bryan 0:b74591d5ab33 141 {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, {P1_1, PWM_0, 3},
be_bryan 0:b74591d5ab33 142 {P1_2, PWM_2, 1}, {P1_2, PWM_1, 2}, {P1_2, PWM_5, 3},
be_bryan 0:b74591d5ab33 143 {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, {P1_3, PWM_1, 3},
be_bryan 0:b74591d5ab33 144 {P1_4, PWM_4, 1}, {P1_4, PWM_2, 2}, {P1_4, PWM_6, 3},
be_bryan 0:b74591d5ab33 145 {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, {P1_5, PWM_2, 3},
be_bryan 0:b74591d5ab33 146 {P1_6, PWM_6, 1}, {P1_6, PWM_3, 2}, {P1_6, PWM_7, 3},
be_bryan 0:b74591d5ab33 147 {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, {P1_7, PWM_3, 3},
be_bryan 0:b74591d5ab33 148
be_bryan 0:b74591d5ab33 149 {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
be_bryan 0:b74591d5ab33 150 {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, {P2_1, PWM_0, 3},
be_bryan 0:b74591d5ab33 151 {P2_2, PWM_2, 1}, {P2_2, PWM_1, 2}, {P2_2, PWM_5, 3},
be_bryan 0:b74591d5ab33 152 {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, {P2_3, PWM_1, 3},
be_bryan 0:b74591d5ab33 153 {P2_4, PWM_4, 1}, {P2_4, PWM_2, 2}, {P2_4, PWM_6, 3},
be_bryan 0:b74591d5ab33 154 {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, {P2_5, PWM_2, 3},
be_bryan 0:b74591d5ab33 155 {P2_6, PWM_6, 1}, {P2_6, PWM_3, 2}, {P2_6, PWM_7, 3},
be_bryan 0:b74591d5ab33 156 {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, {P2_7, PWM_3, 3},
be_bryan 0:b74591d5ab33 157
be_bryan 0:b74591d5ab33 158 {NC, NC, 0}
be_bryan 0:b74591d5ab33 159 };
be_bryan 0:b74591d5ab33 160
be_bryan 0:b74591d5ab33 161 /************ADC***************/
be_bryan 0:b74591d5ab33 162 const PinMap PinMap_ADC[] = {
be_bryan 0:b74591d5ab33 163 {AIN_0P, ADC, 0},
be_bryan 0:b74591d5ab33 164 {AIN_1P, ADC, 0},
be_bryan 0:b74591d5ab33 165 {AIN_2P, ADC, 0},
be_bryan 0:b74591d5ab33 166 {AIN_3P, ADC, 0},
be_bryan 0:b74591d5ab33 167 {AIN_4P, ADC, 0},
be_bryan 0:b74591d5ab33 168 {AIN_5P, ADC, 0},
be_bryan 0:b74591d5ab33 169 {AIN_0N, ADC, 0},
be_bryan 0:b74591d5ab33 170 {AIN_1N, ADC, 0},
be_bryan 0:b74591d5ab33 171 {AIN_2N, ADC, 0},
be_bryan 0:b74591d5ab33 172 {AIN_3N, ADC, 0},
be_bryan 0:b74591d5ab33 173 {AIN_4N, ADC, 0},
be_bryan 0:b74591d5ab33 174 {AIN_5N, ADC, 0},
be_bryan 0:b74591d5ab33 175 {AIN_0D, ADC, 1},
be_bryan 0:b74591d5ab33 176 {AIN_1D, ADC, 1},
be_bryan 0:b74591d5ab33 177 {AIN_2D, ADC, 1},
be_bryan 0:b74591d5ab33 178 {AIN_3D, ADC, 1},
be_bryan 0:b74591d5ab33 179 {AIN_4D, ADC, 1},
be_bryan 0:b74591d5ab33 180 {AIN_5D, ADC, 1},
be_bryan 0:b74591d5ab33 181 {NC, NC, 0}
be_bryan 0:b74591d5ab33 182 };
be_bryan 0:b74591d5ab33 183
be_bryan 0:b74591d5ab33 184 /************DAC***************/
be_bryan 0:b74591d5ab33 185 const PinMap PinMap_DAC[] = {
be_bryan 0:b74591d5ab33 186 {AOUT_AO, DAC0, 0},
be_bryan 0:b74591d5ab33 187 {AOUT_BO, DAC1, 0},
be_bryan 0:b74591d5ab33 188 {AOUT_CO, DAC2, 0},
be_bryan 0:b74591d5ab33 189 {AOUT_DO, DAC3, 0},
be_bryan 0:b74591d5ab33 190 {NC, NC, 0}
be_bryan 0:b74591d5ab33 191 };