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targets/TARGET_ARM_SSG/TARGET_IOTSS/spi_def.h@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /* mbed Microcontroller Library
be_bryan 0:b74591d5ab33 2 * Copyright (c) 2006-2015 ARM Limited
be_bryan 0:b74591d5ab33 3 *
be_bryan 0:b74591d5ab33 4 * Licensed under the Apache License, Version 2.0 (the "License");
be_bryan 0:b74591d5ab33 5 * you may not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 6 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 7 *
be_bryan 0:b74591d5ab33 8 * http://www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 11 * distributed under the License is distributed on an "AS IS" BASIS,
be_bryan 0:b74591d5ab33 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 13 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 14 * limitations under the License.
be_bryan 0:b74591d5ab33 15 * ----------------------------------------------------------------
be_bryan 0:b74591d5ab33 16 * File: apspi.h
be_bryan 0:b74591d5ab33 17 * Release: Version 2.0
be_bryan 0:b74591d5ab33 18 * ----------------------------------------------------------------
be_bryan 0:b74591d5ab33 19 *
be_bryan 0:b74591d5ab33 20 * SSP interface Support
be_bryan 0:b74591d5ab33 21 * =====================
be_bryan 0:b74591d5ab33 22 */
be_bryan 0:b74591d5ab33 23
be_bryan 0:b74591d5ab33 24 #define SSPCS_BASE (0x4002804C) // SSP chip select register
be_bryan 0:b74591d5ab33 25 #define SSP_BASE (0x40020000) // SSP Prime Cell
be_bryan 0:b74591d5ab33 26
be_bryan 0:b74591d5ab33 27 #define SSPCR0 ((volatile unsigned int *)(SSP_BASE + 0x00))
be_bryan 0:b74591d5ab33 28 #define SSPCR1 ((volatile unsigned int *)(SSP_BASE + 0x04))
be_bryan 0:b74591d5ab33 29 #define SSPDR ((volatile unsigned int *)(SSP_BASE + 0x08))
be_bryan 0:b74591d5ab33 30 #define SSPSR ((volatile unsigned int *)(SSP_BASE + 0x0C))
be_bryan 0:b74591d5ab33 31 #define SSPCPSR ((volatile unsigned int *)(SSP_BASE + 0x10))
be_bryan 0:b74591d5ab33 32 #define SSPIMSC ((volatile unsigned int *)(SSP_BASE + 0x14))
be_bryan 0:b74591d5ab33 33 #define SSPRIS ((volatile unsigned int *)(SSP_BASE + 0x18))
be_bryan 0:b74591d5ab33 34 #define SSPMIS ((volatile unsigned int *)(SSP_BASE + 0x1C))
be_bryan 0:b74591d5ab33 35 #define SSPICR ((volatile unsigned int *)(SSP_BASE + 0x20))
be_bryan 0:b74591d5ab33 36 #define SSPDMACR ((volatile unsigned int *)(SSP_BASE + 0x24))
be_bryan 0:b74591d5ab33 37 #define SSPCS ((volatile unsigned int *)(SSPCS_BASE))
be_bryan 0:b74591d5ab33 38
be_bryan 0:b74591d5ab33 39 // SSPCR0 Control register 0
be_bryan 0:b74591d5ab33 40 #define SSPCR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
be_bryan 0:b74591d5ab33 41 #define SSPCR0_SPH 0x0080 // SSPCLKOUT phase
be_bryan 0:b74591d5ab33 42 #define SSPCR0_SPO 0x0040 // SSPCLKOUT polarity
be_bryan 0:b74591d5ab33 43 #define SSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
be_bryan 0:b74591d5ab33 44 #define SSPCR0_DSS_8 0x0007 // Data packet size, 8bits
be_bryan 0:b74591d5ab33 45 #define SSPCR0_DSS_16 0x000F // Data packet size, 16bits
be_bryan 0:b74591d5ab33 46
be_bryan 0:b74591d5ab33 47 // SSPCR1 Control register 1
be_bryan 0:b74591d5ab33 48 #define SSPCR1_SOD 0x0008 // Slave Output mode Disable
be_bryan 0:b74591d5ab33 49 #define SSPCR1_MS 0x0004 // Master or Slave mode
be_bryan 0:b74591d5ab33 50 #define SSPCR1_SSE 0x0002 // Serial port enable
be_bryan 0:b74591d5ab33 51 #define SSPCR1_LBM 0x0001 // Loop Back Mode
be_bryan 0:b74591d5ab33 52
be_bryan 0:b74591d5ab33 53 // SSPSR Status register
be_bryan 0:b74591d5ab33 54 #define SSPSR_BSY 0x0010 // Busy
be_bryan 0:b74591d5ab33 55 #define SSPSR_RFF 0x0008 // Receive FIFO full
be_bryan 0:b74591d5ab33 56 #define SSPSR_RNE 0x0004 // Receive FIFO not empty
be_bryan 0:b74591d5ab33 57 #define SSPSR_TNF 0x0002 // Transmit FIFO not full
be_bryan 0:b74591d5ab33 58 #define SSPSR_TFE 0x0001 // Transmit FIFO empty
be_bryan 0:b74591d5ab33 59
be_bryan 0:b74591d5ab33 60 // SSPCPSR Clock prescale register
be_bryan 0:b74591d5ab33 61 #define SSPCPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
be_bryan 0:b74591d5ab33 62
be_bryan 0:b74591d5ab33 63 // SSPIMSC Interrupt mask set and clear register
be_bryan 0:b74591d5ab33 64 #define SSPIMSC_TXIM 0x0008 // Transmit FIFO not Masked
be_bryan 0:b74591d5ab33 65 #define SSPIMSC_RXIM 0x0004 // Receive FIFO not Masked
be_bryan 0:b74591d5ab33 66 #define SSPIMSC_RTIM 0x0002 // Receive timeout not Masked
be_bryan 0:b74591d5ab33 67 #define SSPIMSC_RORIM 0x0001 // Receive overrun not Masked
be_bryan 0:b74591d5ab33 68
be_bryan 0:b74591d5ab33 69 // SSPRIS Raw interrupt status register
be_bryan 0:b74591d5ab33 70 #define SSPRIS_TXRIS 0x0008 // Raw Transmit interrupt flag
be_bryan 0:b74591d5ab33 71 #define SSPRIS_RXRIS 0x0004 // Raw Receive interrupt flag
be_bryan 0:b74591d5ab33 72 #define SSPRIS_RTRIS 0x0002 // Raw Timemout interrupt flag
be_bryan 0:b74591d5ab33 73 #define SSPRIS_RORRIS 0x0001 // Raw Overrun interrupt flag
be_bryan 0:b74591d5ab33 74
be_bryan 0:b74591d5ab33 75 // SSPMIS Masked interrupt status register
be_bryan 0:b74591d5ab33 76 #define SSPMIS_TXMIS 0x0008 // Masked Transmit interrupt flag
be_bryan 0:b74591d5ab33 77 #define SSPMIS_RXMIS 0x0004 // Masked Receive interrupt flag
be_bryan 0:b74591d5ab33 78 #define SSPMIS_RTMIS 0x0002 // Masked Timemout interrupt flag
be_bryan 0:b74591d5ab33 79 #define SSPMIS_RORMIS 0x0001 // Masked Overrun interrupt flag
be_bryan 0:b74591d5ab33 80
be_bryan 0:b74591d5ab33 81 // SSPICR Interrupt clear register
be_bryan 0:b74591d5ab33 82 #define SSPICR_RTIC 0x0002 // Clears Timeout interrupt flag
be_bryan 0:b74591d5ab33 83 #define SSPICR_RORIC 0x0001 // Clears Overrun interrupt flag
be_bryan 0:b74591d5ab33 84
be_bryan 0:b74591d5ab33 85 // SSPDMACR DMA control register
be_bryan 0:b74591d5ab33 86 #define SSPDMACR_TXDMAE 0x0002 // Enable Transmit FIFO DMA
be_bryan 0:b74591d5ab33 87 #define SSPDMACR_RXDMAE 0x0001 // Enable Receive FIFO DMA
be_bryan 0:b74591d5ab33 88
be_bryan 0:b74591d5ab33 89 // SPICS register (0=Chip Select low)
be_bryan 0:b74591d5ab33 90 #define SSPCS_nCS1 0x0002 // nCS1 (SPI_nSS)
be_bryan 0:b74591d5ab33 91
be_bryan 0:b74591d5ab33 92 // SPI defaults
be_bryan 0:b74591d5ab33 93 #define SSPMAXTIME 1000 // Maximum time to wait for SSP (10*10uS)
be_bryan 0:b74591d5ab33 94
be_bryan 0:b74591d5ab33 95 // EEPROM instruction set
be_bryan 0:b74591d5ab33 96 #define EEWRSR 0x0001 // Write status
be_bryan 0:b74591d5ab33 97 #define EEWRITE 0x0002 // Write data
be_bryan 0:b74591d5ab33 98 #define EEREAD 0x0003 // Read data
be_bryan 0:b74591d5ab33 99 #define EEWDI 0x0004 // Write disable
be_bryan 0:b74591d5ab33 100 #define EEWREN 0x0006 // Write enable
be_bryan 0:b74591d5ab33 101 #define EERDSR 0x0005 // Read status
be_bryan 0:b74591d5ab33 102
be_bryan 0:b74591d5ab33 103 // EEPROM status register flags
be_bryan 0:b74591d5ab33 104 #define EERDSR_WIP 0x0001 // Write in process
be_bryan 0:b74591d5ab33 105 #define EERDSR_WEL 0x0002 // Write enable latch
be_bryan 0:b74591d5ab33 106 #define EERDSR_BP0 0x0004 // Block protect 0
be_bryan 0:b74591d5ab33 107 #define EERDSR_BP1 0x0008 // Block protect 1
be_bryan 0:b74591d5ab33 108 #define EERDSR_WPEN 0x0080 // Write protect enable
be_bryan 0:b74591d5ab33 109
be_bryan 0:b74591d5ab33 110 /* ----------------------------------------------------------------
be_bryan 0:b74591d5ab33 111 *
be_bryan 0:b74591d5ab33 112 * Color LCD Support
be_bryan 0:b74591d5ab33 113 * =================
be_bryan 0:b74591d5ab33 114 */
be_bryan 0:b74591d5ab33 115
be_bryan 0:b74591d5ab33 116 // Color LCD Controller Internal Register addresses
be_bryan 0:b74591d5ab33 117 #define LSSPCS_BASE (0x4002804C) // LSSP chip select register
be_bryan 0:b74591d5ab33 118 #define LSSP_BASE (0x40021000) // LSSP Prime Cell
be_bryan 0:b74591d5ab33 119
be_bryan 0:b74591d5ab33 120 #define LSSPCR0 ((volatile unsigned int *)(LSSP_BASE + 0x00))
be_bryan 0:b74591d5ab33 121 #define LSSPCR1 ((volatile unsigned int *)(LSSP_BASE + 0x04))
be_bryan 0:b74591d5ab33 122 #define LSSPDR ((volatile unsigned int *)(LSSP_BASE + 0x08))
be_bryan 0:b74591d5ab33 123 #define LSSPSR ((volatile unsigned int *)(LSSP_BASE + 0x0C))
be_bryan 0:b74591d5ab33 124 #define LSSPCPSR ((volatile unsigned int *)(LSSP_BASE + 0x10))
be_bryan 0:b74591d5ab33 125 #define LSSPIMSC ((volatile unsigned int *)(LSSP_BASE + 0x14))
be_bryan 0:b74591d5ab33 126 #define LSSPRIS ((volatile unsigned int *)(LSSP_BASE + 0x18))
be_bryan 0:b74591d5ab33 127 #define LSSPMIS ((volatile unsigned int *)(LSSP_BASE + 0x1C))
be_bryan 0:b74591d5ab33 128 #define LSSPICR ((volatile unsigned int *)(LSSP_BASE + 0x20))
be_bryan 0:b74591d5ab33 129 #define LSSPDMACR ((volatile unsigned int *)(LSSP_BASE + 0x24))
be_bryan 0:b74591d5ab33 130 #define LSSPCS ((volatile unsigned int *)(LSSPCS_BASE))
be_bryan 0:b74591d5ab33 131
be_bryan 0:b74591d5ab33 132 // LSSPCR0 Control register 0
be_bryan 0:b74591d5ab33 133 #define LSSPCR0_SCR_DFLT 0x0100 // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
be_bryan 0:b74591d5ab33 134 #define LSSPCR0_SPH 0x0080 // LSSPCLKOUT phase
be_bryan 0:b74591d5ab33 135 #define LSSPCR0_SPO 0x0040 // LSSPCLKOUT polarity
be_bryan 0:b74591d5ab33 136 #define LSSPCR0_FRF_MOT 0x0000 // Frame format, Motorola
be_bryan 0:b74591d5ab33 137 #define LSSPCR0_DSS_8 0x0007 // Data packet size, 8bits
be_bryan 0:b74591d5ab33 138 #define LSSPCR0_DSS_16 0x000F // Data packet size, 16bits
be_bryan 0:b74591d5ab33 139
be_bryan 0:b74591d5ab33 140 // LSSPCR1 Control register 1
be_bryan 0:b74591d5ab33 141 #define LSSPCR1_SOD 0x0008 // Slave Output mode Disable
be_bryan 0:b74591d5ab33 142 #define LSSPCR1_MS 0x0004 // Master or Slave mode
be_bryan 0:b74591d5ab33 143 #define LSSPCR1_SSE 0x0002 // Serial port enable
be_bryan 0:b74591d5ab33 144 #define LSSPCR1_LBM 0x0001 // Loop Back Mode
be_bryan 0:b74591d5ab33 145
be_bryan 0:b74591d5ab33 146 // LSSPSR Status register
be_bryan 0:b74591d5ab33 147 #define LSSPSR_BSY 0x0010 // Busy
be_bryan 0:b74591d5ab33 148 #define LSSPSR_RFF 0x0008 // Receive FIFO full
be_bryan 0:b74591d5ab33 149 #define LSSPSR_RNE 0x0004 // Receive FIFO not empty
be_bryan 0:b74591d5ab33 150 #define LSSPSR_TNF 0x0002 // Transmit FIFO not full
be_bryan 0:b74591d5ab33 151 #define LSSPSR_TFE 0x0001 // Transmit FIFO empty
be_bryan 0:b74591d5ab33 152
be_bryan 0:b74591d5ab33 153 // LSSPCPSR Clock prescale register
be_bryan 0:b74591d5ab33 154 #define LSSPCPSR_DFLT 0x0002 // Clock prescale (use with SCR)
be_bryan 0:b74591d5ab33 155
be_bryan 0:b74591d5ab33 156 // SPICS register
be_bryan 0:b74591d5ab33 157 #define LSSPCS_nCS0 0x0001 // nCS0 (CLCD_CS)
be_bryan 0:b74591d5ab33 158 #define LSSPCS_nCS2 0x0004 // nCS2 (CLCD_T_CS)
be_bryan 0:b74591d5ab33 159 #define LCD_RESET 0x0008 // RESET (CLCD_RESET)
be_bryan 0:b74591d5ab33 160 #define LCD_RS 0x0010 // RS (CLCD_RS)
be_bryan 0:b74591d5ab33 161 #define LCD_RD 0x0020 // RD (CLCD_RD)
be_bryan 0:b74591d5ab33 162 #define LCD_BL 0x0040 // Backlight (CLCD_BL_CTRL)
be_bryan 0:b74591d5ab33 163
be_bryan 0:b74591d5ab33 164 // SPI defaults
be_bryan 0:b74591d5ab33 165 #define LSSPMAXTIME 10000 // Maximum time to wait for LSSP (10*10uS)
be_bryan 0:b74591d5ab33 166 #define LSPI_START (0x70) // Start byte for SPI transfer
be_bryan 0:b74591d5ab33 167 #define LSPI_RD (0x01) // WR bit 1 within start
be_bryan 0:b74591d5ab33 168 #define LSPI_WR (0x00) // WR bit 0 within start
be_bryan 0:b74591d5ab33 169 #define LSPI_DATA (0x02) // RS bit 1 within start byte
be_bryan 0:b74591d5ab33 170 #define LSPI_INDEX (0x00) // RS bit 0 within start byte
be_bryan 0:b74591d5ab33 171
be_bryan 0:b74591d5ab33 172 // Screen size
be_bryan 0:b74591d5ab33 173 #define LCD_WIDTH 320 // Screen Width (in pixels)
be_bryan 0:b74591d5ab33 174 #define LCD_HEIGHT 240 // Screen Height (in pixels)