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cmsis/TARGET_CORTEX_M/mpu_armv8.h@0:b74591d5ab33, 2017-12-11 (annotated)

Committer:
be_bryan
Date:
Mon Dec 11 17:54:04 2017 +0000
Revision:
0:b74591d5ab33
motor ++

Who changed what in which revision?

UserRevisionLine numberNew contents of line
be_bryan 0:b74591d5ab33 1 /******************************************************************************
be_bryan 0:b74591d5ab33 2 * @file mpu_armv8.h
be_bryan 0:b74591d5ab33 3 * @brief CMSIS MPU API for ARMv8 MPU
be_bryan 0:b74591d5ab33 4 * @version V5.0.3
be_bryan 0:b74591d5ab33 5 * @date 09. August 2017
be_bryan 0:b74591d5ab33 6 ******************************************************************************/
be_bryan 0:b74591d5ab33 7 /*
be_bryan 0:b74591d5ab33 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
be_bryan 0:b74591d5ab33 9 *
be_bryan 0:b74591d5ab33 10 * SPDX-License-Identifier: Apache-2.0
be_bryan 0:b74591d5ab33 11 *
be_bryan 0:b74591d5ab33 12 * Licensed under the Apache License, Version 2.0 (the License); you may
be_bryan 0:b74591d5ab33 13 * not use this file except in compliance with the License.
be_bryan 0:b74591d5ab33 14 * You may obtain a copy of the License at
be_bryan 0:b74591d5ab33 15 *
be_bryan 0:b74591d5ab33 16 * www.apache.org/licenses/LICENSE-2.0
be_bryan 0:b74591d5ab33 17 *
be_bryan 0:b74591d5ab33 18 * Unless required by applicable law or agreed to in writing, software
be_bryan 0:b74591d5ab33 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
be_bryan 0:b74591d5ab33 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
be_bryan 0:b74591d5ab33 21 * See the License for the specific language governing permissions and
be_bryan 0:b74591d5ab33 22 * limitations under the License.
be_bryan 0:b74591d5ab33 23 */
be_bryan 0:b74591d5ab33 24
be_bryan 0:b74591d5ab33 25 #ifndef ARM_MPU_ARMV8_H
be_bryan 0:b74591d5ab33 26 #define ARM_MPU_ARMV8_H
be_bryan 0:b74591d5ab33 27
be_bryan 0:b74591d5ab33 28 /** \brief Attribute for device memory (outer only) */
be_bryan 0:b74591d5ab33 29 #define ARM_MPU_ATTR_DEVICE ( 0U )
be_bryan 0:b74591d5ab33 30
be_bryan 0:b74591d5ab33 31 /** \brief Attribute for non-cacheable, normal memory */
be_bryan 0:b74591d5ab33 32 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
be_bryan 0:b74591d5ab33 33
be_bryan 0:b74591d5ab33 34 /** \brief Attribute for normal memory (outer and inner)
be_bryan 0:b74591d5ab33 35 * \param NT Non-Transient: Set to 1 for non-transient data.
be_bryan 0:b74591d5ab33 36 * \param WB Write-Back: Set to 1 to use write-back update policy.
be_bryan 0:b74591d5ab33 37 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
be_bryan 0:b74591d5ab33 38 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
be_bryan 0:b74591d5ab33 39 */
be_bryan 0:b74591d5ab33 40 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
be_bryan 0:b74591d5ab33 41 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
be_bryan 0:b74591d5ab33 42
be_bryan 0:b74591d5ab33 43 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
be_bryan 0:b74591d5ab33 44 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
be_bryan 0:b74591d5ab33 45
be_bryan 0:b74591d5ab33 46 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
be_bryan 0:b74591d5ab33 47 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
be_bryan 0:b74591d5ab33 48
be_bryan 0:b74591d5ab33 49 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
be_bryan 0:b74591d5ab33 50 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
be_bryan 0:b74591d5ab33 51
be_bryan 0:b74591d5ab33 52 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
be_bryan 0:b74591d5ab33 53 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
be_bryan 0:b74591d5ab33 54
be_bryan 0:b74591d5ab33 55 /** \brief Memory Attribute
be_bryan 0:b74591d5ab33 56 * \param O Outer memory attributes
be_bryan 0:b74591d5ab33 57 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
be_bryan 0:b74591d5ab33 58 */
be_bryan 0:b74591d5ab33 59 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
be_bryan 0:b74591d5ab33 60
be_bryan 0:b74591d5ab33 61 /** \brief Normal memory non-shareable */
be_bryan 0:b74591d5ab33 62 #define ARM_MPU_SH_NON (0U)
be_bryan 0:b74591d5ab33 63
be_bryan 0:b74591d5ab33 64 /** \brief Normal memory outer shareable */
be_bryan 0:b74591d5ab33 65 #define ARM_MPU_SH_OUTER (2U)
be_bryan 0:b74591d5ab33 66
be_bryan 0:b74591d5ab33 67 /** \brief Normal memory inner shareable */
be_bryan 0:b74591d5ab33 68 #define ARM_MPU_SH_INNER (3U)
be_bryan 0:b74591d5ab33 69
be_bryan 0:b74591d5ab33 70 /** \brief Memory access permissions
be_bryan 0:b74591d5ab33 71 * \param RO Read-Only: Set to 1 for read-only memory.
be_bryan 0:b74591d5ab33 72 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
be_bryan 0:b74591d5ab33 73 */
be_bryan 0:b74591d5ab33 74 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
be_bryan 0:b74591d5ab33 75
be_bryan 0:b74591d5ab33 76 /** \brief Region Base Address Register value
be_bryan 0:b74591d5ab33 77 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
be_bryan 0:b74591d5ab33 78 * \param SH Defines the Shareability domain for this memory region.
be_bryan 0:b74591d5ab33 79 * \param RO Read-Only: Set to 1 for a read-only memory region.
be_bryan 0:b74591d5ab33 80 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
be_bryan 0:b74591d5ab33 81 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
be_bryan 0:b74591d5ab33 82 */
be_bryan 0:b74591d5ab33 83 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
be_bryan 0:b74591d5ab33 84 ((BASE & MPU_RBAR_BASE_Pos) | \
be_bryan 0:b74591d5ab33 85 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
be_bryan 0:b74591d5ab33 86 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
be_bryan 0:b74591d5ab33 87 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
be_bryan 0:b74591d5ab33 88
be_bryan 0:b74591d5ab33 89 /** \brief Region Limit Address Register value
be_bryan 0:b74591d5ab33 90 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
be_bryan 0:b74591d5ab33 91 * \param IDX The attribute index to be associated with this memory region.
be_bryan 0:b74591d5ab33 92 */
be_bryan 0:b74591d5ab33 93 #define ARM_MPU_RLAR(LIMIT, IDX) \
be_bryan 0:b74591d5ab33 94 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
be_bryan 0:b74591d5ab33 95 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
be_bryan 0:b74591d5ab33 96 (MPU_RLAR_EN_Msk))
be_bryan 0:b74591d5ab33 97
be_bryan 0:b74591d5ab33 98 /**
be_bryan 0:b74591d5ab33 99 * Struct for a single MPU Region
be_bryan 0:b74591d5ab33 100 */
be_bryan 0:b74591d5ab33 101 typedef struct _ARM_MPU_Region_t {
be_bryan 0:b74591d5ab33 102 uint32_t RBAR; /*!< Region Base Address Register value */
be_bryan 0:b74591d5ab33 103 uint32_t RLAR; /*!< Region Limit Address Register value */
be_bryan 0:b74591d5ab33 104 } ARM_MPU_Region_t;
be_bryan 0:b74591d5ab33 105
be_bryan 0:b74591d5ab33 106 /** Enable the MPU.
be_bryan 0:b74591d5ab33 107 * \param MPU_Control Default access permissions for unconfigured regions.
be_bryan 0:b74591d5ab33 108 */
be_bryan 0:b74591d5ab33 109 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
be_bryan 0:b74591d5ab33 110 {
be_bryan 0:b74591d5ab33 111 __DSB();
be_bryan 0:b74591d5ab33 112 __ISB();
be_bryan 0:b74591d5ab33 113 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
be_bryan 0:b74591d5ab33 114 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
be_bryan 0:b74591d5ab33 115 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
be_bryan 0:b74591d5ab33 116 #endif
be_bryan 0:b74591d5ab33 117 }
be_bryan 0:b74591d5ab33 118
be_bryan 0:b74591d5ab33 119 /** Disable the MPU.
be_bryan 0:b74591d5ab33 120 */
be_bryan 0:b74591d5ab33 121 __STATIC_INLINE void ARM_MPU_Disable(void)
be_bryan 0:b74591d5ab33 122 {
be_bryan 0:b74591d5ab33 123 __DSB();
be_bryan 0:b74591d5ab33 124 __ISB();
be_bryan 0:b74591d5ab33 125 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
be_bryan 0:b74591d5ab33 126 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
be_bryan 0:b74591d5ab33 127 #endif
be_bryan 0:b74591d5ab33 128 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
be_bryan 0:b74591d5ab33 129 }
be_bryan 0:b74591d5ab33 130
be_bryan 0:b74591d5ab33 131 #ifdef MPU_NS
be_bryan 0:b74591d5ab33 132 /** Enable the Non-secure MPU.
be_bryan 0:b74591d5ab33 133 * \param MPU_Control Default access permissions for unconfigured regions.
be_bryan 0:b74591d5ab33 134 */
be_bryan 0:b74591d5ab33 135 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
be_bryan 0:b74591d5ab33 136 {
be_bryan 0:b74591d5ab33 137 __DSB();
be_bryan 0:b74591d5ab33 138 __ISB();
be_bryan 0:b74591d5ab33 139 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
be_bryan 0:b74591d5ab33 140 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
be_bryan 0:b74591d5ab33 141 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
be_bryan 0:b74591d5ab33 142 #endif
be_bryan 0:b74591d5ab33 143 }
be_bryan 0:b74591d5ab33 144
be_bryan 0:b74591d5ab33 145 /** Disable the Non-secure MPU.
be_bryan 0:b74591d5ab33 146 */
be_bryan 0:b74591d5ab33 147 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
be_bryan 0:b74591d5ab33 148 {
be_bryan 0:b74591d5ab33 149 __DSB();
be_bryan 0:b74591d5ab33 150 __ISB();
be_bryan 0:b74591d5ab33 151 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
be_bryan 0:b74591d5ab33 152 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
be_bryan 0:b74591d5ab33 153 #endif
be_bryan 0:b74591d5ab33 154 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
be_bryan 0:b74591d5ab33 155 }
be_bryan 0:b74591d5ab33 156 #endif
be_bryan 0:b74591d5ab33 157
be_bryan 0:b74591d5ab33 158 /** Set the memory attribute encoding to the given MPU.
be_bryan 0:b74591d5ab33 159 * \param mpu Pointer to the MPU to be configured.
be_bryan 0:b74591d5ab33 160 * \param idx The attribute index to be set [0-7]
be_bryan 0:b74591d5ab33 161 * \param attr The attribute value to be set.
be_bryan 0:b74591d5ab33 162 */
be_bryan 0:b74591d5ab33 163 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
be_bryan 0:b74591d5ab33 164 {
be_bryan 0:b74591d5ab33 165 const uint8_t reg = idx / 4U;
be_bryan 0:b74591d5ab33 166 const uint32_t pos = ((idx % 4U) * 8U);
be_bryan 0:b74591d5ab33 167 const uint32_t mask = 0xFFU << pos;
be_bryan 0:b74591d5ab33 168
be_bryan 0:b74591d5ab33 169 if (reg >= (sizeof(MPU->MAIR) / sizeof(MPU->MAIR[0]))) {
be_bryan 0:b74591d5ab33 170 return; // invalid index
be_bryan 0:b74591d5ab33 171 }
be_bryan 0:b74591d5ab33 172
be_bryan 0:b74591d5ab33 173 MPU->MAIR[reg] = ((MPU->MAIR[reg] & ~mask) | ((attr << pos) & mask));
be_bryan 0:b74591d5ab33 174 }
be_bryan 0:b74591d5ab33 175
be_bryan 0:b74591d5ab33 176 /** Set the memory attribute encoding.
be_bryan 0:b74591d5ab33 177 * \param idx The attribute index to be set [0-7]
be_bryan 0:b74591d5ab33 178 * \param attr The attribute value to be set.
be_bryan 0:b74591d5ab33 179 */
be_bryan 0:b74591d5ab33 180 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
be_bryan 0:b74591d5ab33 181 {
be_bryan 0:b74591d5ab33 182 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
be_bryan 0:b74591d5ab33 183 }
be_bryan 0:b74591d5ab33 184
be_bryan 0:b74591d5ab33 185 #ifdef MPU_NS
be_bryan 0:b74591d5ab33 186 /** Set the memory attribute encoding to the Non-secure MPU.
be_bryan 0:b74591d5ab33 187 * \param idx The attribute index to be set [0-7]
be_bryan 0:b74591d5ab33 188 * \param attr The attribute value to be set.
be_bryan 0:b74591d5ab33 189 */
be_bryan 0:b74591d5ab33 190 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
be_bryan 0:b74591d5ab33 191 {
be_bryan 0:b74591d5ab33 192 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
be_bryan 0:b74591d5ab33 193 }
be_bryan 0:b74591d5ab33 194 #endif
be_bryan 0:b74591d5ab33 195
be_bryan 0:b74591d5ab33 196 /** Clear and disable the given MPU region of the given MPU.
be_bryan 0:b74591d5ab33 197 * \param mpu Pointer to MPU to be used.
be_bryan 0:b74591d5ab33 198 * \param rnr Region number to be cleared.
be_bryan 0:b74591d5ab33 199 */
be_bryan 0:b74591d5ab33 200 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
be_bryan 0:b74591d5ab33 201 {
be_bryan 0:b74591d5ab33 202 MPU->RNR = rnr;
be_bryan 0:b74591d5ab33 203 MPU->RLAR = 0U;
be_bryan 0:b74591d5ab33 204 }
be_bryan 0:b74591d5ab33 205
be_bryan 0:b74591d5ab33 206 /** Clear and disable the given MPU region.
be_bryan 0:b74591d5ab33 207 * \param rnr Region number to be cleared.
be_bryan 0:b74591d5ab33 208 */
be_bryan 0:b74591d5ab33 209 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
be_bryan 0:b74591d5ab33 210 {
be_bryan 0:b74591d5ab33 211 ARM_MPU_ClrRegionEx(MPU, rnr);
be_bryan 0:b74591d5ab33 212 }
be_bryan 0:b74591d5ab33 213
be_bryan 0:b74591d5ab33 214 #ifdef MPU_NS
be_bryan 0:b74591d5ab33 215 /** Clear and disable the given Non-secure MPU region.
be_bryan 0:b74591d5ab33 216 * \param rnr Region number to be cleared.
be_bryan 0:b74591d5ab33 217 */
be_bryan 0:b74591d5ab33 218 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
be_bryan 0:b74591d5ab33 219 {
be_bryan 0:b74591d5ab33 220 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
be_bryan 0:b74591d5ab33 221 }
be_bryan 0:b74591d5ab33 222 #endif
be_bryan 0:b74591d5ab33 223
be_bryan 0:b74591d5ab33 224 /** Configure the given MPU region of the given MPU.
be_bryan 0:b74591d5ab33 225 * \param mpu Pointer to MPU to be used.
be_bryan 0:b74591d5ab33 226 * \param rnr Region number to be configured.
be_bryan 0:b74591d5ab33 227 * \param rbar Value for RBAR register.
be_bryan 0:b74591d5ab33 228 * \param rlar Value for RLAR register.
be_bryan 0:b74591d5ab33 229 */
be_bryan 0:b74591d5ab33 230 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
be_bryan 0:b74591d5ab33 231 {
be_bryan 0:b74591d5ab33 232 MPU->RNR = rnr;
be_bryan 0:b74591d5ab33 233 MPU->RBAR = rbar;
be_bryan 0:b74591d5ab33 234 MPU->RLAR = rlar;
be_bryan 0:b74591d5ab33 235 }
be_bryan 0:b74591d5ab33 236
be_bryan 0:b74591d5ab33 237 /** Configure the given MPU region.
be_bryan 0:b74591d5ab33 238 * \param rnr Region number to be configured.
be_bryan 0:b74591d5ab33 239 * \param rbar Value for RBAR register.
be_bryan 0:b74591d5ab33 240 * \param rlar Value for RLAR register.
be_bryan 0:b74591d5ab33 241 */
be_bryan 0:b74591d5ab33 242 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
be_bryan 0:b74591d5ab33 243 {
be_bryan 0:b74591d5ab33 244 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
be_bryan 0:b74591d5ab33 245 }
be_bryan 0:b74591d5ab33 246
be_bryan 0:b74591d5ab33 247 #ifdef MPU_NS
be_bryan 0:b74591d5ab33 248 /** Configure the given Non-secure MPU region.
be_bryan 0:b74591d5ab33 249 * \param rnr Region number to be configured.
be_bryan 0:b74591d5ab33 250 * \param rbar Value for RBAR register.
be_bryan 0:b74591d5ab33 251 * \param rlar Value for RLAR register.
be_bryan 0:b74591d5ab33 252 */
be_bryan 0:b74591d5ab33 253 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
be_bryan 0:b74591d5ab33 254 {
be_bryan 0:b74591d5ab33 255 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
be_bryan 0:b74591d5ab33 256 }
be_bryan 0:b74591d5ab33 257 #endif
be_bryan 0:b74591d5ab33 258
be_bryan 0:b74591d5ab33 259 /** Memcopy with strictly ordered memory access, e.g. for register targets.
be_bryan 0:b74591d5ab33 260 * \param dst Destination data is copied to.
be_bryan 0:b74591d5ab33 261 * \param src Source data is copied from.
be_bryan 0:b74591d5ab33 262 * \param len Amount of data words to be copied.
be_bryan 0:b74591d5ab33 263 */
be_bryan 0:b74591d5ab33 264 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
be_bryan 0:b74591d5ab33 265 {
be_bryan 0:b74591d5ab33 266 uint32_t i;
be_bryan 0:b74591d5ab33 267 for (i = 0U; i < len; ++i)
be_bryan 0:b74591d5ab33 268 {
be_bryan 0:b74591d5ab33 269 dst[i] = src[i];
be_bryan 0:b74591d5ab33 270 }
be_bryan 0:b74591d5ab33 271 }
be_bryan 0:b74591d5ab33 272
be_bryan 0:b74591d5ab33 273 /** Load the given number of MPU regions from a table to the given MPU.
be_bryan 0:b74591d5ab33 274 * \param mpu Pointer to the MPU registers to be used.
be_bryan 0:b74591d5ab33 275 * \param rnr First region number to be configured.
be_bryan 0:b74591d5ab33 276 * \param table Pointer to the MPU configuration table.
be_bryan 0:b74591d5ab33 277 * \param cnt Amount of regions to be configured.
be_bryan 0:b74591d5ab33 278 */
be_bryan 0:b74591d5ab33 279 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
be_bryan 0:b74591d5ab33 280 {
be_bryan 0:b74591d5ab33 281 static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
be_bryan 0:b74591d5ab33 282 if (cnt == 1U) {
be_bryan 0:b74591d5ab33 283 mpu->RNR = rnr;
be_bryan 0:b74591d5ab33 284 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
be_bryan 0:b74591d5ab33 285 } else {
be_bryan 0:b74591d5ab33 286 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
be_bryan 0:b74591d5ab33 287 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
be_bryan 0:b74591d5ab33 288
be_bryan 0:b74591d5ab33 289 mpu->RNR = rnrBase;
be_bryan 0:b74591d5ab33 290 if ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
be_bryan 0:b74591d5ab33 291 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
be_bryan 0:b74591d5ab33 292 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
be_bryan 0:b74591d5ab33 293 ARM_MPU_LoadEx(mpu, rnr + c, table + c, cnt - c);
be_bryan 0:b74591d5ab33 294 } else {
be_bryan 0:b74591d5ab33 295 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
be_bryan 0:b74591d5ab33 296 }
be_bryan 0:b74591d5ab33 297 }
be_bryan 0:b74591d5ab33 298 }
be_bryan 0:b74591d5ab33 299
be_bryan 0:b74591d5ab33 300 /** Load the given number of MPU regions from a table.
be_bryan 0:b74591d5ab33 301 * \param rnr First region number to be configured.
be_bryan 0:b74591d5ab33 302 * \param table Pointer to the MPU configuration table.
be_bryan 0:b74591d5ab33 303 * \param cnt Amount of regions to be configured.
be_bryan 0:b74591d5ab33 304 */
be_bryan 0:b74591d5ab33 305 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
be_bryan 0:b74591d5ab33 306 {
be_bryan 0:b74591d5ab33 307 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
be_bryan 0:b74591d5ab33 308 }
be_bryan 0:b74591d5ab33 309
be_bryan 0:b74591d5ab33 310 #ifdef MPU_NS
be_bryan 0:b74591d5ab33 311 /** Load the given number of MPU regions from a table to the Non-secure MPU.
be_bryan 0:b74591d5ab33 312 * \param rnr First region number to be configured.
be_bryan 0:b74591d5ab33 313 * \param table Pointer to the MPU configuration table.
be_bryan 0:b74591d5ab33 314 * \param cnt Amount of regions to be configured.
be_bryan 0:b74591d5ab33 315 */
be_bryan 0:b74591d5ab33 316 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
be_bryan 0:b74591d5ab33 317 {
be_bryan 0:b74591d5ab33 318 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
be_bryan 0:b74591d5ab33 319 }
be_bryan 0:b74591d5ab33 320 #endif
be_bryan 0:b74591d5ab33 321
be_bryan 0:b74591d5ab33 322 #endif
be_bryan 0:b74591d5ab33 323