nmuart.c

00001 /**
00002  *
00003  * \file
00004  *
00005  * \brief This module contains NMC1000 UART protocol bus APIs implementation.
00006  *
00007  * Copyright (c) 2016 Atmel Corporation. All rights reserved.
00008  *
00009  * \asf_license_start
00010  *
00011  * \page License
00012  *
00013  * Redistribution and use in source and binary forms, with or without
00014  * modification, are permitted provided that the following conditions are met:
00015  *
00016  * 1. Redistributions of source code must retain the above copyright notice,
00017  *    this list of conditions and the following disclaimer.
00018  *
00019  * 2. Redistributions in binary form must reproduce the above copyright notice,
00020  *    this list of conditions and the following disclaimer in the documentation
00021  *    and/or other materials provided with the distribution.
00022  *
00023  * 3. The name of Atmel may not be used to endorse or promote products derived
00024  *    from this software without specific prior written permission.
00025  *
00026  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
00027  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00028  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00029  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
00030  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00032  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00033  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
00034  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
00035  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00036  * POSSIBILITY OF SUCH DAMAGE.
00037  *
00038  * \asf_license_stop
00039  *
00040  */
00041 
00042 #include "common/include/nm_common.h"
00043 
00044 #ifdef CONF_WINC_USE_UART
00045 
00046 #include "driver/source/nmuart.h"
00047 #include "bus_wrapper/include/nm_bus_wrapper.h"
00048 
00049 #define HDR_SZ  12
00050 
00051 static uint8 get_cs(uint8* b, uint8 sz){
00052     int i;
00053     uint8 cs = 0;
00054     for(i = 0; i < sz; i++)
00055         cs ^= b[i];
00056     return cs;
00057 }
00058 
00059 /*
00060 *   @fn         nm_uart_sync_cmd
00061 *   @brief      Check COM Port
00062 *   @return     M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
00063 *   @author     Dina El Sissy
00064 *   @date       13 AUG 2012
00065 *   @version    1.0
00066 */
00067 sint8 nm_uart_sync_cmd (void)
00068 {
00069     tstrNmUartDefault strUart;
00070     sint8 s8Ret = -1;
00071     uint8 b [HDR_SZ+1];
00072     uint8 rsz;
00073     uint8 onchip = 0;
00074 
00075     /*read reg*/
00076     b[0] = 0x12;
00077 
00078     rsz = 1;
00079     strUart.pu8Buf  = b;
00080     strUart.u16Sz  = 1;
00081 
00082     if(M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
00083     {
00084         strUart.u16Sz  = rsz;
00085         if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00086         {
00087             s8Ret = M2M_ERR_BUS_FAIL;
00088         }
00089     }
00090     else
00091     {
00092         M2M_ERR("failed to send cfg bytes\n");
00093         s8Ret = M2M_ERR_BUS_FAIL;
00094     }
00095     if (b[0] == 0x5a)
00096     {
00097         s8Ret = 0;
00098         onchip = 1;
00099         M2M_INFO("Built-in WINC1500 UART Found\n");
00100     }
00101     else if(b[0] == 0x5b)
00102     {
00103         s8Ret = 0;
00104         onchip = 0;
00105         M2M_INFO("WINC1500 Serial Bridge Found\n");
00106     }
00107     /*TODO: this should be the way we read the register since the cortus is little endian*/
00108     /**pu32RetVal = b[0] | ((uint32)b[1] << 8) | ((uint32)b[2] << 16) | ((uint32)b[3] << 24);*/
00109     if(s8Ret == M2M_SUCCESS)
00110         s8Ret = (sint8)onchip;
00111     return s8Ret;
00112 }
00113  sint8 nm_uart_read_reg_with_ret (uint32 u32Addr, uint32* pu32RetVal)
00114 {
00115     tstrNmUartDefault strUart;
00116     sint8 s8Ret = M2M_SUCCESS;
00117     uint8 b [HDR_SZ+1];
00118     uint8 rsz;
00119 
00120     /*read reg*/
00121     b[0] = 0xa5;
00122     b[1] = 0;
00123     b[2] = 0;
00124     b[3] = 0;
00125     b[4] = 0;
00126     b[5] = (uint8)(u32Addr & 0x000000ff);
00127     b[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
00128     b[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
00129     b[8] = (uint8)((u32Addr & 0xff000000)>>24);
00130     b[9] = 0;
00131     b[10] = 0;
00132     b[11] = 0;
00133     b[12] = 0;
00134 
00135     b[2] = get_cs(&b[1],HDR_SZ);
00136 
00137     rsz = 4;
00138     strUart.pu8Buf  = b;
00139     strUart.u16Sz  = sizeof(b);
00140 
00141     if(M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
00142     {
00143         if(!nm_bus_get_chip_type())
00144         {
00145             strUart.u16Sz  = 1;
00146             if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00147             {
00148                 s8Ret = M2M_ERR_BUS_FAIL;
00149             }
00150             if(b[0] == 0xAC)
00151             {
00152                 M2M_DBG("Successfully sent the command\n");
00153                 strUart.u16Sz  = rsz;
00154                 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00155                 {
00156                     s8Ret = M2M_ERR_BUS_FAIL;
00157                 }
00158             }
00159             else
00160             {
00161                 s8Ret = M2M_ERR_BUS_FAIL;
00162             }
00163         }
00164         else
00165         {
00166             strUart.u16Sz  = rsz;
00167             if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00168             {
00169                 s8Ret = M2M_ERR_BUS_FAIL;
00170             }
00171         }
00172     }
00173     else
00174     {
00175         M2M_ERR("failed to send cfg bytes\n");
00176         s8Ret = M2M_ERR_BUS_FAIL;
00177     }
00178     /*TODO: this should be the way we read the register since the cortus is little endian*/
00179     /**pu32RetVal = b[0] | ((uint32)b[1] << 8) | ((uint32)b[2] << 16) | ((uint32)b[3] << 24);*/
00180 
00181     *pu32RetVal = ((uint32)b[0] << 24) | ((uint32)b[1] << 16) | ((uint32)b[2] << 8) | b[3];
00182 
00183     return s8Ret;
00184 }
00185 
00186 /*
00187 *   @fn         nm_uart_read_reg
00188 *   @brief      Read register
00189 *   @param [in] u32Addr
00190 *               Register address
00191 *   @return     Register value
00192 *   @author     Dina El Sissy
00193 *   @date       13 AUG 2012
00194 *   @version    1.0
00195 */
00196 uint32 nm_uart_read_reg(uint32 u32Addr)
00197 {
00198     uint32 val;
00199     nm_uart_read_reg_with_ret (u32Addr , &val);
00200     return val;
00201 }
00202 
00203 /*
00204 *   @fn         nm_uart_write_reg
00205 *   @brief      write register
00206 *   @param [in] u32Addr
00207 *               Register address
00208 *   @param [in] u32Val
00209 *               Value to be written to the register
00210 *   @return     M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
00211 *   @author     Dina El Sissy
00212 *   @date       13 AUG 2012
00213 *   @version    1.0
00214 */
00215 sint8 nm_uart_write_reg(uint32 u32Addr, uint32 u32Val)
00216 {
00217     tstrNmUartDefault strUart;
00218     sint8 s8Ret = M2M_SUCCESS;
00219     uint8 b[HDR_SZ+1];
00220 
00221     /*write reg*/
00222     b[0] = 0xa5;
00223     b[1] = 1;
00224     b[2] = 0;
00225     b[3] = 0;
00226     b[4] = 0;
00227     b[5] = (uint8)(u32Addr & 0x000000ff);
00228     b[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
00229     b[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
00230     b[8] = (uint8)((u32Addr & 0xff000000)>>24);
00231     b[9] = (uint8)(u32Val & 0x000000ff);
00232     b[10] = (uint8)((u32Val & 0x0000ff00)>>8);
00233     b[11] = (uint8)((u32Val & 0x00ff0000)>>16);
00234     b[12] = (uint8)((u32Val & 0xff000000)>>24);
00235 
00236     b[2] = get_cs(&b[1],HDR_SZ);
00237 
00238     get_cs(&b[1],HDR_SZ);
00239 
00240     strUart.pu8Buf  = b;
00241     strUart.u16Sz  = sizeof(b);
00242 
00243     if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
00244     {
00245         M2M_ERR("write error\n");
00246         s8Ret = M2M_ERR_BUS_FAIL;
00247     }
00248     else
00249     {
00250         if(!nm_bus_get_chip_type())
00251         {
00252             //check for the ack from the SAMD21 for the packet reception.
00253             strUart.u16Sz  = 1;
00254             if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00255             {
00256                 s8Ret = M2M_ERR_BUS_FAIL;
00257             }
00258             if(b[0] == 0xAC)
00259             {
00260                 M2M_DBG("Successfully sent the reg write command\n");
00261             }
00262             else
00263             {
00264                 M2M_ERR("write error\n");
00265                 s8Ret = M2M_ERR_BUS_FAIL;
00266             }
00267         }
00268     }
00269 
00270     return s8Ret;
00271 }
00272 
00273 
00274 /**
00275 *   @fn         nm_uart_read_block
00276 *   @brief      Read block of data
00277 *   @param [in] u32Addr
00278 *               Start address
00279 *   @param [out]    puBuf
00280 *               Pointer to a buffer used to return the read data
00281 *   @param [in] u16Sz
00282 *               Number of bytes to read. The buffer size must be >= u16Sz
00283 *   @return     M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
00284 *   @author     Dina El Sissy
00285 *   @date       13 AUG 2012
00286 *   @version    1.0
00287 */
00288 sint8 nm_uart_read_block(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz)
00289 {
00290     tstrNmUartDefault strUart;
00291     sint8 s8Ret = M2M_SUCCESS;
00292     uint8 au8Buf[HDR_SZ+1];
00293 
00294     au8Buf[0] = 0xa5;
00295     au8Buf[1] = 2;
00296     au8Buf[2] = 0;
00297     au8Buf[3] = (uint8)(u16Sz & 0x00ff);
00298     au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8);
00299     au8Buf[5] = (uint8)(u32Addr & 0x000000ff);
00300     au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
00301     au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
00302     au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24);
00303     au8Buf[9] = 0;
00304     au8Buf[10] = 0;
00305     au8Buf[11] = 0;
00306     au8Buf[12] = 0;
00307 
00308     au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ);
00309 
00310     strUart.pu8Buf  = au8Buf;
00311     strUart.u16Sz  = sizeof(au8Buf);
00312 
00313     if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
00314     {
00315         M2M_ERR("write error\n");
00316         s8Ret = M2M_ERR_BUS_FAIL;
00317     }
00318     else
00319     {
00320         if(!nm_bus_get_chip_type())
00321         {
00322             //check for the ack from the SAMD21 for the packet reception.
00323             strUart.u16Sz  = 1;
00324             if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00325             {
00326                 s8Ret = M2M_ERR_BUS_FAIL;
00327             }
00328             if(au8Buf[0] == 0xAC)
00329             {
00330                 M2M_DBG("Successfully sent the block read command\n");
00331                 strUart.pu8Buf  = pu8Buf;
00332                 strUart.u16Sz  = u16Sz;
00333 
00334                 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00335                 {
00336                     M2M_ERR("read error\n");
00337                     s8Ret = M2M_ERR_BUS_FAIL;
00338                 }
00339             }
00340             else
00341             {
00342                 M2M_ERR("write error (Error sending the block read command)\n");
00343                 s8Ret = M2M_ERR_BUS_FAIL;
00344             }
00345         }
00346         else
00347         {
00348             strUart.pu8Buf  = pu8Buf;
00349             strUart.u16Sz  = u16Sz;
00350 
00351             if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00352             {
00353                 M2M_ERR("read error\n");
00354                 s8Ret = M2M_ERR_BUS_FAIL;
00355             }
00356         }
00357     }
00358 
00359     return s8Ret;
00360 }
00361 
00362 /**
00363 *   @fn         nm_uart_write_block
00364 *   @brief      Write block of data
00365 *   @param [in] u32Addr
00366 *               Start address
00367 *   @param [in] puBuf
00368 *               Pointer to the buffer holding the data to be written
00369 *   @param [in] u16Sz
00370 *               Number of bytes to write. The buffer size must be >= u16Sz
00371 *   @return     M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
00372 *   @author     Dina El Sissy
00373 *   @date       13 AUG 2012
00374 *   @version    1.0
00375 */
00376 sint8 nm_uart_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
00377 {
00378     tstrNmUartDefault strUart;
00379     sint8 s8Ret = M2M_SUCCESS;
00380     static uint8 au8Buf[HDR_SZ+1];
00381 
00382     au8Buf[0] = 0xa5;
00383     au8Buf[1] = 3;
00384     au8Buf[2] = 0;
00385     au8Buf[3] = (uint8)(u16Sz & 0x00ff);
00386     au8Buf[4] = (uint8)((u16Sz & 0xff00)>>8);
00387     au8Buf[5] = (uint8)(u32Addr & 0x000000ff);
00388     au8Buf[6] = (uint8)((u32Addr & 0x0000ff00)>>8);
00389     au8Buf[7] = (uint8)((u32Addr & 0x00ff0000)>>16);
00390     au8Buf[8] = (uint8)((u32Addr & 0xff000000)>>24);
00391     au8Buf[9] = 0;
00392     au8Buf[10] = 0;
00393     au8Buf[11] = 0;
00394     au8Buf[12] = 0;
00395 
00396     au8Buf[2] = get_cs(&au8Buf[1],HDR_SZ);
00397 
00398     strUart.pu8Buf  = au8Buf;
00399     strUart.u16Sz  = sizeof(au8Buf);
00400 
00401     if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
00402     {
00403         M2M_ERR("write error\n");
00404         s8Ret = M2M_ERR_BUS_FAIL;
00405     }
00406     else
00407     {
00408         if(!nm_bus_get_chip_type())
00409         {
00410             //check for the ack from the SAMD21 for the packet reception.
00411             strUart.u16Sz  = 1;
00412             if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00413             {
00414                 s8Ret = M2M_ERR_BUS_FAIL;
00415             }
00416             if(au8Buf[0] == 0xAC)
00417             {
00418                 M2M_DBG("Successfully sent the block Write command\n");
00419                 strUart.pu8Buf  = puBuf;
00420                 strUart.u16Sz  = u16Sz;
00421 
00422                 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
00423                 {
00424                     M2M_ERR("write error\n");
00425                     s8Ret = M2M_ERR_BUS_FAIL;
00426                 }
00427                 else
00428                 {
00429                     //check for the ack from the SAMD21 for the payload reception.
00430                     strUart.pu8Buf  = au8Buf;
00431                     strUart.u16Sz  = 1;
00432                     if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00433                     {
00434                         s8Ret = M2M_ERR_BUS_FAIL;
00435                     }
00436                     if(au8Buf[0] == 0xAC)
00437                     {
00438                         M2M_DBG("Successfully sent the data payload\n");
00439                     }
00440                     else
00441                     {
00442                         M2M_ERR("write error\n");
00443                         s8Ret = M2M_ERR_BUS_FAIL;
00444                     }
00445                 }
00446             }
00447             else
00448             {
00449                 M2M_ERR("write error (Error sending the block write command)\n");
00450                 s8Ret = M2M_ERR_BUS_FAIL;
00451             }
00452         }
00453         else
00454         {
00455             strUart.pu8Buf  = puBuf;
00456             strUart.u16Sz  = u16Sz;
00457 
00458             if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
00459             {
00460                 M2M_ERR("write error\n");
00461                 s8Ret = M2M_ERR_BUS_FAIL;
00462             }
00463         }
00464     }
00465     return s8Ret;
00466 }
00467 
00468 /**
00469 *   @fn         nm_uart_reconfigure
00470 *   @brief      Reconfigures the UART interface
00471 *   @param [in] ptr
00472 *               Pointer to a DWORD containing baudrate at this moment.
00473 *   @return     M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
00474 *   @author     Viswanathan Murugesan
00475 *   @date       22 OCT 2014
00476 *   @version    1.0
00477 */
00478 sint8 nm_uart_reconfigure(void *ptr)
00479 {
00480     tstrNmUartDefault strUart;
00481     sint8 s8Ret = M2M_SUCCESS;
00482     uint8 b[HDR_SZ+1];
00483 
00484     /*write reg*/
00485     b[0] = 0xa5;
00486     b[1] = 5;
00487     b[2] = 0;
00488     b[3] = 0;
00489     b[4] = 0;
00490     b[5] = 0;
00491     b[6] = 0;
00492     b[7] = 0;
00493     b[8] = 0;
00494     b[9] = (uint8)((*(unsigned long *)ptr) & 0x000000ff);
00495     b[10] = (uint8)(((*(unsigned long *)ptr) & 0x0000ff00)>>8);
00496     b[11] = (uint8)(((*(unsigned long *)ptr) & 0x00ff0000)>>16);
00497     b[12] = (uint8)(((*(unsigned long *)ptr) & 0xff000000)>>24);
00498 
00499     b[2] = get_cs(&b[1],HDR_SZ);
00500 
00501     get_cs(&b[1],HDR_SZ);
00502 
00503     strUart.pu8Buf  = b;
00504     strUart.u16Sz  = sizeof(b);
00505 
00506     if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strUart))
00507     {
00508         M2M_ERR("write error\n");
00509         s8Ret = M2M_ERR_BUS_FAIL;
00510     }
00511     else
00512     {
00513         if(!nm_bus_get_chip_type())
00514         {
00515             //check for the ack from the SAMD21 for the packet reception.
00516             strUart.u16Sz  = 1;
00517             if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strUart))
00518             {
00519                 s8Ret = M2M_ERR_BUS_FAIL;
00520             }
00521             if(b[0] == 0xAC)
00522             {
00523                 M2M_DBG("Successfully sent the UART reconfigure command\n");
00524             }
00525             else
00526             {
00527                 M2M_ERR("write error\n");
00528                 s8Ret = M2M_ERR_BUS_FAIL;
00529             }
00530         }
00531     }
00532 
00533     return s8Ret;
00534 }
00535 #endif
00536 /* EOF */
00537