nmspi.c

00001 /**
00002  *
00003  * \file
00004  *
00005  * \brief This module contains NMC1000 SPI protocol bus APIs implementation.
00006  *
00007  * Copyright (c) 2016-2017 Atmel Corporation. All rights reserved.
00008  *
00009  * \asf_license_start
00010  *
00011  * \page License
00012  *
00013  * Redistribution and use in source and binary forms, with or without
00014  * modification, are permitted provided that the following conditions are met:
00015  *
00016  * 1. Redistributions of source code must retain the above copyright notice,
00017  *    this list of conditions and the following disclaimer.
00018  *
00019  * 2. Redistributions in binary form must reproduce the above copyright notice,
00020  *    this list of conditions and the following disclaimer in the documentation
00021  *    and/or other materials provided with the distribution.
00022  *
00023  * 3. The name of Atmel may not be used to endorse or promote products derived
00024  *    from this software without specific prior written permission.
00025  *
00026  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
00027  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00028  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00029  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
00030  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00032  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00033  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
00034  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
00035  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00036  * POSSIBILITY OF SUCH DAMAGE.
00037  *
00038  * \asf_license_stop
00039  *
00040  */
00041 #include "common/include/nm_common.h"
00042 
00043 #ifdef CONF_WINC_USE_SPI
00044 
00045 #define USE_OLD_SPI_SW
00046 
00047 #include "bus_wrapper/include/nm_bus_wrapper.h"
00048 #include "nmspi.h"
00049 
00050 #define NMI_PERIPH_REG_BASE 0x1000
00051 #define NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE+0xa00)
00052 #define NMI_CHIPID  (NMI_PERIPH_REG_BASE)
00053 #define NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408)
00054 #define NMI_INTR_ENABLE (NMI_INTR_REG_BASE)
00055 
00056 #define NMI_SPI_REG_BASE 0xe800
00057 #define NMI_SPI_CTL (NMI_SPI_REG_BASE)
00058 #define NMI_SPI_MASTER_DMA_ADDR (NMI_SPI_REG_BASE+0x4)
00059 #define NMI_SPI_MASTER_DMA_COUNT (NMI_SPI_REG_BASE+0x8)
00060 #define NMI_SPI_SLAVE_DMA_ADDR (NMI_SPI_REG_BASE+0xc)
00061 #define NMI_SPI_SLAVE_DMA_COUNT (NMI_SPI_REG_BASE+0x10)
00062 #define NMI_SPI_TX_MODE (NMI_SPI_REG_BASE+0x20)
00063 #define NMI_SPI_PROTOCOL_CONFIG (NMI_SPI_REG_BASE+0x24)
00064 #define NMI_SPI_INTR_CTL (NMI_SPI_REG_BASE+0x2c)
00065 #define NMI_SPI_MISC_CTRL (NMI_SPI_REG_BASE+0x48)
00066 
00067 #define NMI_SPI_PROTOCOL_OFFSET (NMI_SPI_PROTOCOL_CONFIG-NMI_SPI_REG_BASE)
00068 
00069 #define SPI_BASE                NMI_SPI_REG_BASE
00070 
00071 #define CMD_DMA_WRITE           0xc1
00072 #define CMD_DMA_READ            0xc2
00073 #define CMD_INTERNAL_WRITE      0xc3
00074 #define CMD_INTERNAL_READ       0xc4
00075 #define CMD_TERMINATE           0xc5
00076 #define CMD_REPEAT              0xc6
00077 #define CMD_DMA_EXT_WRITE       0xc7
00078 #define CMD_DMA_EXT_READ        0xc8
00079 #define CMD_SINGLE_WRITE        0xc9
00080 #define CMD_SINGLE_READ         0xca
00081 #define CMD_RESET               0xcf
00082 
00083 #define N_OK                     1
00084 #define N_FAIL                   0
00085 #define N_RESET                 -1
00086 #define N_RETRY                 -2
00087 
00088 #define SPI_RESP_RETRY_COUNT    (10)
00089 #define SPI_RETRY_COUNT         (10)
00090 #define DATA_PKT_SZ_256         256
00091 #define DATA_PKT_SZ_512         512
00092 #define DATA_PKT_SZ_1K          1024
00093 #define DATA_PKT_SZ_4K          (4 * 1024)
00094 #define DATA_PKT_SZ_8K          (8 * 1024)
00095 #define DATA_PKT_SZ             DATA_PKT_SZ_8K
00096 
00097 static uint8    gu8Crc_off  =   0;
00098 
00099 static sint8 nmi_spi_read(uint8* b, uint16 sz)
00100 {
00101     tstrNmSpiRw spi;
00102     spi.pu8InBuf  = NULL;
00103     spi.pu8OutBuf  = b;
00104     spi.u16Sz  = sz;
00105     return nm_bus_ioctl(NM_BUS_IOCTL_RW, &spi);
00106 }
00107 
00108 static sint8 nmi_spi_write(uint8* b, uint16 sz)
00109 {
00110     tstrNmSpiRw spi;
00111     spi.pu8InBuf  = b;
00112     spi.pu8OutBuf  = NULL;
00113     spi.u16Sz  = sz;
00114     return nm_bus_ioctl(NM_BUS_IOCTL_RW, &spi);
00115 }
00116 #ifndef USE_OLD_SPI_SW
00117 static sint8 nmi_spi_rw(uint8 *bin,uint8* bout,uint16 sz)
00118 {
00119     tstrNmSpiRw spi;
00120     spi.pu8InBuf  = bin;
00121     spi.pu8OutBuf  = bout;
00122     spi.u16Sz  = sz;
00123     return nm_bus_ioctl(NM_BUS_IOCTL_RW, &spi); 
00124 }
00125 #endif
00126 /********************************************
00127 
00128     Crc7
00129 
00130 ********************************************/
00131 
00132 static const uint8 crc7_syndrome_table[256] = {
00133     0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
00134     0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
00135     0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
00136     0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
00137     0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
00138     0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
00139     0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
00140     0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
00141     0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
00142     0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
00143     0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
00144     0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
00145     0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
00146     0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
00147     0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
00148     0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
00149     0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
00150     0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
00151     0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
00152     0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
00153     0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
00154     0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
00155     0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
00156     0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
00157     0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
00158     0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
00159     0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
00160     0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
00161     0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
00162     0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
00163     0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
00164     0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
00165 };
00166 
00167 
00168 static uint8 crc7_byte(uint8 crc, uint8 data)
00169 {
00170     return crc7_syndrome_table[(crc << 1) ^ data];
00171 }
00172 
00173 static uint8 crc7(uint8 crc, const uint8 *buffer, uint32 len)
00174 {
00175     while (len--)
00176         crc = crc7_byte(crc, *buffer++);
00177     return crc;
00178 }
00179 
00180 /********************************************
00181 
00182     Spi protocol Function
00183 
00184 ********************************************/
00185 
00186 #define CMD_DMA_WRITE           0xc1
00187 #define CMD_DMA_READ            0xc2
00188 #define CMD_INTERNAL_WRITE      0xc3
00189 #define CMD_INTERNAL_READ       0xc4
00190 #define CMD_TERMINATE           0xc5
00191 #define CMD_REPEAT              0xc6
00192 #define CMD_DMA_EXT_WRITE       0xc7
00193 #define CMD_DMA_EXT_READ        0xc8
00194 #define CMD_SINGLE_WRITE        0xc9
00195 #define CMD_SINGLE_READ         0xca
00196 #define CMD_RESET               0xcf
00197 
00198 #define DATA_PKT_SZ_256         256
00199 #define DATA_PKT_SZ_512         512
00200 #define DATA_PKT_SZ_1K          1024
00201 #define DATA_PKT_SZ_4K          (4 * 1024)
00202 #define DATA_PKT_SZ_8K          (8 * 1024)
00203 #define DATA_PKT_SZ             DATA_PKT_SZ_8K
00204 
00205 static sint8 spi_cmd(uint8 cmd, uint32 adr, uint32 u32data, uint32 sz,uint8 clockless)
00206 {
00207     uint8 bc[9];
00208     uint8 len = 5;
00209     sint8 result = N_OK;
00210 
00211     bc[0] = cmd;
00212     switch (cmd) {
00213     case CMD_SINGLE_READ:               /* single word (4 bytes) read */
00214         bc[1] = (uint8)(adr >> 16);
00215         bc[2] = (uint8)(adr >> 8);
00216         bc[3] = (uint8)adr;
00217         len = 5;
00218         break;
00219     case CMD_INTERNAL_READ:         /* internal register read */
00220         bc[1] = (uint8)(adr >> 8);
00221         if(clockless)  bc[1] |= (1 << 7);
00222         bc[2] = (uint8)adr;
00223         bc[3] = 0x00;
00224         len = 5;
00225         break;
00226     case CMD_TERMINATE:                 /* termination */
00227         bc[1] = 0x00;
00228         bc[2] = 0x00;
00229         bc[3] = 0x00;
00230         len = 5;
00231         break;
00232     case CMD_REPEAT:                        /* repeat */
00233         bc[1] = 0x00;
00234         bc[2] = 0x00;
00235         bc[3] = 0x00;
00236         len = 5;
00237         break;
00238     case CMD_RESET:                         /* reset */
00239         bc[1] = 0xff;
00240         bc[2] = 0xff;
00241         bc[3] = 0xff;
00242         len = 5;
00243         break;
00244     case CMD_DMA_WRITE:                 /* dma write */
00245     case CMD_DMA_READ:                  /* dma read */
00246         bc[1] = (uint8)(adr >> 16);
00247         bc[2] = (uint8)(adr >> 8);
00248         bc[3] = (uint8)adr;
00249         bc[4] = (uint8)(sz >> 8);
00250         bc[5] = (uint8)(sz);
00251         len = 7;
00252         break;
00253     case CMD_DMA_EXT_WRITE:     /* dma extended write */
00254     case CMD_DMA_EXT_READ:          /* dma extended read */
00255         bc[1] = (uint8)(adr >> 16);
00256         bc[2] = (uint8)(adr >> 8);
00257         bc[3] = (uint8)adr;
00258         bc[4] = (uint8)(sz >> 16);
00259         bc[5] = (uint8)(sz >> 8);
00260         bc[6] = (uint8)(sz);
00261         len = 8;
00262         break;
00263     case CMD_INTERNAL_WRITE:        /* internal register write */
00264         bc[1] = (uint8)(adr >> 8);
00265         if(clockless)  bc[1] |= (1 << 7);
00266         bc[2] = (uint8)(adr);
00267         bc[3] = (uint8)(u32data >> 24);
00268         bc[4] = (uint8)(u32data >> 16);
00269         bc[5] = (uint8)(u32data >> 8);
00270         bc[6] = (uint8)(u32data);
00271         len = 8;
00272         break;
00273     case CMD_SINGLE_WRITE:          /* single word write */
00274         bc[1] = (uint8)(adr >> 16);
00275         bc[2] = (uint8)(adr >> 8);
00276         bc[3] = (uint8)(adr);
00277         bc[4] = (uint8)(u32data >> 24);
00278         bc[5] = (uint8)(u32data >> 16);
00279         bc[6] = (uint8)(u32data >> 8);
00280         bc[7] = (uint8)(u32data);
00281         len = 9;
00282         break;
00283     default:
00284         result = N_FAIL;
00285         break;
00286     }
00287 
00288     if (result) {
00289         if (!gu8Crc_off)
00290             bc[len-1] = (crc7(0x7f, (const uint8 *)&bc[0], len-1)) << 1;
00291         else
00292             len-=1;
00293 
00294         if (M2M_SUCCESS != nmi_spi_write(bc, len)) {
00295             M2M_ERR("[nmi spi]: Failed cmd write, bus error...\n");
00296             result = N_FAIL;
00297         }
00298     }
00299 
00300     return result;
00301 }
00302 
00303 static sint8 spi_data_rsp(uint8 cmd)
00304 {
00305     uint8 len;
00306     uint8 rsp[3];
00307     sint8 result = N_OK;
00308 
00309     if (!gu8Crc_off)
00310         len = 2;
00311     else
00312         len = 3;
00313 
00314     if (M2M_SUCCESS != nmi_spi_read(&rsp[0], len)) {
00315         M2M_ERR("[nmi spi]: Failed bus error...\n");
00316         result = N_FAIL;
00317         goto _fail_;
00318     }
00319         
00320     if((rsp[len-1] != 0)||(rsp[len-2] != 0xC3))
00321     {
00322         M2M_ERR("[nmi spi]: Failed data response read, %x %x %x\n",rsp[0],rsp[1],rsp[2]);
00323         result = N_FAIL;
00324         goto _fail_;
00325     }
00326 _fail_:
00327 
00328     return result;
00329 }
00330 
00331 static sint8 spi_cmd_rsp (uint8 cmd)
00332 {
00333     uint8 rsp;
00334     sint8 result = N_OK;
00335     sint8 s8RetryCnt;
00336 
00337     /**
00338         Command/Control response
00339     **/
00340     if ((cmd == CMD_RESET) ||
00341          (cmd == CMD_TERMINATE) ||
00342          (cmd == CMD_REPEAT)) {
00343         if (M2M_SUCCESS != nmi_spi_read(&rsp, 1)) {
00344             result = N_FAIL;
00345             goto _fail_;
00346         }
00347     }
00348 
00349     /* wait for response */
00350     s8RetryCnt = SPI_RESP_RETRY_COUNT;
00351     do
00352     {
00353         if (M2M_SUCCESS != nmi_spi_read(&rsp, 1)) {
00354             M2M_ERR("[nmi spi]: Failed cmd response read, bus error...\n");
00355             result = N_FAIL;
00356             goto _fail_;
00357         }
00358     } while((rsp != cmd) && (s8RetryCnt-- >0));
00359 
00360     /**
00361         State response
00362     **/
00363     /* wait for response */
00364     s8RetryCnt = SPI_RESP_RETRY_COUNT;
00365     do
00366     {
00367         if (M2M_SUCCESS != nmi_spi_read(&rsp, 1)) {
00368             M2M_ERR("[nmi spi]: Failed cmd response read, bus error...\n");
00369             result = N_FAIL;
00370             goto _fail_;
00371         }
00372     } while((rsp != 0x00) && (s8RetryCnt-- >0));
00373 
00374 _fail_:
00375 
00376     return result;
00377 }
00378 #ifndef USE_OLD_SPI_SW
00379 static int spi_cmd_complete (uint8_t cmd, uint32_t adr, uint8_t *b, uint32_t sz, uint8_t clockless)
00380 {
00381     uint8_t wb[32], rb[32];
00382     uint8_t wix, rix;
00383     uint32_t len2;
00384     uint8_t rsp;
00385     int len = 0;
00386     int result = N_OK;
00387 
00388     wb[0] = cmd;
00389     switch (cmd) {
00390     case CMD_SINGLE_READ:               /* single word (4 bytes) read */
00391         wb[1] = (uint8_t)(adr >> 16);
00392         wb[2] = (uint8_t)(adr >> 8);
00393         wb[3] = (uint8_t)adr;
00394         len = 5;
00395         break; 
00396     case CMD_INTERNAL_READ:         /* internal register read */ 
00397         wb[1] = (uint8_t)(adr >> 8);
00398         if(clockless == 1)  wb[1] |= (1 << 7);
00399         wb[2] = (uint8_t)adr;
00400         wb[3] = 0x00;
00401         len = 5;
00402         break;
00403     case CMD_TERMINATE:                 /* termination */
00404         wb[1] = 0x00;
00405         wb[2] = 0x00;
00406         wb[3] = 0x00;
00407         len = 5;
00408         break;
00409     case CMD_REPEAT:                        /* repeat */
00410         wb[1] = 0x00;
00411         wb[2] = 0x00;
00412         wb[3] = 0x00;
00413         len = 5;
00414         break;
00415     case CMD_RESET:                         /* reset */
00416         wb[1] = 0xff;
00417         wb[2] = 0xff;
00418         wb[3] = 0xff;
00419         len = 5;
00420         break;
00421     case CMD_DMA_WRITE:                 /* dma write */
00422     case CMD_DMA_READ:                  /* dma read */
00423         wb[1] = (uint8_t)(adr >> 16);
00424         wb[2] = (uint8_t)(adr >> 8);
00425         wb[3] = (uint8_t)adr;
00426         wb[4] = (uint8_t)(sz >> 8);
00427         wb[5] = (uint8_t)(sz);
00428         len = 7;
00429         break;
00430     case CMD_DMA_EXT_WRITE:     /* dma extended write */
00431     case CMD_DMA_EXT_READ:          /* dma extended read */
00432         wb[1] = (uint8_t)(adr >> 16);
00433         wb[2] = (uint8_t)(adr >> 8);
00434         wb[3] = (uint8_t)adr;
00435         wb[4] = (uint8_t)(sz >> 16);
00436         wb[5] = (uint8_t)(sz >> 8);
00437         wb[6] = (uint8_t)(sz);
00438         len = 8;
00439         break;
00440     case CMD_INTERNAL_WRITE:        /* internal register write */
00441         wb[1] = (uint8_t)(adr >> 8);
00442         if(clockless == 1)  wb[1] |= (1 << 7);
00443         wb[2] = (uint8_t)(adr);
00444         wb[3] = b[3];
00445         wb[4] = b[2];
00446         wb[5] = b[1];
00447         wb[6] = b[0];
00448         len = 8;
00449         break;
00450     case CMD_SINGLE_WRITE:          /* single word write */
00451         wb[1] = (uint8_t)(adr >> 16);
00452         wb[2] = (uint8_t)(adr >> 8);
00453         wb[3] = (uint8_t)(adr);
00454         wb[4] = b[3];
00455         wb[5] = b[2];
00456         wb[6] = b[1];
00457         wb[7] = b[0];
00458         len = 9;
00459         break;
00460     default:
00461         result = N_FAIL;
00462         break;
00463     }
00464 
00465     if (result != N_OK) {
00466         return result;
00467     }
00468 
00469     if (!gu8Crc_off) {
00470         wb[len-1] = (crc7(0x7f, (const uint8_t *)&wb[0], len-1)) << 1;
00471     } else {
00472         len -=1;
00473     }
00474 
00475 #define NUM_SKIP_BYTES (1)
00476 #define NUM_RSP_BYTES (2)
00477 #define NUM_DATA_HDR_BYTES (1)
00478 #define NUM_DATA_BYTES (4)
00479 #define NUM_CRC_BYTES (2)
00480 #define NUM_DUMMY_BYTES (3)
00481 
00482     if ((cmd == CMD_RESET) ||
00483         (cmd == CMD_TERMINATE) ||
00484         (cmd == CMD_REPEAT)) {
00485             len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
00486     } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
00487         if (!gu8Crc_off) {
00488             len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES 
00489             + NUM_CRC_BYTES + NUM_DUMMY_BYTES); 
00490         } else {
00491             len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES 
00492             + NUM_DUMMY_BYTES);
00493         }
00494     } else {
00495         len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
00496     }
00497 #undef NUM_DUMMY_BYTES
00498 
00499     if(len2 > (sizeof(wb)/sizeof(wb[0]))) {
00500         M2M_ERR("[nmi spi]: spi buffer size too small (%d) (%d)\n",
00501             len2, (sizeof(wb)/sizeof(wb[0])));
00502         result = N_FAIL;
00503         return result;
00504     }
00505     /* zero spi write buffers. */
00506     for(wix = len; wix< len2; wix++) {
00507         wb[wix] = 0;
00508     }
00509     rix = len;
00510 
00511     if (nmi_spi_rw(wb, rb, len2) != M2M_SUCCESS) {
00512         M2M_ERR("[nmi spi]: Failed cmd write, bus error...\n");
00513         result = N_FAIL;
00514         return result;
00515     }
00516 
00517 #if 0
00518     {
00519         int jj;
00520         printk("--- cnd = %x, len=%d, len2=%d\n", cmd, len, len2);
00521         for(jj=0; jj<sizeof(wb)/sizeof(wb[0]); jj++) {
00522 
00523             if(jj >= len2) break;
00524             if(((jj+1)%16) != 0) {
00525                 if((jj%16) == 0) {
00526                     printk("wb[%02x]: %02x ", jj, wb[jj]);
00527                 } else {
00528                     printk("%02x ", wb[jj]);
00529                 }
00530             } else {
00531                 printk("%02x\n", wb[jj]);
00532             }
00533         }
00534         printk("\n");
00535 
00536         for(jj=0; jj<sizeof(rb)/sizeof(rb[0]); jj++) {
00537 
00538                 if(jj >= len2) break;
00539                 if(((jj+1)%16) != 0) {
00540                     if((jj%16) == 0) {
00541                         printk("rb[%02x]: %02x ", jj, rb[jj]);
00542                     } else {
00543                         printk("%02x ", rb[jj]);
00544                     }
00545                 } else {
00546                     printk("%02x\n", rb[jj]);
00547                 }
00548             }
00549         printk("\n");
00550     }
00551 #endif
00552 
00553     /**
00554     Command/Control response
00555     **/
00556     if ((cmd == CMD_RESET) ||
00557         (cmd == CMD_TERMINATE) ||
00558         (cmd == CMD_REPEAT)) {
00559             rix++; /* skip 1 byte */
00560     }
00561 
00562     rsp = rb[rix++];
00563 
00564 
00565     if (rsp != cmd) {
00566         M2M_ERR("[nmi spi]: Failed cmd response, cmd (%02x), resp (%02x)\n", cmd, rsp);
00567         result = N_FAIL;
00568         return result;
00569     }
00570 
00571     /**
00572     State response
00573     **/
00574     rsp = rb[rix++];
00575     if (rsp != 0x00) {
00576         M2M_ERR("[nmi spi]: Failed cmd state response state (%02x)\n", rsp);
00577         result = N_FAIL;
00578         return result;
00579     }
00580 
00581     if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
00582         || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
00583             int retry;
00584             //uint16_t crc1, crc2;
00585             uint8_t crc[2];
00586             /**
00587             Data Respnose header
00588             **/
00589             retry = SPI_RESP_RETRY_COUNT;
00590             do {
00591                 /* ensure there is room in buffer later to read data and crc */
00592                 if(rix < len2) { 
00593                     rsp = rb[rix++];
00594                 } else {
00595                     retry = 0;
00596                     break;
00597                 }
00598                 if (((rsp >> 4) & 0xf) == 0xf)
00599                     break;
00600             } while (retry--);
00601 
00602             if (retry <= 0) {
00603                 M2M_ERR("[nmi spi]: Error, data read response (%02x)\n", rsp);
00604                 result = N_RESET;
00605                 return result;
00606             }
00607 
00608             if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
00609                 /**
00610                 Read bytes
00611                 **/
00612                 if((rix+3) < len2) { 
00613                     b[0] = rb[rix++];
00614                     b[1] = rb[rix++];
00615                     b[2] = rb[rix++];
00616                     b[3] = rb[rix++];
00617                 } else {
00618                     M2M_ERR("[nmi spi]: buffer overrun when reading data.\n");
00619                     result = N_FAIL;
00620                     return result;
00621                 }
00622 
00623                 if (!gu8Crc_off) {                      
00624                     /**
00625                     Read Crc
00626                     **/
00627                     if((rix+1) < len2) { 
00628                         crc[0] = rb[rix++];
00629                         crc[1] = rb[rix++];
00630                     } else {
00631                         M2M_ERR("[nmi spi]: buffer overrun when reading crc.\n");
00632                         result = N_FAIL;
00633                         return result;
00634                     }
00635                 }
00636             } else if((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
00637                 int ix;
00638 
00639                 /* some data may be read in response to dummy bytes. */
00640                 for(ix=0; (rix < len2) && (ix < sz);) {
00641                     b[ix++] = rb[rix++];                
00642                 }
00643 #if 0
00644                 if(ix) M2M_INFO("ttt %d %d\n", sz, ix);
00645 #endif
00646                 sz -= ix;
00647 
00648                 if(sz > 0) {
00649                     int nbytes;
00650                     
00651                     if (sz <= (DATA_PKT_SZ-ix)) {
00652                         nbytes = sz;
00653                     } else {
00654                         nbytes = DATA_PKT_SZ-ix;
00655                     }
00656 
00657                     /**
00658                     Read bytes
00659                     **/
00660                     if (nmi_spi_read(&b[ix], nbytes) != M2M_SUCCESS) {
00661                         M2M_ERR("[nmi spi]: Failed data block read, bus error...\n");
00662                         result = N_FAIL;
00663                         goto _error_;
00664                     }
00665 
00666                     /**
00667                     Read Crc
00668                     **/
00669                     if (!gu8Crc_off) {
00670                         if (nmi_spi_read(crc, 2) != M2M_SUCCESS) {
00671                             M2M_ERR("[nmi spi]: Failed data block crc read, bus error...\n");
00672                             result = N_FAIL;
00673                             goto _error_;
00674                         }
00675                     }
00676 
00677                     
00678                     ix += nbytes;
00679                     sz -= nbytes;
00680                 }
00681 
00682                 /*  if any data in left unread, then read the rest using normal DMA code.*/ 
00683                 while(sz > 0) {
00684                     int nbytes;
00685             
00686                     if (sz <= DATA_PKT_SZ) {
00687                         nbytes = sz;
00688                     } else {
00689                         nbytes = DATA_PKT_SZ;
00690                     }
00691 
00692                     /** 
00693                     read data response only on the next DMA cycles not 
00694                     the first DMA since data response header is already 
00695                     handled above for the first DMA.
00696                     **/
00697                     /**
00698                     Data Respnose header
00699                     **/
00700                     retry = SPI_RESP_RETRY_COUNT;
00701                     do {
00702                         if (nmi_spi_read(&rsp, 1) != M2M_SUCCESS) {
00703                             M2M_ERR("[nmi spi]: Failed data response read, bus error...\n");
00704                             result = N_FAIL;
00705                             break;
00706                         }
00707                         if (((rsp >> 4) & 0xf) == 0xf)
00708                             break;
00709                     } while (retry--);
00710 
00711                     if (result == N_FAIL)
00712                         break;
00713 
00714 
00715                     /**
00716                     Read bytes
00717                     **/
00718                     if (nmi_spi_read(&b[ix], nbytes) != M2M_SUCCESS) {
00719                         M2M_ERR("[nmi spi]: Failed data block read, bus error...\n");
00720                         result = N_FAIL;
00721                         break;
00722                     }
00723 
00724                     /**
00725                     Read Crc
00726                     **/
00727                     if (!gu8Crc_off) {
00728                         if (nmi_spi_read(crc, 2) != M2M_SUCCESS) {
00729                             M2M_ERR("[nmi spi]: Failed data block crc read, bus error...\n");
00730                             result = N_FAIL;
00731                             break;
00732                         }
00733                     }
00734 
00735                     ix += nbytes;
00736                     sz -= nbytes;
00737                 }
00738             }
00739     }
00740 _error_:
00741     return result;
00742 }
00743 #endif
00744 static sint8 spi_data_read (uint8 *b, uint16 sz,uint8 clockless)
00745 {
00746     sint16 retry, ix, nbytes;
00747     sint8 result = N_OK;
00748     uint8 crc[2];
00749     uint8 rsp;
00750 
00751     /**
00752         Data
00753     **/
00754     ix = 0;
00755     do {
00756         if (sz <= DATA_PKT_SZ)
00757             nbytes = sz;
00758         else
00759             nbytes = DATA_PKT_SZ;
00760 
00761         /**
00762             Data Respnose header
00763         **/
00764         retry = SPI_RESP_RETRY_COUNT;
00765         do {
00766             if (M2M_SUCCESS != nmi_spi_read(&rsp, 1)) {
00767                 M2M_ERR("[nmi spi]: Failed data response read, bus error...\n");
00768                 result = N_FAIL;
00769                 break;
00770             }
00771             if (((rsp >> 4) & 0xf) == 0xf)
00772                 break;
00773         } while (retry--);
00774 
00775         if (result == N_FAIL)
00776             break;
00777 
00778         if (retry <= 0) {
00779             M2M_ERR("[nmi spi]: Failed data response read...(%02x)\n", rsp);
00780             result = N_FAIL;
00781             break;
00782         }
00783 
00784         /**
00785             Read bytes
00786         **/
00787         if (M2M_SUCCESS != nmi_spi_read(&b[ix], nbytes)) {
00788             M2M_ERR("[nmi spi]: Failed data block read, bus error...\n");
00789             result = N_FAIL;
00790             break;
00791         }
00792         if(!clockless)
00793         {
00794             /**
00795             Read Crc
00796             **/
00797             if (!gu8Crc_off) {
00798                 if (M2M_SUCCESS != nmi_spi_read(crc, 2)) {
00799                     M2M_ERR("[nmi spi]: Failed data block crc read, bus error...\n");
00800                     result = N_FAIL;
00801                     break;
00802                 }
00803             }
00804         }
00805         ix += nbytes;
00806         sz -= nbytes;
00807 
00808     } while (sz);
00809 
00810     return result;
00811 }
00812 
00813 static sint8 spi_data_write (uint8 *b, uint16 sz)
00814 {
00815     sint16 ix;
00816     uint16 nbytes;
00817     sint8 result = 1;
00818     uint8 cmd, order, crc[2] = {0};
00819     //uint8 rsp;
00820 
00821     /**
00822         Data
00823     **/
00824     ix = 0;
00825     do {
00826         if (sz <= DATA_PKT_SZ)
00827             nbytes = sz;
00828         else
00829             nbytes = DATA_PKT_SZ;
00830 
00831         /**
00832             Write command
00833         **/
00834         cmd = 0xf0;
00835         if (ix == 0)  {
00836             if (sz <= DATA_PKT_SZ)
00837                 order = 0x3;
00838             else
00839                 order = 0x1;
00840         } else {
00841             if (sz <= DATA_PKT_SZ)
00842                 order = 0x3;
00843             else
00844                 order = 0x2;
00845         }
00846         cmd |= order;
00847         if (M2M_SUCCESS != nmi_spi_write(&cmd, 1)) {
00848             M2M_ERR("[nmi spi]: Failed data block cmd write, bus error...\n");
00849             result = N_FAIL;
00850             break;
00851         }
00852 
00853         /**
00854             Write data
00855         **/
00856         if (M2M_SUCCESS != nmi_spi_write(&b[ix], nbytes)) {
00857             M2M_ERR("[nmi spi]: Failed data block write, bus error...\n");
00858             result = N_FAIL;
00859             break;
00860         }
00861 
00862         /**
00863             Write Crc
00864         **/
00865         if (!gu8Crc_off) {
00866             if (M2M_SUCCESS != nmi_spi_write(crc, 2)) {
00867                 M2M_ERR("[nmi spi]: Failed data block crc write, bus error...\n");
00868                 result = N_FAIL;
00869                 break;
00870             }
00871         }
00872 
00873         ix += nbytes;
00874         sz -= nbytes;
00875     } while (sz);
00876 
00877 
00878     return result;
00879 }
00880 
00881 /********************************************
00882 
00883     Spi Internal Read/Write Function
00884 
00885 ********************************************/
00886 
00887 /********************************************
00888 
00889     Spi interfaces
00890 
00891 ********************************************/
00892 
00893 static sint8 spi_write_reg (uint32 addr, uint32 u32data)
00894 {
00895     uint8 retry = SPI_RETRY_COUNT;
00896     sint8 result = N_OK;
00897     uint8 cmd = CMD_SINGLE_WRITE;
00898     uint8 clockless = 0;
00899     
00900 _RETRY_:    
00901     if (addr <= 0x30)
00902     {
00903         /**
00904         NMC1000 clockless registers.
00905         **/
00906         cmd = CMD_INTERNAL_WRITE;
00907         clockless = 1;
00908     }
00909     else
00910     {
00911         cmd = CMD_SINGLE_WRITE;
00912         clockless = 0;
00913     }
00914 
00915 #if defined USE_OLD_SPI_SW
00916     result = spi_cmd(cmd, addr, u32data, 4, clockless);
00917     if (result != N_OK) {
00918         M2M_ERR("[nmi spi]: Failed cmd, write reg (%08x)...\n", (unsigned int)addr);
00919         goto _FAIL_;
00920     }
00921 
00922     result = spi_cmd_rsp (cmd);
00923     if (result != N_OK) {
00924         M2M_ERR("[nmi spi]: Failed cmd response, write reg (%08x)...\n", (unsigned int)addr);
00925         goto _FAIL_;
00926     }
00927 
00928 #else
00929 
00930     result = spi_cmd_complete (cmd, addr, (uint8*)&u32data, 4, clockless);
00931     if (result != N_OK) {
00932         M2M_ERR( "[nmi spi]: Failed cmd, write reg (%08x)...\n", addr);
00933         goto _FAIL_;
00934     }
00935 
00936 #endif
00937 _FAIL_:
00938     if(result != N_OK)
00939     {
00940         nm_bsp_sleep(1);
00941         spi_cmd(CMD_RESET, 0, 0, 0, 0);
00942         spi_cmd_rsp (CMD_RESET);
00943         M2M_ERR("Reset and retry %d %lx %lx\n",retry,addr,u32data);
00944         nm_bsp_sleep(1);
00945         retry--;
00946         if(retry) goto _RETRY_;
00947     }
00948 
00949     return result;
00950 }
00951 
00952 static sint8 nm_spi_write (uint32 addr, uint8 *buf, uint16 size)
00953 {
00954     sint8 result;
00955     uint8 retry = SPI_RETRY_COUNT;
00956     uint8 cmd = CMD_DMA_EXT_WRITE;
00957 
00958 
00959 _RETRY_:
00960     /**
00961         Command
00962     **/
00963 #if defined USE_OLD_SPI_SW
00964     //Workaround hardware problem with single byte transfers over SPI bus
00965     if (size == 1)
00966         size = 2;
00967 
00968     result = spi_cmd(cmd, addr, 0, size,0);
00969     if (result != N_OK) {
00970         M2M_ERR("[nmi spi]: Failed cmd, write block (%08x)...\n", (unsigned int)addr);
00971         goto _FAIL_;
00972     }
00973 
00974     result = spi_cmd_rsp (cmd);
00975     if (result != N_OK) {
00976         M2M_ERR("[nmi spi ]: Failed cmd response, write block (%08x)...\n", (unsigned int)addr);
00977         goto _FAIL_;
00978     }
00979 #else
00980     result = spi_cmd_complete (cmd, addr, NULL, size, 0);
00981     if (result != N_OK) {
00982         M2M_ERR( "[nmi spi]: Failed cmd, write block (%08x)...\n", addr);
00983         goto _FAIL_;
00984     }
00985 #endif
00986 
00987     /**
00988         Data
00989     **/
00990     result = spi_data_write (buf, size);
00991     if (result != N_OK) {
00992         M2M_ERR("[nmi spi]: Failed block data write...\n");
00993         goto _FAIL_;
00994     }
00995     /**
00996         Data RESP
00997     **/
00998     result = spi_data_rsp(cmd);
00999     if (result != N_OK) {
01000         M2M_ERR("[nmi spi]: Failed block data write...\n");
01001         goto _FAIL_;
01002     }
01003     
01004 _FAIL_:
01005     if(result != N_OK)
01006     {
01007         nm_bsp_sleep(1);
01008         spi_cmd(CMD_RESET, 0, 0, 0, 0);
01009         spi_cmd_rsp (CMD_RESET);
01010         M2M_ERR("Reset and retry %d %lx %d\n",retry,addr,size);
01011         nm_bsp_sleep(1);
01012         retry--;
01013         if(retry) goto _RETRY_;
01014     }
01015 
01016 
01017     return result;
01018 }
01019 
01020 static sint8 spi_read_reg (uint32 addr, uint32 *u32data)
01021 {
01022     uint8 retry = SPI_RETRY_COUNT;
01023     sint8 result = N_OK;
01024     uint8 cmd = CMD_SINGLE_READ;
01025     uint8 tmp[4];
01026     uint8 clockless = 0;
01027 
01028 _RETRY_:
01029 
01030     if (addr <= 0xff)
01031     {
01032         /**
01033         NMC1000 clockless registers.
01034         **/
01035         cmd = CMD_INTERNAL_READ;
01036         clockless = 1;
01037     }
01038     else
01039     {
01040         cmd = CMD_SINGLE_READ;
01041         clockless = 0;
01042     }
01043 
01044 #if defined USE_OLD_SPI_SW
01045     result = spi_cmd(cmd, addr, 0, 4, clockless);
01046     if (result != N_OK) {
01047         M2M_ERR("[nmi spi]: Failed cmd, read reg (%08x)...\n", (unsigned int)addr);
01048         goto _FAIL_;
01049     }
01050 
01051     result = spi_cmd_rsp (cmd);
01052     if (result != N_OK) {
01053         M2M_ERR("[nmi spi]: Failed cmd response, read reg (%08x)...\n", (unsigned int)addr);
01054         goto _FAIL_;
01055     }
01056 
01057     /* to avoid endianess issues */
01058     result = spi_data_read (&tmp[0], 4, clockless);
01059     if (result != N_OK) {
01060         M2M_ERR("[nmi spi]: Failed data read...\n");
01061         goto _FAIL_;
01062     }
01063 #else
01064     result = spi_cmd_complete (cmd, addr, (uint8*)&tmp[0], 4, clockless);
01065     if (result != N_OK) {
01066         M2M_ERR( "[nmi spi]: Failed cmd, read reg (%08x)...\n", addr);
01067         goto _FAIL_;
01068     }
01069 
01070 #endif
01071 
01072     *u32data = tmp[0] |
01073         ((uint32)tmp[1] << 8) |
01074         ((uint32)tmp[2] << 16) |
01075         ((uint32)tmp[3] << 24);
01076         
01077 _FAIL_:
01078     if(result != N_OK)
01079     {
01080         
01081         nm_bsp_sleep(1);
01082         spi_cmd(CMD_RESET, 0, 0, 0, 0);
01083         spi_cmd_rsp (CMD_RESET);
01084         M2M_ERR("Reset and retry %d %lx\n",retry,addr);
01085         nm_bsp_sleep(1);
01086         retry--;
01087         if(retry) goto _RETRY_;
01088     }
01089         
01090     return result;
01091 }
01092 
01093 static sint8 nm_spi_read (uint32 addr, uint8 *buf, uint16 size)
01094 {
01095     uint8 cmd = CMD_DMA_EXT_READ;
01096     sint8 result;
01097     uint8 retry = SPI_RETRY_COUNT;
01098 #if defined USE_OLD_SPI_SW
01099     uint8 tmp[2];
01100     uint8 single_byte_workaround = 0;
01101 #endif
01102 
01103 _RETRY_:
01104 
01105     /**
01106         Command
01107     **/
01108 #if defined USE_OLD_SPI_SW
01109     if (size == 1)
01110     {
01111         //Workaround hardware problem with single byte transfers over SPI bus
01112         size = 2;
01113         single_byte_workaround = 1;
01114     }
01115     result = spi_cmd(cmd, addr, 0, size,0);
01116     if (result != N_OK) {
01117         M2M_ERR("[nmi spi]: Failed cmd, read block (%08x)...\n", (unsigned int)addr);
01118         goto _FAIL_;
01119     }
01120 
01121     result = spi_cmd_rsp (cmd);
01122     if (result != N_OK) {
01123         M2M_ERR("[nmi spi]: Failed cmd response, read block (%08x)...\n", (unsigned int)addr);
01124         goto _FAIL_;
01125     }
01126 
01127     /**
01128         Data
01129     **/
01130     if (single_byte_workaround)
01131     {
01132         result = spi_data_read (tmp, size,0);
01133         buf[0] = tmp[0];
01134     }
01135     else
01136         result = spi_data_read (buf, size,0);
01137 
01138     if (result != N_OK) {
01139         M2M_ERR("[nmi spi]: Failed block data read...\n");
01140         goto _FAIL_;
01141     }
01142 #else
01143     result = spi_cmd_complete (cmd, addr, buf, size, 0);
01144     if (result != N_OK) {
01145         M2M_ERR("[nmi spi]: Failed cmd, read block (%08x)...\n", addr);
01146         goto _FAIL_;
01147     }
01148 #endif
01149 
01150 _FAIL_:
01151     if(result != N_OK)
01152     {
01153         nm_bsp_sleep(1);
01154         spi_cmd(CMD_RESET, 0, 0, 0, 0);
01155         spi_cmd_rsp (CMD_RESET);
01156         M2M_ERR("Reset and retry %d %lx %d\n",retry,addr,size);
01157         nm_bsp_sleep(1);
01158         retry--;
01159         if(retry) goto _RETRY_;
01160     }
01161 
01162     return result;
01163 }
01164 
01165 /********************************************
01166 
01167     Bus interfaces
01168 
01169 ********************************************/
01170 
01171 static void spi_init_pkt_sz(void)
01172 {
01173     uint32 val32;
01174 
01175     /* Make sure SPI max. packet size fits the defined DATA_PKT_SZ.  */
01176     val32 = nm_spi_read_reg(SPI_BASE+0x24);
01177     val32 &= ~(0x7 << 4);
01178     switch(DATA_PKT_SZ)
01179     {
01180     case 256:  val32 |= (0 << 4); break;
01181     case 512:  val32 |= (1 << 4); break;
01182     case 1024: val32 |= (2 << 4); break;
01183     case 2048: val32 |= (3 << 4); break;
01184     case 4096: val32 |= (4 << 4); break;
01185     case 8192: val32 |= (5 << 4); break;
01186 
01187     }
01188     nm_spi_write_reg(SPI_BASE+0x24, val32);
01189 }
01190 
01191 sint8 nm_spi_reset(void)
01192 {
01193     spi_cmd(CMD_RESET, 0, 0, 0, 0);
01194     spi_cmd_rsp (CMD_RESET);
01195     return M2M_SUCCESS;
01196 }
01197 
01198 /*
01199 *   @fn     nm_spi_init
01200 *   @brief  Initialize the SPI
01201 *   @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
01202 *   @author M. Abdelmawla
01203 *   @date   11 July 2012
01204 *   @version    1.0
01205 */
01206 sint8 nm_spi_init (void)
01207 {
01208     uint32 chipid;
01209     uint32 reg = 0;
01210     
01211 
01212     /**
01213         configure protocol
01214     **/
01215     gu8Crc_off = 0;
01216 
01217     // TODO: We can remove the CRC trials if there is a definite way to reset
01218     // the SPI to it's initial value.
01219     if (!spi_read_reg (NMI_SPI_PROTOCOL_CONFIG, &reg)) {
01220         /* Read failed. Try with CRC off. This might happen when module
01221         is removed but chip isn't reset*/
01222         gu8Crc_off = 1;
01223         M2M_ERR("[nmi spi]: Failed internal read protocol with CRC on, retyring with CRC off...\n");
01224         if (!spi_read_reg (NMI_SPI_PROTOCOL_CONFIG, &reg)){
01225             // Reaad failed with both CRC on and off, something went bad
01226             M2M_ERR( "[nmi spi]: Failed internal read protocol...\n");
01227             return 0;
01228         }
01229     }
01230     if(gu8Crc_off == 0)
01231     {
01232         reg &= ~0xc;    /* disable crc checking */
01233         reg &= ~0x70;
01234         reg |= (0x5 << 4);
01235         if (!spi_write_reg (NMI_SPI_PROTOCOL_CONFIG, reg)) {
01236             M2M_ERR( "[nmi spi]: Failed internal write protocol reg...\n");
01237             return 0;
01238         }
01239         gu8Crc_off = 1;
01240     }
01241 
01242     /**
01243         make sure can read back chip id correctly
01244     **/
01245     if (!spi_read_reg (0x1000, &chipid)) {
01246         M2M_ERR("[nmi spi]: Fail cmd read chip id...\n");
01247         return M2M_ERR_BUS_FAIL;
01248     }
01249 
01250     M2M_DBG("[nmi spi]: chipid (%08x)\n", (unsigned int)chipid);
01251     spi_init_pkt_sz();
01252 
01253 
01254     return M2M_SUCCESS;
01255 }
01256 
01257 /*
01258 *   @fn     nm_spi_init
01259 *   @brief  DeInitialize the SPI 
01260 *   @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
01261 *   @author Samer Sarhan
01262 *   @date   27 Feb 2015
01263 *   @version    1.0
01264 */ 
01265 sint8 nm_spi_deinit(void)
01266 {
01267     gu8Crc_off = 0;
01268     return M2M_SUCCESS;
01269 }
01270 
01271 /*
01272 *   @fn     nm_spi_read_reg
01273 *   @brief  Read register
01274 *   @param [in] u32Addr
01275 *               Register address
01276 *   @return Register value
01277 *   @author M. Abdelmawla
01278 *   @date   11 July 2012
01279 *   @version    1.0
01280 */
01281 uint32 nm_spi_read_reg(uint32 u32Addr)
01282 {
01283     uint32 u32Val;
01284 
01285     spi_read_reg (u32Addr, &u32Val);
01286 
01287     return u32Val;
01288 }
01289 
01290 /*
01291 *   @fn     nm_spi_read_reg_with_ret
01292 *   @brief  Read register with error code return
01293 *   @param [in] u32Addr
01294 *               Register address
01295 *   @param [out]    pu32RetVal
01296 *               Pointer to u32 variable used to return the read value
01297 *   @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
01298 *   @author M. Abdelmawla
01299 *   @date   11 July 2012
01300 *   @version    1.0
01301 */
01302 sint8 nm_spi_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal)
01303 {
01304     sint8 s8Ret;
01305 
01306     s8Ret = spi_read_reg (u32Addr,pu32RetVal);
01307 
01308     if(N_OK == s8Ret) s8Ret = M2M_SUCCESS;
01309     else s8Ret = M2M_ERR_BUS_FAIL;
01310 
01311     return s8Ret;
01312 }
01313 
01314 /*
01315 *   @fn     nm_spi_write_reg
01316 *   @brief  write register
01317 *   @param [in] u32Addr
01318 *               Register address
01319 *   @param [in] u32Val
01320 *               Value to be written to the register
01321 *   @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
01322 *   @author M. Abdelmawla
01323 *   @date   11 July 2012
01324 *   @version    1.0
01325 */
01326 sint8 nm_spi_write_reg(uint32 u32Addr, uint32 u32Val)
01327 {
01328     sint8 s8Ret;
01329 
01330     s8Ret = spi_write_reg (u32Addr, u32Val);
01331 
01332     if(N_OK == s8Ret) s8Ret = M2M_SUCCESS;
01333     else s8Ret = M2M_ERR_BUS_FAIL;
01334 
01335     return s8Ret;
01336 }
01337 
01338 /*
01339 *   @fn     nm_spi_read_block
01340 *   @brief  Read block of data
01341 *   @param [in] u32Addr
01342 *               Start address
01343 *   @param [out]    puBuf
01344 *               Pointer to a buffer used to return the read data
01345 *   @param [in] u16Sz
01346 *               Number of bytes to read. The buffer size must be >= u16Sz
01347 *   @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
01348 *   @author M. Abdelmawla
01349 *   @date   11 July 2012
01350 *   @version    1.0
01351 */
01352 sint8 nm_spi_read_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
01353 {
01354     sint8 s8Ret;
01355 
01356     s8Ret = nm_spi_read (u32Addr, puBuf, u16Sz);
01357 
01358     if(N_OK == s8Ret) s8Ret = M2M_SUCCESS;
01359     else s8Ret = M2M_ERR_BUS_FAIL;
01360 
01361     return s8Ret;
01362 }
01363 
01364 /*
01365 *   @fn     nm_spi_write_block
01366 *   @brief  Write block of data
01367 *   @param [in] u32Addr
01368 *               Start address
01369 *   @param [in] puBuf
01370 *               Pointer to the buffer holding the data to be written
01371 *   @param [in] u16Sz
01372 *               Number of bytes to write. The buffer size must be >= u16Sz
01373 *   @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
01374 *   @author M. Abdelmawla
01375 *   @date   11 July 2012
01376 *   @version    1.0
01377 */
01378 sint8 nm_spi_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
01379 {
01380     sint8 s8Ret;
01381 
01382     s8Ret = nm_spi_write (u32Addr, puBuf, u16Sz);
01383 
01384     if(N_OK == s8Ret) s8Ret = M2M_SUCCESS;
01385     else s8Ret = M2M_ERR_BUS_FAIL;
01386 
01387     return s8Ret;
01388 }
01389 
01390 #endif
01391