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Dependents: NNN50_CE_Test_UDP NNN50_linux_firmware NNN50_SoftAP_HelloWorld NNN50_BLEWIFISensor ... more
nmi2c.c
00001 /** 00002 * 00003 * \file 00004 * 00005 * \brief This module contains NMC1000 I2C protocol bus APIs implementation. 00006 * 00007 * Copyright (c) 2016 Atmel Corporation. All rights reserved. 00008 * 00009 * \asf_license_start 00010 * 00011 * \page License 00012 * 00013 * Redistribution and use in source and binary forms, with or without 00014 * modification, are permitted provided that the following conditions are met: 00015 * 00016 * 1. Redistributions of source code must retain the above copyright notice, 00017 * this list of conditions and the following disclaimer. 00018 * 00019 * 2. Redistributions in binary form must reproduce the above copyright notice, 00020 * this list of conditions and the following disclaimer in the documentation 00021 * and/or other materials provided with the distribution. 00022 * 00023 * 3. The name of Atmel may not be used to endorse or promote products derived 00024 * from this software without specific prior written permission. 00025 * 00026 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 00027 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 00028 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 00029 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 00030 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00031 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 00032 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 00033 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 00034 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 00035 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00036 * POSSIBILITY OF SUCH DAMAGE. 00037 * 00038 * \asf_license_stop 00039 * 00040 */ 00041 00042 #include "common/include/nm_common.h" 00043 00044 #ifdef CONF_WINC_USE_I2C 00045 00046 #include "nmi2c.h" 00047 #include "bus_wrapper/include/nm_bus_wrapper.h" 00048 00049 00050 /* 00051 * @fn nm_i2c_read_reg_with_ret 00052 * @brief Read register with error code return 00053 * @param [in] u32Addr 00054 * Register address 00055 * @param [out] pu32RetVal 00056 * Pointer to u32 variable used to return the read value 00057 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure 00058 * @author M. Abdelmawla 00059 * @date 11 July 2012 00060 * @version 1.0 00061 */ 00062 sint8 nm_i2c_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal) 00063 { 00064 uint8 b[6]; 00065 uint8 rsz; 00066 tstrNmI2cDefault strI2c; 00067 sint8 s8Ret = M2M_SUCCESS; 00068 00069 if(u32Addr < 0xff) { /* clockless i2c */ 00070 b[0] = 0x09; 00071 b[1] = (uint8)(u32Addr); 00072 rsz = 1; 00073 strI2c.u16Sz = 2; 00074 } else { 00075 b[0] = 0x80; 00076 b[1] = (uint8)(u32Addr >> 24); 00077 b[2] = (uint8)(u32Addr >> 16); 00078 b[3] = (uint8)(u32Addr >> 8); 00079 b[4] = (uint8)(u32Addr); 00080 b[5] = 0x04; 00081 rsz = 4; 00082 strI2c.u16Sz = 6; 00083 } 00084 00085 strI2c.pu8Buf = b; 00086 00087 if(M2M_SUCCESS == nm_bus_ioctl(NM_BUS_IOCTL_W, &strI2c)) 00088 { 00089 strI2c.u16Sz = rsz; 00090 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strI2c)) 00091 { 00092 //M2M_ERR("read error\n"); 00093 s8Ret = M2M_ERR_BUS_FAIL; 00094 } 00095 } 00096 else 00097 { 00098 M2M_ERR("failed to send cfg bytes\n"); 00099 s8Ret = M2M_ERR_BUS_FAIL; 00100 } 00101 00102 if (rsz == 1) { 00103 *pu32RetVal = b[0]; 00104 } else { 00105 *pu32RetVal = b[0] | ((uint32)b[1] << 8) | ((uint32)b[2] << 16) | ((uint32)b[3] << 24); 00106 } 00107 return s8Ret; 00108 } 00109 00110 /* 00111 * @fn nm_i2c_read_reg 00112 * @brief Read register 00113 * @param [in] u32Addr 00114 * Register address 00115 * @return Register value 00116 * @author M. Abdelmawla 00117 * @date 11 July 2012 00118 * @version 1.0 00119 */ 00120 uint32 nm_i2c_read_reg(uint32 u32Addr) 00121 { 00122 uint32 val; 00123 nm_i2c_read_reg_with_ret(u32Addr, &val); 00124 return val; 00125 } 00126 00127 /* 00128 * @fn nm_i2c_write_reg 00129 * @brief write register 00130 * @param [in] u32Addr 00131 * Register address 00132 * @param [in] u32Val 00133 * Value to be written to the register 00134 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure 00135 * @author M. Abdelmawla 00136 * @date 11 July 2012 00137 * @version 1.0 00138 */ 00139 sint8 nm_i2c_write_reg(uint32 u32Addr, uint32 u32Val) 00140 { 00141 tstrNmI2cDefault strI2c; 00142 uint8 b[16]; 00143 sint8 s8Ret = M2M_SUCCESS; 00144 00145 if(u32Addr < 0xff) { /* clockless i2c */ 00146 b[0] = 0x19; 00147 b[1] = (uint8)(u32Addr); 00148 b[2] = (uint8)(u32Val); 00149 strI2c.u16Sz = 3; 00150 } else { 00151 b[0] = 0x90; 00152 b[1] = (uint8)(u32Addr >> 24); 00153 b[2] = (uint8)(u32Addr >> 16); 00154 b[3] = (uint8)(u32Addr >> 8); 00155 b[4] = (uint8)u32Addr; 00156 b[5] = 0x04; 00157 b[6] = (uint8)u32Val; 00158 b[7] = (uint8)(u32Val >> 8); 00159 b[8] = (uint8)(u32Val >> 16); 00160 b[9] = (uint8)(u32Val >> 24); 00161 strI2c.u16Sz = 10; 00162 } 00163 00164 strI2c.pu8Buf = b; 00165 00166 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strI2c)) 00167 { 00168 M2M_ERR("write error\n"); 00169 s8Ret = M2M_ERR_BUS_FAIL; 00170 } 00171 00172 return s8Ret; 00173 } 00174 00175 /* 00176 * @fn nm_i2c_read_block 00177 * @brief Read block of data 00178 * @param [in] u32Addr 00179 * Start address 00180 * @param [out] puBuf 00181 * Pointer to a buffer used to return the read data 00182 * @param [in] u16Sz 00183 * Number of bytes to read. The buffer size must be >= u16Sz 00184 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure 00185 * @author M. Abdelmawla 00186 * @date 11 July 2012 00187 * @version 1.0 00188 */ 00189 sint8 nm_i2c_read_block(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz) 00190 { 00191 tstrNmI2cDefault strI2c; 00192 uint8 au8Buf[7]; 00193 sint8 s8Ret = M2M_SUCCESS; 00194 00195 au8Buf[0] = 0x02; 00196 au8Buf[1] = (uint8)(u32Addr >> 24); 00197 au8Buf[2] = (uint8)(u32Addr >> 16); 00198 au8Buf[3] = (uint8)(u32Addr >> 8); 00199 au8Buf[4] = (uint8)(u32Addr >> 0); 00200 au8Buf[5] = (uint8)(u16Sz >> 8); 00201 au8Buf[6] = (uint8)(u16Sz); 00202 00203 strI2c.pu8Buf = au8Buf; 00204 strI2c.u16Sz = sizeof(au8Buf); 00205 00206 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W, &strI2c)) 00207 { 00208 M2M_ERR("write error\n"); 00209 s8Ret = M2M_ERR_BUS_FAIL; 00210 } 00211 else 00212 { 00213 strI2c.pu8Buf = pu8Buf; 00214 strI2c.u16Sz = u16Sz; 00215 00216 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_R, &strI2c)) 00217 { 00218 M2M_ERR("read error\n"); 00219 s8Ret = M2M_ERR_BUS_FAIL; 00220 } 00221 } 00222 00223 return s8Ret; 00224 } 00225 00226 /* 00227 * @fn nm_i2c_write_block 00228 * @brief Write block of data 00229 * @param [in] u32Addr 00230 * Start address 00231 * @param [in] puBuf 00232 * Pointer to the buffer holding the data to be written 00233 * @param [in] u16Sz 00234 * Number of bytes to write. The buffer size must be >= u16Sz 00235 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure 00236 * @author M. Abdelmawla 00237 * @date 11 July 2012 00238 * @version 1.0 00239 */ 00240 sint8 nm_i2c_write_block(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz) 00241 { 00242 uint8 au8Buf[7]; 00243 tstrNmI2cSpecial strI2c; 00244 sint8 s8Ret = M2M_SUCCESS; 00245 00246 au8Buf[0] = 0x12; 00247 au8Buf[1] = (uint8)(u32Addr >> 24); 00248 au8Buf[2] = (uint8)(u32Addr >> 16); 00249 au8Buf[3] = (uint8)(u32Addr >> 8); 00250 au8Buf[4] = (uint8)(u32Addr); 00251 au8Buf[5] = (uint8)(u16Sz >> 8); 00252 au8Buf[6] = (uint8)(u16Sz); 00253 00254 strI2c.pu8Buf1 = au8Buf; 00255 strI2c.pu8Buf2 = pu8Buf; 00256 strI2c.u16Sz1 = sizeof(au8Buf); 00257 strI2c.u16Sz2 = u16Sz; 00258 00259 if(M2M_SUCCESS != nm_bus_ioctl(NM_BUS_IOCTL_W_SPECIAL, &strI2c)) 00260 { 00261 M2M_ERR("write error\n"); 00262 s8Ret = M2M_ERR_BUS_FAIL; 00263 } 00264 00265 return s8Ret; 00266 } 00267 00268 #endif 00269 /* EOF */ 00270
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