nmasic.c

00001 /**
00002  *
00003  * \file
00004  *
00005  * \brief This module contains NMC1500 ASIC specific internal APIs.
00006  *
00007  * Copyright (c) 2016-2017 Atmel Corporation. All rights reserved.
00008  *
00009  * \asf_license_start
00010  *
00011  * \page License
00012  *
00013  * Redistribution and use in source and binary forms, with or without
00014  * modification, are permitted provided that the following conditions are met:
00015  *
00016  * 1. Redistributions of source code must retain the above copyright notice,
00017  *    this list of conditions and the following disclaimer.
00018  *
00019  * 2. Redistributions in binary form must reproduce the above copyright notice,
00020  *    this list of conditions and the following disclaimer in the documentation
00021  *    and/or other materials provided with the distribution.
00022  *
00023  * 3. The name of Atmel may not be used to endorse or promote products derived
00024  *    from this software without specific prior written permission.
00025  *
00026  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
00027  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00028  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00029  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
00030  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00031  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
00032  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
00033  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
00034  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
00035  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00036  * POSSIBILITY OF SUCH DAMAGE.
00037  *
00038  * \asf_license_stop
00039  *
00040  */
00041 
00042 #include "common/include/nm_common.h"
00043 #include "driver/source/nmbus.h"
00044 #include "bsp/include/nm_bsp.h"
00045 #include "driver/source/nmasic.h"
00046 #include "driver/include/m2m_types.h"
00047 
00048 #define NMI_GLB_RESET_0             (NMI_PERIPH_REG_BASE + 0x400)
00049 #define NMI_INTR_REG_BASE           (NMI_PERIPH_REG_BASE + 0xa00)
00050 #define NMI_PIN_MUX_0               (NMI_PERIPH_REG_BASE + 0x408)
00051 #define NMI_INTR_ENABLE             (NMI_INTR_REG_BASE)
00052 #define GET_UINT32(X,Y)             (X[0+Y] + ((uint32)X[1+Y]<<8) + ((uint32)X[2+Y]<<16) +((uint32)X[3+Y]<<24))
00053 
00054 /*SPI and I2C only*/
00055 #define CORT_HOST_COMM              (0x10)
00056 #define HOST_CORT_COMM              (0x0b)
00057 #define WAKE_CLK_REG                (0x1)
00058 #define CLOCKS_EN_REG               (0xf)
00059 
00060 
00061 
00062 #define TIMEOUT                     (0xfffffffful)
00063 #define WAKUP_TRAILS_TIMEOUT        (4)
00064 
00065 sint8 chip_apply_conf(uint32 u32Conf)
00066 {
00067     sint8 ret = M2M_SUCCESS;
00068     uint32 val32 = u32Conf;
00069     
00070 #if (defined __ENABLE_PMU__) || (defined CONF_WINC_INT_PMU)
00071     val32 |= rHAVE_USE_PMU_BIT;
00072 #endif
00073 #ifdef __ENABLE_SLEEP_CLK_SRC_RTC__
00074     val32 |= rHAVE_SLEEP_CLK_SRC_RTC_BIT;
00075 #elif defined __ENABLE_SLEEP_CLK_SRC_XO__
00076     val32 |= rHAVE_SLEEP_CLK_SRC_XO_BIT;
00077 #endif
00078 #ifdef __ENABLE_EXT_PA_INV_TX_RX__
00079     val32 |= rHAVE_EXT_PA_INV_TX_RX;
00080 #endif
00081 #ifdef __ENABLE_LEGACY_RF_SETTINGS__
00082     val32 |= rHAVE_LEGACY_RF_SETTINGS;
00083 #endif
00084 #ifdef __DISABLE_FIRMWARE_LOGS__
00085     val32 |= rHAVE_LOGS_DISABLED_BIT;
00086 #endif
00087 
00088     val32 |= rHAVE_RESERVED1_BIT;
00089     do  {
00090         nm_write_reg(rNMI_GP_REG_1, val32);
00091         if(val32 != 0) {        
00092             uint32 reg = 0;
00093             ret = nm_read_reg_with_ret(rNMI_GP_REG_1, &reg);
00094             if(ret == M2M_SUCCESS) {
00095                 if(reg == val32)
00096                     break;
00097             }
00098         } else {
00099             break;
00100         }
00101     } while(1);
00102 
00103     return M2M_SUCCESS;
00104 }
00105 void chip_idle(void)
00106 {
00107     uint32 reg = 0;
00108     nm_read_reg_with_ret(WAKE_CLK_REG, &reg);
00109     if(reg & NBIT1)
00110     {
00111         reg &=~ NBIT1;
00112         nm_write_reg(WAKE_CLK_REG, reg);
00113     }
00114 }
00115 
00116 sint8 enable_interrupts (void)
00117 {
00118     uint32 reg = 0;
00119     sint8 ret = M2M_SUCCESS;
00120     /**
00121     interrupt pin mux select
00122     **/
00123     ret = nm_read_reg_with_ret(NMI_PIN_MUX_0, &reg);
00124     if (M2M_SUCCESS != ret) goto ERR1;
00125     
00126     reg |= ((uint32) 1 << 8);
00127     ret = nm_write_reg(NMI_PIN_MUX_0, reg);
00128     if (M2M_SUCCESS != ret) goto ERR1;
00129     
00130     /**
00131     interrupt enable
00132     **/
00133     ret = nm_read_reg_with_ret(NMI_INTR_ENABLE, &reg);
00134     if (M2M_SUCCESS != ret) goto ERR1;
00135     
00136     reg |= ((uint32) 1 << 16);
00137     ret = nm_write_reg(NMI_INTR_ENABLE, reg);
00138     if (M2M_SUCCESS != ret) goto ERR1;
00139 ERR1:   
00140     return ret;
00141 }
00142 
00143 sint8 cpu_start (void) {
00144     uint32 reg = 0;
00145     sint8 ret;
00146 
00147     /**
00148     reset regs
00149     */
00150     ret = nm_write_reg(BOOTROM_REG,0);
00151     ret += nm_write_reg(NMI_STATE_REG,0);
00152     ret += nm_write_reg(NMI_REV_REG,0);
00153     /**
00154     Go...
00155     **/
00156     ret += nm_read_reg_with_ret(0x1118, &reg);
00157     reg |= (1 << 0);
00158     ret += nm_write_reg(0x1118, reg);
00159     ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, &reg);
00160     if ((reg & (1ul << 10)) == (1ul << 10)) {
00161         reg &= ~(1ul << 10);
00162         ret += nm_write_reg(NMI_GLB_RESET_0, reg);
00163     }
00164     reg |= (1ul << 10);
00165     ret += nm_write_reg(NMI_GLB_RESET_0, reg);
00166     nm_bsp_sleep(1);
00167     return ret;
00168 }
00169 
00170 uint32 nmi_get_chipid(void)
00171 {
00172     static uint32 chipid = 0;
00173 
00174     if (chipid == 0) {
00175         uint32 rfrevid;
00176         
00177         if((nm_read_reg_with_ret(0x1000, &chipid)) != M2M_SUCCESS) {
00178             chipid = 0;
00179             return 0;
00180         }
00181         //if((ret = nm_read_reg_with_ret(0x11fc, &revid)) != M2M_SUCCESS) {
00182         //  return 0;
00183         //}
00184         if((nm_read_reg_with_ret(0x13f4, &rfrevid)) != M2M_SUCCESS) {
00185             chipid = 0;
00186             return 0;
00187         }
00188 
00189         if (chipid == 0x1002a0)  {
00190             if (rfrevid == 0x1) { /* 1002A0 */
00191             } else /* if (rfrevid == 0x2) */ { /* 1002A1 */
00192                 chipid = 0x1002a1;
00193             }
00194         } else if(chipid == 0x1002b0) {
00195             if(rfrevid == 3) { /* 1002B0 */
00196             } else if(rfrevid == 4) { /* 1002B1 */
00197                 chipid = 0x1002b1;
00198             } else /* if(rfrevid == 5) */ { /* 1002B2 */
00199                 chipid = 0x1002b2;
00200             }
00201         }else if(chipid == 0x1000F0) { 
00202             if((nm_read_reg_with_ret(0x3B0000, &chipid)) != M2M_SUCCESS) {
00203             chipid = 0;
00204             return 0;
00205             }
00206         }else {
00207             
00208         }
00209 //#define PROBE_FLASH
00210 #ifdef PROBE_FLASH
00211         if(chipid) {
00212             UWORD32 flashid;
00213 
00214             flashid = probe_spi_flash();
00215             if(flashid == 0x1230ef) {
00216                 chipid &= ~(0x0f0000);
00217                 chipid |= 0x050000;
00218             }
00219             if(flashid == 0xc21320c2) {
00220                 chipid &= ~(0x0f0000);
00221                 chipid |= 0x050000;
00222             }
00223         }
00224 #else
00225         /*M2M is by default have SPI flash*/
00226         chipid &= ~(0x0f0000);
00227         chipid |= 0x050000;
00228 #endif /* PROBE_FLASH */
00229     }
00230     return chipid;
00231 }
00232 
00233 uint32 nmi_get_rfrevid(void)
00234 {
00235     uint32 rfrevid;
00236     if((nm_read_reg_with_ret(0x13f4, &rfrevid)) != M2M_SUCCESS) {
00237         rfrevid = 0;
00238         return 0;
00239     }
00240     return rfrevid;
00241 }
00242 
00243 void restore_pmu_settings_after_global_reset(void)
00244 {
00245     /*
00246     * Must restore PMU register value after
00247     * global reset if PMU toggle is done at
00248     * least once since the last hard reset.
00249     */
00250     if(REV(nmi_get_chipid()) >= REV_2B0) {
00251         nm_write_reg(0x1e48, 0xb78469ce);
00252     }
00253 }
00254 
00255 void nmi_update_pll(void)
00256 {
00257     uint32 pll;
00258 
00259     pll = nm_read_reg(0x1428);
00260     pll &= ~0x1ul;
00261     nm_write_reg(0x1428, pll);
00262     pll |= 0x1ul;
00263     nm_write_reg(0x1428, pll);
00264 
00265 }
00266 void nmi_set_sys_clk_src_to_xo(void)
00267 {
00268     uint32 val32;
00269 
00270     /* Switch system clock source to XO. This will take effect after nmi_update_pll(). */
00271     val32 = nm_read_reg(0x141c);
00272     val32 |= (1 << 2);
00273     nm_write_reg(0x141c, val32);
00274 
00275     /* Do PLL update */
00276     nmi_update_pll();
00277 }
00278 sint8 chip_sleep(void)
00279 {
00280     uint32 reg;
00281     sint8 ret = M2M_SUCCESS;
00282     
00283     while(1)
00284     {
00285         ret = nm_read_reg_with_ret(CORT_HOST_COMM,&reg);
00286         if(ret != M2M_SUCCESS) goto ERR1;
00287         if((reg & NBIT0) == 0) break;
00288     }
00289     
00290     /* Clear bit 1 */
00291     ret = nm_read_reg_with_ret(WAKE_CLK_REG, &reg);
00292     if(ret != M2M_SUCCESS)goto ERR1;
00293     if(reg & NBIT1)
00294     {
00295         reg &=~NBIT1;
00296         ret = nm_write_reg(WAKE_CLK_REG, reg);
00297         if(ret != M2M_SUCCESS)goto ERR1;
00298     }
00299     
00300     ret = nm_read_reg_with_ret(HOST_CORT_COMM, &reg);
00301     if(ret != M2M_SUCCESS)goto ERR1;
00302     if(reg & NBIT0)
00303     {
00304         reg &= ~NBIT0;
00305         ret = nm_write_reg(HOST_CORT_COMM, reg);
00306         if(ret != M2M_SUCCESS)goto ERR1;
00307     }
00308 
00309 ERR1:
00310     return ret;
00311 }
00312 sint8 chip_wake(void)
00313 {
00314     sint8 ret = M2M_SUCCESS;
00315     uint32 reg = 0, clk_status_reg = 0,trials = 0;
00316 
00317     ret = nm_read_reg_with_ret(HOST_CORT_COMM, &reg);
00318     if(ret != M2M_SUCCESS)goto _WAKE_EXIT;
00319     
00320     if(!(reg & NBIT0))
00321     {
00322         /*USE bit 0 to indicate host wakeup*/
00323         ret = nm_write_reg(HOST_CORT_COMM, reg|NBIT0);
00324         if(ret != M2M_SUCCESS)goto _WAKE_EXIT;
00325     }
00326         
00327     ret = nm_read_reg_with_ret(WAKE_CLK_REG, &reg);
00328     if(ret != M2M_SUCCESS)goto _WAKE_EXIT;
00329     /* Set bit 1 */
00330     if(!(reg & NBIT1))
00331     {
00332         ret = nm_write_reg(WAKE_CLK_REG, reg | NBIT1);
00333         if(ret != M2M_SUCCESS) goto _WAKE_EXIT; 
00334     }
00335 
00336     do
00337     {
00338         ret = nm_read_reg_with_ret(CLOCKS_EN_REG, &clk_status_reg);
00339         if(ret != M2M_SUCCESS) {
00340             M2M_ERR("Bus error (5).%d %lx\n",ret,clk_status_reg);
00341             goto _WAKE_EXIT;
00342         }
00343         if(clk_status_reg & NBIT2) {
00344             break;
00345         }
00346         nm_bsp_sleep(2);
00347         trials++;
00348         if(trials > WAKUP_TRAILS_TIMEOUT)
00349         {
00350             M2M_ERR("Failed to wakup the chip\n");
00351             ret = M2M_ERR_TIME_OUT;
00352             goto _WAKE_EXIT;
00353         }
00354     }while(1);
00355     
00356     /*workaround sometimes spi fail to read clock regs after reading/writing clockless registers*/
00357     nm_bus_reset();
00358     
00359 _WAKE_EXIT:
00360     return ret;
00361 }
00362 sint8 cpu_halt(void)
00363 {
00364     sint8 ret;
00365     uint32 reg = 0;
00366     ret = nm_read_reg_with_ret(0x1118, &reg);
00367     reg |= (1 << 0);
00368     ret += nm_write_reg(0x1118, reg);
00369     ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, &reg);
00370     if ((reg & (1ul << 10)) == (1ul << 10)) {
00371         reg &= ~(1ul << 10);
00372         ret += nm_write_reg(NMI_GLB_RESET_0, reg);
00373         ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, &reg);
00374     }
00375     return ret;
00376 }
00377 sint8 chip_reset_and_cpu_halt(void)
00378 {
00379     sint8 ret = M2M_SUCCESS;
00380 
00381     /*Wakeup needed only for I2C interface*/
00382     ret = chip_wake();
00383     if(ret != M2M_SUCCESS) goto ERR1;
00384     /*Reset and CPU halt need for no wait board only*/
00385     ret = chip_reset();
00386     if(ret != M2M_SUCCESS) goto ERR1;
00387     ret = cpu_halt();
00388     if(ret != M2M_SUCCESS) goto ERR1;   
00389 ERR1:
00390     return ret;
00391 }
00392 sint8 chip_reset(void)
00393 {
00394     sint8 ret = M2M_SUCCESS;
00395     ret = nm_write_reg(NMI_GLB_RESET_0, 0);
00396     nm_bsp_sleep(50);
00397     return ret;
00398 }
00399 
00400 sint8 wait_for_bootrom(uint8 arg)
00401 {
00402     sint8 ret = M2M_SUCCESS;
00403     uint32 reg = 0, cnt = 0;
00404     uint32 u32GpReg1 = 0;
00405     uint32 u32DriverVerInfo = M2M_MAKE_VERSION_INFO(M2M_RELEASE_VERSION_MAJOR_NO,\
00406                 M2M_RELEASE_VERSION_MINOR_NO, M2M_RELEASE_VERSION_PATCH_NO,\
00407                 M2M_RELEASE_VERSION_MAJOR_NO, M2M_RELEASE_VERSION_MINOR_NO,\
00408                 M2M_RELEASE_VERSION_PATCH_NO);
00409 
00410 
00411     reg = 0;
00412     while(1) {
00413         reg = nm_read_reg(0x1014);  /* wait for efuse loading done */
00414         if (reg & 0x80000000) {
00415             break;
00416         }
00417         nm_bsp_sleep(1); /* TODO: Why bus error if this delay is not here. */
00418     }
00419     reg = nm_read_reg(M2M_WAIT_FOR_HOST_REG);
00420     reg &= 0x1;
00421 
00422     /* check if waiting for the host will be skipped or not */
00423     if(reg == 0)
00424     {
00425         reg = 0;
00426         while(reg != M2M_FINISH_BOOT_ROM)
00427         {
00428             nm_bsp_sleep(1);
00429             reg = nm_read_reg(BOOTROM_REG);
00430 
00431             if(++cnt > TIMEOUT)
00432             {
00433                 M2M_DBG("failed to load firmware from flash.\n");
00434                 ret = M2M_ERR_INIT;
00435                 goto ERR2;
00436             }
00437         }
00438     }
00439     
00440     if(M2M_WIFI_MODE_ATE_HIGH  == arg) {
00441         nm_write_reg(NMI_REV_REG, M2M_ATE_FW_START_VALUE);
00442         nm_write_reg(NMI_STATE_REG, NBIT20);
00443     }else if(M2M_WIFI_MODE_ATE_LOW  == arg) {
00444         nm_write_reg(NMI_REV_REG, M2M_ATE_FW_START_VALUE);
00445         nm_write_reg(NMI_STATE_REG, 0);
00446     }else if(M2M_WIFI_MODE_ETHERNET  == arg){
00447         u32GpReg1 = rHAVE_ETHERNET_MODE_BIT;
00448         nm_write_reg(NMI_STATE_REG, u32DriverVerInfo);
00449     } else {
00450         /*bypass this step*/
00451         nm_write_reg(NMI_STATE_REG, u32DriverVerInfo);
00452     }
00453 
00454     if(REV(nmi_get_chipid()) >= REV_3A0){
00455         chip_apply_conf(u32GpReg1 | rHAVE_USE_PMU_BIT);
00456     } else {
00457         chip_apply_conf(u32GpReg1);
00458     }
00459     M2M_INFO("DriverVerInfo: 0x%08lx\n",u32DriverVerInfo);
00460 
00461     nm_write_reg(BOOTROM_REG,M2M_START_FIRMWARE);
00462 
00463 #ifdef __ROM_TEST__
00464     rom_test();
00465 #endif /* __ROM_TEST__ */
00466 
00467 ERR2:
00468     return ret;
00469 }
00470 
00471 sint8 wait_for_firmware_start(uint8 arg)
00472 {
00473     sint8 ret = M2M_SUCCESS;
00474     uint32 reg = 0, cnt = 0;
00475     uint32 u32Timeout = TIMEOUT;
00476     volatile uint32 regAddress = NMI_STATE_REG;
00477     volatile uint32 checkValue = M2M_FINISH_INIT_STATE;
00478     
00479     if((M2M_WIFI_MODE_ATE_HIGH  == arg)||(M2M_WIFI_MODE_ATE_LOW  == arg)) {
00480         regAddress = NMI_REV_REG;
00481         checkValue = M2M_ATE_FW_IS_UP_VALUE;
00482     } else {
00483         /*bypass this step*/
00484     }
00485     
00486     
00487     while (checkValue != reg)
00488     {
00489         nm_bsp_sleep(2); /* TODO: Why bus error if this delay is not here. */
00490         M2M_DBG("%x %x %x\n",(unsigned int)nm_read_reg(0x108c),(unsigned int)nm_read_reg(0x108c),(unsigned int)nm_read_reg(0x14A0));
00491         reg = nm_read_reg(regAddress);
00492         if(++cnt >= u32Timeout)
00493         {
00494             M2M_DBG("Time out for wait firmware Run\n");
00495             ret = M2M_ERR_INIT;
00496             goto ERR;
00497         }
00498     }
00499     if(M2M_FINISH_INIT_STATE == checkValue)
00500     {
00501         nm_write_reg(NMI_STATE_REG, 0);
00502     }
00503 ERR:
00504     return ret;
00505 }
00506 
00507 sint8 chip_deinit (void)
00508 {
00509     uint32 reg = 0;
00510     sint8 ret;
00511 
00512     /**
00513     stop the firmware, need a re-download
00514     **/
00515     ret = nm_read_reg_with_ret(NMI_GLB_RESET_0, &reg);
00516     if (ret != M2M_SUCCESS) {
00517         M2M_ERR("failed to de-initialize\n");
00518         goto ERR1;
00519     }
00520     reg &= ~(1 << 10);
00521     ret = nm_write_reg(NMI_GLB_RESET_0, reg);
00522     if (ret != M2M_SUCCESS) {
00523         M2M_ERR("failed to de-initialize\n");
00524         goto ERR1;
00525     }
00526 
00527 ERR1:
00528     return ret;
00529 }
00530 
00531 #ifdef CONF_PERIPH
00532 
00533 sint8 set_gpio_dir(uint8 gpio, uint8 dir)
00534 {
00535     uint32 val32;
00536     sint8 ret;
00537 
00538     ret = nm_read_reg_with_ret(0x20108, &val32);
00539     if(ret != M2M_SUCCESS) goto _EXIT;
00540 
00541     if(dir) {
00542         val32 |= (1ul << gpio);
00543     } else {
00544         val32 &= ~(1ul << gpio);
00545     }
00546 
00547     ret = nm_write_reg(0x20108, val32);
00548 
00549 _EXIT:
00550     return ret;
00551 }
00552 sint8 set_gpio_val(uint8 gpio, uint8 val)
00553 {
00554     uint32 val32;
00555     sint8 ret;
00556 
00557     ret = nm_read_reg_with_ret(0x20100, &val32);
00558     if(ret != M2M_SUCCESS) goto _EXIT;
00559 
00560     if(val) {
00561         val32 |= (1ul << gpio);
00562     } else {
00563         val32 &= ~(1ul << gpio);
00564     }
00565 
00566     ret = nm_write_reg(0x20100, val32);
00567 
00568 _EXIT:
00569     return ret;
00570 }
00571 
00572 sint8 get_gpio_val(uint8 gpio, uint8* val)
00573 {
00574     uint32 val32;
00575     sint8 ret;
00576 
00577     ret = nm_read_reg_with_ret(0x20104, &val32);
00578     if(ret != M2M_SUCCESS) goto _EXIT;
00579 
00580     *val = (uint8)((val32 >> gpio) & 0x01);
00581 
00582 _EXIT:
00583     return ret;
00584 }
00585 
00586 sint8 pullup_ctrl(uint32 pinmask, uint8 enable)
00587 {
00588     sint8 s8Ret;
00589     uint32 val32;
00590     s8Ret = nm_read_reg_with_ret(0x142c, &val32);
00591     if(s8Ret != M2M_SUCCESS) {
00592         M2M_ERR("[pullup_ctrl]: failed to read\n");
00593         goto _EXIT;
00594     }
00595     if(enable) {
00596         val32 &= ~pinmask;
00597         } else {
00598         val32 |= pinmask;
00599     }
00600     s8Ret = nm_write_reg(0x142c, val32);
00601     if(s8Ret  != M2M_SUCCESS) {
00602         M2M_ERR("[pullup_ctrl]: failed to write\n");
00603         goto _EXIT;
00604     }
00605 _EXIT:
00606     return s8Ret;
00607 }
00608 #endif /* CONF_PERIPH */
00609 
00610 sint8 nmi_get_otp_mac_address(uint8 *pu8MacAddr,  uint8 * pu8IsValid)
00611 {
00612     sint8 ret;
00613     uint32  u32RegValue;
00614     uint8   mac[6];
00615     tstrGpRegs strgp = {0};
00616 
00617     ret = nm_read_reg_with_ret(rNMI_GP_REG_2, &u32RegValue);
00618     if(ret != M2M_SUCCESS) goto _EXIT_ERR;
00619 
00620     ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs));
00621     if(ret != M2M_SUCCESS) goto _EXIT_ERR;
00622     u32RegValue = strgp.u32Mac_efuse_mib;
00623 
00624     if(!EFUSED_MAC(u32RegValue)) {
00625         M2M_DBG("Default MAC\n");
00626         m2m_memset(pu8MacAddr, 0, 6);
00627         goto _EXIT_ERR;
00628     }
00629 
00630     M2M_DBG("OTP MAC\n");
00631     u32RegValue >>=16;
00632     ret = nm_read_block(u32RegValue|0x30000, mac, 6);
00633     m2m_memcpy(pu8MacAddr,mac,6);
00634     if(pu8IsValid) *pu8IsValid = 1;
00635     return ret;
00636 
00637 _EXIT_ERR:
00638     if(pu8IsValid) *pu8IsValid = 0;
00639     return ret;
00640 }
00641 
00642 sint8 nmi_get_mac_address(uint8 *pu8MacAddr)
00643 {
00644     sint8 ret;
00645     uint32  u32RegValue;
00646     uint8   mac[6];
00647     tstrGpRegs strgp = {0};
00648 
00649     ret = nm_read_reg_with_ret(rNMI_GP_REG_2, &u32RegValue);
00650     if(ret != M2M_SUCCESS) goto _EXIT_ERR;
00651 
00652     ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs));
00653     if(ret != M2M_SUCCESS) goto _EXIT_ERR;
00654     u32RegValue = strgp.u32Mac_efuse_mib;
00655 
00656     u32RegValue &=0x0000ffff;
00657     ret = nm_read_block(u32RegValue|0x30000, mac, 6);
00658     m2m_memcpy(pu8MacAddr, mac, 6);
00659 
00660     return ret;
00661 
00662 _EXIT_ERR:
00663     return ret;
00664 }
00665