Delta / NNN50_WIFI_API

NNN50 WIFI_API library

Dependents:   NNN50_CE_Test_UDP NNN50_linux_firmware NNN50_SoftAP_HelloWorld NNN50_BLEWIFISensor ... more

This is mbed compatible EthernetInterface lib exclude for Delta DFCM-NNN50 platform.

Additional information and examples can be found in mbed Handbook

wifi_host_driver/driver/source/nmbus.c@32:8298a2fb074f, 2017-09-04 (annotated)

Committer:
tsungta
Date:
Mon Sep 04 05:40:11 2017 +0000
Revision:
32:8298a2fb074f
Parent:
28:2abbf8463fa8 
56:f4cc53f; Add getRSSI() to readout RSSI while connected with AP router; Add SSL support refer to TCPSocketConnection.connect()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tsungta 28:2abbf8463fa8 1 /**
tsungta 28:2abbf8463fa8 2 *
tsungta 28:2abbf8463fa8 3 * \file
tsungta 28:2abbf8463fa8 4 *
tsungta 28:2abbf8463fa8 5 * \brief This module contains NMC1000 bus APIs implementation.
tsungta 28:2abbf8463fa8 6 *
tsungta 28:2abbf8463fa8 7 * Copyright (c) 2016-2017 Atmel Corporation. All rights reserved.
tsungta 28:2abbf8463fa8 8 *
tsungta 28:2abbf8463fa8 9 * \asf_license_start
tsungta 28:2abbf8463fa8 10 *
tsungta 28:2abbf8463fa8 11 * \page License
tsungta 28:2abbf8463fa8 12 *
tsungta 28:2abbf8463fa8 13 * Redistribution and use in source and binary forms, with or without
tsungta 28:2abbf8463fa8 14 * modification, are permitted provided that the following conditions are met:
tsungta 28:2abbf8463fa8 15 *
tsungta 28:2abbf8463fa8 16 * 1. Redistributions of source code must retain the above copyright notice,
tsungta 28:2abbf8463fa8 17 * this list of conditions and the following disclaimer.
tsungta 28:2abbf8463fa8 18 *
tsungta 28:2abbf8463fa8 19 * 2. Redistributions in binary form must reproduce the above copyright notice,
tsungta 28:2abbf8463fa8 20 * this list of conditions and the following disclaimer in the documentation
tsungta 28:2abbf8463fa8 21 * and/or other materials provided with the distribution.
tsungta 28:2abbf8463fa8 22 *
tsungta 28:2abbf8463fa8 23 * 3. The name of Atmel may not be used to endorse or promote products derived
tsungta 28:2abbf8463fa8 24 * from this software without specific prior written permission.
tsungta 28:2abbf8463fa8 25 *
tsungta 28:2abbf8463fa8 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
tsungta 28:2abbf8463fa8 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
tsungta 28:2abbf8463fa8 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
tsungta 28:2abbf8463fa8 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
tsungta 28:2abbf8463fa8 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tsungta 28:2abbf8463fa8 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
tsungta 28:2abbf8463fa8 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
tsungta 28:2abbf8463fa8 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
tsungta 28:2abbf8463fa8 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
tsungta 28:2abbf8463fa8 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
tsungta 28:2abbf8463fa8 36 * POSSIBILITY OF SUCH DAMAGE.
tsungta 28:2abbf8463fa8 37 *
tsungta 28:2abbf8463fa8 38 * \asf_license_stop
tsungta 28:2abbf8463fa8 39 *
tsungta 28:2abbf8463fa8 40 */
tsungta 28:2abbf8463fa8 41 #ifndef CORTUS_APP
tsungta 28:2abbf8463fa8 42
tsungta 28:2abbf8463fa8 43 #include "nmbus.h"
tsungta 28:2abbf8463fa8 44 #include "nmi2c.h"
tsungta 28:2abbf8463fa8 45 #include "nmspi.h"
tsungta 28:2abbf8463fa8 46 #include "nmuart.h"
tsungta 28:2abbf8463fa8 47
tsungta 28:2abbf8463fa8 48 #define MAX_TRX_CFG_SZ 8
tsungta 28:2abbf8463fa8 49
tsungta 28:2abbf8463fa8 50 /**
tsungta 28:2abbf8463fa8 51 * @fn nm_bus_iface_init
tsungta 28:2abbf8463fa8 52 * @brief Initialize bus interface
tsungta 28:2abbf8463fa8 53 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
tsungta 28:2abbf8463fa8 54 * @author M. Abdelmawla
tsungta 28:2abbf8463fa8 55 * @date 11 July 2012
tsungta 28:2abbf8463fa8 56 * @version 1.0
tsungta 28:2abbf8463fa8 57 */
tsungta 28:2abbf8463fa8 58 sint8 nm_bus_iface_init(void *pvInitVal)
tsungta 28:2abbf8463fa8 59 {
tsungta 28:2abbf8463fa8 60 sint8 ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 61 ret = nm_bus_init(pvInitVal);
tsungta 28:2abbf8463fa8 62 return ret;
tsungta 28:2abbf8463fa8 63 }
tsungta 28:2abbf8463fa8 64
tsungta 28:2abbf8463fa8 65 /**
tsungta 28:2abbf8463fa8 66 * @fn nm_bus_iface_deinit
tsungta 28:2abbf8463fa8 67 * @brief Deinitialize bus interface
tsungta 28:2abbf8463fa8 68 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
tsungta 28:2abbf8463fa8 69 * @author Samer Sarhan
tsungta 28:2abbf8463fa8 70 * @date 07 April 2014
tsungta 28:2abbf8463fa8 71 * @version 1.0
tsungta 28:2abbf8463fa8 72 */
tsungta 28:2abbf8463fa8 73 sint8 nm_bus_iface_deinit(void)
tsungta 28:2abbf8463fa8 74 {
tsungta 28:2abbf8463fa8 75 sint8 ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 76 ret = nm_bus_deinit();
tsungta 28:2abbf8463fa8 77
tsungta 28:2abbf8463fa8 78 return ret;
tsungta 28:2abbf8463fa8 79 }
tsungta 28:2abbf8463fa8 80
tsungta 28:2abbf8463fa8 81 /**
tsungta 28:2abbf8463fa8 82 * @fn nm_bus_reset
tsungta 28:2abbf8463fa8 83 * @brief reset bus interface
tsungta 28:2abbf8463fa8 84 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
tsungta 28:2abbf8463fa8 85 * @version 1.0
tsungta 28:2abbf8463fa8 86 */
tsungta 28:2abbf8463fa8 87 sint8 nm_bus_reset(void)
tsungta 28:2abbf8463fa8 88 {
tsungta 28:2abbf8463fa8 89 sint8 ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 90 #ifdef CONF_WINC_USE_UART
tsungta 28:2abbf8463fa8 91 #elif defined (CONF_WINC_USE_SPI)
tsungta 28:2abbf8463fa8 92 return nm_spi_reset();
tsungta 28:2abbf8463fa8 93 #elif defined (CONF_WINC_USE_I2C)
tsungta 28:2abbf8463fa8 94 #else
tsungta 28:2abbf8463fa8 95 #error "Plesae define bus usage"
tsungta 28:2abbf8463fa8 96 #endif
tsungta 28:2abbf8463fa8 97
tsungta 28:2abbf8463fa8 98 return ret;
tsungta 28:2abbf8463fa8 99 }
tsungta 28:2abbf8463fa8 100
tsungta 28:2abbf8463fa8 101 /**
tsungta 28:2abbf8463fa8 102 * @fn nm_bus_iface_reconfigure
tsungta 28:2abbf8463fa8 103 * @brief reconfigure bus interface
tsungta 28:2abbf8463fa8 104 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
tsungta 28:2abbf8463fa8 105 * @author Viswanathan Murugesan
tsungta 28:2abbf8463fa8 106 * @date 22 Oct 2014
tsungta 28:2abbf8463fa8 107 * @version 1.0
tsungta 28:2abbf8463fa8 108 */
tsungta 28:2abbf8463fa8 109 sint8 nm_bus_iface_reconfigure(void *ptr)
tsungta 28:2abbf8463fa8 110 {
tsungta 28:2abbf8463fa8 111 sint8 ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 112 #ifdef CONF_WINC_USE_UART
tsungta 28:2abbf8463fa8 113 ret = nm_uart_reconfigure(ptr);
tsungta 28:2abbf8463fa8 114 #endif
tsungta 28:2abbf8463fa8 115 return ret;
tsungta 28:2abbf8463fa8 116 }
tsungta 28:2abbf8463fa8 117 /*
tsungta 28:2abbf8463fa8 118 * @fn nm_read_reg
tsungta 28:2abbf8463fa8 119 * @brief Read register
tsungta 28:2abbf8463fa8 120 * @param [in] u32Addr
tsungta 28:2abbf8463fa8 121 * Register address
tsungta 28:2abbf8463fa8 122 * @return Register value
tsungta 28:2abbf8463fa8 123 * @author M. Abdelmawla
tsungta 28:2abbf8463fa8 124 * @date 11 July 2012
tsungta 28:2abbf8463fa8 125 * @version 1.0
tsungta 28:2abbf8463fa8 126 */
tsungta 28:2abbf8463fa8 127 uint32 nm_read_reg(uint32 u32Addr)
tsungta 28:2abbf8463fa8 128 {
tsungta 28:2abbf8463fa8 129 #ifdef CONF_WINC_USE_UART
tsungta 28:2abbf8463fa8 130 return nm_uart_read_reg(u32Addr);
tsungta 28:2abbf8463fa8 131 #elif defined (CONF_WINC_USE_SPI)
tsungta 28:2abbf8463fa8 132 return nm_spi_read_reg(u32Addr);
tsungta 28:2abbf8463fa8 133 #elif defined (CONF_WINC_USE_I2C)
tsungta 28:2abbf8463fa8 134 return nm_i2c_read_reg(u32Addr);
tsungta 28:2abbf8463fa8 135 #else
tsungta 28:2abbf8463fa8 136 #error "Plesae define bus usage"
tsungta 28:2abbf8463fa8 137 #endif
tsungta 28:2abbf8463fa8 138
tsungta 28:2abbf8463fa8 139 }
tsungta 28:2abbf8463fa8 140
tsungta 28:2abbf8463fa8 141 /*
tsungta 28:2abbf8463fa8 142 * @fn nm_read_reg_with_ret
tsungta 28:2abbf8463fa8 143 * @brief Read register with error code return
tsungta 28:2abbf8463fa8 144 * @param [in] u32Addr
tsungta 28:2abbf8463fa8 145 * Register address
tsungta 28:2abbf8463fa8 146 * @param [out] pu32RetVal
tsungta 28:2abbf8463fa8 147 * Pointer to u32 variable used to return the read value
tsungta 28:2abbf8463fa8 148 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
tsungta 28:2abbf8463fa8 149 * @author M. Abdelmawla
tsungta 28:2abbf8463fa8 150 * @date 11 July 2012
tsungta 28:2abbf8463fa8 151 * @version 1.0
tsungta 28:2abbf8463fa8 152 */
tsungta 28:2abbf8463fa8 153 sint8 nm_read_reg_with_ret(uint32 u32Addr, uint32* pu32RetVal)
tsungta 28:2abbf8463fa8 154 {
tsungta 28:2abbf8463fa8 155 #ifdef CONF_WINC_USE_UART
tsungta 28:2abbf8463fa8 156 return nm_uart_read_reg_with_ret(u32Addr,pu32RetVal);
tsungta 28:2abbf8463fa8 157 #elif defined (CONF_WINC_USE_SPI)
tsungta 28:2abbf8463fa8 158 return nm_spi_read_reg_with_ret(u32Addr,pu32RetVal);
tsungta 28:2abbf8463fa8 159 #elif defined (CONF_WINC_USE_I2C)
tsungta 28:2abbf8463fa8 160 return nm_i2c_read_reg_with_ret(u32Addr,pu32RetVal);
tsungta 28:2abbf8463fa8 161 #else
tsungta 28:2abbf8463fa8 162 #error "Plesae define bus usage"
tsungta 28:2abbf8463fa8 163 #endif
tsungta 28:2abbf8463fa8 164 }
tsungta 28:2abbf8463fa8 165
tsungta 28:2abbf8463fa8 166 /*
tsungta 28:2abbf8463fa8 167 * @fn nm_write_reg
tsungta 28:2abbf8463fa8 168 * @brief write register
tsungta 28:2abbf8463fa8 169 * @param [in] u32Addr
tsungta 28:2abbf8463fa8 170 * Register address
tsungta 28:2abbf8463fa8 171 * @param [in] u32Val
tsungta 28:2abbf8463fa8 172 * Value to be written to the register
tsungta 28:2abbf8463fa8 173 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
tsungta 28:2abbf8463fa8 174 * @author M. Abdelmawla
tsungta 28:2abbf8463fa8 175 * @date 11 July 2012
tsungta 28:2abbf8463fa8 176 * @version 1.0
tsungta 28:2abbf8463fa8 177 */
tsungta 28:2abbf8463fa8 178 sint8 nm_write_reg(uint32 u32Addr, uint32 u32Val)
tsungta 28:2abbf8463fa8 179 {
tsungta 28:2abbf8463fa8 180 #ifdef CONF_WINC_USE_UART
tsungta 28:2abbf8463fa8 181 return nm_uart_write_reg(u32Addr,u32Val);
tsungta 28:2abbf8463fa8 182 #elif defined (CONF_WINC_USE_SPI)
tsungta 28:2abbf8463fa8 183 return nm_spi_write_reg(u32Addr,u32Val);
tsungta 28:2abbf8463fa8 184 #elif defined (CONF_WINC_USE_I2C)
tsungta 28:2abbf8463fa8 185 return nm_i2c_write_reg(u32Addr,u32Val);
tsungta 28:2abbf8463fa8 186 #else
tsungta 28:2abbf8463fa8 187 #error "Plesae define bus usage"
tsungta 28:2abbf8463fa8 188 #endif
tsungta 28:2abbf8463fa8 189 }
tsungta 28:2abbf8463fa8 190
tsungta 28:2abbf8463fa8 191 static sint8 p_nm_read_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
tsungta 28:2abbf8463fa8 192 {
tsungta 28:2abbf8463fa8 193 #ifdef CONF_WINC_USE_UART
tsungta 28:2abbf8463fa8 194 return nm_uart_read_block(u32Addr,puBuf,u16Sz);
tsungta 28:2abbf8463fa8 195 #elif defined (CONF_WINC_USE_SPI)
tsungta 28:2abbf8463fa8 196 return nm_spi_read_block(u32Addr,puBuf,u16Sz);
tsungta 28:2abbf8463fa8 197 #elif defined (CONF_WINC_USE_I2C)
tsungta 28:2abbf8463fa8 198 return nm_i2c_read_block(u32Addr,puBuf,u16Sz);
tsungta 28:2abbf8463fa8 199 #else
tsungta 28:2abbf8463fa8 200 #error "Plesae define bus usage"
tsungta 28:2abbf8463fa8 201 #endif
tsungta 28:2abbf8463fa8 202
tsungta 28:2abbf8463fa8 203 }
tsungta 28:2abbf8463fa8 204 /*
tsungta 28:2abbf8463fa8 205 * @fn nm_read_block
tsungta 28:2abbf8463fa8 206 * @brief Read block of data
tsungta 28:2abbf8463fa8 207 * @param [in] u32Addr
tsungta 28:2abbf8463fa8 208 * Start address
tsungta 28:2abbf8463fa8 209 * @param [out] puBuf
tsungta 28:2abbf8463fa8 210 * Pointer to a buffer used to return the read data
tsungta 28:2abbf8463fa8 211 * @param [in] u32Sz
tsungta 28:2abbf8463fa8 212 * Number of bytes to read. The buffer size must be >= u32Sz
tsungta 28:2abbf8463fa8 213 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
tsungta 28:2abbf8463fa8 214 * @author M. Abdelmawla
tsungta 28:2abbf8463fa8 215 * @date 11 July 2012
tsungta 28:2abbf8463fa8 216 * @version 1.0
tsungta 28:2abbf8463fa8 217 */
tsungta 28:2abbf8463fa8 218 sint8 nm_read_block(uint32 u32Addr, uint8 *puBuf, uint32 u32Sz)
tsungta 28:2abbf8463fa8 219 {
tsungta 28:2abbf8463fa8 220 uint16 u16MaxTrxSz = egstrNmBusCapabilities.u16MaxTrxSz - MAX_TRX_CFG_SZ;
tsungta 28:2abbf8463fa8 221 uint32 off = 0;
tsungta 28:2abbf8463fa8 222 sint8 s8Ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 223
tsungta 28:2abbf8463fa8 224 for(;;)
tsungta 28:2abbf8463fa8 225 {
tsungta 28:2abbf8463fa8 226 if(u32Sz <= u16MaxTrxSz)
tsungta 28:2abbf8463fa8 227 {
tsungta 28:2abbf8463fa8 228 s8Ret += p_nm_read_block(u32Addr, &puBuf[off], (uint16)u32Sz);
tsungta 28:2abbf8463fa8 229 break;
tsungta 28:2abbf8463fa8 230 }
tsungta 28:2abbf8463fa8 231 else
tsungta 28:2abbf8463fa8 232 {
tsungta 28:2abbf8463fa8 233 s8Ret += p_nm_read_block(u32Addr, &puBuf[off], u16MaxTrxSz);
tsungta 28:2abbf8463fa8 234 if(M2M_SUCCESS != s8Ret) break;
tsungta 28:2abbf8463fa8 235 u32Sz -= u16MaxTrxSz;
tsungta 28:2abbf8463fa8 236 off += u16MaxTrxSz;
tsungta 28:2abbf8463fa8 237 u32Addr += u16MaxTrxSz;
tsungta 28:2abbf8463fa8 238 }
tsungta 28:2abbf8463fa8 239 }
tsungta 28:2abbf8463fa8 240
tsungta 28:2abbf8463fa8 241 return s8Ret;
tsungta 28:2abbf8463fa8 242 }
tsungta 28:2abbf8463fa8 243
tsungta 28:2abbf8463fa8 244 static sint8 p_nm_write_block(uint32 u32Addr, uint8 *puBuf, uint16 u16Sz)
tsungta 28:2abbf8463fa8 245 {
tsungta 28:2abbf8463fa8 246 #ifdef CONF_WINC_USE_UART
tsungta 28:2abbf8463fa8 247 return nm_uart_write_block(u32Addr,puBuf,u16Sz);
tsungta 28:2abbf8463fa8 248 #elif defined (CONF_WINC_USE_SPI)
tsungta 28:2abbf8463fa8 249 return nm_spi_write_block(u32Addr,puBuf,u16Sz);
tsungta 28:2abbf8463fa8 250 #elif defined (CONF_WINC_USE_I2C)
tsungta 28:2abbf8463fa8 251 return nm_i2c_write_block(u32Addr,puBuf,u16Sz);
tsungta 28:2abbf8463fa8 252 #else
tsungta 28:2abbf8463fa8 253 #error "Plesae define bus usage"
tsungta 28:2abbf8463fa8 254 #endif
tsungta 28:2abbf8463fa8 255
tsungta 28:2abbf8463fa8 256 }
tsungta 28:2abbf8463fa8 257 /**
tsungta 28:2abbf8463fa8 258 * @fn nm_write_block
tsungta 28:2abbf8463fa8 259 * @brief Write block of data
tsungta 28:2abbf8463fa8 260 * @param [in] u32Addr
tsungta 28:2abbf8463fa8 261 * Start address
tsungta 28:2abbf8463fa8 262 * @param [in] puBuf
tsungta 28:2abbf8463fa8 263 * Pointer to the buffer holding the data to be written
tsungta 28:2abbf8463fa8 264 * @param [in] u32Sz
tsungta 28:2abbf8463fa8 265 * Number of bytes to write. The buffer size must be >= u32Sz
tsungta 28:2abbf8463fa8 266 * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
tsungta 28:2abbf8463fa8 267 * @author M. Abdelmawla
tsungta 28:2abbf8463fa8 268 * @date 11 July 2012
tsungta 28:2abbf8463fa8 269 * @version 1.0
tsungta 28:2abbf8463fa8 270 */
tsungta 28:2abbf8463fa8 271 sint8 nm_write_block(uint32 u32Addr, uint8 *puBuf, uint32 u32Sz)
tsungta 28:2abbf8463fa8 272 {
tsungta 28:2abbf8463fa8 273 uint16 u16MaxTrxSz = egstrNmBusCapabilities.u16MaxTrxSz - MAX_TRX_CFG_SZ;
tsungta 28:2abbf8463fa8 274 uint32 off = 0;
tsungta 28:2abbf8463fa8 275 sint8 s8Ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 276
tsungta 28:2abbf8463fa8 277 for(;;)
tsungta 28:2abbf8463fa8 278 {
tsungta 28:2abbf8463fa8 279 if(u32Sz <= u16MaxTrxSz)
tsungta 28:2abbf8463fa8 280 {
tsungta 28:2abbf8463fa8 281 s8Ret += p_nm_write_block(u32Addr, &puBuf[off], (uint16)u32Sz);
tsungta 28:2abbf8463fa8 282 break;
tsungta 28:2abbf8463fa8 283 }
tsungta 28:2abbf8463fa8 284 else
tsungta 28:2abbf8463fa8 285 {
tsungta 28:2abbf8463fa8 286 s8Ret += p_nm_write_block(u32Addr, &puBuf[off], u16MaxTrxSz);
tsungta 28:2abbf8463fa8 287 if(M2M_SUCCESS != s8Ret) break;
tsungta 28:2abbf8463fa8 288 u32Sz -= u16MaxTrxSz;
tsungta 28:2abbf8463fa8 289 off += u16MaxTrxSz;
tsungta 28:2abbf8463fa8 290 u32Addr += u16MaxTrxSz;
tsungta 28:2abbf8463fa8 291 }
tsungta 28:2abbf8463fa8 292 }
tsungta 28:2abbf8463fa8 293
tsungta 28:2abbf8463fa8 294 return s8Ret;
tsungta 28:2abbf8463fa8 295 }
tsungta 28:2abbf8463fa8 296
tsungta 28:2abbf8463fa8 297 #endif
tsungta 28:2abbf8463fa8 298
tsungta 28:2abbf8463fa8 299