Delta / NNN50_WIFI_API

NNN50 WIFI_API library

Dependents:   NNN50_CE_Test_UDP NNN50_linux_firmware NNN50_SoftAP_HelloWorld NNN50_BLEWIFISensor ... more

This is mbed compatible EthernetInterface lib exclude for Delta DFCM-NNN50 platform.

Additional information and examples can be found in mbed Handbook

wifi_host_driver/driver/source/m2m_ate_mode.c@32:8298a2fb074f, 2017-09-04 (annotated)

Committer:
tsungta
Date:
Mon Sep 04 05:40:11 2017 +0000
Revision:
32:8298a2fb074f
Parent:
28:2abbf8463fa8 
56:f4cc53f; Add getRSSI() to readout RSSI while connected with AP router; Add SSL support refer to TCPSocketConnection.connect()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tsungta 28:2abbf8463fa8 1 /**
tsungta 28:2abbf8463fa8 2 *
tsungta 28:2abbf8463fa8 3 * \file
tsungta 28:2abbf8463fa8 4 *
tsungta 28:2abbf8463fa8 5 * \brief NMC1500 Peripherials Application Interface.
tsungta 28:2abbf8463fa8 6 *
tsungta 28:2abbf8463fa8 7 * Copyright (c) 2016-2017 Atmel Corporation. All rights reserved.
tsungta 28:2abbf8463fa8 8 *
tsungta 28:2abbf8463fa8 9 * \asf_license_start
tsungta 28:2abbf8463fa8 10 *
tsungta 28:2abbf8463fa8 11 * \page License
tsungta 28:2abbf8463fa8 12 *
tsungta 28:2abbf8463fa8 13 * Redistribution and use in source and binary forms, with or without
tsungta 28:2abbf8463fa8 14 * modification, are permitted provided that the following conditions are met:
tsungta 28:2abbf8463fa8 15 *
tsungta 28:2abbf8463fa8 16 * 1. Redistributions of source code must retain the above copyright notice,
tsungta 28:2abbf8463fa8 17 * this list of conditions and the following disclaimer.
tsungta 28:2abbf8463fa8 18 *
tsungta 28:2abbf8463fa8 19 * 2. Redistributions in binary form must reproduce the above copyright notice,
tsungta 28:2abbf8463fa8 20 * this list of conditions and the following disclaimer in the documentation
tsungta 28:2abbf8463fa8 21 * and/or other materials provided with the distribution.
tsungta 28:2abbf8463fa8 22 *
tsungta 28:2abbf8463fa8 23 * 3. The name of Atmel may not be used to endorse or promote products derived
tsungta 28:2abbf8463fa8 24 * from this software without specific prior written permission.
tsungta 28:2abbf8463fa8 25 *
tsungta 28:2abbf8463fa8 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
tsungta 28:2abbf8463fa8 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
tsungta 28:2abbf8463fa8 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
tsungta 28:2abbf8463fa8 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
tsungta 28:2abbf8463fa8 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
tsungta 28:2abbf8463fa8 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
tsungta 28:2abbf8463fa8 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
tsungta 28:2abbf8463fa8 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
tsungta 28:2abbf8463fa8 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
tsungta 28:2abbf8463fa8 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
tsungta 28:2abbf8463fa8 36 * POSSIBILITY OF SUCH DAMAGE.
tsungta 28:2abbf8463fa8 37 *
tsungta 28:2abbf8463fa8 38 * \asf_license_stop
tsungta 28:2abbf8463fa8 39 *
tsungta 28:2abbf8463fa8 40 */
tsungta 28:2abbf8463fa8 41
tsungta 28:2abbf8463fa8 42 #ifdef _M2M_ATE_FW_
tsungta 28:2abbf8463fa8 43 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
tsungta 28:2abbf8463fa8 44 INCLUDES
tsungta 28:2abbf8463fa8 45 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
tsungta 28:2abbf8463fa8 46 #include "driver\include\m2m_ate_mode.h"
tsungta 28:2abbf8463fa8 47 #include "driver\source\nmasic.h"
tsungta 28:2abbf8463fa8 48 #include "driver\source\nmdrv.h"
tsungta 28:2abbf8463fa8 49 #include "m2m_hif.h"
tsungta 28:2abbf8463fa8 50 #include "driver\source\nmbus.h"
tsungta 28:2abbf8463fa8 51 #include "bsp\include\nm_bsp.h"
tsungta 28:2abbf8463fa8 52 #include "math.h"
tsungta 28:2abbf8463fa8 53
tsungta 28:2abbf8463fa8 54 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
tsungta 28:2abbf8463fa8 55 MACROS
tsungta 28:2abbf8463fa8 56 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
tsungta 28:2abbf8463fa8 57 #define rInterrupt_CORTUS_0 (0x10a8)
tsungta 28:2abbf8463fa8 58 #define rInterrupt_CORTUS_1 (0x10ac)
tsungta 28:2abbf8463fa8 59 #define rInterrupt_CORTUS_2 (0x10b0)
tsungta 28:2abbf8463fa8 60
tsungta 28:2abbf8463fa8 61 #define rBurstTx_NMI_TX_RATE (0x161d00)
tsungta 28:2abbf8463fa8 62 #define rBurstTx_NMI_NUM_TX_FRAMES (0x161d04)
tsungta 28:2abbf8463fa8 63 #define rBurstTx_NMI_TX_FRAME_LEN (0x161d08)
tsungta 28:2abbf8463fa8 64 #define rBurstTx_NMI_TX_CW_PARAM (0x161d0c)
tsungta 28:2abbf8463fa8 65 #define rBurstTx_NMI_TX_GAIN (0x161d10)
tsungta 28:2abbf8463fa8 66 #define rBurstTx_NMI_TX_DPD_CTRL (0x161d14)
tsungta 28:2abbf8463fa8 67 #define rBurstTx_NMI_USE_PMU (0x161d18)
tsungta 28:2abbf8463fa8 68 #define rBurstTx_NMI_TEST_CH (0x161d1c)
tsungta 28:2abbf8463fa8 69 #define rBurstTx_NMI_TX_PHY_CONT (0x161d20)
tsungta 28:2abbf8463fa8 70 #define rBurstTx_NMI_TX_CW_MODE (0x161d24)
tsungta 28:2abbf8463fa8 71 #define rBurstTx_NMI_TEST_XO_OFF (0x161d28)
tsungta 28:2abbf8463fa8 72 #define rBurstTx_NMI_USE_EFUSE_XO_OFF (0x161d2c)
tsungta 28:2abbf8463fa8 73
tsungta 28:2abbf8463fa8 74 #define rBurstTx_NMI_MAC_FILTER_ENABLE_DA (0x161d30)
tsungta 28:2abbf8463fa8 75 #define rBurstTx_NMI_MAC_ADDR_LO_PEER (0x161d34)
tsungta 28:2abbf8463fa8 76 #define rBurstTx_NMI_MAC_ADDR_LO_SELF (0x161d38)
tsungta 28:2abbf8463fa8 77 #define rBurstTx_NMI_MAC_ADDR_HI_PEER (0x161d3c)
tsungta 28:2abbf8463fa8 78 #define rBurstTx_NMI_MAC_ADDR_HI_SELF (0x161d40)
tsungta 28:2abbf8463fa8 79 #define rBurstTx_NMI_RX_PKT_CNT_SUCCESS (0x161d44)
tsungta 28:2abbf8463fa8 80 #define rBurstTx_NMI_RX_PKT_CNT_FAIL (0x161d48)
tsungta 28:2abbf8463fa8 81 #define rBurstTx_NMI_SET_SELF_MAC_ADDR (0x161d4c)
tsungta 28:2abbf8463fa8 82 #define rBurstTx_NMI_MAC_ADDR_LO_SA (0x161d50)
tsungta 28:2abbf8463fa8 83 #define rBurstTx_NMI_MAC_ADDR_HI_SA (0x161d54)
tsungta 28:2abbf8463fa8 84 #define rBurstTx_NMI_MAC_FILTER_ENABLE_SA (0x161d58)
tsungta 28:2abbf8463fa8 85
tsungta 28:2abbf8463fa8 86 #define rBurstRx_NMI_RX_ALL_PKTS_CONT (0x9898)
tsungta 28:2abbf8463fa8 87 #define rBurstRx_NMI_RX_ERR_PKTS_CONT (0x988c)
tsungta 28:2abbf8463fa8 88
tsungta 28:2abbf8463fa8 89 #define TX_DGAIN_MAX_NUM_REGS (4)
tsungta 28:2abbf8463fa8 90 #define TX_DGAIN_REG_BASE_ADDRESS (0x1240)
tsungta 28:2abbf8463fa8 91 #define TX_GAIN_CODE_MAX_NUM_REGS (3)
tsungta 28:2abbf8463fa8 92 #define TX_GAIN_CODE_BASE_ADDRESS (0x1250)
tsungta 28:2abbf8463fa8 93 #define TX_PA_MAX_NUM_REGS (3)
tsungta 28:2abbf8463fa8 94 #define TX_PA_BASE_ADDRESS (0x1e58)
tsungta 28:2abbf8463fa8 95 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
tsungta 28:2abbf8463fa8 96 VARIABLES
tsungta 28:2abbf8463fa8 97 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
tsungta 28:2abbf8463fa8 98 volatile static uint8 gu8AteIsRunning = 0; /*!< ATE firmware status, 1 means ATE is running otherwise stopped */
tsungta 28:2abbf8463fa8 99 volatile static uint8 gu8RxState = 0; /*!< RX status, 1 means Rx is running otherwise stopped */
tsungta 28:2abbf8463fa8 100 volatile static uint8 gu8TxState = 0; /*!< TX status, 1 means Tx is running otherwise stopped */
tsungta 28:2abbf8463fa8 101 volatile static uint32 gaAteFwTxRates[M2M_ATE_MAX_NUM_OF_RATES] =
tsungta 28:2abbf8463fa8 102 {
tsungta 28:2abbf8463fa8 103 0x01, 0x02, 0x05, 0x0B, /*B-Rats*/
tsungta 28:2abbf8463fa8 104 0x06, 0x09, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x36, /*G-Rats*/
tsungta 28:2abbf8463fa8 105 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87 /*N-Rats*/
tsungta 28:2abbf8463fa8 106 };
tsungta 28:2abbf8463fa8 107
tsungta 28:2abbf8463fa8 108 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
tsungta 28:2abbf8463fa8 109 STATIC FUNCTIONS
tsungta 28:2abbf8463fa8 110 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
tsungta 28:2abbf8463fa8 111 static void m2m_ate_set_rx_status(uint8 u8Value)
tsungta 28:2abbf8463fa8 112 {
tsungta 28:2abbf8463fa8 113 gu8RxState = u8Value;
tsungta 28:2abbf8463fa8 114 }
tsungta 28:2abbf8463fa8 115
tsungta 28:2abbf8463fa8 116 static void m2m_ate_set_tx_status(uint8 u8Value)
tsungta 28:2abbf8463fa8 117 {
tsungta 28:2abbf8463fa8 118 gu8TxState = u8Value;
tsungta 28:2abbf8463fa8 119 }
tsungta 28:2abbf8463fa8 120
tsungta 28:2abbf8463fa8 121 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*
tsungta 28:2abbf8463fa8 122 FUNCTION IMPLEMENTATION
tsungta 28:2abbf8463fa8 123 *=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
tsungta 28:2abbf8463fa8 124 /*!
tsungta 28:2abbf8463fa8 125 @fn \
tsungta 28:2abbf8463fa8 126 sint8 m2m_ate_init(void);
tsungta 28:2abbf8463fa8 127
tsungta 28:2abbf8463fa8 128 @brief
tsungta 28:2abbf8463fa8 129 This function used to download ATE firmware from flash and start it
tsungta 28:2abbf8463fa8 130
tsungta 28:2abbf8463fa8 131 @return
tsungta 28:2abbf8463fa8 132 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 133 */
tsungta 28:2abbf8463fa8 134 sint8 m2m_ate_init(void)
tsungta 28:2abbf8463fa8 135 {
tsungta 28:2abbf8463fa8 136 sint8 s8Ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 137 uint8 u8WifiMode = M2M_WIFI_MODE_ATE_HIGH;
tsungta 28:2abbf8463fa8 138
tsungta 28:2abbf8463fa8 139 s8Ret = nm_drv_init(&u8WifiMode);
tsungta 28:2abbf8463fa8 140
tsungta 28:2abbf8463fa8 141 return s8Ret;
tsungta 28:2abbf8463fa8 142 }
tsungta 28:2abbf8463fa8 143
tsungta 28:2abbf8463fa8 144 /*!
tsungta 28:2abbf8463fa8 145 @fn \
tsungta 28:2abbf8463fa8 146 sint8 m2m_ate_init(tstrM2mAteInit *pstrInit);
tsungta 28:2abbf8463fa8 147
tsungta 28:2abbf8463fa8 148 @brief
tsungta 28:2abbf8463fa8 149 This function used to download ATE firmware from flash and start it
tsungta 28:2abbf8463fa8 150
tsungta 28:2abbf8463fa8 151 @return
tsungta 28:2abbf8463fa8 152 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 153 */
tsungta 28:2abbf8463fa8 154 sint8 m2m_ate_init_param(tstrM2mAteInit *pstrInit)
tsungta 28:2abbf8463fa8 155 {
tsungta 28:2abbf8463fa8 156 sint8 s8Ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 157
tsungta 28:2abbf8463fa8 158 s8Ret = nm_drv_init((void*)&pstrInit->u8RxPwrMode);
tsungta 28:2abbf8463fa8 159
tsungta 28:2abbf8463fa8 160 return s8Ret;
tsungta 28:2abbf8463fa8 161 }
tsungta 28:2abbf8463fa8 162
tsungta 28:2abbf8463fa8 163 /*!
tsungta 28:2abbf8463fa8 164 @fn \
tsungta 28:2abbf8463fa8 165 sint8 m2m_ate_deinit(void);
tsungta 28:2abbf8463fa8 166
tsungta 28:2abbf8463fa8 167 @brief
tsungta 28:2abbf8463fa8 168 De-Initialization of ATE firmware mode
tsungta 28:2abbf8463fa8 169
tsungta 28:2abbf8463fa8 170 @return
tsungta 28:2abbf8463fa8 171 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 172 */
tsungta 28:2abbf8463fa8 173 sint8 m2m_ate_deinit(void)
tsungta 28:2abbf8463fa8 174 {
tsungta 28:2abbf8463fa8 175 return nm_drv_deinit(NULL);
tsungta 28:2abbf8463fa8 176 }
tsungta 28:2abbf8463fa8 177
tsungta 28:2abbf8463fa8 178 /*!
tsungta 28:2abbf8463fa8 179 @fn \
tsungta 28:2abbf8463fa8 180 sint8 m2m_ate_set_fw_state(uint8);
tsungta 28:2abbf8463fa8 181
tsungta 28:2abbf8463fa8 182 @brief
tsungta 28:2abbf8463fa8 183 This function used to change ATE firmware status from running to stopped or vice versa.
tsungta 28:2abbf8463fa8 184
tsungta 28:2abbf8463fa8 185 @param [in] u8State
tsungta 28:2abbf8463fa8 186 Required state of ATE firmware, one of \ref tenuM2mAteFwState enumeration values.
tsungta 28:2abbf8463fa8 187 @return
tsungta 28:2abbf8463fa8 188 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 189 \sa
tsungta 28:2abbf8463fa8 190 m2m_ate_init
tsungta 28:2abbf8463fa8 191 */
tsungta 28:2abbf8463fa8 192 sint8 m2m_ate_set_fw_state(uint8 u8State)
tsungta 28:2abbf8463fa8 193 {
tsungta 28:2abbf8463fa8 194 sint8 s8Ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 195 uint32_t u32Val = 0;
tsungta 28:2abbf8463fa8 196
tsungta 28:2abbf8463fa8 197 if((M2M_ATE_FW_STATE_STOP == u8State) && (M2M_ATE_FW_STATE_STOP != gu8AteIsRunning))
tsungta 28:2abbf8463fa8 198 {
tsungta 28:2abbf8463fa8 199 u32Val = nm_read_reg(rNMI_GLB_RESET);
tsungta 28:2abbf8463fa8 200 u32Val &= ~(1 << 10);
tsungta 28:2abbf8463fa8 201 s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val);
tsungta 28:2abbf8463fa8 202 gu8AteIsRunning = M2M_ATE_FW_STATE_STOP;
tsungta 28:2abbf8463fa8 203 }
tsungta 28:2abbf8463fa8 204 else if((M2M_ATE_FW_STATE_RUN == u8State) && (M2M_ATE_FW_STATE_RUN != gu8AteIsRunning))
tsungta 28:2abbf8463fa8 205 {
tsungta 28:2abbf8463fa8 206 /* 0x1118[0]=0 at power-on-reset: pad-based control. */
tsungta 28:2abbf8463fa8 207 /* Switch cortus reset register to register control. 0x1118[0]=1. */
tsungta 28:2abbf8463fa8 208 u32Val = nm_read_reg(rNMI_BOOT_RESET_MUX);
tsungta 28:2abbf8463fa8 209 u32Val |= (1 << 0);
tsungta 28:2abbf8463fa8 210 s8Ret = nm_write_reg(rNMI_BOOT_RESET_MUX, u32Val);
tsungta 28:2abbf8463fa8 211 if(M2M_SUCCESS != s8Ret)
tsungta 28:2abbf8463fa8 212 {
tsungta 28:2abbf8463fa8 213 goto __EXIT;
tsungta 28:2abbf8463fa8 214 }
tsungta 28:2abbf8463fa8 215 /**
tsungta 28:2abbf8463fa8 216 Write the firmware download complete magic value 0x10ADD09E at
tsungta 28:2abbf8463fa8 217 location 0xFFFF000C (Cortus map) or C000C (AHB map).
tsungta 28:2abbf8463fa8 218 This will let the boot-rom code execute from RAM.
tsungta 28:2abbf8463fa8 219 **/
tsungta 28:2abbf8463fa8 220 s8Ret = nm_write_reg(0xc0000, 0x71);
tsungta 28:2abbf8463fa8 221 if(M2M_SUCCESS != s8Ret)
tsungta 28:2abbf8463fa8 222 {
tsungta 28:2abbf8463fa8 223 goto __EXIT;
tsungta 28:2abbf8463fa8 224 }
tsungta 28:2abbf8463fa8 225
tsungta 28:2abbf8463fa8 226 u32Val = nm_read_reg(rNMI_GLB_RESET);
tsungta 28:2abbf8463fa8 227 if((u32Val & (1ul << 10)) == (1ul << 10))
tsungta 28:2abbf8463fa8 228 {
tsungta 28:2abbf8463fa8 229 u32Val &= ~(1ul << 10);
tsungta 28:2abbf8463fa8 230 s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val);
tsungta 28:2abbf8463fa8 231 if(M2M_SUCCESS != s8Ret)
tsungta 28:2abbf8463fa8 232 {
tsungta 28:2abbf8463fa8 233 goto __EXIT;
tsungta 28:2abbf8463fa8 234 }
tsungta 28:2abbf8463fa8 235 }
tsungta 28:2abbf8463fa8 236
tsungta 28:2abbf8463fa8 237 u32Val |= (1ul << 10);
tsungta 28:2abbf8463fa8 238 s8Ret = nm_write_reg(rNMI_GLB_RESET, u32Val);
tsungta 28:2abbf8463fa8 239 if(M2M_SUCCESS != s8Ret)
tsungta 28:2abbf8463fa8 240 {
tsungta 28:2abbf8463fa8 241 goto __EXIT;
tsungta 28:2abbf8463fa8 242 }
tsungta 28:2abbf8463fa8 243 gu8AteIsRunning = M2M_ATE_FW_STATE_RUN;
tsungta 28:2abbf8463fa8 244 }
tsungta 28:2abbf8463fa8 245 else
tsungta 28:2abbf8463fa8 246 {
tsungta 28:2abbf8463fa8 247 s8Ret = M2M_ATE_ERR_UNHANDLED_CASE;
tsungta 28:2abbf8463fa8 248 }
tsungta 28:2abbf8463fa8 249
tsungta 28:2abbf8463fa8 250 __EXIT:
tsungta 28:2abbf8463fa8 251 if((M2M_SUCCESS == s8Ret) && (M2M_ATE_FW_STATE_RUN == gu8AteIsRunning))
tsungta 28:2abbf8463fa8 252 {
tsungta 28:2abbf8463fa8 253 nm_bsp_sleep(500); /*wait for ATE firmware start up*/
tsungta 28:2abbf8463fa8 254 }
tsungta 28:2abbf8463fa8 255 return s8Ret;
tsungta 28:2abbf8463fa8 256 }
tsungta 28:2abbf8463fa8 257
tsungta 28:2abbf8463fa8 258 /*!
tsungta 28:2abbf8463fa8 259 @fn \
tsungta 28:2abbf8463fa8 260 sint8 m2m_ate_get_fw_state(uint8);
tsungta 28:2abbf8463fa8 261
tsungta 28:2abbf8463fa8 262 @brief
tsungta 28:2abbf8463fa8 263 This function used to return status of ATE firmware.
tsungta 28:2abbf8463fa8 264
tsungta 28:2abbf8463fa8 265 @return
tsungta 28:2abbf8463fa8 266 The function SHALL return status of ATE firmware, one of \ref tenuM2mAteFwState enumeration values.
tsungta 28:2abbf8463fa8 267 \sa
tsungta 28:2abbf8463fa8 268 m2m_ate_init, m2m_ate_set_fw_state
tsungta 28:2abbf8463fa8 269 */
tsungta 28:2abbf8463fa8 270 sint8 m2m_ate_get_fw_state(void)
tsungta 28:2abbf8463fa8 271 {
tsungta 28:2abbf8463fa8 272 return gu8AteIsRunning;
tsungta 28:2abbf8463fa8 273 }
tsungta 28:2abbf8463fa8 274
tsungta 28:2abbf8463fa8 275 /*!
tsungta 28:2abbf8463fa8 276 @fn \
tsungta 28:2abbf8463fa8 277 uint32 m2m_ate_get_tx_rate(uint8);
tsungta 28:2abbf8463fa8 278
tsungta 28:2abbf8463fa8 279 @brief
tsungta 28:2abbf8463fa8 280 This function used to return value of TX rate required by application developer.
tsungta 28:2abbf8463fa8 281
tsungta 28:2abbf8463fa8 282 @param [in] u8Index
tsungta 28:2abbf8463fa8 283 Index of required rate , one of \ref tenuM2mAteTxIndexOfRates enumeration values.
tsungta 28:2abbf8463fa8 284 @return
tsungta 28:2abbf8463fa8 285 The function SHALL return 0 for in case of failure otherwise selected rate value.
tsungta 28:2abbf8463fa8 286 \sa
tsungta 28:2abbf8463fa8 287 tenuM2mAteTxIndexOfRates
tsungta 28:2abbf8463fa8 288 */
tsungta 28:2abbf8463fa8 289 uint32 m2m_ate_get_tx_rate(uint8 u8Index)
tsungta 28:2abbf8463fa8 290 {
tsungta 28:2abbf8463fa8 291 if(M2M_ATE_MAX_NUM_OF_RATES <= u8Index)
tsungta 28:2abbf8463fa8 292 {
tsungta 28:2abbf8463fa8 293 return 0;
tsungta 28:2abbf8463fa8 294 }
tsungta 28:2abbf8463fa8 295 return gaAteFwTxRates[u8Index];
tsungta 28:2abbf8463fa8 296 }
tsungta 28:2abbf8463fa8 297
tsungta 28:2abbf8463fa8 298 /*!
tsungta 28:2abbf8463fa8 299 @fn \
tsungta 28:2abbf8463fa8 300 sint8 m2m_ate_get_tx_status(void);
tsungta 28:2abbf8463fa8 301
tsungta 28:2abbf8463fa8 302 @brief
tsungta 28:2abbf8463fa8 303 This function used to return status of TX test case either running or stopped.
tsungta 28:2abbf8463fa8 304
tsungta 28:2abbf8463fa8 305 @return
tsungta 28:2abbf8463fa8 306 The function SHALL return status of ATE firmware, 1 if TX is running otherwise 0.
tsungta 28:2abbf8463fa8 307 \sa
tsungta 28:2abbf8463fa8 308 m2m_ate_start_tx, m2m_ate_stop_tx
tsungta 28:2abbf8463fa8 309 */
tsungta 28:2abbf8463fa8 310 sint8 m2m_ate_get_tx_status(void)
tsungta 28:2abbf8463fa8 311 {
tsungta 28:2abbf8463fa8 312 return gu8TxState;
tsungta 28:2abbf8463fa8 313 }
tsungta 28:2abbf8463fa8 314
tsungta 28:2abbf8463fa8 315 /*!
tsungta 28:2abbf8463fa8 316 @fn \
tsungta 28:2abbf8463fa8 317 sint8 m2m_ate_start_tx(tstrM2mAteTx *)
tsungta 28:2abbf8463fa8 318
tsungta 28:2abbf8463fa8 319 @brief
tsungta 28:2abbf8463fa8 320 This function used to start TX test case.
tsungta 28:2abbf8463fa8 321
tsungta 28:2abbf8463fa8 322 @param [in] strM2mAteTx
tsungta 28:2abbf8463fa8 323 Type of \ref tstrM2mAteTx, with the values required to enable TX test case. You must use \ref m2m_ate_init first.
tsungta 28:2abbf8463fa8 324 @return
tsungta 28:2abbf8463fa8 325 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 326 \sa
tsungta 28:2abbf8463fa8 327 m2m_ate_init, m2m_ate_stop_tx, m2m_ate_get_tx_status
tsungta 28:2abbf8463fa8 328 */
tsungta 28:2abbf8463fa8 329 sint8 m2m_ate_start_tx(tstrM2mAteTx * strM2mAteTx)
tsungta 28:2abbf8463fa8 330 {
tsungta 28:2abbf8463fa8 331 sint8 s8Ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 332 uint8 u8LoopCntr = 0;
tsungta 28:2abbf8463fa8 333 uint32_t val32;
tsungta 28:2abbf8463fa8 334
tsungta 28:2abbf8463fa8 335
tsungta 28:2abbf8463fa8 336 if(NULL == strM2mAteTx)
tsungta 28:2abbf8463fa8 337 {
tsungta 28:2abbf8463fa8 338 s8Ret = M2M_ATE_ERR_VALIDATE;
tsungta 28:2abbf8463fa8 339 goto __EXIT;
tsungta 28:2abbf8463fa8 340 }
tsungta 28:2abbf8463fa8 341
tsungta 28:2abbf8463fa8 342 if(0 != m2m_ate_get_tx_status())
tsungta 28:2abbf8463fa8 343 {
tsungta 28:2abbf8463fa8 344 s8Ret = M2M_ATE_ERR_TX_ALREADY_RUNNING;
tsungta 28:2abbf8463fa8 345 goto __EXIT;
tsungta 28:2abbf8463fa8 346 }
tsungta 28:2abbf8463fa8 347
tsungta 28:2abbf8463fa8 348 if(0 != m2m_ate_get_rx_status())
tsungta 28:2abbf8463fa8 349 {
tsungta 28:2abbf8463fa8 350 s8Ret = M2M_ATE_ERR_RX_ALREADY_RUNNING;
tsungta 28:2abbf8463fa8 351 goto __EXIT;
tsungta 28:2abbf8463fa8 352 }
tsungta 28:2abbf8463fa8 353
tsungta 28:2abbf8463fa8 354 if( (strM2mAteTx->channel_num < M2M_ATE_CHANNEL_1) ||
tsungta 28:2abbf8463fa8 355 (strM2mAteTx->channel_num > M2M_ATE_CHANNEL_14) ||
tsungta 28:2abbf8463fa8 356 (strM2mAteTx->tx_gain_sel < M2M_ATE_TX_GAIN_DYNAMIC) ||
tsungta 28:2abbf8463fa8 357 (strM2mAteTx->tx_gain_sel > M2M_ATE_TX_GAIN_TELEC) ||
tsungta 28:2abbf8463fa8 358 (strM2mAteTx->frame_len > M2M_ATE_MAX_FRAME_LENGTH) ||
tsungta 28:2abbf8463fa8 359 (strM2mAteTx->frame_len < M2M_ATE_MIN_FRAME_LENGTH)
tsungta 28:2abbf8463fa8 360 )
tsungta 28:2abbf8463fa8 361 {
tsungta 28:2abbf8463fa8 362 s8Ret = M2M_ATE_ERR_VALIDATE;
tsungta 28:2abbf8463fa8 363 goto __EXIT;
tsungta 28:2abbf8463fa8 364 }
tsungta 28:2abbf8463fa8 365
tsungta 28:2abbf8463fa8 366 if( (strM2mAteTx->duty_cycle < M2M_ATE_TX_DUTY_MAX_VALUE /*1*/) ||
tsungta 28:2abbf8463fa8 367 (strM2mAteTx->duty_cycle > M2M_ATE_TX_DUTY_MIN_VALUE /*10*/ ) ||
tsungta 28:2abbf8463fa8 368 (strM2mAteTx->dpd_ctrl < M2M_ATE_TX_DPD_DYNAMIC) ||
tsungta 28:2abbf8463fa8 369 (strM2mAteTx->dpd_ctrl > M2M_ATE_TX_DPD_ENABLED) ||
tsungta 28:2abbf8463fa8 370 (strM2mAteTx->use_pmu > M2M_ATE_PMU_ENABLE) ||
tsungta 28:2abbf8463fa8 371 (strM2mAteTx->phy_burst_tx < M2M_ATE_TX_SRC_MAC) ||
tsungta 28:2abbf8463fa8 372 (strM2mAteTx->phy_burst_tx > M2M_ATE_TX_SRC_PHY) ||
tsungta 28:2abbf8463fa8 373 (strM2mAteTx->cw_tx < M2M_ATE_TX_MODE_NORM) ||
tsungta 28:2abbf8463fa8 374 (strM2mAteTx->cw_tx > M2M_ATE_TX_MODE_CW)
tsungta 28:2abbf8463fa8 375 )
tsungta 28:2abbf8463fa8 376 {
tsungta 28:2abbf8463fa8 377 s8Ret = M2M_ATE_ERR_VALIDATE;
tsungta 28:2abbf8463fa8 378 goto __EXIT;
tsungta 28:2abbf8463fa8 379 }
tsungta 28:2abbf8463fa8 380
tsungta 28:2abbf8463fa8 381 for(u8LoopCntr=0; u8LoopCntr<M2M_ATE_MAX_NUM_OF_RATES; u8LoopCntr++)
tsungta 28:2abbf8463fa8 382 {
tsungta 28:2abbf8463fa8 383 if(gaAteFwTxRates[u8LoopCntr] == strM2mAteTx->data_rate)
tsungta 28:2abbf8463fa8 384 {
tsungta 28:2abbf8463fa8 385 break;
tsungta 28:2abbf8463fa8 386 }
tsungta 28:2abbf8463fa8 387 }
tsungta 28:2abbf8463fa8 388
tsungta 28:2abbf8463fa8 389 if(M2M_ATE_MAX_NUM_OF_RATES == u8LoopCntr)
tsungta 28:2abbf8463fa8 390 {
tsungta 28:2abbf8463fa8 391 s8Ret = M2M_ATE_ERR_VALIDATE;
tsungta 28:2abbf8463fa8 392 goto __EXIT;
tsungta 28:2abbf8463fa8 393 }
tsungta 28:2abbf8463fa8 394
tsungta 28:2abbf8463fa8 395
tsungta 28:2abbf8463fa8 396
tsungta 28:2abbf8463fa8 397 s8Ret += nm_write_reg(rBurstTx_NMI_USE_PMU, strM2mAteTx->use_pmu);
tsungta 28:2abbf8463fa8 398 s8Ret += nm_write_reg(rBurstTx_NMI_TX_PHY_CONT, strM2mAteTx->phy_burst_tx);
tsungta 28:2abbf8463fa8 399 s8Ret += nm_write_reg(rBurstTx_NMI_NUM_TX_FRAMES, strM2mAteTx->num_frames);
tsungta 28:2abbf8463fa8 400 s8Ret += nm_write_reg(rBurstTx_NMI_TX_GAIN, strM2mAteTx->tx_gain_sel);
tsungta 28:2abbf8463fa8 401 s8Ret += nm_write_reg(rBurstTx_NMI_TEST_CH, strM2mAteTx->channel_num);
tsungta 28:2abbf8463fa8 402 s8Ret += nm_write_reg(rBurstTx_NMI_TX_FRAME_LEN, strM2mAteTx->frame_len);
tsungta 28:2abbf8463fa8 403 s8Ret += nm_write_reg(rBurstTx_NMI_TX_CW_PARAM, strM2mAteTx->duty_cycle);
tsungta 28:2abbf8463fa8 404 s8Ret += nm_write_reg(rBurstTx_NMI_TX_DPD_CTRL, strM2mAteTx->dpd_ctrl);
tsungta 28:2abbf8463fa8 405 s8Ret += nm_write_reg(rBurstTx_NMI_TX_RATE, strM2mAteTx->data_rate);
tsungta 28:2abbf8463fa8 406 s8Ret += nm_write_reg(rBurstTx_NMI_TX_CW_MODE, strM2mAteTx->cw_tx);
tsungta 28:2abbf8463fa8 407 s8Ret += nm_write_reg(rBurstTx_NMI_TEST_XO_OFF, strM2mAteTx->xo_offset_x1000);
tsungta 28:2abbf8463fa8 408 s8Ret += nm_write_reg(rBurstTx_NMI_USE_EFUSE_XO_OFF, strM2mAteTx->use_efuse_xo_offset);
tsungta 28:2abbf8463fa8 409
tsungta 28:2abbf8463fa8 410 val32 = strM2mAteTx->peer_mac_addr[5] << 0;
tsungta 28:2abbf8463fa8 411 val32 |= strM2mAteTx->peer_mac_addr[4] << 8;
tsungta 28:2abbf8463fa8 412 val32 |= strM2mAteTx->peer_mac_addr[3] << 16;
tsungta 28:2abbf8463fa8 413 nm_write_reg(rBurstTx_NMI_MAC_ADDR_LO_PEER, val32 );
tsungta 28:2abbf8463fa8 414
tsungta 28:2abbf8463fa8 415 val32 = strM2mAteTx->peer_mac_addr[2] << 0;
tsungta 28:2abbf8463fa8 416 val32 |= strM2mAteTx->peer_mac_addr[1] << 8;
tsungta 28:2abbf8463fa8 417 val32 |= strM2mAteTx->peer_mac_addr[0] << 16;
tsungta 28:2abbf8463fa8 418 nm_write_reg(rBurstTx_NMI_MAC_ADDR_HI_PEER, val32 );
tsungta 28:2abbf8463fa8 419
tsungta 28:2abbf8463fa8 420 if(M2M_SUCCESS == s8Ret)
tsungta 28:2abbf8463fa8 421 {
tsungta 28:2abbf8463fa8 422 s8Ret += nm_write_reg(rInterrupt_CORTUS_0, 1); /*Interrupt Cortus*/
tsungta 28:2abbf8463fa8 423 m2m_ate_set_tx_status(1);
tsungta 28:2abbf8463fa8 424 nm_bsp_sleep(200); /*Recommended*/
tsungta 28:2abbf8463fa8 425 }
tsungta 28:2abbf8463fa8 426
tsungta 28:2abbf8463fa8 427 __EXIT:
tsungta 28:2abbf8463fa8 428 return s8Ret;
tsungta 28:2abbf8463fa8 429 }
tsungta 28:2abbf8463fa8 430
tsungta 28:2abbf8463fa8 431 /*!
tsungta 28:2abbf8463fa8 432 @fn \
tsungta 28:2abbf8463fa8 433 sint8 m2m_ate_stop_tx(void)
tsungta 28:2abbf8463fa8 434
tsungta 28:2abbf8463fa8 435 @brief
tsungta 28:2abbf8463fa8 436 This function used to stop TX test case.
tsungta 28:2abbf8463fa8 437
tsungta 28:2abbf8463fa8 438 @return
tsungta 28:2abbf8463fa8 439 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 440 \sa
tsungta 28:2abbf8463fa8 441 m2m_ate_init, m2m_ate_start_tx, m2m_ate_get_tx_status
tsungta 28:2abbf8463fa8 442 */
tsungta 28:2abbf8463fa8 443 sint8 m2m_ate_stop_tx(void)
tsungta 28:2abbf8463fa8 444 {
tsungta 28:2abbf8463fa8 445 sint8 s8Ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 446
tsungta 28:2abbf8463fa8 447 s8Ret = nm_write_reg(rInterrupt_CORTUS_1, 1);
tsungta 28:2abbf8463fa8 448 if(M2M_SUCCESS == s8Ret)
tsungta 28:2abbf8463fa8 449 {
tsungta 28:2abbf8463fa8 450 m2m_ate_set_tx_status(0);
tsungta 28:2abbf8463fa8 451 }
tsungta 28:2abbf8463fa8 452
tsungta 28:2abbf8463fa8 453 return s8Ret;
tsungta 28:2abbf8463fa8 454 }
tsungta 28:2abbf8463fa8 455
tsungta 28:2abbf8463fa8 456 /*!
tsungta 28:2abbf8463fa8 457 @fn \
tsungta 28:2abbf8463fa8 458 sint8 m2m_ate_get_rx_status(uint8);
tsungta 28:2abbf8463fa8 459
tsungta 28:2abbf8463fa8 460 @brief
tsungta 28:2abbf8463fa8 461 This function used to return status of RX test case either running or stopped.
tsungta 28:2abbf8463fa8 462
tsungta 28:2abbf8463fa8 463 @return
tsungta 28:2abbf8463fa8 464 The function SHALL return status of ATE firmware, 1 if RX is running otherwise 0.
tsungta 28:2abbf8463fa8 465 \sa
tsungta 28:2abbf8463fa8 466 m2m_ate_start_rx, m2m_ate_stop_rx
tsungta 28:2abbf8463fa8 467 */
tsungta 28:2abbf8463fa8 468 sint8 m2m_ate_get_rx_status(void)
tsungta 28:2abbf8463fa8 469 {
tsungta 28:2abbf8463fa8 470 return gu8RxState;
tsungta 28:2abbf8463fa8 471 }
tsungta 28:2abbf8463fa8 472
tsungta 28:2abbf8463fa8 473 /*!
tsungta 28:2abbf8463fa8 474 @fn \
tsungta 28:2abbf8463fa8 475 sint8 m2m_ate_start_rx(tstrM2mAteRx *)
tsungta 28:2abbf8463fa8 476
tsungta 28:2abbf8463fa8 477 @brief
tsungta 28:2abbf8463fa8 478 This function used to start RX test case.
tsungta 28:2abbf8463fa8 479
tsungta 28:2abbf8463fa8 480 @param [in] strM2mAteRx
tsungta 28:2abbf8463fa8 481 Type of \ref tstrM2mAteRx, with the values required to enable RX test case. You must use \ref m2m_ate_init first.
tsungta 28:2abbf8463fa8 482 @return
tsungta 28:2abbf8463fa8 483 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 484 \sa
tsungta 28:2abbf8463fa8 485 m2m_ate_init, m2m_ate_stop_rx, m2m_ate_get_rx_status
tsungta 28:2abbf8463fa8 486 */
tsungta 28:2abbf8463fa8 487 sint8 m2m_ate_start_rx(tstrM2mAteRx * strM2mAteRxStr)
tsungta 28:2abbf8463fa8 488 {
tsungta 28:2abbf8463fa8 489 sint8 s8Ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 490 uint32 val32;
tsungta 28:2abbf8463fa8 491 if(NULL == strM2mAteRxStr)
tsungta 28:2abbf8463fa8 492 {
tsungta 28:2abbf8463fa8 493 s8Ret = M2M_ATE_ERR_VALIDATE;
tsungta 28:2abbf8463fa8 494 goto __EXIT;
tsungta 28:2abbf8463fa8 495 }
tsungta 28:2abbf8463fa8 496
tsungta 28:2abbf8463fa8 497 if(0 != m2m_ate_get_tx_status())
tsungta 28:2abbf8463fa8 498 {
tsungta 28:2abbf8463fa8 499 s8Ret = M2M_ATE_ERR_TX_ALREADY_RUNNING;
tsungta 28:2abbf8463fa8 500 goto __EXIT;
tsungta 28:2abbf8463fa8 501 }
tsungta 28:2abbf8463fa8 502
tsungta 28:2abbf8463fa8 503 if(0 != m2m_ate_get_rx_status())
tsungta 28:2abbf8463fa8 504 {
tsungta 28:2abbf8463fa8 505 s8Ret = M2M_ATE_ERR_RX_ALREADY_RUNNING;
tsungta 28:2abbf8463fa8 506 goto __EXIT;
tsungta 28:2abbf8463fa8 507 }
tsungta 28:2abbf8463fa8 508
tsungta 28:2abbf8463fa8 509 if( (strM2mAteRxStr->channel_num < M2M_ATE_CHANNEL_1) ||
tsungta 28:2abbf8463fa8 510 (strM2mAteRxStr->channel_num > M2M_ATE_CHANNEL_14)||
tsungta 28:2abbf8463fa8 511 (strM2mAteRxStr->use_pmu > M2M_ATE_PMU_ENABLE)
tsungta 28:2abbf8463fa8 512 )
tsungta 28:2abbf8463fa8 513 {
tsungta 28:2abbf8463fa8 514 s8Ret = M2M_ATE_ERR_VALIDATE;
tsungta 28:2abbf8463fa8 515 goto __EXIT;
tsungta 28:2abbf8463fa8 516 }
tsungta 28:2abbf8463fa8 517
tsungta 28:2abbf8463fa8 518 s8Ret += nm_write_reg(rBurstTx_NMI_TEST_CH, strM2mAteRxStr->channel_num);
tsungta 28:2abbf8463fa8 519 s8Ret += nm_write_reg(rBurstTx_NMI_USE_PMU, strM2mAteRxStr->use_pmu);
tsungta 28:2abbf8463fa8 520 s8Ret += nm_write_reg(rBurstTx_NMI_TEST_XO_OFF, strM2mAteRxStr->xo_offset_x1000);
tsungta 28:2abbf8463fa8 521 s8Ret += nm_write_reg(rBurstTx_NMI_USE_EFUSE_XO_OFF, strM2mAteRxStr->use_efuse_xo_offset);
tsungta 28:2abbf8463fa8 522
tsungta 28:2abbf8463fa8 523 if(strM2mAteRxStr->override_self_mac_addr)
tsungta 28:2abbf8463fa8 524 {
tsungta 28:2abbf8463fa8 525 val32 = strM2mAteRxStr->self_mac_addr[5] << 0;
tsungta 28:2abbf8463fa8 526 val32 |= strM2mAteRxStr->self_mac_addr[4] << 8;
tsungta 28:2abbf8463fa8 527 val32 |= strM2mAteRxStr->self_mac_addr[3] << 16;
tsungta 28:2abbf8463fa8 528 nm_write_reg(rBurstTx_NMI_MAC_ADDR_LO_SELF, val32 );
tsungta 28:2abbf8463fa8 529
tsungta 28:2abbf8463fa8 530 val32 = strM2mAteRxStr->self_mac_addr[2] << 0;
tsungta 28:2abbf8463fa8 531 val32 |= strM2mAteRxStr->self_mac_addr[1] << 8;
tsungta 28:2abbf8463fa8 532 val32 |= strM2mAteRxStr->self_mac_addr[0] << 16;
tsungta 28:2abbf8463fa8 533 nm_write_reg(rBurstTx_NMI_MAC_ADDR_HI_SELF, val32 );
tsungta 28:2abbf8463fa8 534 }
tsungta 28:2abbf8463fa8 535
tsungta 28:2abbf8463fa8 536 if(strM2mAteRxStr->mac_filter_en_sa)
tsungta 28:2abbf8463fa8 537 {
tsungta 28:2abbf8463fa8 538 val32 = strM2mAteRxStr->peer_mac_addr[5] << 0;
tsungta 28:2abbf8463fa8 539 val32 |= strM2mAteRxStr->peer_mac_addr[4] << 8;
tsungta 28:2abbf8463fa8 540 val32 |= strM2mAteRxStr->peer_mac_addr[3] << 16;
tsungta 28:2abbf8463fa8 541 nm_write_reg(rBurstTx_NMI_MAC_ADDR_LO_SA, val32 );
tsungta 28:2abbf8463fa8 542
tsungta 28:2abbf8463fa8 543 val32 = strM2mAteRxStr->peer_mac_addr[2] << 0;
tsungta 28:2abbf8463fa8 544 val32 |= strM2mAteRxStr->peer_mac_addr[1] << 8;
tsungta 28:2abbf8463fa8 545 val32 |= strM2mAteRxStr->peer_mac_addr[0] << 16;
tsungta 28:2abbf8463fa8 546 nm_write_reg(rBurstTx_NMI_MAC_ADDR_HI_SA, val32 );
tsungta 28:2abbf8463fa8 547 }
tsungta 28:2abbf8463fa8 548
tsungta 28:2abbf8463fa8 549 nm_write_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_DA, strM2mAteRxStr->mac_filter_en_da);
tsungta 28:2abbf8463fa8 550 nm_write_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_SA, strM2mAteRxStr->mac_filter_en_sa);
tsungta 28:2abbf8463fa8 551 nm_write_reg(rBurstTx_NMI_SET_SELF_MAC_ADDR, strM2mAteRxStr->override_self_mac_addr);
tsungta 28:2abbf8463fa8 552
tsungta 28:2abbf8463fa8 553 if(M2M_SUCCESS == s8Ret)
tsungta 28:2abbf8463fa8 554 {
tsungta 28:2abbf8463fa8 555 s8Ret += nm_write_reg(rInterrupt_CORTUS_2, 1); /*Interrupt Cortus*/
tsungta 28:2abbf8463fa8 556 m2m_ate_set_rx_status(1);
tsungta 28:2abbf8463fa8 557 nm_bsp_sleep(10); /*Recommended*/
tsungta 28:2abbf8463fa8 558 }
tsungta 28:2abbf8463fa8 559
tsungta 28:2abbf8463fa8 560 __EXIT:
tsungta 28:2abbf8463fa8 561 return s8Ret;
tsungta 28:2abbf8463fa8 562 }
tsungta 28:2abbf8463fa8 563
tsungta 28:2abbf8463fa8 564 /*!
tsungta 28:2abbf8463fa8 565 @fn \
tsungta 28:2abbf8463fa8 566 sint8 m2m_ate_stop_rx(void)
tsungta 28:2abbf8463fa8 567
tsungta 28:2abbf8463fa8 568 @brief
tsungta 28:2abbf8463fa8 569 This function used to stop RX test case.
tsungta 28:2abbf8463fa8 570
tsungta 28:2abbf8463fa8 571 @return
tsungta 28:2abbf8463fa8 572 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 573 \sa
tsungta 28:2abbf8463fa8 574 m2m_ate_init, m2m_ate_start_rx, m2m_ate_get_rx_status
tsungta 28:2abbf8463fa8 575 */
tsungta 28:2abbf8463fa8 576 sint8 m2m_ate_stop_rx(void)
tsungta 28:2abbf8463fa8 577 {
tsungta 28:2abbf8463fa8 578 m2m_ate_set_rx_status(0);
tsungta 28:2abbf8463fa8 579 nm_bsp_sleep(200); /*Recommended*/
tsungta 28:2abbf8463fa8 580 return M2M_SUCCESS;
tsungta 28:2abbf8463fa8 581 }
tsungta 28:2abbf8463fa8 582
tsungta 28:2abbf8463fa8 583 /*!
tsungta 28:2abbf8463fa8 584 @fn \
tsungta 28:2abbf8463fa8 585 sint8 m2m_ate_read_rx_status(tstrM2mAteRxStatus *)
tsungta 28:2abbf8463fa8 586
tsungta 28:2abbf8463fa8 587 @brief
tsungta 28:2abbf8463fa8 588 This function used to read RX statistics from ATE firmware.
tsungta 28:2abbf8463fa8 589
tsungta 28:2abbf8463fa8 590 @param [out] strM2mAteRxStatus
tsungta 28:2abbf8463fa8 591 Type of \ref tstrM2mAteRxStatus used to save statistics of RX test case. You must use \ref m2m_ate_start_rx first.
tsungta 28:2abbf8463fa8 592 @return
tsungta 28:2abbf8463fa8 593 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 594 \sa
tsungta 28:2abbf8463fa8 595 m2m_ate_init, m2m_ate_start_rx
tsungta 28:2abbf8463fa8 596 */
tsungta 28:2abbf8463fa8 597 sint8 m2m_ate_read_rx_status(tstrM2mAteRxStatus *strM2mAteRxStatus)
tsungta 28:2abbf8463fa8 598 {
tsungta 28:2abbf8463fa8 599 sint8 s8Ret = M2M_SUCCESS;
tsungta 28:2abbf8463fa8 600
tsungta 28:2abbf8463fa8 601 if(NULL == strM2mAteRxStatus)
tsungta 28:2abbf8463fa8 602 {
tsungta 28:2abbf8463fa8 603 s8Ret = M2M_ATE_ERR_VALIDATE;
tsungta 28:2abbf8463fa8 604 goto __EXIT;
tsungta 28:2abbf8463fa8 605 }
tsungta 28:2abbf8463fa8 606
tsungta 28:2abbf8463fa8 607 if(0 != m2m_ate_get_tx_status())
tsungta 28:2abbf8463fa8 608 {
tsungta 28:2abbf8463fa8 609 s8Ret = M2M_ATE_ERR_TX_ALREADY_RUNNING;
tsungta 28:2abbf8463fa8 610 goto __EXIT;
tsungta 28:2abbf8463fa8 611 }
tsungta 28:2abbf8463fa8 612
tsungta 28:2abbf8463fa8 613 if (nm_read_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_DA) || nm_read_reg(rBurstTx_NMI_MAC_FILTER_ENABLE_SA))
tsungta 28:2abbf8463fa8 614 {
tsungta 28:2abbf8463fa8 615 strM2mAteRxStatus->num_rx_pkts = nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_SUCCESS) + nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_FAIL);
tsungta 28:2abbf8463fa8 616 strM2mAteRxStatus->num_good_pkts = nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_SUCCESS);
tsungta 28:2abbf8463fa8 617 strM2mAteRxStatus->num_err_pkts = nm_read_reg(rBurstTx_NMI_RX_PKT_CNT_FAIL);
tsungta 28:2abbf8463fa8 618 }
tsungta 28:2abbf8463fa8 619 else
tsungta 28:2abbf8463fa8 620 {
tsungta 28:2abbf8463fa8 621 strM2mAteRxStatus->num_rx_pkts = nm_read_reg(rBurstRx_NMI_RX_ALL_PKTS_CONT) + nm_read_reg(0x989c);
tsungta 28:2abbf8463fa8 622 strM2mAteRxStatus->num_err_pkts = nm_read_reg(rBurstRx_NMI_RX_ERR_PKTS_CONT);
tsungta 28:2abbf8463fa8 623 strM2mAteRxStatus->num_good_pkts = strM2mAteRxStatus->num_rx_pkts - strM2mAteRxStatus->num_err_pkts;
tsungta 28:2abbf8463fa8 624 }
tsungta 28:2abbf8463fa8 625
tsungta 28:2abbf8463fa8 626 __EXIT:
tsungta 28:2abbf8463fa8 627 return s8Ret;
tsungta 28:2abbf8463fa8 628 }
tsungta 28:2abbf8463fa8 629 /*!
tsungta 28:2abbf8463fa8 630 @fn \
tsungta 28:2abbf8463fa8 631 sint8 m2m_ate_set_dig_gain(double dGaindB)
tsungta 28:2abbf8463fa8 632
tsungta 28:2abbf8463fa8 633 @brief
tsungta 28:2abbf8463fa8 634 This function is used to set the digital gain
tsungta 28:2abbf8463fa8 635
tsungta 28:2abbf8463fa8 636 @param [in] double dGaindB
tsungta 28:2abbf8463fa8 637 The digital gain value required to be set.
tsungta 28:2abbf8463fa8 638 @return
tsungta 28:2abbf8463fa8 639 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 640 */
tsungta 28:2abbf8463fa8 641 sint8 m2m_ate_set_dig_gain(double dGaindB)
tsungta 28:2abbf8463fa8 642 {
tsungta 28:2abbf8463fa8 643 uint32_t dGain, val32;
tsungta 28:2abbf8463fa8 644 dGain = (uint32_t)(pow(10, dGaindB/20.0) * 1024.0);
tsungta 28:2abbf8463fa8 645
tsungta 28:2abbf8463fa8 646 val32 = nm_read_reg(0x160cd0);
tsungta 28:2abbf8463fa8 647 val32 &= ~(0x1ffful << 0);
tsungta 28:2abbf8463fa8 648 val32 |= (((uint32_t)dGain) << 0);
tsungta 28:2abbf8463fa8 649 nm_write_reg(0x160cd0, val32);
tsungta 28:2abbf8463fa8 650 return M2M_SUCCESS;
tsungta 28:2abbf8463fa8 651 }
tsungta 28:2abbf8463fa8 652 /*!
tsungta 28:2abbf8463fa8 653 @fn \
tsungta 28:2abbf8463fa8 654 sint8 m2m_ate_get_dig_gain(double * dGaindB)
tsungta 28:2abbf8463fa8 655
tsungta 28:2abbf8463fa8 656 @brief
tsungta 28:2abbf8463fa8 657 This function is used to get the digital gain
tsungta 28:2abbf8463fa8 658
tsungta 28:2abbf8463fa8 659 @param [out] double * dGaindB
tsungta 28:2abbf8463fa8 660 The retrieved digital gain value obtained from HW registers in dB.
tsungta 28:2abbf8463fa8 661 @return
tsungta 28:2abbf8463fa8 662 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 663 */
tsungta 28:2abbf8463fa8 664 sint8 m2m_ate_get_dig_gain(double * dGaindB)
tsungta 28:2abbf8463fa8 665 {
tsungta 28:2abbf8463fa8 666 uint32 dGain, val32;
tsungta 28:2abbf8463fa8 667
tsungta 28:2abbf8463fa8 668 if(!dGaindB) return M2M_ERR_INVALID_ARG;
tsungta 28:2abbf8463fa8 669
tsungta 28:2abbf8463fa8 670 val32 = nm_read_reg(0x160cd0);
tsungta 28:2abbf8463fa8 671
tsungta 28:2abbf8463fa8 672 dGain = (val32 >> 0) & 0x1ffful;
tsungta 28:2abbf8463fa8 673 *dGaindB = 20.0*log10((double)dGain / 1024.0);
tsungta 28:2abbf8463fa8 674
tsungta 28:2abbf8463fa8 675 return M2M_SUCCESS;
tsungta 28:2abbf8463fa8 676 }
tsungta 28:2abbf8463fa8 677 /*!
tsungta 28:2abbf8463fa8 678 @fn \
tsungta 28:2abbf8463fa8 679 void m2m_ate_set_pa_gain(uint8 gain_db)
tsungta 28:2abbf8463fa8 680
tsungta 28:2abbf8463fa8 681 @brief
tsungta 28:2abbf8463fa8 682 This function is used to set the PA gain (18/15/12/9/6/3/0 only)
tsungta 28:2abbf8463fa8 683
tsungta 28:2abbf8463fa8 684 @param [in] uint8 gain_db
tsungta 28:2abbf8463fa8 685 PA gain level allowed (18/15/12/9/6/3/0 only)
tsungta 28:2abbf8463fa8 686
tsungta 28:2abbf8463fa8 687 */
tsungta 28:2abbf8463fa8 688 void m2m_ate_set_pa_gain(uint8 gain_db)
tsungta 28:2abbf8463fa8 689 {
tsungta 28:2abbf8463fa8 690 uint32 PA_1e9c;
tsungta 28:2abbf8463fa8 691 uint8 aGain[] = {
tsungta 28:2abbf8463fa8 692 /* "0 dB" */ 0x00,
tsungta 28:2abbf8463fa8 693 /* "3 dB" */ 0x01,
tsungta 28:2abbf8463fa8 694 /* "6 dB" */ 0x03,
tsungta 28:2abbf8463fa8 695 /* "9 dB" */ 0x07,
tsungta 28:2abbf8463fa8 696 /* "12 dB" */ 0x0f,
tsungta 28:2abbf8463fa8 697 /* "15 dB" */ 0x1f,
tsungta 28:2abbf8463fa8 698 /* "18 dB" */ 0x3f };
tsungta 28:2abbf8463fa8 699 /* The variable PA gain is valid only for High power mode */
tsungta 28:2abbf8463fa8 700 PA_1e9c = nm_read_reg(0x1e9c);
tsungta 28:2abbf8463fa8 701 /* TX bank 0. */
tsungta 28:2abbf8463fa8 702 PA_1e9c &= ~(0x3ful << 8);
tsungta 28:2abbf8463fa8 703 PA_1e9c |= (((uint32)aGain[gain_db/3] & 0x3f) << 8);
tsungta 28:2abbf8463fa8 704 nm_write_reg(0x1e9c, PA_1e9c);
tsungta 28:2abbf8463fa8 705 }
tsungta 28:2abbf8463fa8 706 /*!
tsungta 28:2abbf8463fa8 707 @fn \
tsungta 28:2abbf8463fa8 708 sint8 m2m_ate_get_pa_gain(double *paGaindB)
tsungta 28:2abbf8463fa8 709
tsungta 28:2abbf8463fa8 710 @brief
tsungta 28:2abbf8463fa8 711 This function is used to get the PA gain
tsungta 28:2abbf8463fa8 712
tsungta 28:2abbf8463fa8 713 @param [out] double *paGaindB
tsungta 28:2abbf8463fa8 714 The retrieved PA gain value obtained from HW registers in dB.
tsungta 28:2abbf8463fa8 715 @return
tsungta 28:2abbf8463fa8 716 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 717 */
tsungta 28:2abbf8463fa8 718 sint8 m2m_ate_get_pa_gain(double *paGaindB)
tsungta 28:2abbf8463fa8 719 {
tsungta 28:2abbf8463fa8 720 uint32 val32, paGain;
tsungta 28:2abbf8463fa8 721 uint32 m_cmbPAGainStep;
tsungta 28:2abbf8463fa8 722
tsungta 28:2abbf8463fa8 723 if(!paGaindB)
tsungta 28:2abbf8463fa8 724 return M2M_ERR_INVALID_ARG;
tsungta 28:2abbf8463fa8 725
tsungta 28:2abbf8463fa8 726 val32 = nm_read_reg(0x1e9c);
tsungta 28:2abbf8463fa8 727
tsungta 28:2abbf8463fa8 728 paGain = (val32 >> 8) & 0x3f;
tsungta 28:2abbf8463fa8 729
tsungta 28:2abbf8463fa8 730 switch(paGain){
tsungta 28:2abbf8463fa8 731 case 0x1:
tsungta 28:2abbf8463fa8 732 m_cmbPAGainStep = 5;
tsungta 28:2abbf8463fa8 733 break;
tsungta 28:2abbf8463fa8 734 case 0x3:
tsungta 28:2abbf8463fa8 735 m_cmbPAGainStep = 4;
tsungta 28:2abbf8463fa8 736 break;
tsungta 28:2abbf8463fa8 737 case 0x7:
tsungta 28:2abbf8463fa8 738 m_cmbPAGainStep = 3;
tsungta 28:2abbf8463fa8 739 break;
tsungta 28:2abbf8463fa8 740 case 0xf:
tsungta 28:2abbf8463fa8 741 m_cmbPAGainStep = 2;
tsungta 28:2abbf8463fa8 742 break;
tsungta 28:2abbf8463fa8 743 case 0x1f:
tsungta 28:2abbf8463fa8 744 m_cmbPAGainStep = 1;
tsungta 28:2abbf8463fa8 745 break;
tsungta 28:2abbf8463fa8 746 case 0x3f:
tsungta 28:2abbf8463fa8 747 m_cmbPAGainStep = 0;
tsungta 28:2abbf8463fa8 748 break;
tsungta 28:2abbf8463fa8 749 default:
tsungta 28:2abbf8463fa8 750 m_cmbPAGainStep = 0;
tsungta 28:2abbf8463fa8 751 break;
tsungta 28:2abbf8463fa8 752 }
tsungta 28:2abbf8463fa8 753
tsungta 28:2abbf8463fa8 754 *paGaindB = 18 - m_cmbPAGainStep*3;
tsungta 28:2abbf8463fa8 755
tsungta 28:2abbf8463fa8 756 return M2M_SUCCESS;
tsungta 28:2abbf8463fa8 757 }
tsungta 28:2abbf8463fa8 758 /*!
tsungta 28:2abbf8463fa8 759 @fn \
tsungta 28:2abbf8463fa8 760 sint8 m2m_ate_get_ppa_gain(double * ppaGaindB)
tsungta 28:2abbf8463fa8 761
tsungta 28:2abbf8463fa8 762 @brief
tsungta 28:2abbf8463fa8 763 This function is used to get the PPA gain
tsungta 28:2abbf8463fa8 764
tsungta 28:2abbf8463fa8 765 @param [out] uint32 * ppaGaindB
tsungta 28:2abbf8463fa8 766 The retrieved PPA gain value obtained from HW registers in dB.
tsungta 28:2abbf8463fa8 767 @return
tsungta 28:2abbf8463fa8 768 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 769 */
tsungta 28:2abbf8463fa8 770 sint8 m2m_ate_get_ppa_gain(double * ppaGaindB)
tsungta 28:2abbf8463fa8 771 {
tsungta 28:2abbf8463fa8 772 uint32 val32, ppaGain, m_cmbPPAGainStep;
tsungta 28:2abbf8463fa8 773
tsungta 28:2abbf8463fa8 774 if(!ppaGaindB) return M2M_ERR_INVALID_ARG;
tsungta 28:2abbf8463fa8 775
tsungta 28:2abbf8463fa8 776 val32 = nm_read_reg(0x1ea0);
tsungta 28:2abbf8463fa8 777
tsungta 28:2abbf8463fa8 778 ppaGain = (val32 >> 5) & 0x7;
tsungta 28:2abbf8463fa8 779
tsungta 28:2abbf8463fa8 780 switch(ppaGain){
tsungta 28:2abbf8463fa8 781 case 0x1:
tsungta 28:2abbf8463fa8 782 m_cmbPPAGainStep = 2;
tsungta 28:2abbf8463fa8 783 break;
tsungta 28:2abbf8463fa8 784 case 0x3:
tsungta 28:2abbf8463fa8 785 m_cmbPPAGainStep = 1;
tsungta 28:2abbf8463fa8 786 break;
tsungta 28:2abbf8463fa8 787 case 0x7:
tsungta 28:2abbf8463fa8 788 m_cmbPPAGainStep = 0;
tsungta 28:2abbf8463fa8 789 break;
tsungta 28:2abbf8463fa8 790 default:
tsungta 28:2abbf8463fa8 791 m_cmbPPAGainStep = 3;
tsungta 28:2abbf8463fa8 792 break;
tsungta 28:2abbf8463fa8 793 }
tsungta 28:2abbf8463fa8 794
tsungta 28:2abbf8463fa8 795 *ppaGaindB = 9 - m_cmbPPAGainStep*3;
tsungta 28:2abbf8463fa8 796
tsungta 28:2abbf8463fa8 797
tsungta 28:2abbf8463fa8 798 return M2M_SUCCESS;
tsungta 28:2abbf8463fa8 799 }
tsungta 28:2abbf8463fa8 800 /*!
tsungta 28:2abbf8463fa8 801 @fn \
tsungta 28:2abbf8463fa8 802 sint8 m2m_ate_get_tot_gain(double * totGaindB)
tsungta 28:2abbf8463fa8 803
tsungta 28:2abbf8463fa8 804 @brief
tsungta 28:2abbf8463fa8 805 This function is used to calculate the total gain
tsungta 28:2abbf8463fa8 806
tsungta 28:2abbf8463fa8 807 @param [out] double * totGaindB
tsungta 28:2abbf8463fa8 808 The retrieved total gain value obtained from calculations made based on the digital gain, PA and PPA gain values.
tsungta 28:2abbf8463fa8 809 @return
tsungta 28:2abbf8463fa8 810 The function SHALL return 0 for success and a negative value otherwise.
tsungta 28:2abbf8463fa8 811 */
tsungta 28:2abbf8463fa8 812 sint8 m2m_ate_get_tot_gain(double * totGaindB)
tsungta 28:2abbf8463fa8 813 {
tsungta 28:2abbf8463fa8 814 double dGaindB, paGaindB, ppaGaindB;
tsungta 28:2abbf8463fa8 815
tsungta 28:2abbf8463fa8 816 if(!totGaindB) return M2M_ERR_INVALID_ARG;
tsungta 28:2abbf8463fa8 817
tsungta 28:2abbf8463fa8 818 m2m_ate_get_pa_gain(&paGaindB);
tsungta 28:2abbf8463fa8 819 m2m_ate_get_ppa_gain(&ppaGaindB);
tsungta 28:2abbf8463fa8 820 m2m_ate_get_dig_gain(&dGaindB);
tsungta 28:2abbf8463fa8 821
tsungta 28:2abbf8463fa8 822 *totGaindB = dGaindB + paGaindB + ppaGaindB;
tsungta 28:2abbf8463fa8 823
tsungta 28:2abbf8463fa8 824 return M2M_SUCCESS;
tsungta 28:2abbf8463fa8 825 }
tsungta 28:2abbf8463fa8 826
tsungta 28:2abbf8463fa8 827 #endif //_M2M_ATE_FW_
tsungta 28:2abbf8463fa8 828