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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.h@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32l0xx_hal_i2s.h
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.7.0
sahilmgandhi 18:6a4db94011d3 6 * @date 31-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief Header file of I2S HAL module.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37
sahilmgandhi 18:6a4db94011d3 38 /* Define to prevent recursive inclusion -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 39 #ifndef __STM32L0xx_HAL_I2S_H
sahilmgandhi 18:6a4db94011d3 40 #define __STM32L0xx_HAL_I2S_H
sahilmgandhi 18:6a4db94011d3 41
sahilmgandhi 18:6a4db94011d3 42 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 43 extern "C" {
sahilmgandhi 18:6a4db94011d3 44 #endif
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L011xx) && !defined (STM32L021xx)
sahilmgandhi 18:6a4db94011d3 47 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 48 #include "stm32l0xx_hal_def.h"
sahilmgandhi 18:6a4db94011d3 49
sahilmgandhi 18:6a4db94011d3 50 /** @addtogroup STM32L0xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 51 * @{
sahilmgandhi 18:6a4db94011d3 52 */
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 /** @defgroup I2S I2S
sahilmgandhi 18:6a4db94011d3 55 * @{
sahilmgandhi 18:6a4db94011d3 56 */
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 /* Exported types ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 59 /** @defgroup I2S_Exported_Types I2S Exported Types
sahilmgandhi 18:6a4db94011d3 60 * @{
sahilmgandhi 18:6a4db94011d3 61 */
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /**
sahilmgandhi 18:6a4db94011d3 64 * @brief I2S Init structure definition
sahilmgandhi 18:6a4db94011d3 65 */
sahilmgandhi 18:6a4db94011d3 66 typedef struct
sahilmgandhi 18:6a4db94011d3 67 {
sahilmgandhi 18:6a4db94011d3 68 uint32_t Mode; /*!< Specifies the I2S operating mode.
sahilmgandhi 18:6a4db94011d3 69 This parameter can be a value of @ref I2S_Mode */
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
sahilmgandhi 18:6a4db94011d3 72 This parameter can be a value of @ref I2S_Standard */
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
sahilmgandhi 18:6a4db94011d3 75 This parameter can be a value of @ref I2S_Data_Format */
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
sahilmgandhi 18:6a4db94011d3 78 This parameter can be a value of @ref I2S_MCLK_Output */
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
sahilmgandhi 18:6a4db94011d3 81 This parameter can be a value of @ref I2S_Audio_Frequency */
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
sahilmgandhi 18:6a4db94011d3 84 This parameter can be a value of @ref I2S_Clock_Polarity */
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 }I2S_InitTypeDef;
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 /**
sahilmgandhi 18:6a4db94011d3 89 * @brief HAL State structures definition
sahilmgandhi 18:6a4db94011d3 90 */
sahilmgandhi 18:6a4db94011d3 91 typedef enum
sahilmgandhi 18:6a4db94011d3 92 {
sahilmgandhi 18:6a4db94011d3 93 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
sahilmgandhi 18:6a4db94011d3 94 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
sahilmgandhi 18:6a4db94011d3 95 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
sahilmgandhi 18:6a4db94011d3 96 HAL_I2S_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
sahilmgandhi 18:6a4db94011d3 97 HAL_I2S_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
sahilmgandhi 18:6a4db94011d3 98 HAL_I2S_STATE_TIMEOUT = 0x03U, /*!< I2S timeout state */
sahilmgandhi 18:6a4db94011d3 99 HAL_I2S_STATE_ERROR = 0x04U /*!< I2S error state */
sahilmgandhi 18:6a4db94011d3 100 }HAL_I2S_StateTypeDef;
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102 /**
sahilmgandhi 18:6a4db94011d3 103 * @brief I2S handle Structure definition
sahilmgandhi 18:6a4db94011d3 104 */
sahilmgandhi 18:6a4db94011d3 105 typedef struct
sahilmgandhi 18:6a4db94011d3 106 {
sahilmgandhi 18:6a4db94011d3 107 SPI_TypeDef *Instance; /* I2S registers base address */
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 I2S_InitTypeDef Init; /* I2S communication parameters */
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
sahilmgandhi 18:6a4db94011d3 112
sahilmgandhi 18:6a4db94011d3 113 __IO uint16_t TxXferSize; /* I2S Tx transfer size */
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
sahilmgandhi 18:6a4db94011d3 116
sahilmgandhi 18:6a4db94011d3 117 uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
sahilmgandhi 18:6a4db94011d3 118
sahilmgandhi 18:6a4db94011d3 119 __IO uint16_t RxXferSize; /* I2S Rx transfer size */
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 __IO uint16_t RxXferCount; /* I2S Rx transfer counter
sahilmgandhi 18:6a4db94011d3 122 (This field is initialized at the
sahilmgandhi 18:6a4db94011d3 123 same value as transfer size at the
sahilmgandhi 18:6a4db94011d3 124 beginning of the transfer and
sahilmgandhi 18:6a4db94011d3 125 decremented when a sample is received.
sahilmgandhi 18:6a4db94011d3 126 NbSamplesReceived = RxBufferSize-RxBufferCount) */
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
sahilmgandhi 18:6a4db94011d3 131
sahilmgandhi 18:6a4db94011d3 132 __IO HAL_LockTypeDef Lock; /* I2S locking object */
sahilmgandhi 18:6a4db94011d3 133
sahilmgandhi 18:6a4db94011d3 134 __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 __IO uint32_t ErrorCode; /* I2S Error code */
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 }I2S_HandleTypeDef;
sahilmgandhi 18:6a4db94011d3 139 /**
sahilmgandhi 18:6a4db94011d3 140 * @}
sahilmgandhi 18:6a4db94011d3 141 */
sahilmgandhi 18:6a4db94011d3 142
sahilmgandhi 18:6a4db94011d3 143 /* Exported constants --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 144 /** @defgroup I2S_Exported_Constants I2S Exported Constants
sahilmgandhi 18:6a4db94011d3 145 * @{
sahilmgandhi 18:6a4db94011d3 146 */
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 /**
sahilmgandhi 18:6a4db94011d3 149 * @defgroup I2S_ErrorCode I2S Error Code
sahilmgandhi 18:6a4db94011d3 150 * @{
sahilmgandhi 18:6a4db94011d3 151 */
sahilmgandhi 18:6a4db94011d3 152 #define HAL_I2S_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
sahilmgandhi 18:6a4db94011d3 153 #define HAL_I2S_ERROR_UDR ((uint32_t)0x01U) /*!< I2S Underrun error */
sahilmgandhi 18:6a4db94011d3 154 #define HAL_I2S_ERROR_OVR ((uint32_t)0x02U) /*!< I2S Overrun error */
sahilmgandhi 18:6a4db94011d3 155 #define HAL_I2S_ERROR_FRE ((uint32_t)0x04U) /*!< I2S Frame format error */
sahilmgandhi 18:6a4db94011d3 156 #define HAL_I2S_ERROR_DMA ((uint32_t)0x08U) /*!< DMA transfer error */
sahilmgandhi 18:6a4db94011d3 157 /**
sahilmgandhi 18:6a4db94011d3 158 * @}
sahilmgandhi 18:6a4db94011d3 159 */
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 /** @defgroup I2S_Mode I2S Mode
sahilmgandhi 18:6a4db94011d3 162 * @{
sahilmgandhi 18:6a4db94011d3 163 */
sahilmgandhi 18:6a4db94011d3 164 #define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000U)
sahilmgandhi 18:6a4db94011d3 165 #define I2S_MODE_SLAVE_RX ((uint32_t) SPI_I2SCFGR_I2SCFG_0)
sahilmgandhi 18:6a4db94011d3 166 #define I2S_MODE_MASTER_TX ((uint32_t) SPI_I2SCFGR_I2SCFG_1)
sahilmgandhi 18:6a4db94011d3 167 #define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\
sahilmgandhi 18:6a4db94011d3 168 SPI_I2SCFGR_I2SCFG_1))
sahilmgandhi 18:6a4db94011d3 169 /**
sahilmgandhi 18:6a4db94011d3 170 * @}
sahilmgandhi 18:6a4db94011d3 171 */
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /** @defgroup I2S_Standard I2S Standard
sahilmgandhi 18:6a4db94011d3 174 * @{
sahilmgandhi 18:6a4db94011d3 175 */
sahilmgandhi 18:6a4db94011d3 176 #define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000U)
sahilmgandhi 18:6a4db94011d3 177 #define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
sahilmgandhi 18:6a4db94011d3 178 #define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
sahilmgandhi 18:6a4db94011d3 179 #define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
sahilmgandhi 18:6a4db94011d3 180 SPI_I2SCFGR_I2SSTD_1))
sahilmgandhi 18:6a4db94011d3 181 #define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
sahilmgandhi 18:6a4db94011d3 182 SPI_I2SCFGR_I2SSTD_1 |\
sahilmgandhi 18:6a4db94011d3 183 SPI_I2SCFGR_PCMSYNC))
sahilmgandhi 18:6a4db94011d3 184 /** @defgroup I2S_Legacy I2S Legacy
sahilmgandhi 18:6a4db94011d3 185 * @{
sahilmgandhi 18:6a4db94011d3 186 */
sahilmgandhi 18:6a4db94011d3 187 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
sahilmgandhi 18:6a4db94011d3 188 /**
sahilmgandhi 18:6a4db94011d3 189 * @}
sahilmgandhi 18:6a4db94011d3 190 */
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 /**
sahilmgandhi 18:6a4db94011d3 193 * @}
sahilmgandhi 18:6a4db94011d3 194 */
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 /** @defgroup I2S_Data_Format I2S Data Format
sahilmgandhi 18:6a4db94011d3 197 * @{
sahilmgandhi 18:6a4db94011d3 198 */
sahilmgandhi 18:6a4db94011d3 199 #define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000U)
sahilmgandhi 18:6a4db94011d3 200 #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN)
sahilmgandhi 18:6a4db94011d3 201 #define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
sahilmgandhi 18:6a4db94011d3 202 #define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
sahilmgandhi 18:6a4db94011d3 203 /**
sahilmgandhi 18:6a4db94011d3 204 * @}
sahilmgandhi 18:6a4db94011d3 205 */
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 /** @defgroup I2S_MCLK_Output I2S MCLK Output
sahilmgandhi 18:6a4db94011d3 208 * @{
sahilmgandhi 18:6a4db94011d3 209 */
sahilmgandhi 18:6a4db94011d3 210 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
sahilmgandhi 18:6a4db94011d3 211 #define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 212 /**
sahilmgandhi 18:6a4db94011d3 213 * @}
sahilmgandhi 18:6a4db94011d3 214 */
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
sahilmgandhi 18:6a4db94011d3 217 * @{
sahilmgandhi 18:6a4db94011d3 218 */
sahilmgandhi 18:6a4db94011d3 219 #define I2S_AUDIOFREQ_192K ((uint32_t)192000U)
sahilmgandhi 18:6a4db94011d3 220 #define I2S_AUDIOFREQ_96K ((uint32_t)96000U)
sahilmgandhi 18:6a4db94011d3 221 #define I2S_AUDIOFREQ_48K ((uint32_t)48000U)
sahilmgandhi 18:6a4db94011d3 222 #define I2S_AUDIOFREQ_44K ((uint32_t)44100U)
sahilmgandhi 18:6a4db94011d3 223 #define I2S_AUDIOFREQ_32K ((uint32_t)32000U)
sahilmgandhi 18:6a4db94011d3 224 #define I2S_AUDIOFREQ_22K ((uint32_t)22050U)
sahilmgandhi 18:6a4db94011d3 225 #define I2S_AUDIOFREQ_16K ((uint32_t)16000U)
sahilmgandhi 18:6a4db94011d3 226 #define I2S_AUDIOFREQ_11K ((uint32_t)11025U)
sahilmgandhi 18:6a4db94011d3 227 #define I2S_AUDIOFREQ_8K ((uint32_t)8000U)
sahilmgandhi 18:6a4db94011d3 228 #define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
sahilmgandhi 18:6a4db94011d3 229 /**
sahilmgandhi 18:6a4db94011d3 230 * @}
sahilmgandhi 18:6a4db94011d3 231 */
sahilmgandhi 18:6a4db94011d3 232
sahilmgandhi 18:6a4db94011d3 233 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
sahilmgandhi 18:6a4db94011d3 234 * @{
sahilmgandhi 18:6a4db94011d3 235 */
sahilmgandhi 18:6a4db94011d3 236 #define I2S_CPOL_LOW ((uint32_t)0x00000000U)
sahilmgandhi 18:6a4db94011d3 237 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
sahilmgandhi 18:6a4db94011d3 238 /**
sahilmgandhi 18:6a4db94011d3 239 * @}
sahilmgandhi 18:6a4db94011d3 240 */
sahilmgandhi 18:6a4db94011d3 241
sahilmgandhi 18:6a4db94011d3 242 /** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
sahilmgandhi 18:6a4db94011d3 243 * @{
sahilmgandhi 18:6a4db94011d3 244 */
sahilmgandhi 18:6a4db94011d3 245 #define I2S_IT_TXE SPI_CR2_TXEIE
sahilmgandhi 18:6a4db94011d3 246 #define I2S_IT_RXNE SPI_CR2_RXNEIE
sahilmgandhi 18:6a4db94011d3 247 #define I2S_IT_ERR SPI_CR2_ERRIE
sahilmgandhi 18:6a4db94011d3 248 /**
sahilmgandhi 18:6a4db94011d3 249 * @}
sahilmgandhi 18:6a4db94011d3 250 */
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 /** @defgroup I2S_Flag_definition I2S Flag definition
sahilmgandhi 18:6a4db94011d3 253 * @{
sahilmgandhi 18:6a4db94011d3 254 */
sahilmgandhi 18:6a4db94011d3 255 #define I2S_FLAG_TXE SPI_SR_TXE
sahilmgandhi 18:6a4db94011d3 256 #define I2S_FLAG_RXNE SPI_SR_RXNE
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 #define I2S_FLAG_UDR SPI_SR_UDR
sahilmgandhi 18:6a4db94011d3 259 #define I2S_FLAG_OVR SPI_SR_OVR
sahilmgandhi 18:6a4db94011d3 260 #define I2S_FLAG_FRE SPI_SR_FRE
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
sahilmgandhi 18:6a4db94011d3 263 #define I2S_FLAG_BSY SPI_SR_BSY
sahilmgandhi 18:6a4db94011d3 264 /**
sahilmgandhi 18:6a4db94011d3 265 * @}
sahilmgandhi 18:6a4db94011d3 266 */
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /**
sahilmgandhi 18:6a4db94011d3 269 * @}
sahilmgandhi 18:6a4db94011d3 270 */
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /* Exported macro ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 273 /** @defgroup I2S_Exported_Macros I2S Exported Macros
sahilmgandhi 18:6a4db94011d3 274 * @{
sahilmgandhi 18:6a4db94011d3 275 */
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 /** @brief Reset I2S handle state
sahilmgandhi 18:6a4db94011d3 278 * @param __HANDLE__: specifies the I2S Handle.
sahilmgandhi 18:6a4db94011d3 279 * @retval None
sahilmgandhi 18:6a4db94011d3 280 */
sahilmgandhi 18:6a4db94011d3 281 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 /** @brief Enable the specified SPI peripheral (in I2S mode).
sahilmgandhi 18:6a4db94011d3 284 * @param __HANDLE__: specifies the I2S Handle.
sahilmgandhi 18:6a4db94011d3 285 * @retval None
sahilmgandhi 18:6a4db94011d3 286 */
sahilmgandhi 18:6a4db94011d3 287 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
sahilmgandhi 18:6a4db94011d3 288
sahilmgandhi 18:6a4db94011d3 289 /** @brief Disable the specified SPI peripheral (in I2S mode).
sahilmgandhi 18:6a4db94011d3 290 * @param __HANDLE__: specifies the I2S Handle.
sahilmgandhi 18:6a4db94011d3 291 * @retval None
sahilmgandhi 18:6a4db94011d3 292 */
sahilmgandhi 18:6a4db94011d3 293 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 /** @brief Enable the specified I2S interrupts.
sahilmgandhi 18:6a4db94011d3 296 * @param __HANDLE__: specifies the I2S Handle.
sahilmgandhi 18:6a4db94011d3 297 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
sahilmgandhi 18:6a4db94011d3 298 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 299 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
sahilmgandhi 18:6a4db94011d3 300 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
sahilmgandhi 18:6a4db94011d3 301 * @arg I2S_IT_ERR: Error interrupt enable
sahilmgandhi 18:6a4db94011d3 302 * @retval None
sahilmgandhi 18:6a4db94011d3 303 */
sahilmgandhi 18:6a4db94011d3 304 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 /** @brief Disable the specified I2S interrupts.
sahilmgandhi 18:6a4db94011d3 307 * @param __HANDLE__: specifies the I2S Handle.
sahilmgandhi 18:6a4db94011d3 308 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
sahilmgandhi 18:6a4db94011d3 309 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 310 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
sahilmgandhi 18:6a4db94011d3 311 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
sahilmgandhi 18:6a4db94011d3 312 * @arg I2S_IT_ERR: Error interrupt enable
sahilmgandhi 18:6a4db94011d3 313 * @retval None
sahilmgandhi 18:6a4db94011d3 314 */
sahilmgandhi 18:6a4db94011d3 315 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
sahilmgandhi 18:6a4db94011d3 318 * @param __HANDLE__: specifies the I2S Handle.
sahilmgandhi 18:6a4db94011d3 319 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
sahilmgandhi 18:6a4db94011d3 320 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
sahilmgandhi 18:6a4db94011d3 321 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 322 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
sahilmgandhi 18:6a4db94011d3 323 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
sahilmgandhi 18:6a4db94011d3 324 * @arg I2S_IT_ERR: Error interrupt enable
sahilmgandhi 18:6a4db94011d3 325 * @retval The new state of __IT__ (TRUE or FALSE).
sahilmgandhi 18:6a4db94011d3 326 */
sahilmgandhi 18:6a4db94011d3 327 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 /** @brief Checks whether the specified I2S flag is set or not.
sahilmgandhi 18:6a4db94011d3 330 * @param __HANDLE__: specifies the I2S Handle.
sahilmgandhi 18:6a4db94011d3 331 * @param __FLAG__: specifies the flag to check.
sahilmgandhi 18:6a4db94011d3 332 * This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 333 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
sahilmgandhi 18:6a4db94011d3 334 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
sahilmgandhi 18:6a4db94011d3 335 * @arg I2S_FLAG_UDR: Underrun flag
sahilmgandhi 18:6a4db94011d3 336 * @arg I2S_FLAG_OVR: Overrun flag
sahilmgandhi 18:6a4db94011d3 337 * @arg I2S_FLAG_CHSIDE: Channel Side flag
sahilmgandhi 18:6a4db94011d3 338 * @arg I2S_FLAG_BSY: Busy flag
sahilmgandhi 18:6a4db94011d3 339 * @retval The new state of __FLAG__ (TRUE or FALSE).
sahilmgandhi 18:6a4db94011d3 340 */
sahilmgandhi 18:6a4db94011d3 341 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 /** @brief Clears the I2S OVR pending flag.
sahilmgandhi 18:6a4db94011d3 344 * @param __HANDLE__: specifies the I2S Handle.
sahilmgandhi 18:6a4db94011d3 345 * @retval None
sahilmgandhi 18:6a4db94011d3 346 */
sahilmgandhi 18:6a4db94011d3 347 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
sahilmgandhi 18:6a4db94011d3 348 tmpreg = (__HANDLE__)->Instance->SR;\
sahilmgandhi 18:6a4db94011d3 349 UNUSED(tmpreg);\
sahilmgandhi 18:6a4db94011d3 350 }while(0)
sahilmgandhi 18:6a4db94011d3 351 /** @brief Clears the I2S UDR pending flag.
sahilmgandhi 18:6a4db94011d3 352 * @param __HANDLE__: specifies the I2S Handle.
sahilmgandhi 18:6a4db94011d3 353 * @retval None
sahilmgandhi 18:6a4db94011d3 354 */
sahilmgandhi 18:6a4db94011d3 355 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
sahilmgandhi 18:6a4db94011d3 356 /**
sahilmgandhi 18:6a4db94011d3 357 * @}
sahilmgandhi 18:6a4db94011d3 358 */
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 361 /** @defgroup I2S_Exported_Functions I2S Exported Functions
sahilmgandhi 18:6a4db94011d3 362 * @{
sahilmgandhi 18:6a4db94011d3 363 */
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 366 * @{
sahilmgandhi 18:6a4db94011d3 367 */
sahilmgandhi 18:6a4db94011d3 368 /* Initialization/de-initialization functions ********************************/
sahilmgandhi 18:6a4db94011d3 369 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 370 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 371 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 372 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 373 /**
sahilmgandhi 18:6a4db94011d3 374 * @}
sahilmgandhi 18:6a4db94011d3 375 */
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
sahilmgandhi 18:6a4db94011d3 378 * @{
sahilmgandhi 18:6a4db94011d3 379 */
sahilmgandhi 18:6a4db94011d3 380 /* I/O operation functions ***************************************************/
sahilmgandhi 18:6a4db94011d3 381 /* Blocking mode: Polling */
sahilmgandhi 18:6a4db94011d3 382 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 383 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /* Non-Blocking mode: Interrupt */
sahilmgandhi 18:6a4db94011d3 386 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 387 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 388 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 /* Non-Blocking mode: DMA */
sahilmgandhi 18:6a4db94011d3 391 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 392 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 395 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 396 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
sahilmgandhi 18:6a4db94011d3 399 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 400 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 401 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 402 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 403 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 404 /**
sahilmgandhi 18:6a4db94011d3 405 * @}
sahilmgandhi 18:6a4db94011d3 406 */
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 /** @defgroup I2S_Exported_Functions_Group3 Peripheral Control and State functions
sahilmgandhi 18:6a4db94011d3 409 * @{
sahilmgandhi 18:6a4db94011d3 410 */
sahilmgandhi 18:6a4db94011d3 411 /* Peripheral Control and State functions ************************************/
sahilmgandhi 18:6a4db94011d3 412 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 413 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
sahilmgandhi 18:6a4db94011d3 414 /**
sahilmgandhi 18:6a4db94011d3 415 * @}
sahilmgandhi 18:6a4db94011d3 416 */
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 /**
sahilmgandhi 18:6a4db94011d3 419 * @}
sahilmgandhi 18:6a4db94011d3 420 */
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 423 /** @defgroup I2S_Private I2S Private
sahilmgandhi 18:6a4db94011d3 424 * @{
sahilmgandhi 18:6a4db94011d3 425 */
sahilmgandhi 18:6a4db94011d3 426 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
sahilmgandhi 18:6a4db94011d3 427 ((MODE) == I2S_MODE_SLAVE_RX) || \
sahilmgandhi 18:6a4db94011d3 428 ((MODE) == I2S_MODE_MASTER_TX) || \
sahilmgandhi 18:6a4db94011d3 429 ((MODE) == I2S_MODE_MASTER_RX))
sahilmgandhi 18:6a4db94011d3 430
sahilmgandhi 18:6a4db94011d3 431 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
sahilmgandhi 18:6a4db94011d3 432 ((STANDARD) == I2S_STANDARD_MSB) || \
sahilmgandhi 18:6a4db94011d3 433 ((STANDARD) == I2S_STANDARD_LSB) || \
sahilmgandhi 18:6a4db94011d3 434 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
sahilmgandhi 18:6a4db94011d3 435 ((STANDARD) == I2S_STANDARD_PCM_LONG))
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
sahilmgandhi 18:6a4db94011d3 438 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
sahilmgandhi 18:6a4db94011d3 439 ((FORMAT) == I2S_DATAFORMAT_24B) || \
sahilmgandhi 18:6a4db94011d3 440 ((FORMAT) == I2S_DATAFORMAT_32B))
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
sahilmgandhi 18:6a4db94011d3 443 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
sahilmgandhi 18:6a4db94011d3 444
sahilmgandhi 18:6a4db94011d3 445 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
sahilmgandhi 18:6a4db94011d3 446 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
sahilmgandhi 18:6a4db94011d3 447 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
sahilmgandhi 18:6a4db94011d3 450 ((CPOL) == I2S_CPOL_HIGH))
sahilmgandhi 18:6a4db94011d3 451 /**
sahilmgandhi 18:6a4db94011d3 452 * @}
sahilmgandhi 18:6a4db94011d3 453 */
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 /* Define the private group ***********************************/
sahilmgandhi 18:6a4db94011d3 456 /**************************************************************/
sahilmgandhi 18:6a4db94011d3 457 /** @defgroup I2S_Private I2S Private
sahilmgandhi 18:6a4db94011d3 458 * @{
sahilmgandhi 18:6a4db94011d3 459 */
sahilmgandhi 18:6a4db94011d3 460 /**
sahilmgandhi 18:6a4db94011d3 461 * @}
sahilmgandhi 18:6a4db94011d3 462 */
sahilmgandhi 18:6a4db94011d3 463 /**************************************************************/
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 /**
sahilmgandhi 18:6a4db94011d3 466 * @}
sahilmgandhi 18:6a4db94011d3 467 */
sahilmgandhi 18:6a4db94011d3 468
sahilmgandhi 18:6a4db94011d3 469 /**
sahilmgandhi 18:6a4db94011d3 470 * @}
sahilmgandhi 18:6a4db94011d3 471 */
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 #endif /* !STM32L031xx && !STM32L041xx && !STM32L011xx && !STM32L021xx */
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 476 }
sahilmgandhi 18:6a4db94011d3 477 #endif
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 #endif /* __STM32L0xx_HAL_I2S_H */
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/