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core_sc000.h
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00001 /**************************************************************************//** 00002 * @file core_sc000.h 00003 * @brief CMSIS SC000 Core Peripheral Access Layer Header File 00004 * @version V4.10 00005 * @date 18. March 2015 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2015 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_SC000_H_GENERIC 00043 #define __CORE_SC000_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup SC000 00067 @{ 00068 */ 00069 00070 /* CMSIS SC000 definitions */ 00071 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ 00072 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ 00074 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_SC (000) /*!< Cortex secure core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. 00112 This core does not support an FPU at all 00113 */ 00114 #define __FPU_USED 0 00115 00116 #if defined ( __CC_ARM ) 00117 #if defined __TARGET_FPU_VFP 00118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00119 #endif 00120 00121 #elif defined ( __GNUC__ ) 00122 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00124 #endif 00125 00126 #elif defined ( __ICCARM__ ) 00127 #if defined __ARMVFP__ 00128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00129 #endif 00130 00131 #elif defined ( __TMS470__ ) 00132 #if defined __TI__VFP_SUPPORT____ 00133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00134 #endif 00135 00136 #elif defined ( __TASKING__ ) 00137 #if defined __FPU_VFP__ 00138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00139 #endif 00140 00141 #elif defined ( __CSMC__ ) /* Cosmic */ 00142 #if ( __CSMC__ & 0x400) // FPU present for parser 00143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00144 #endif 00145 #endif 00146 00147 #include <stdint.h> /* standard types definitions */ 00148 #include <core_cmInstr.h> /* Core Instruction Access */ 00149 #include <core_cmFunc.h> /* Core Function Access */ 00150 00151 #ifdef __cplusplus 00152 } 00153 #endif 00154 00155 #endif /* __CORE_SC000_H_GENERIC */ 00156 00157 #ifndef __CMSIS_GENERIC 00158 00159 #ifndef __CORE_SC000_H_DEPENDANT 00160 #define __CORE_SC000_H_DEPENDANT 00161 00162 #ifdef __cplusplus 00163 extern "C" { 00164 #endif 00165 00166 /* check device defines and use defaults */ 00167 #if defined __CHECK_DEVICE_DEFINES 00168 #ifndef __SC000_REV 00169 #define __SC000_REV 0x0000 00170 #warning "__SC000_REV not defined in device header file; using default!" 00171 #endif 00172 00173 #ifndef __MPU_PRESENT 00174 #define __MPU_PRESENT 0 00175 #warning "__MPU_PRESENT not defined in device header file; using default!" 00176 #endif 00177 00178 #ifndef __NVIC_PRIO_BITS 00179 #define __NVIC_PRIO_BITS 2 00180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00181 #endif 00182 00183 #ifndef __Vendor_SysTickConfig 00184 #define __Vendor_SysTickConfig 0 00185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00186 #endif 00187 #endif 00188 00189 /* IO definitions (access restrictions to peripheral registers) */ 00190 /** 00191 \defgroup CMSIS_glob_defs CMSIS Global Defines 00192 00193 <strong>IO Type Qualifiers</strong> are used 00194 \li to specify the access to peripheral variables. 00195 \li for automatic generation of peripheral register debug information. 00196 */ 00197 #ifdef __cplusplus 00198 #define __I volatile /*!< Defines 'read only' permissions */ 00199 #else 00200 #define __I volatile const /*!< Defines 'read only' permissions */ 00201 #endif 00202 #define __O volatile /*!< Defines 'write only' permissions */ 00203 #define __IO volatile /*!< Defines 'read / write' permissions */ 00204 00205 /*@} end of group SC000 */ 00206 00207 00208 00209 /******************************************************************************* 00210 * Register Abstraction 00211 Core Register contain: 00212 - Core Register 00213 - Core NVIC Register 00214 - Core SCB Register 00215 - Core SysTick Register 00216 - Core MPU Register 00217 ******************************************************************************/ 00218 /** \defgroup CMSIS_core_register Defines and Type Definitions 00219 \brief Type definitions and defines for Cortex-M processor based devices. 00220 */ 00221 00222 /** \ingroup CMSIS_core_register 00223 \defgroup CMSIS_CORE Status and Control Registers 00224 \brief Core Register type definitions. 00225 @{ 00226 */ 00227 00228 /** \brief Union type to access the Application Program Status Register (APSR). 00229 */ 00230 typedef union 00231 { 00232 struct 00233 { 00234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 00235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00239 } b; /*!< Structure used for bit access */ 00240 uint32_t w; /*!< Type used for word access */ 00241 } APSR_Type; 00242 00243 /* APSR Register Definitions */ 00244 #define APSR_N_Pos 31 /*!< APSR: N Position */ 00245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00246 00247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */ 00248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00249 00250 #define APSR_C_Pos 29 /*!< APSR: C Position */ 00251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00252 00253 #define APSR_V_Pos 28 /*!< APSR: V Position */ 00254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00255 00256 00257 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00258 */ 00259 typedef union 00260 { 00261 struct 00262 { 00263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00265 } b; /*!< Structure used for bit access */ 00266 uint32_t w; /*!< Type used for word access */ 00267 } IPSR_Type; 00268 00269 /* IPSR Register Definitions */ 00270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ 00271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00272 00273 00274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00275 */ 00276 typedef union 00277 { 00278 struct 00279 { 00280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 00284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00288 } b; /*!< Structure used for bit access */ 00289 uint32_t w; /*!< Type used for word access */ 00290 } xPSR_Type; 00291 00292 /* xPSR Register Definitions */ 00293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */ 00294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00295 00296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ 00297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00298 00299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */ 00300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00301 00302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */ 00303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00304 00305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */ 00306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00307 00308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ 00309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00310 00311 00312 /** \brief Union type to access the Control Registers (CONTROL). 00313 */ 00314 typedef union 00315 { 00316 struct 00317 { 00318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */ 00319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00321 } b; /*!< Structure used for bit access */ 00322 uint32_t w; /*!< Type used for word access */ 00323 } CONTROL_Type; 00324 00325 /* CONTROL Register Definitions */ 00326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ 00327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00328 00329 /*@} end of group CMSIS_CORE */ 00330 00331 00332 /** \ingroup CMSIS_core_register 00333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00334 \brief Type definitions for the NVIC Registers 00335 @{ 00336 */ 00337 00338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00339 */ 00340 typedef struct 00341 { 00342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00343 uint32_t RESERVED0[31]; 00344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00345 uint32_t RSERVED1[31]; 00346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00347 uint32_t RESERVED2[31]; 00348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00349 uint32_t RESERVED3[31]; 00350 uint32_t RESERVED4[64]; 00351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00352 } NVIC_Type; 00353 00354 /*@} end of group CMSIS_NVIC */ 00355 00356 00357 /** \ingroup CMSIS_core_register 00358 \defgroup CMSIS_SCB System Control Block (SCB) 00359 \brief Type definitions for the System Control Block Registers 00360 @{ 00361 */ 00362 00363 /** \brief Structure type to access the System Control Block (SCB). 00364 */ 00365 typedef struct 00366 { 00367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00373 uint32_t RESERVED0[1]; 00374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00376 uint32_t RESERVED1[154]; 00377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ 00378 } SCB_Type; 00379 00380 /* SCB CPUID Register Definitions */ 00381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00383 00384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00386 00387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00389 00390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00392 00393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00395 00396 /* SCB Interrupt Control State Register Definitions */ 00397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00399 00400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00402 00403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00405 00406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00408 00409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00411 00412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00414 00415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00417 00418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00420 00421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00423 00424 /* SCB Interrupt Control State Register Definitions */ 00425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00427 00428 /* SCB Application Interrupt and Reset Control Register Definitions */ 00429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00431 00432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00434 00435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00437 00438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00440 00441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00443 00444 /* SCB System Control Register Definitions */ 00445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00447 00448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00450 00451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00453 00454 /* SCB Configuration Control Register Definitions */ 00455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00457 00458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00460 00461 /* SCB System Handler Control and State Register Definitions */ 00462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00464 00465 /*@} end of group CMSIS_SCB */ 00466 00467 00468 /** \ingroup CMSIS_core_register 00469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00470 \brief Type definitions for the System Control and ID Register not in the SCB 00471 @{ 00472 */ 00473 00474 /** \brief Structure type to access the System Control and ID Register not in the SCB. 00475 */ 00476 typedef struct 00477 { 00478 uint32_t RESERVED0[2]; 00479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00480 } SCnSCB_Type; 00481 00482 /* Auxiliary Control Register Definitions */ 00483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 00484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00485 00486 /*@} end of group CMSIS_SCnotSCB */ 00487 00488 00489 /** \ingroup CMSIS_core_register 00490 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00491 \brief Type definitions for the System Timer Registers. 00492 @{ 00493 */ 00494 00495 /** \brief Structure type to access the System Timer (SysTick). 00496 */ 00497 typedef struct 00498 { 00499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00503 } SysTick_Type; 00504 00505 /* SysTick Control / Status Register Definitions */ 00506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00508 00509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00511 00512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00514 00515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00517 00518 /* SysTick Reload Register Definitions */ 00519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00521 00522 /* SysTick Current Register Definitions */ 00523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00525 00526 /* SysTick Calibration Register Definitions */ 00527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00529 00530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00532 00533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00535 00536 /*@} end of group CMSIS_SysTick */ 00537 00538 #if (__MPU_PRESENT == 1) 00539 /** \ingroup CMSIS_core_register 00540 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00541 \brief Type definitions for the Memory Protection Unit (MPU) 00542 @{ 00543 */ 00544 00545 /** \brief Structure type to access the Memory Protection Unit (MPU). 00546 */ 00547 typedef struct 00548 { 00549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00554 } MPU_Type; 00555 00556 /* MPU Type Register */ 00557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 00558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00559 00560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 00561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00562 00563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 00564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 00565 00566 /* MPU Control Register */ 00567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 00568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00569 00570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 00571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00572 00573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 00574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 00575 00576 /* MPU Region Number Register */ 00577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 00578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 00579 00580 /* MPU Region Base Address Register */ 00581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ 00582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00583 00584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 00585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00586 00587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 00588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 00589 00590 /* MPU Region Attribute and Size Register */ 00591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 00592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00593 00594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 00595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00596 00597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 00598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00599 00600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 00601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00602 00603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 00604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00605 00606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 00607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00608 00609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 00610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00611 00612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 00613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00614 00615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 00616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00617 00618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 00619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 00620 00621 /*@} end of group CMSIS_MPU */ 00622 #endif 00623 00624 00625 /** \ingroup CMSIS_core_register 00626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) 00628 are only accessible over DAP and not via processor. Therefore 00629 they are not covered by the Cortex-M0 header file. 00630 @{ 00631 */ 00632 /*@} end of group CMSIS_CoreDebug */ 00633 00634 00635 /** \ingroup CMSIS_core_register 00636 \defgroup CMSIS_core_base Core Definitions 00637 \brief Definitions for base addresses, unions, and structures. 00638 @{ 00639 */ 00640 00641 /* Memory mapping of SC000 Hardware */ 00642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00646 00647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 00648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00651 00652 #if (__MPU_PRESENT == 1) 00653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00655 #endif 00656 00657 /*@} */ 00658 00659 00660 00661 /******************************************************************************* 00662 * Hardware Abstraction Layer 00663 Core Function Interface contains: 00664 - Core NVIC Functions 00665 - Core SysTick Functions 00666 - Core Register Access Functions 00667 ******************************************************************************/ 00668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00669 */ 00670 00671 00672 00673 /* ########################## NVIC functions #################################### */ 00674 /** \ingroup CMSIS_Core_FunctionInterface 00675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00676 \brief Functions that manage interrupts and exceptions via the NVIC. 00677 @{ 00678 */ 00679 00680 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00681 /* The following MACROS handle generation of the register offset and byte masks */ 00682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 00683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 00684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 00685 00686 00687 /** \brief Enable External Interrupt 00688 00689 The function enables a device-specific interrupt in the NVIC interrupt controller. 00690 00691 \param [in] IRQn External interrupt number. Value cannot be negative. 00692 */ 00693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00694 { 00695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00696 } 00697 00698 00699 /** \brief Disable External Interrupt 00700 00701 The function disables a device-specific interrupt in the NVIC interrupt controller. 00702 00703 \param [in] IRQn External interrupt number. Value cannot be negative. 00704 */ 00705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00706 { 00707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00708 __DSB(); 00709 __ISB(); 00710 } 00711 00712 00713 /** \brief Get Pending Interrupt 00714 00715 The function reads the pending register in the NVIC and returns the pending bit 00716 for the specified interrupt. 00717 00718 \param [in] IRQn Interrupt number. 00719 00720 \return 0 Interrupt status is not pending. 00721 \return 1 Interrupt status is pending. 00722 */ 00723 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00724 { 00725 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 00726 } 00727 00728 00729 /** \brief Set Pending Interrupt 00730 00731 The function sets the pending bit of an external interrupt. 00732 00733 \param [in] IRQn Interrupt number. Value cannot be negative. 00734 */ 00735 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00736 { 00737 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00738 } 00739 00740 00741 /** \brief Clear Pending Interrupt 00742 00743 The function clears the pending bit of an external interrupt. 00744 00745 \param [in] IRQn External interrupt number. Value cannot be negative. 00746 */ 00747 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00748 { 00749 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 00750 } 00751 00752 00753 /** \brief Set Interrupt Priority 00754 00755 The function sets the priority of an interrupt. 00756 00757 \note The priority cannot be set for every core interrupt. 00758 00759 \param [in] IRQn Interrupt number. 00760 \param [in] priority Priority to set. 00761 */ 00762 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00763 { 00764 if((int32_t)(IRQn) < 0) { 00765 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00766 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00767 } 00768 else { 00769 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 00770 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 00771 } 00772 } 00773 00774 00775 /** \brief Get Interrupt Priority 00776 00777 The function reads the priority of an interrupt. The interrupt 00778 number can be positive to specify an external (device specific) 00779 interrupt, or negative to specify an internal (core) interrupt. 00780 00781 00782 \param [in] IRQn Interrupt number. 00783 \return Interrupt Priority. Value is aligned automatically to the implemented 00784 priority bits of the microcontroller. 00785 */ 00786 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00787 { 00788 00789 if((int32_t)(IRQn) < 0) { 00790 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); 00791 } 00792 else { 00793 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); 00794 } 00795 } 00796 00797 00798 /** \brief System Reset 00799 00800 The function initiates a system reset request to reset the MCU. 00801 */ 00802 __STATIC_INLINE void NVIC_SystemReset(void) 00803 { 00804 __DSB(); /* Ensure all outstanding memory accesses included 00805 buffered write are completed before reset */ 00806 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 00807 SCB_AIRCR_SYSRESETREQ_Msk); 00808 __DSB(); /* Ensure completion of memory access */ 00809 while(1) { __NOP(); } /* wait until reset */ 00810 } 00811 00812 /*@} end of CMSIS_Core_NVICFunctions */ 00813 00814 00815 00816 /* ################################## SysTick function ############################################ */ 00817 /** \ingroup CMSIS_Core_FunctionInterface 00818 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00819 \brief Functions that configure the System. 00820 @{ 00821 */ 00822 00823 #if (__Vendor_SysTickConfig == 0) 00824 00825 /** \brief System Tick Configuration 00826 00827 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00828 Counter is in free running mode to generate periodic interrupts. 00829 00830 \param [in] ticks Number of ticks between two interrupts. 00831 00832 \return 0 Function succeeded. 00833 \return 1 Function failed. 00834 00835 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00836 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00837 must contain a vendor-specific implementation of this function. 00838 00839 */ 00840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00841 { 00842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ 00843 00844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 00845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 00846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 00847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00848 SysTick_CTRL_TICKINT_Msk | 00849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00850 return (0UL); /* Function successful */ 00851 } 00852 00853 #endif 00854 00855 /*@} end of CMSIS_Core_SysTickFunctions */ 00856 00857 00858 00859 00860 #ifdef __cplusplus 00861 } 00862 #endif 00863 00864 #endif /* __CORE_SC000_H_DEPENDANT */ 00865 00866 #endif /* __CMSIS_GENERIC */
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