core_cm3.h

00001 /**************************************************************************//**
00002  * @file     core_cm3.h
00003  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
00004  * @version  V4.10
00005  * @date     18. March 2015
00006  *
00007  * @note
00008  *
00009  ******************************************************************************/
00010 /* Copyright (c) 2009 - 2015 ARM LIMITED
00011 
00012    All rights reserved.
00013    Redistribution and use in source and binary forms, with or without
00014    modification, are permitted provided that the following conditions are met:
00015    - Redistributions of source code must retain the above copyright
00016      notice, this list of conditions and the following disclaimer.
00017    - Redistributions in binary form must reproduce the above copyright
00018      notice, this list of conditions and the following disclaimer in the
00019      documentation and/or other materials provided with the distribution.
00020    - Neither the name of ARM nor the names of its contributors may be used
00021      to endorse or promote products derived from this software without
00022      specific prior written permission.
00023    *
00024    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00027    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
00028    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00029    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00030    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00031    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00032    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00033    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00034    POSSIBILITY OF SUCH DAMAGE.
00035    ---------------------------------------------------------------------------*/
00036 
00037 
00038 #if defined ( __ICCARM__ )
00039  #pragma system_include  /* treat file as system include file for MISRA check */
00040 #endif
00041 
00042 #ifndef __CORE_CM3_H_GENERIC
00043 #define __CORE_CM3_H_GENERIC
00044 
00045 #ifdef __cplusplus
00046  extern "C" {
00047 #endif
00048 
00049 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00050   CMSIS violates the following MISRA-C:2004 rules:
00051 
00052    \li Required Rule 8.5, object/function definition in header file.<br>
00053      Function definitions in header files are used to allow 'inlining'.
00054 
00055    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00056      Unions are used for effective representation of core registers.
00057 
00058    \li Advisory Rule 19.7, Function-like macro defined.<br>
00059      Function-like macros are used to allow more efficient code.
00060  */
00061 
00062 
00063 /*******************************************************************************
00064  *                 CMSIS definitions
00065  ******************************************************************************/
00066 /** \ingroup Cortex_M3
00067   @{
00068  */
00069 
00070 /*  CMSIS CM3 definitions */
00071 #define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
00072 #define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
00073 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
00074                                     __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
00075 
00076 #define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
00077 
00078 
00079 #if   defined ( __CC_ARM )
00080   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
00081   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
00082   #define __STATIC_INLINE  static __inline
00083 
00084 #elif defined ( __GNUC__ )
00085   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
00086   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
00087   #define __STATIC_INLINE  static inline
00088 
00089 #elif defined ( __ICCARM__ )
00090   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
00091   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
00092   #define __STATIC_INLINE  static inline
00093 
00094 #elif defined ( __TMS470__ )
00095   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
00096   #define __STATIC_INLINE  static inline
00097 
00098 #elif defined ( __TASKING__ )
00099   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
00100   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
00101   #define __STATIC_INLINE  static inline
00102 
00103 #elif defined ( __CSMC__ )
00104   #define __packed
00105   #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
00106   #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
00107   #define __STATIC_INLINE  static inline
00108 
00109 #endif
00110 
00111 /** __FPU_USED indicates whether an FPU is used or not.
00112     This core does not support an FPU at all
00113 */
00114 #define __FPU_USED       0
00115 
00116 #if defined ( __CC_ARM )
00117   #if defined __TARGET_FPU_VFP
00118     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00119   #endif
00120 
00121 #elif defined ( __GNUC__ )
00122   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00123     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00124   #endif
00125 
00126 #elif defined ( __ICCARM__ )
00127   #if defined __ARMVFP__
00128     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00129   #endif
00130 
00131 #elif defined ( __TMS470__ )
00132   #if defined __TI__VFP_SUPPORT____
00133     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00134   #endif
00135 
00136 #elif defined ( __TASKING__ )
00137   #if defined __FPU_VFP__
00138     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00139   #endif
00140 
00141 #elif defined ( __CSMC__ )      /* Cosmic */
00142   #if ( __CSMC__ & 0x400)       // FPU present for parser
00143     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00144   #endif
00145 #endif
00146 
00147 #include <stdint.h>                      /* standard types definitions                      */
00148 #include <core_cmInstr.h>                /* Core Instruction Access                         */
00149 #include <core_cmFunc.h>                 /* Core Function Access                            */
00150 
00151 #ifdef __cplusplus
00152 }
00153 #endif
00154 
00155 #endif /* __CORE_CM3_H_GENERIC */
00156 
00157 #ifndef __CMSIS_GENERIC
00158 
00159 #ifndef __CORE_CM3_H_DEPENDANT
00160 #define __CORE_CM3_H_DEPENDANT
00161 
00162 #ifdef __cplusplus
00163  extern "C" {
00164 #endif
00165 
00166 /* check device defines and use defaults */
00167 #if defined __CHECK_DEVICE_DEFINES
00168   #ifndef __CM3_REV
00169     #define __CM3_REV               0x0200
00170     #warning "__CM3_REV not defined in device header file; using default!"
00171   #endif
00172 
00173   #ifndef __MPU_PRESENT
00174     #define __MPU_PRESENT             0
00175     #warning "__MPU_PRESENT not defined in device header file; using default!"
00176   #endif
00177 
00178   #ifndef __NVIC_PRIO_BITS
00179     #define __NVIC_PRIO_BITS          4
00180     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00181   #endif
00182 
00183   #ifndef __Vendor_SysTickConfig
00184     #define __Vendor_SysTickConfig    0
00185     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00186   #endif
00187 #endif
00188 
00189 /* IO definitions (access restrictions to peripheral registers) */
00190 /**
00191     \defgroup CMSIS_glob_defs CMSIS Global Defines
00192 
00193     <strong>IO Type Qualifiers</strong> are used
00194     \li to specify the access to peripheral variables.
00195     \li for automatic generation of peripheral register debug information.
00196 */
00197 #ifdef __cplusplus
00198   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
00199 #else
00200   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
00201 #endif
00202 #define     __O     volatile             /*!< Defines 'write only' permissions                */
00203 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
00204 
00205 #ifdef __cplusplus
00206   #define   __IM    volatile             /*!< Defines 'read only' permissions                 */
00207 #else
00208   #define   __IM    volatile const       /*!< Defines 'read only' permissions                 */
00209 #endif
00210 #define     __OM    volatile             /*!< Defines 'write only' permissions                */
00211 #define     __IOM   volatile             /*!< Defines 'read / write' permissions              */
00212 
00213 /*@} end of group Cortex_M3 */
00214 
00215 
00216 
00217 /*******************************************************************************
00218  *                 Register Abstraction
00219   Core Register contain:
00220   - Core Register
00221   - Core NVIC Register
00222   - Core SCB Register
00223   - Core SysTick Register
00224   - Core Debug Register
00225   - Core MPU Register
00226  ******************************************************************************/
00227 /** \defgroup CMSIS_core_register Defines and Type Definitions
00228     \brief Type definitions and defines for Cortex-M processor based devices.
00229 */
00230 
00231 /** \ingroup    CMSIS_core_register
00232     \defgroup   CMSIS_CORE  Status and Control Registers
00233     \brief  Core Register type definitions.
00234   @{
00235  */
00236 
00237 /** \brief  Union type to access the Application Program Status Register (APSR).
00238  */
00239 typedef union
00240 {
00241   struct
00242   {
00243     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
00244     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00245     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00246     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00247     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00248     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00249   } b;                                   /*!< Structure used for bit  access                  */
00250   uint32_t w;                            /*!< Type      used for word access                  */
00251 } APSR_Type;
00252 
00253 /* APSR Register Definitions */
00254 #define APSR_N_Pos                         31                                             /*!< APSR: N Position */
00255 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
00256 
00257 #define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
00258 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
00259 
00260 #define APSR_C_Pos                         29                                             /*!< APSR: C Position */
00261 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
00262 
00263 #define APSR_V_Pos                         28                                             /*!< APSR: V Position */
00264 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
00265 
00266 #define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
00267 #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
00268 
00269 
00270 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
00271  */
00272 typedef union
00273 {
00274   struct
00275   {
00276     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00277     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
00278   } b;                                   /*!< Structure used for bit  access                  */
00279   uint32_t w;                            /*!< Type      used for word access                  */
00280 } IPSR_Type;
00281 
00282 /* IPSR Register Definitions */
00283 #define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
00284 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
00285 
00286 
00287 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00288  */
00289 typedef union
00290 {
00291   struct
00292   {
00293     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00294     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
00295     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
00296     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
00297     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00298     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00299     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00300     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00301     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00302   } b;                                   /*!< Structure used for bit  access                  */
00303   uint32_t w;                            /*!< Type      used for word access                  */
00304 } xPSR_Type;
00305 
00306 /* xPSR Register Definitions */
00307 #define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
00308 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
00309 
00310 #define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
00311 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
00312 
00313 #define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
00314 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
00315 
00316 #define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
00317 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
00318 
00319 #define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
00320 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
00321 
00322 #define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
00323 #define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
00324 
00325 #define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
00326 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
00327 
00328 #define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
00329 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
00330 
00331 
00332 /** \brief  Union type to access the Control Registers (CONTROL).
00333  */
00334 typedef union
00335 {
00336   struct
00337   {
00338     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
00339     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
00340     uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
00341   } b;                                   /*!< Structure used for bit  access                  */
00342   uint32_t w;                            /*!< Type      used for word access                  */
00343 } CONTROL_Type;
00344 
00345 /* CONTROL Register Definitions */
00346 #define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
00347 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
00348 
00349 #define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
00350 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
00351 
00352 /*@} end of group CMSIS_CORE */
00353 
00354 
00355 /** \ingroup    CMSIS_core_register
00356     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00357     \brief      Type definitions for the NVIC Registers
00358   @{
00359  */
00360 
00361 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00362  */
00363 typedef struct
00364 {
00365   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
00366        uint32_t RESERVED0[24];
00367   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
00368        uint32_t RSERVED1[24];
00369   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
00370        uint32_t RESERVED2[24];
00371   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
00372        uint32_t RESERVED3[24];
00373   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
00374        uint32_t RESERVED4[56];
00375   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
00376        uint32_t RESERVED5[644];
00377   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
00378 }  NVIC_Type;
00379 
00380 /* Software Triggered Interrupt Register Definitions */
00381 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
00382 #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
00383 
00384 /*@} end of group CMSIS_NVIC */
00385 
00386 
00387 /** \ingroup  CMSIS_core_register
00388     \defgroup CMSIS_SCB     System Control Block (SCB)
00389     \brief      Type definitions for the System Control Block Registers
00390   @{
00391  */
00392 
00393 /** \brief  Structure type to access the System Control Block (SCB).
00394  */
00395 typedef struct
00396 {
00397   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
00398   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
00399   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
00400   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
00401   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
00402   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
00403   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
00404   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
00405   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
00406   __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
00407   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
00408   __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
00409   __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
00410   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
00411   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
00412   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
00413   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
00414   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
00415   __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
00416        uint32_t RESERVED0[5];
00417   __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
00418 } SCB_Type;
00419 
00420 /* SCB CPUID Register Definitions */
00421 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
00422 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00423 
00424 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
00425 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00426 
00427 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
00428 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00429 
00430 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
00431 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00432 
00433 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
00434 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
00435 
00436 /* SCB Interrupt Control State Register Definitions */
00437 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
00438 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00439 
00440 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
00441 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00442 
00443 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
00444 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00445 
00446 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
00447 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00448 
00449 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
00450 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00451 
00452 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
00453 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00454 
00455 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
00456 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00457 
00458 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
00459 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00460 
00461 #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
00462 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
00463 
00464 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
00465 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
00466 
00467 /* SCB Vector Table Offset Register Definitions */
00468 #if (__CM3_REV < 0x0201)                   /* core r2p1 */
00469 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
00470 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
00471 
00472 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00473 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
00474 #else
00475 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00476 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
00477 #endif
00478 
00479 /* SCB Application Interrupt and Reset Control Register Definitions */
00480 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
00481 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00482 
00483 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
00484 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00485 
00486 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
00487 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00488 
00489 #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
00490 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
00491 
00492 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
00493 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00494 
00495 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
00496 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00497 
00498 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
00499 #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
00500 
00501 /* SCB System Control Register Definitions */
00502 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
00503 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00504 
00505 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
00506 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00507 
00508 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
00509 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00510 
00511 /* SCB Configuration Control Register Definitions */
00512 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
00513 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00514 
00515 #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
00516 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
00517 
00518 #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
00519 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
00520 
00521 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
00522 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00523 
00524 #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
00525 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
00526 
00527 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
00528 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
00529 
00530 /* SCB System Handler Control and State Register Definitions */
00531 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
00532 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
00533 
00534 #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
00535 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
00536 
00537 #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
00538 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
00539 
00540 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
00541 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00542 
00543 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
00544 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
00545 
00546 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
00547 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
00548 
00549 #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
00550 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
00551 
00552 #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
00553 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
00554 
00555 #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
00556 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
00557 
00558 #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
00559 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
00560 
00561 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
00562 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
00563 
00564 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
00565 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
00566 
00567 #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
00568 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
00569 
00570 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
00571 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
00572 
00573 /* SCB Configurable Fault Status Registers Definitions */
00574 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
00575 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
00576 
00577 #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
00578 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
00579 
00580 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
00581 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
00582 
00583 /* SCB Hard Fault Status Registers Definitions */
00584 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
00585 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
00586 
00587 #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
00588 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
00589 
00590 #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
00591 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
00592 
00593 /* SCB Debug Fault Status Register Definitions */
00594 #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
00595 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
00596 
00597 #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
00598 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
00599 
00600 #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
00601 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
00602 
00603 #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
00604 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
00605 
00606 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
00607 #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
00608 
00609 /*@} end of group CMSIS_SCB */
00610 
00611 
00612 /** \ingroup  CMSIS_core_register
00613     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
00614     \brief      Type definitions for the System Control and ID Register not in the SCB
00615   @{
00616  */
00617 
00618 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
00619  */
00620 typedef struct
00621 {
00622        uint32_t RESERVED0[1];
00623   __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
00624 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
00625   __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
00626 #else
00627        uint32_t RESERVED1[1];
00628 #endif
00629 } SCnSCB_Type;
00630 
00631 /* Interrupt Controller Type Register Definitions */
00632 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
00633 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
00634 
00635 /* Auxiliary Control Register Definitions */
00636 
00637 #define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
00638 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
00639 
00640 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
00641 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
00642 
00643 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
00644 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
00645 
00646 /*@} end of group CMSIS_SCnotSCB */
00647 
00648 
00649 /** \ingroup  CMSIS_core_register
00650     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00651     \brief      Type definitions for the System Timer Registers.
00652   @{
00653  */
00654 
00655 /** \brief  Structure type to access the System Timer (SysTick).
00656  */
00657 typedef struct
00658 {
00659   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00660   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
00661   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
00662   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
00663 } SysTick_Type;
00664 
00665 /* SysTick Control / Status Register Definitions */
00666 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
00667 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00668 
00669 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
00670 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00671 
00672 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
00673 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00674 
00675 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
00676 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
00677 
00678 /* SysTick Reload Register Definitions */
00679 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
00680 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
00681 
00682 /* SysTick Current Register Definitions */
00683 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
00684 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
00685 
00686 /* SysTick Calibration Register Definitions */
00687 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
00688 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00689 
00690 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
00691 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00692 
00693 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
00694 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
00695 
00696 /*@} end of group CMSIS_SysTick */
00697 
00698 
00699 /** \ingroup  CMSIS_core_register
00700     \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
00701     \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
00702   @{
00703  */
00704 
00705 /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
00706  */
00707 typedef struct
00708 {
00709   __O  union
00710   {
00711     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
00712     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
00713     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
00714   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
00715        uint32_t RESERVED0[864];
00716   __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
00717        uint32_t RESERVED1[15];
00718   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
00719        uint32_t RESERVED2[15];
00720   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
00721        uint32_t RESERVED3[29];
00722   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
00723   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
00724   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
00725        uint32_t RESERVED4[43];
00726   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
00727   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
00728        uint32_t RESERVED5[6];
00729   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
00730   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
00731   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
00732   __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
00733   __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
00734   __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
00735   __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
00736   __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
00737   __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
00738   __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
00739   __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
00740   __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
00741 } ITM_Type;
00742 
00743 /* ITM Trace Privilege Register Definitions */
00744 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
00745 #define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
00746 
00747 /* ITM Trace Control Register Definitions */
00748 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
00749 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
00750 
00751 #define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
00752 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
00753 
00754 #define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
00755 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
00756 
00757 #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
00758 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
00759 
00760 #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
00761 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
00762 
00763 #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
00764 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
00765 
00766 #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
00767 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
00768 
00769 #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
00770 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
00771 
00772 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
00773 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
00774 
00775 /* ITM Integration Write Register Definitions */
00776 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
00777 #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
00778 
00779 /* ITM Integration Read Register Definitions */
00780 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
00781 #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
00782 
00783 /* ITM Integration Mode Control Register Definitions */
00784 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
00785 #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
00786 
00787 /* ITM Lock Status Register Definitions */
00788 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
00789 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
00790 
00791 #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
00792 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
00793 
00794 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
00795 #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
00796 
00797 /*@}*/ /* end of group CMSIS_ITM */
00798 
00799 
00800 /** \ingroup  CMSIS_core_register
00801     \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
00802     \brief      Type definitions for the Data Watchpoint and Trace (DWT)
00803   @{
00804  */
00805 
00806 /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
00807  */
00808 typedef struct
00809 {
00810   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
00811   __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
00812   __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
00813   __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
00814   __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
00815   __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
00816   __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
00817   __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
00818   __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
00819   __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
00820   __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
00821        uint32_t RESERVED0[1];
00822   __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
00823   __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
00824   __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
00825        uint32_t RESERVED1[1];
00826   __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
00827   __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
00828   __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
00829        uint32_t RESERVED2[1];
00830   __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
00831   __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
00832   __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
00833 } DWT_Type;
00834 
00835 /* DWT Control Register Definitions */
00836 #define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
00837 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
00838 
00839 #define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
00840 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
00841 
00842 #define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
00843 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
00844 
00845 #define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
00846 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
00847 
00848 #define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
00849 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
00850 
00851 #define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
00852 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
00853 
00854 #define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
00855 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
00856 
00857 #define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
00858 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
00859 
00860 #define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
00861 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
00862 
00863 #define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
00864 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
00865 
00866 #define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
00867 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
00868 
00869 #define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
00870 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
00871 
00872 #define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
00873 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
00874 
00875 #define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
00876 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
00877 
00878 #define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
00879 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
00880 
00881 #define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
00882 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
00883 
00884 #define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
00885 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
00886 
00887 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
00888 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
00889 
00890 /* DWT CPI Count Register Definitions */
00891 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
00892 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
00893 
00894 /* DWT Exception Overhead Count Register Definitions */
00895 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
00896 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
00897 
00898 /* DWT Sleep Count Register Definitions */
00899 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
00900 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
00901 
00902 /* DWT LSU Count Register Definitions */
00903 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
00904 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
00905 
00906 /* DWT Folded-instruction Count Register Definitions */
00907 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
00908 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
00909 
00910 /* DWT Comparator Mask Register Definitions */
00911 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
00912 #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
00913 
00914 /* DWT Comparator Function Register Definitions */
00915 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
00916 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
00917 
00918 #define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
00919 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
00920 
00921 #define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
00922 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
00923 
00924 #define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
00925 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
00926 
00927 #define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
00928 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
00929 
00930 #define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
00931 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
00932 
00933 #define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
00934 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
00935 
00936 #define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
00937 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
00938 
00939 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
00940 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
00941 
00942 /*@}*/ /* end of group CMSIS_DWT */
00943 
00944 
00945 /** \ingroup  CMSIS_core_register
00946     \defgroup CMSIS_TPI     Trace Port Interface (TPI)
00947     \brief      Type definitions for the Trace Port Interface (TPI)
00948   @{
00949  */
00950 
00951 /** \brief  Structure type to access the Trace Port Interface Register (TPI).
00952  */
00953 typedef struct
00954 {
00955   __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
00956   __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
00957        uint32_t RESERVED0[2];
00958   __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
00959        uint32_t RESERVED1[55];
00960   __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
00961        uint32_t RESERVED2[131];
00962   __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
00963   __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
00964   __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
00965        uint32_t RESERVED3[759];
00966   __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
00967   __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
00968   __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
00969        uint32_t RESERVED4[1];
00970   __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
00971   __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
00972   __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
00973        uint32_t RESERVED5[39];
00974   __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
00975   __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
00976        uint32_t RESERVED7[8];
00977   __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
00978   __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
00979 } TPI_Type;
00980 
00981 /* TPI Asynchronous Clock Prescaler Register Definitions */
00982 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
00983 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
00984 
00985 /* TPI Selected Pin Protocol Register Definitions */
00986 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
00987 #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
00988 
00989 /* TPI Formatter and Flush Status Register Definitions */
00990 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
00991 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
00992 
00993 #define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
00994 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
00995 
00996 #define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
00997 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
00998 
00999 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
01000 #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
01001 
01002 /* TPI Formatter and Flush Control Register Definitions */
01003 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
01004 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
01005 
01006 #define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
01007 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
01008 
01009 /* TPI TRIGGER Register Definitions */
01010 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
01011 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
01012 
01013 /* TPI Integration ETM Data Register Definitions (FIFO0) */
01014 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
01015 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
01016 
01017 #define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
01018 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
01019 
01020 #define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
01021 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
01022 
01023 #define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
01024 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
01025 
01026 #define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
01027 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
01028 
01029 #define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
01030 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
01031 
01032 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
01033 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
01034 
01035 /* TPI ITATBCTR2 Register Definitions */
01036 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
01037 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
01038 
01039 /* TPI Integration ITM Data Register Definitions (FIFO1) */
01040 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
01041 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
01042 
01043 #define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
01044 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
01045 
01046 #define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
01047 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
01048 
01049 #define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
01050 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
01051 
01052 #define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
01053 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
01054 
01055 #define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
01056 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
01057 
01058 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
01059 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
01060 
01061 /* TPI ITATBCTR0 Register Definitions */
01062 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
01063 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
01064 
01065 /* TPI Integration Mode Control Register Definitions */
01066 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
01067 #define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
01068 
01069 /* TPI DEVID Register Definitions */
01070 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
01071 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
01072 
01073 #define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
01074 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
01075 
01076 #define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
01077 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
01078 
01079 #define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
01080 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
01081 
01082 #define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
01083 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
01084 
01085 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
01086 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
01087 
01088 /* TPI DEVTYPE Register Definitions */
01089 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
01090 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
01091 
01092 #define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
01093 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
01094 
01095 /*@}*/ /* end of group CMSIS_TPI */
01096 
01097 
01098 #if (__MPU_PRESENT == 1)
01099 /** \ingroup  CMSIS_core_register
01100     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
01101     \brief      Type definitions for the Memory Protection Unit (MPU)
01102   @{
01103  */
01104 
01105 /** \brief  Structure type to access the Memory Protection Unit (MPU).
01106  */
01107 typedef struct
01108 {
01109   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
01110   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
01111   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
01112   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
01113   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
01114   __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
01115   __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
01116   __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
01117   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
01118   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
01119   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
01120 } MPU_Type;
01121 
01122 /* MPU Type Register */
01123 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
01124 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
01125 
01126 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
01127 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
01128 
01129 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
01130 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
01131 
01132 /* MPU Control Register */
01133 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
01134 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
01135 
01136 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
01137 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
01138 
01139 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
01140 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
01141 
01142 /* MPU Region Number Register */
01143 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
01144 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
01145 
01146 /* MPU Region Base Address Register */
01147 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
01148 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
01149 
01150 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
01151 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
01152 
01153 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
01154 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
01155 
01156 /* MPU Region Attribute and Size Register */
01157 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
01158 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
01159 
01160 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
01161 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
01162 
01163 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
01164 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
01165 
01166 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
01167 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
01168 
01169 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
01170 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
01171 
01172 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
01173 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
01174 
01175 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
01176 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
01177 
01178 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
01179 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
01180 
01181 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
01182 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
01183 
01184 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
01185 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
01186 
01187 /*@} end of group CMSIS_MPU */
01188 #endif
01189 
01190 
01191 /** \ingroup  CMSIS_core_register
01192     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
01193     \brief      Type definitions for the Core Debug Registers
01194   @{
01195  */
01196 
01197 /** \brief  Structure type to access the Core Debug Register (CoreDebug).
01198  */
01199 typedef struct
01200 {
01201   __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
01202   __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
01203   __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
01204   __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
01205 } CoreDebug_Type;
01206 
01207 /* Debug Halting Control and Status Register */
01208 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
01209 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
01210 
01211 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
01212 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
01213 
01214 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
01215 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
01216 
01217 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
01218 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
01219 
01220 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
01221 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
01222 
01223 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
01224 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
01225 
01226 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
01227 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
01228 
01229 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
01230 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
01231 
01232 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
01233 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
01234 
01235 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
01236 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
01237 
01238 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
01239 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
01240 
01241 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
01242 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
01243 
01244 /* Debug Core Register Selector Register */
01245 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
01246 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
01247 
01248 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
01249 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
01250 
01251 /* Debug Exception and Monitor Control Register */
01252 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
01253 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
01254 
01255 #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
01256 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
01257 
01258 #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
01259 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
01260 
01261 #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
01262 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
01263 
01264 #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
01265 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
01266 
01267 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
01268 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
01269 
01270 #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
01271 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
01272 
01273 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
01274 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
01275 
01276 #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
01277 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
01278 
01279 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
01280 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
01281 
01282 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
01283 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
01284 
01285 #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
01286 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
01287 
01288 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
01289 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
01290 
01291 /*@} end of group CMSIS_CoreDebug */
01292 
01293 
01294 /** \ingroup    CMSIS_core_register
01295     \defgroup   CMSIS_core_base     Core Definitions
01296     \brief      Definitions for base addresses, unions, and structures.
01297   @{
01298  */
01299 
01300 /* Memory mapping of Cortex-M3 Hardware */
01301 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
01302 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
01303 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
01304 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
01305 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
01306 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
01307 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
01308 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
01309 
01310 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
01311 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
01312 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
01313 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
01314 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
01315 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
01316 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
01317 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
01318 
01319 #if (__MPU_PRESENT == 1)
01320   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
01321   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
01322 #endif
01323 
01324 /*@} */
01325 
01326 
01327 
01328 /*******************************************************************************
01329  *                Hardware Abstraction Layer
01330   Core Function Interface contains:
01331   - Core NVIC Functions
01332   - Core SysTick Functions
01333   - Core Debug Functions
01334   - Core Register Access Functions
01335  ******************************************************************************/
01336 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
01337 */
01338 
01339 
01340 
01341 /* ##########################   NVIC functions  #################################### */
01342 /** \ingroup  CMSIS_Core_FunctionInterface
01343     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
01344     \brief      Functions that manage interrupts and exceptions via the NVIC.
01345     @{
01346  */
01347 
01348 #ifdef CMSIS_NVIC_VIRTUAL
01349   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
01350     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
01351   #endif
01352   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
01353 #else
01354   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
01355   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
01356   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
01357   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
01358   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
01359   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
01360   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
01361   #define NVIC_GetActive              __NVIC_GetActive
01362   #define NVIC_SetPriority            __NVIC_SetPriority
01363   #define NVIC_GetPriority            __NVIC_GetPriority
01364   #define NVIC_SystemReset            __NVIC_SystemReset
01365 #endif /* CMSIS_NVIC_VIRTUAL */
01366 
01367 #ifdef CMSIS_VECTAB_VIRTUAL
01368   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
01369    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
01370   #endif
01371   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
01372 #else
01373   #define NVIC_SetVector              __NVIC_SetVector
01374   #define NVIC_GetVector              __NVIC_GetVector
01375 #endif  /* CMSIS_VECTAB_VIRTUAL */
01376 
01377 /** \brief  Set Priority Grouping
01378 
01379   The function sets the priority grouping field using the required unlock sequence.
01380   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
01381   Only values from 0..7 are used.
01382   In case of a conflict between priority grouping and available
01383   priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01384 
01385     \param [in]      PriorityGroup  Priority grouping field.
01386  */
01387 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
01388 {
01389   uint32_t reg_value;
01390   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
01391 
01392   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
01393   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
01394   reg_value  =  (reg_value                                   |
01395                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
01396                 (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
01397   SCB->AIRCR =  reg_value;
01398 }
01399 
01400 
01401 /** \brief  Get Priority Grouping
01402 
01403   The function reads the priority grouping field from the NVIC Interrupt Controller.
01404 
01405     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
01406  */
01407 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
01408 {
01409   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
01410 }
01411 
01412 
01413 /** \brief  Enable External Interrupt
01414 
01415     The function enables a device-specific interrupt in the NVIC interrupt controller.
01416 
01417     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01418  */
01419 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
01420 {
01421   NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
01422 }
01423 
01424 
01425 /** \brief  Disable External Interrupt
01426 
01427     The function disables a device-specific interrupt in the NVIC interrupt controller.
01428 
01429     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01430  */
01431 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
01432 {
01433   NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
01434   __DSB();
01435   __ISB();
01436 }
01437 
01438 
01439 /** \brief  Get Pending Interrupt
01440 
01441     The function reads the pending register in the NVIC and returns the pending bit
01442     for the specified interrupt.
01443 
01444     \param [in]      IRQn  Interrupt number.
01445 
01446     \return             0  Interrupt status is not pending.
01447     \return             1  Interrupt status is pending.
01448  */
01449 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
01450 {
01451   return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
01452 }
01453 
01454 
01455 /** \brief  Set Pending Interrupt
01456 
01457     The function sets the pending bit of an external interrupt.
01458 
01459     \param [in]      IRQn  Interrupt number. Value cannot be negative.
01460  */
01461 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
01462 {
01463   NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
01464 }
01465 
01466 
01467 /** \brief  Clear Pending Interrupt
01468 
01469     The function clears the pending bit of an external interrupt.
01470 
01471     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01472  */
01473 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
01474 {
01475   NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
01476 }
01477 
01478 
01479 /** \brief  Get Active Interrupt
01480 
01481     The function reads the active register in NVIC and returns the active bit.
01482 
01483     \param [in]      IRQn  Interrupt number.
01484 
01485     \return             0  Interrupt status is not active.
01486     \return             1  Interrupt status is active.
01487  */
01488 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
01489 {
01490   return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
01491 }
01492 
01493 
01494 /** \brief  Set Interrupt Priority
01495 
01496     The function sets the priority of an interrupt.
01497 
01498     \note The priority cannot be set for every core interrupt.
01499 
01500     \param [in]      IRQn  Interrupt number.
01501     \param [in]  priority  Priority to set.
01502  */
01503 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
01504 {
01505   if((int32_t)IRQn < 0) {
01506     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
01507   }
01508   else {
01509     NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
01510   }
01511 }
01512 
01513 
01514 /** \brief  Get Interrupt Priority
01515 
01516     The function reads the priority of an interrupt. The interrupt
01517     number can be positive to specify an external (device specific)
01518     interrupt, or negative to specify an internal (core) interrupt.
01519 
01520 
01521     \param [in]   IRQn  Interrupt number.
01522     \return             Interrupt Priority. Value is aligned automatically to the implemented
01523                         priority bits of the microcontroller.
01524  */
01525 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
01526 {
01527 
01528   if((int32_t)IRQn < 0) {
01529     return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
01530   }
01531   else {
01532     return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
01533   }
01534 }
01535 
01536 
01537 /** \brief  Encode Priority
01538 
01539     The function encodes the priority for an interrupt with the given priority group,
01540     preemptive priority value, and subpriority value.
01541     In case of a conflict between priority grouping and available
01542     priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01543 
01544     \param [in]     PriorityGroup  Used priority group.
01545     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
01546     \param [in]       SubPriority  Subpriority value (starting from 0).
01547     \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
01548  */
01549 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
01550 {
01551   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
01552   uint32_t PreemptPriorityBits;
01553   uint32_t SubPriorityBits;
01554 
01555   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
01556   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
01557 
01558   return (
01559            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
01560            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
01561          );
01562 }
01563 
01564 
01565 /** \brief  Decode Priority
01566 
01567     The function decodes an interrupt priority value with a given priority group to
01568     preemptive priority value and subpriority value.
01569     In case of a conflict between priority grouping and available
01570     priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
01571 
01572     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
01573     \param [in]     PriorityGroup  Used priority group.
01574     \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
01575     \param [out]     pSubPriority  Subpriority value (starting from 0).
01576  */
01577 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
01578 {
01579   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
01580   uint32_t PreemptPriorityBits;
01581   uint32_t SubPriorityBits;
01582 
01583   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
01584   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
01585 
01586   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
01587   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
01588 }
01589 
01590 
01591 /** \brief  System Reset
01592 
01593     The function initiates a system reset request to reset the MCU.
01594  */
01595 __STATIC_INLINE void __NVIC_SystemReset(void)
01596 {
01597   __DSB();                                                          /* Ensure all outstanding memory accesses included
01598                                                                        buffered write are completed before reset */
01599   SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
01600                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
01601                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
01602   __DSB();                                                          /* Ensure completion of memory access */
01603   while(1) { __NOP(); }                                             /* wait until reset */
01604 }
01605 
01606 /*@} end of CMSIS_Core_NVICFunctions */
01607 
01608 
01609 
01610 /* ##################################    SysTick function  ############################################ */
01611 /** \ingroup  CMSIS_Core_FunctionInterface
01612     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
01613     \brief      Functions that configure the System.
01614   @{
01615  */
01616 
01617 #if (__Vendor_SysTickConfig == 0)
01618 
01619 /** \brief  System Tick Configuration
01620 
01621     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
01622     Counter is in free running mode to generate periodic interrupts.
01623 
01624     \param [in]  ticks  Number of ticks between two interrupts.
01625 
01626     \return          0  Function succeeded.
01627     \return          1  Function failed.
01628 
01629     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
01630     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
01631     must contain a vendor-specific implementation of this function.
01632 
01633  */
01634 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
01635 {
01636   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
01637 
01638   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
01639   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
01640   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
01641   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
01642                    SysTick_CTRL_TICKINT_Msk   |
01643                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
01644   return (0UL);                                                     /* Function successful */
01645 }
01646 
01647 #endif
01648 
01649 /*@} end of CMSIS_Core_SysTickFunctions */
01650 
01651 
01652 
01653 /* ##################################### Debug In/Output function ########################################### */
01654 /** \ingroup  CMSIS_Core_FunctionInterface
01655     \defgroup CMSIS_core_DebugFunctions ITM Functions
01656     \brief   Functions that access the ITM debug interface.
01657   @{
01658  */
01659 
01660 extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
01661 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
01662 
01663 
01664 /** \brief  ITM Send Character
01665 
01666     The function transmits a character via the ITM channel 0, and
01667     \li Just returns when no debugger is connected that has booked the output.
01668     \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
01669 
01670     \param [in]     ch  Character to transmit.
01671 
01672     \returns            Character to transmit.
01673  */
01674 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
01675 {
01676   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
01677       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
01678   {
01679     while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
01680     ITM->PORT[0].u8 = (uint8_t)ch;
01681   }
01682   return (ch);
01683 }
01684 
01685 
01686 /** \brief  ITM Receive Character
01687 
01688     The function inputs a character via the external variable \ref ITM_RxBuffer.
01689 
01690     \return             Received character.
01691     \return         -1  No character pending.
01692  */
01693 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
01694   int32_t ch = -1;                           /* no character available */
01695 
01696   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
01697     ch = ITM_RxBuffer;
01698     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
01699   }
01700 
01701   return (ch);
01702 }
01703 
01704 
01705 /** \brief  ITM Check Character
01706 
01707     The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
01708 
01709     \return          0  No character available.
01710     \return          1  Character available.
01711  */
01712 __STATIC_INLINE int32_t ITM_CheckChar (void) {
01713 
01714   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
01715     return (0);                                 /* no character available */
01716   } else {
01717     return (1);                                 /*    character available */
01718   }
01719 }
01720 
01721 /*@} end of CMSIS_core_DebugFunctions */
01722 
01723 
01724 
01725 
01726 #ifdef __cplusplus
01727 }
01728 #endif
01729 
01730 #endif /* __CORE_CM3_H_DEPENDANT */
01731 
01732 #endif /* __CMSIS_GENERIC */