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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dma.c@29:ec2c5a69acd6, 2017-05-24 (annotated)

Committer:
sahilmgandhi
Date:
Wed May 24 01:57:01 2017 +0000
Revision:
29:ec2c5a69acd6
Parent:
18:6a4db94011d3 
Need to change ir2-ir3 to now be ir1 - ir4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32f0xx_hal_dma.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.5.0
sahilmgandhi 18:6a4db94011d3 6 * @date 04-November-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief DMA HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 10 * functionalities of the Direct Memory Access (DMA) peripheral:
sahilmgandhi 18:6a4db94011d3 11 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 12 * + IO operation functions
sahilmgandhi 18:6a4db94011d3 13 * + Peripheral State and errors functions
sahilmgandhi 18:6a4db94011d3 14 @verbatim
sahilmgandhi 18:6a4db94011d3 15 ==============================================================================
sahilmgandhi 18:6a4db94011d3 16 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 17 ==============================================================================
sahilmgandhi 18:6a4db94011d3 18 [..]
sahilmgandhi 18:6a4db94011d3 19 (#) Enable and configure the peripheral to be connected to the DMA Channel
sahilmgandhi 18:6a4db94011d3 20 (except for internal SRAM / FLASH memories: no initialization is
sahilmgandhi 18:6a4db94011d3 21 necessary). Please refer to Reference manual for connection between peripherals
sahilmgandhi 18:6a4db94011d3 22 and DMA requests .
sahilmgandhi 18:6a4db94011d3 23
sahilmgandhi 18:6a4db94011d3 24 (#) For a given Channel, program the required configuration through the following parameters:
sahilmgandhi 18:6a4db94011d3 25 Transfer Direction, Source and Destination data formats,
sahilmgandhi 18:6a4db94011d3 26 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
sahilmgandhi 18:6a4db94011d3 27 using HAL_DMA_Init() function.
sahilmgandhi 18:6a4db94011d3 28
sahilmgandhi 18:6a4db94011d3 29 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
sahilmgandhi 18:6a4db94011d3 30 detection.
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 (#) Use HAL_DMA_Abort() function to abort the current transfer
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
sahilmgandhi 18:6a4db94011d3 35 *** Polling mode IO operation ***
sahilmgandhi 18:6a4db94011d3 36 =================================
sahilmgandhi 18:6a4db94011d3 37 [..]
sahilmgandhi 18:6a4db94011d3 38 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
sahilmgandhi 18:6a4db94011d3 39 address and destination address and the Length of data to be transferred
sahilmgandhi 18:6a4db94011d3 40 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
sahilmgandhi 18:6a4db94011d3 41 case a fixed Timeout can be configured by User depending from his application.
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 *** Interrupt mode IO operation ***
sahilmgandhi 18:6a4db94011d3 44 ===================================
sahilmgandhi 18:6a4db94011d3 45 [..]
sahilmgandhi 18:6a4db94011d3 46 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
sahilmgandhi 18:6a4db94011d3 47 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
sahilmgandhi 18:6a4db94011d3 48 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
sahilmgandhi 18:6a4db94011d3 49 Source address and destination address and the Length of data to be transferred.
sahilmgandhi 18:6a4db94011d3 50 In this case the DMA interrupt is configured
sahilmgandhi 18:6a4db94011d3 51 (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
sahilmgandhi 18:6a4db94011d3 52 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
sahilmgandhi 18:6a4db94011d3 53 add his own function by customization of function pointer XferCpltCallback and
sahilmgandhi 18:6a4db94011d3 54 XferErrorCallback (i.e a member of DMA handle structure).
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 *** DMA HAL driver macros list ***
sahilmgandhi 18:6a4db94011d3 57 =============================================
sahilmgandhi 18:6a4db94011d3 58 [..]
sahilmgandhi 18:6a4db94011d3 59 Below the list of most used macros in DMA HAL driver.
sahilmgandhi 18:6a4db94011d3 60
sahilmgandhi 18:6a4db94011d3 61 [..]
sahilmgandhi 18:6a4db94011d3 62 (@) You can refer to the DMA HAL driver header file for more useful macros
sahilmgandhi 18:6a4db94011d3 63
sahilmgandhi 18:6a4db94011d3 64 @endverbatim
sahilmgandhi 18:6a4db94011d3 65 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 66 * @attention
sahilmgandhi 18:6a4db94011d3 67 *
sahilmgandhi 18:6a4db94011d3 68 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 69 *
sahilmgandhi 18:6a4db94011d3 70 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 71 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 72 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 73 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 74 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 75 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 76 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 77 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 78 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 79 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 80 *
sahilmgandhi 18:6a4db94011d3 81 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 82 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 83 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 84 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 85 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 86 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 87 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 88 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 89 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 90 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 91 *
sahilmgandhi 18:6a4db94011d3 92 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 93 */
sahilmgandhi 18:6a4db94011d3 94
sahilmgandhi 18:6a4db94011d3 95 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 96 #include "stm32f0xx_hal.h"
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 /** @addtogroup STM32F0xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 99 * @{
sahilmgandhi 18:6a4db94011d3 100 */
sahilmgandhi 18:6a4db94011d3 101
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 /** @defgroup DMA DMA
sahilmgandhi 18:6a4db94011d3 104 * @brief DMA HAL module driver
sahilmgandhi 18:6a4db94011d3 105 * @{
sahilmgandhi 18:6a4db94011d3 106 */
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 #ifdef HAL_DMA_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 111 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 112 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 113 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 114 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 115 /** @defgroup DMA_Private_Functions DMA Private Functions
sahilmgandhi 18:6a4db94011d3 116 * @{
sahilmgandhi 18:6a4db94011d3 117 */
sahilmgandhi 18:6a4db94011d3 118 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
sahilmgandhi 18:6a4db94011d3 119 static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 120 /**
sahilmgandhi 18:6a4db94011d3 121 * @}
sahilmgandhi 18:6a4db94011d3 122 */
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 /* Exported functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 125
sahilmgandhi 18:6a4db94011d3 126 /** @defgroup DMA_Exported_Functions DMA Exported Functions
sahilmgandhi 18:6a4db94011d3 127 * @{
sahilmgandhi 18:6a4db94011d3 128 */
sahilmgandhi 18:6a4db94011d3 129
sahilmgandhi 18:6a4db94011d3 130 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 131 * @brief Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 132 *
sahilmgandhi 18:6a4db94011d3 133 @verbatim
sahilmgandhi 18:6a4db94011d3 134 ===============================================================================
sahilmgandhi 18:6a4db94011d3 135 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 136 ===============================================================================
sahilmgandhi 18:6a4db94011d3 137 [..]
sahilmgandhi 18:6a4db94011d3 138 This section provides functions allowing to initialize the DMA Channel source
sahilmgandhi 18:6a4db94011d3 139 and destination addresses, incrementation and data sizes, transfer direction,
sahilmgandhi 18:6a4db94011d3 140 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
sahilmgandhi 18:6a4db94011d3 141 [..]
sahilmgandhi 18:6a4db94011d3 142 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
sahilmgandhi 18:6a4db94011d3 143 reference manual.
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 @endverbatim
sahilmgandhi 18:6a4db94011d3 146 * @{
sahilmgandhi 18:6a4db94011d3 147 */
sahilmgandhi 18:6a4db94011d3 148
sahilmgandhi 18:6a4db94011d3 149 /**
sahilmgandhi 18:6a4db94011d3 150 * @brief Initialize the DMA according to the specified
sahilmgandhi 18:6a4db94011d3 151 * parameters in the DMA_InitTypeDef and initialize the associated handle.
sahilmgandhi 18:6a4db94011d3 152 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 153 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 154 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 155 */
sahilmgandhi 18:6a4db94011d3 156 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 157 {
sahilmgandhi 18:6a4db94011d3 158 uint32_t tmp = 0U;
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /* Check the DMA handle allocation */
sahilmgandhi 18:6a4db94011d3 161 if(NULL == hdma)
sahilmgandhi 18:6a4db94011d3 162 {
sahilmgandhi 18:6a4db94011d3 163 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 167 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
sahilmgandhi 18:6a4db94011d3 168 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
sahilmgandhi 18:6a4db94011d3 169 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
sahilmgandhi 18:6a4db94011d3 170 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
sahilmgandhi 18:6a4db94011d3 171 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
sahilmgandhi 18:6a4db94011d3 172 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
sahilmgandhi 18:6a4db94011d3 173 assert_param(IS_DMA_MODE(hdma->Init.Mode));
sahilmgandhi 18:6a4db94011d3 174 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 177 hdma->State = HAL_DMA_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /* Get the CR register value */
sahilmgandhi 18:6a4db94011d3 180 tmp = hdma->Instance->CCR;
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
sahilmgandhi 18:6a4db94011d3 183 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
sahilmgandhi 18:6a4db94011d3 184 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
sahilmgandhi 18:6a4db94011d3 185 DMA_CCR_DIR));
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 /* Prepare the DMA Channel configuration */
sahilmgandhi 18:6a4db94011d3 188 tmp |= hdma->Init.Direction |
sahilmgandhi 18:6a4db94011d3 189 hdma->Init.PeriphInc | hdma->Init.MemInc |
sahilmgandhi 18:6a4db94011d3 190 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
sahilmgandhi 18:6a4db94011d3 191 hdma->Init.Mode | hdma->Init.Priority;
sahilmgandhi 18:6a4db94011d3 192
sahilmgandhi 18:6a4db94011d3 193 /* Write to DMA Channel CR register */
sahilmgandhi 18:6a4db94011d3 194 hdma->Instance->CCR = tmp;
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 /* Initialize DmaBaseAddress and ChannelIndex parameters used
sahilmgandhi 18:6a4db94011d3 197 by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
sahilmgandhi 18:6a4db94011d3 198 DMA_CalcBaseAndBitshift(hdma);
sahilmgandhi 18:6a4db94011d3 199
sahilmgandhi 18:6a4db94011d3 200 /* Clean callbacks */
sahilmgandhi 18:6a4db94011d3 201 hdma->XferCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 202 hdma->XferHalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 203 hdma->XferErrorCallback = NULL;
sahilmgandhi 18:6a4db94011d3 204 hdma->XferAbortCallback = NULL;
sahilmgandhi 18:6a4db94011d3 205
sahilmgandhi 18:6a4db94011d3 206 /* Initialise the error code */
sahilmgandhi 18:6a4db94011d3 207 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 /* Initialize the DMA state*/
sahilmgandhi 18:6a4db94011d3 210 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 211
sahilmgandhi 18:6a4db94011d3 212 /* Allocate lock resource and initialize it */
sahilmgandhi 18:6a4db94011d3 213 hdma->Lock = HAL_UNLOCKED;
sahilmgandhi 18:6a4db94011d3 214
sahilmgandhi 18:6a4db94011d3 215 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 216 }
sahilmgandhi 18:6a4db94011d3 217
sahilmgandhi 18:6a4db94011d3 218 /**
sahilmgandhi 18:6a4db94011d3 219 * @brief DeInitialize the DMA peripheral
sahilmgandhi 18:6a4db94011d3 220 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 221 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 222 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 223 */
sahilmgandhi 18:6a4db94011d3 224 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 225 {
sahilmgandhi 18:6a4db94011d3 226 /* Check the DMA handle allocation */
sahilmgandhi 18:6a4db94011d3 227 if(NULL == hdma)
sahilmgandhi 18:6a4db94011d3 228 {
sahilmgandhi 18:6a4db94011d3 229 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 230 }
sahilmgandhi 18:6a4db94011d3 231
sahilmgandhi 18:6a4db94011d3 232 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 233 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
sahilmgandhi 18:6a4db94011d3 234
sahilmgandhi 18:6a4db94011d3 235 /* Disable the selected DMA Channelx */
sahilmgandhi 18:6a4db94011d3 236 hdma->Instance->CCR &= ~DMA_CCR_EN;
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /* Reset DMA Channel control register */
sahilmgandhi 18:6a4db94011d3 239 hdma->Instance->CCR = 0U;
sahilmgandhi 18:6a4db94011d3 240
sahilmgandhi 18:6a4db94011d3 241 /* Reset DMA Channel Number of Data to Transfer register */
sahilmgandhi 18:6a4db94011d3 242 hdma->Instance->CNDTR = 0U;
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 /* Reset DMA Channel peripheral address register */
sahilmgandhi 18:6a4db94011d3 245 hdma->Instance->CPAR = 0U;
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 /* Reset DMA Channel memory address register */
sahilmgandhi 18:6a4db94011d3 248 hdma->Instance->CMAR = 0U;
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 /* Get DMA Base Address */
sahilmgandhi 18:6a4db94011d3 251 DMA_CalcBaseAndBitshift(hdma);
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 /* Clear all flags */
sahilmgandhi 18:6a4db94011d3 254 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 /* Initialize the error code */
sahilmgandhi 18:6a4db94011d3 257 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 258
sahilmgandhi 18:6a4db94011d3 259 /* Initialize the DMA state */
sahilmgandhi 18:6a4db94011d3 260 hdma->State = HAL_DMA_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 263 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 264
sahilmgandhi 18:6a4db94011d3 265 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 266 }
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /**
sahilmgandhi 18:6a4db94011d3 269 * @}
sahilmgandhi 18:6a4db94011d3 270 */
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
sahilmgandhi 18:6a4db94011d3 273 * @brief I/O operation functions
sahilmgandhi 18:6a4db94011d3 274 *
sahilmgandhi 18:6a4db94011d3 275 @verbatim
sahilmgandhi 18:6a4db94011d3 276 ===============================================================================
sahilmgandhi 18:6a4db94011d3 277 ##### IO operation functions #####
sahilmgandhi 18:6a4db94011d3 278 ===============================================================================
sahilmgandhi 18:6a4db94011d3 279 [..] This section provides functions allowing to:
sahilmgandhi 18:6a4db94011d3 280 (+) Configure the source, destination address and data length and Start DMA transfer
sahilmgandhi 18:6a4db94011d3 281 (+) Configure the source, destination address and data length and
sahilmgandhi 18:6a4db94011d3 282 Start DMA transfer with interrupt
sahilmgandhi 18:6a4db94011d3 283 (+) Abort DMA transfer
sahilmgandhi 18:6a4db94011d3 284 (+) Poll for transfer complete
sahilmgandhi 18:6a4db94011d3 285 (+) Handle DMA interrupt request
sahilmgandhi 18:6a4db94011d3 286
sahilmgandhi 18:6a4db94011d3 287 @endverbatim
sahilmgandhi 18:6a4db94011d3 288 * @{
sahilmgandhi 18:6a4db94011d3 289 */
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /**
sahilmgandhi 18:6a4db94011d3 292 * @brief Start the DMA Transfer.
sahilmgandhi 18:6a4db94011d3 293 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 294 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 295 * @param SrcAddress: The source memory Buffer address
sahilmgandhi 18:6a4db94011d3 296 * @param DstAddress: The destination memory Buffer address
sahilmgandhi 18:6a4db94011d3 297 * @param DataLength: The length of data to be transferred from source to destination
sahilmgandhi 18:6a4db94011d3 298 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 299 */
sahilmgandhi 18:6a4db94011d3 300 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
sahilmgandhi 18:6a4db94011d3 301 {
sahilmgandhi 18:6a4db94011d3 302 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 305 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Process locked */
sahilmgandhi 18:6a4db94011d3 308 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 311 {
sahilmgandhi 18:6a4db94011d3 312 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 313 hdma->State = HAL_DMA_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 316
sahilmgandhi 18:6a4db94011d3 317 /* Disable the peripheral */
sahilmgandhi 18:6a4db94011d3 318 hdma->Instance->CCR &= ~DMA_CCR_EN;
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 /* Configure the source, destination address and the data length */
sahilmgandhi 18:6a4db94011d3 321 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 /* Enable the Peripheral */
sahilmgandhi 18:6a4db94011d3 324 hdma->Instance->CCR |= DMA_CCR_EN;
sahilmgandhi 18:6a4db94011d3 325 }
sahilmgandhi 18:6a4db94011d3 326 else
sahilmgandhi 18:6a4db94011d3 327 {
sahilmgandhi 18:6a4db94011d3 328 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 329 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 /* Remain BUSY */
sahilmgandhi 18:6a4db94011d3 332 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 333 }
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 return status;
sahilmgandhi 18:6a4db94011d3 336 }
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 /**
sahilmgandhi 18:6a4db94011d3 339 * @brief Start the DMA Transfer with interrupt enabled.
sahilmgandhi 18:6a4db94011d3 340 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 341 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 342 * @param SrcAddress: The source memory Buffer address
sahilmgandhi 18:6a4db94011d3 343 * @param DstAddress: The destination memory Buffer address
sahilmgandhi 18:6a4db94011d3 344 * @param DataLength: The length of data to be transferred from source to destination
sahilmgandhi 18:6a4db94011d3 345 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 346 */
sahilmgandhi 18:6a4db94011d3 347 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
sahilmgandhi 18:6a4db94011d3 348 {
sahilmgandhi 18:6a4db94011d3 349 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 352 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 /* Process locked */
sahilmgandhi 18:6a4db94011d3 355 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 356
sahilmgandhi 18:6a4db94011d3 357 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 358 {
sahilmgandhi 18:6a4db94011d3 359 /* Change DMA peripheral state */
sahilmgandhi 18:6a4db94011d3 360 hdma->State = HAL_DMA_STATE_BUSY;
sahilmgandhi 18:6a4db94011d3 361
sahilmgandhi 18:6a4db94011d3 362 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 /* Disable the peripheral */
sahilmgandhi 18:6a4db94011d3 365 hdma->Instance->CCR &= ~DMA_CCR_EN;
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 /* Configure the source, destination address and the data length */
sahilmgandhi 18:6a4db94011d3 368 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 /* Enable the transfer complete, & transfer error interrupts */
sahilmgandhi 18:6a4db94011d3 371 /* Half transfer interrupt is optional: enable it only if associated callback is available */
sahilmgandhi 18:6a4db94011d3 372 if(NULL != hdma->XferHalfCpltCallback )
sahilmgandhi 18:6a4db94011d3 373 {
sahilmgandhi 18:6a4db94011d3 374 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
sahilmgandhi 18:6a4db94011d3 375 }
sahilmgandhi 18:6a4db94011d3 376 else
sahilmgandhi 18:6a4db94011d3 377 {
sahilmgandhi 18:6a4db94011d3 378 hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE);
sahilmgandhi 18:6a4db94011d3 379 hdma->Instance->CCR &= ~DMA_IT_HT;
sahilmgandhi 18:6a4db94011d3 380 }
sahilmgandhi 18:6a4db94011d3 381
sahilmgandhi 18:6a4db94011d3 382 /* Enable the Peripheral */
sahilmgandhi 18:6a4db94011d3 383 hdma->Instance->CCR |= DMA_CCR_EN;
sahilmgandhi 18:6a4db94011d3 384 }
sahilmgandhi 18:6a4db94011d3 385 else
sahilmgandhi 18:6a4db94011d3 386 {
sahilmgandhi 18:6a4db94011d3 387 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 388 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 /* Remain BUSY */
sahilmgandhi 18:6a4db94011d3 391 status = HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 392 }
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 return status;
sahilmgandhi 18:6a4db94011d3 395 }
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 /**
sahilmgandhi 18:6a4db94011d3 398 * @brief Abort the DMA Transfer.
sahilmgandhi 18:6a4db94011d3 399 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 400 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 401 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 402 */
sahilmgandhi 18:6a4db94011d3 403 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 404 {
sahilmgandhi 18:6a4db94011d3 405 /* Disable DMA IT */
sahilmgandhi 18:6a4db94011d3 406 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
sahilmgandhi 18:6a4db94011d3 407
sahilmgandhi 18:6a4db94011d3 408 /* Disable the channel */
sahilmgandhi 18:6a4db94011d3 409 hdma->Instance->CCR &= ~DMA_CCR_EN;
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 /* Clear all flags */
sahilmgandhi 18:6a4db94011d3 412 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
sahilmgandhi 18:6a4db94011d3 413
sahilmgandhi 18:6a4db94011d3 414 /* Change the DMA state*/
sahilmgandhi 18:6a4db94011d3 415 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 418 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 421 }
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 /**
sahilmgandhi 18:6a4db94011d3 424 * @brief Abort the DMA Transfer in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 425 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 426 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 427 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 428 */
sahilmgandhi 18:6a4db94011d3 429 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 430 {
sahilmgandhi 18:6a4db94011d3 431 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 if(HAL_DMA_STATE_BUSY != hdma->State)
sahilmgandhi 18:6a4db94011d3 434 {
sahilmgandhi 18:6a4db94011d3 435 /* no transfer ongoing */
sahilmgandhi 18:6a4db94011d3 436 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 439 }
sahilmgandhi 18:6a4db94011d3 440 else
sahilmgandhi 18:6a4db94011d3 441 {
sahilmgandhi 18:6a4db94011d3 442
sahilmgandhi 18:6a4db94011d3 443 /* Disable DMA IT */
sahilmgandhi 18:6a4db94011d3 444 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 /* Disable the channel */
sahilmgandhi 18:6a4db94011d3 447 hdma->Instance->CCR &= ~DMA_CCR_EN;
sahilmgandhi 18:6a4db94011d3 448
sahilmgandhi 18:6a4db94011d3 449 /* Clear all flags */
sahilmgandhi 18:6a4db94011d3 450 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 451
sahilmgandhi 18:6a4db94011d3 452 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 453 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 454
sahilmgandhi 18:6a4db94011d3 455 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 456 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 /* Call User Abort callback */
sahilmgandhi 18:6a4db94011d3 459 if(hdma->XferAbortCallback != NULL)
sahilmgandhi 18:6a4db94011d3 460 {
sahilmgandhi 18:6a4db94011d3 461 hdma->XferAbortCallback(hdma);
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464 return status;
sahilmgandhi 18:6a4db94011d3 465 }
sahilmgandhi 18:6a4db94011d3 466
sahilmgandhi 18:6a4db94011d3 467 /**
sahilmgandhi 18:6a4db94011d3 468 * @brief Polling for transfer complete.
sahilmgandhi 18:6a4db94011d3 469 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 470 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 471 * @param CompleteLevel: Specifies the DMA level complete.
sahilmgandhi 18:6a4db94011d3 472 * @param Timeout: Timeout duration.
sahilmgandhi 18:6a4db94011d3 473 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 474 */
sahilmgandhi 18:6a4db94011d3 475 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 476 {
sahilmgandhi 18:6a4db94011d3 477 uint32_t temp;
sahilmgandhi 18:6a4db94011d3 478 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 if(HAL_DMA_STATE_BUSY != hdma->State)
sahilmgandhi 18:6a4db94011d3 481 {
sahilmgandhi 18:6a4db94011d3 482 /* no transfer ongoing */
sahilmgandhi 18:6a4db94011d3 483 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
sahilmgandhi 18:6a4db94011d3 484 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 485 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 486 }
sahilmgandhi 18:6a4db94011d3 487
sahilmgandhi 18:6a4db94011d3 488 /* Polling mode not supported in circular mode */
sahilmgandhi 18:6a4db94011d3 489 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
sahilmgandhi 18:6a4db94011d3 490 {
sahilmgandhi 18:6a4db94011d3 491 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
sahilmgandhi 18:6a4db94011d3 492 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 493 }
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 /* Get the level transfer complete flag */
sahilmgandhi 18:6a4db94011d3 496 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
sahilmgandhi 18:6a4db94011d3 497 {
sahilmgandhi 18:6a4db94011d3 498 /* Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 499 temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 500 }
sahilmgandhi 18:6a4db94011d3 501 else
sahilmgandhi 18:6a4db94011d3 502 {
sahilmgandhi 18:6a4db94011d3 503 /* Half Transfer Complete flag */
sahilmgandhi 18:6a4db94011d3 504 temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 505 }
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 /* Get tick */
sahilmgandhi 18:6a4db94011d3 508 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 509
sahilmgandhi 18:6a4db94011d3 510 while(RESET == (hdma->DmaBaseAddress->ISR & temp))
sahilmgandhi 18:6a4db94011d3 511 {
sahilmgandhi 18:6a4db94011d3 512 if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))
sahilmgandhi 18:6a4db94011d3 513 {
sahilmgandhi 18:6a4db94011d3 514 /* When a DMA transfer error occurs */
sahilmgandhi 18:6a4db94011d3 515 /* A hardware clear of its EN bits is performed */
sahilmgandhi 18:6a4db94011d3 516 /* Clear all flags */
sahilmgandhi 18:6a4db94011d3 517 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 518
sahilmgandhi 18:6a4db94011d3 519 /* Update error code */
sahilmgandhi 18:6a4db94011d3 520 hdma->ErrorCode = HAL_DMA_ERROR_TE;
sahilmgandhi 18:6a4db94011d3 521
sahilmgandhi 18:6a4db94011d3 522 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 523 hdma->State= HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 524
sahilmgandhi 18:6a4db94011d3 525 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 526 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 527
sahilmgandhi 18:6a4db94011d3 528 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 529 }
sahilmgandhi 18:6a4db94011d3 530 /* Check for the Timeout */
sahilmgandhi 18:6a4db94011d3 531 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 532 {
sahilmgandhi 18:6a4db94011d3 533 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
sahilmgandhi 18:6a4db94011d3 534 {
sahilmgandhi 18:6a4db94011d3 535 /* Update error code */
sahilmgandhi 18:6a4db94011d3 536 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 537
sahilmgandhi 18:6a4db94011d3 538 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 539 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 540
sahilmgandhi 18:6a4db94011d3 541 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 542 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 545 }
sahilmgandhi 18:6a4db94011d3 546 }
sahilmgandhi 18:6a4db94011d3 547 }
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
sahilmgandhi 18:6a4db94011d3 550 {
sahilmgandhi 18:6a4db94011d3 551 /* Clear the transfer complete flag */
sahilmgandhi 18:6a4db94011d3 552 hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 553
sahilmgandhi 18:6a4db94011d3 554 /* The selected Channelx EN bit is cleared (DMA is disabled and
sahilmgandhi 18:6a4db94011d3 555 all transfers are complete) */
sahilmgandhi 18:6a4db94011d3 556 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 557 }
sahilmgandhi 18:6a4db94011d3 558 else
sahilmgandhi 18:6a4db94011d3 559 {
sahilmgandhi 18:6a4db94011d3 560 /* Clear the half transfer complete flag */
sahilmgandhi 18:6a4db94011d3 561 hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 562 }
sahilmgandhi 18:6a4db94011d3 563
sahilmgandhi 18:6a4db94011d3 564 /* Process unlocked */
sahilmgandhi 18:6a4db94011d3 565 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 566
sahilmgandhi 18:6a4db94011d3 567 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 568 }
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 /**
sahilmgandhi 18:6a4db94011d3 571 * @brief Handle DMA interrupt request.
sahilmgandhi 18:6a4db94011d3 572 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 573 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 574 * @retval None
sahilmgandhi 18:6a4db94011d3 575 */
sahilmgandhi 18:6a4db94011d3 576 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 577 {
sahilmgandhi 18:6a4db94011d3 578 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
sahilmgandhi 18:6a4db94011d3 579 uint32_t source_it = hdma->Instance->CCR;
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 /* Half Transfer Complete Interrupt management ******************************/
sahilmgandhi 18:6a4db94011d3 582 if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
sahilmgandhi 18:6a4db94011d3 583 {
sahilmgandhi 18:6a4db94011d3 584 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
sahilmgandhi 18:6a4db94011d3 585 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
sahilmgandhi 18:6a4db94011d3 586 {
sahilmgandhi 18:6a4db94011d3 587 /* Disable the half transfer interrupt */
sahilmgandhi 18:6a4db94011d3 588 hdma->Instance->CCR &= ~DMA_IT_HT;
sahilmgandhi 18:6a4db94011d3 589 }
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 /* Clear the half transfer complete flag */
sahilmgandhi 18:6a4db94011d3 592 hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 /* DMA peripheral state is not updated in Half Transfer */
sahilmgandhi 18:6a4db94011d3 595 /* State is updated only in Transfer Complete case */
sahilmgandhi 18:6a4db94011d3 596
sahilmgandhi 18:6a4db94011d3 597 if(hdma->XferHalfCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 598 {
sahilmgandhi 18:6a4db94011d3 599 /* Half transfer callback */
sahilmgandhi 18:6a4db94011d3 600 hdma->XferHalfCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 601 }
sahilmgandhi 18:6a4db94011d3 602 }
sahilmgandhi 18:6a4db94011d3 603
sahilmgandhi 18:6a4db94011d3 604 /* Transfer Complete Interrupt management ***********************************/
sahilmgandhi 18:6a4db94011d3 605 else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
sahilmgandhi 18:6a4db94011d3 606 {
sahilmgandhi 18:6a4db94011d3 607 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
sahilmgandhi 18:6a4db94011d3 608 {
sahilmgandhi 18:6a4db94011d3 609 /* Disable the transfer complete & transfer error interrupts */
sahilmgandhi 18:6a4db94011d3 610 /* if the DMA mode is not CIRCULAR */
sahilmgandhi 18:6a4db94011d3 611 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE);
sahilmgandhi 18:6a4db94011d3 612
sahilmgandhi 18:6a4db94011d3 613 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 614 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 615 }
sahilmgandhi 18:6a4db94011d3 616
sahilmgandhi 18:6a4db94011d3 617 /* Clear the transfer complete flag */
sahilmgandhi 18:6a4db94011d3 618 hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 619
sahilmgandhi 18:6a4db94011d3 620 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 621 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 622
sahilmgandhi 18:6a4db94011d3 623 if(hdma->XferCpltCallback != NULL)
sahilmgandhi 18:6a4db94011d3 624 {
sahilmgandhi 18:6a4db94011d3 625 /* Transfer complete callback */
sahilmgandhi 18:6a4db94011d3 626 hdma->XferCpltCallback(hdma);
sahilmgandhi 18:6a4db94011d3 627 }
sahilmgandhi 18:6a4db94011d3 628 }
sahilmgandhi 18:6a4db94011d3 629
sahilmgandhi 18:6a4db94011d3 630 /* Transfer Error Interrupt management ***************************************/
sahilmgandhi 18:6a4db94011d3 631 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
sahilmgandhi 18:6a4db94011d3 632 {
sahilmgandhi 18:6a4db94011d3 633 /* When a DMA transfer error occurs */
sahilmgandhi 18:6a4db94011d3 634 /* A hardware clear of its EN bits is performed */
sahilmgandhi 18:6a4db94011d3 635 /* Then, disable all DMA interrupts */
sahilmgandhi 18:6a4db94011d3 636 hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
sahilmgandhi 18:6a4db94011d3 637
sahilmgandhi 18:6a4db94011d3 638 /* Clear all flags */
sahilmgandhi 18:6a4db94011d3 639 hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
sahilmgandhi 18:6a4db94011d3 640
sahilmgandhi 18:6a4db94011d3 641 /* Update error code */
sahilmgandhi 18:6a4db94011d3 642 hdma->ErrorCode = HAL_DMA_ERROR_TE;
sahilmgandhi 18:6a4db94011d3 643
sahilmgandhi 18:6a4db94011d3 644 /* Change the DMA state */
sahilmgandhi 18:6a4db94011d3 645 hdma->State = HAL_DMA_STATE_READY;
sahilmgandhi 18:6a4db94011d3 646
sahilmgandhi 18:6a4db94011d3 647 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 648 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 649
sahilmgandhi 18:6a4db94011d3 650 if(hdma->XferErrorCallback != NULL)
sahilmgandhi 18:6a4db94011d3 651 {
sahilmgandhi 18:6a4db94011d3 652 /* Transfer error callback */
sahilmgandhi 18:6a4db94011d3 653 hdma->XferErrorCallback(hdma);
sahilmgandhi 18:6a4db94011d3 654 }
sahilmgandhi 18:6a4db94011d3 655 }
sahilmgandhi 18:6a4db94011d3 656 }
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 /**
sahilmgandhi 18:6a4db94011d3 659 * @brief Register callbacks
sahilmgandhi 18:6a4db94011d3 660 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 661 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 662 * @param CallbackID: User Callback identifer
sahilmgandhi 18:6a4db94011d3 663 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
sahilmgandhi 18:6a4db94011d3 664 * @param pCallback: pointer to private callback function which has pointer to
sahilmgandhi 18:6a4db94011d3 665 * a DMA_HandleTypeDef structure as parameter.
sahilmgandhi 18:6a4db94011d3 666 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 667 */
sahilmgandhi 18:6a4db94011d3 668 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
sahilmgandhi 18:6a4db94011d3 669 {
sahilmgandhi 18:6a4db94011d3 670 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 671
sahilmgandhi 18:6a4db94011d3 672 /* Process locked */
sahilmgandhi 18:6a4db94011d3 673 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 674
sahilmgandhi 18:6a4db94011d3 675 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 676 {
sahilmgandhi 18:6a4db94011d3 677 switch (CallbackID)
sahilmgandhi 18:6a4db94011d3 678 {
sahilmgandhi 18:6a4db94011d3 679 case HAL_DMA_XFER_CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 680 hdma->XferCpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 681 break;
sahilmgandhi 18:6a4db94011d3 682
sahilmgandhi 18:6a4db94011d3 683 case HAL_DMA_XFER_HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 684 hdma->XferHalfCpltCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 685 break;
sahilmgandhi 18:6a4db94011d3 686
sahilmgandhi 18:6a4db94011d3 687 case HAL_DMA_XFER_ERROR_CB_ID:
sahilmgandhi 18:6a4db94011d3 688 hdma->XferErrorCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 689 break;
sahilmgandhi 18:6a4db94011d3 690
sahilmgandhi 18:6a4db94011d3 691 case HAL_DMA_XFER_ABORT_CB_ID:
sahilmgandhi 18:6a4db94011d3 692 hdma->XferAbortCallback = pCallback;
sahilmgandhi 18:6a4db94011d3 693 break;
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 default:
sahilmgandhi 18:6a4db94011d3 696 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 697 break;
sahilmgandhi 18:6a4db94011d3 698 }
sahilmgandhi 18:6a4db94011d3 699 }
sahilmgandhi 18:6a4db94011d3 700 else
sahilmgandhi 18:6a4db94011d3 701 {
sahilmgandhi 18:6a4db94011d3 702 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 703 }
sahilmgandhi 18:6a4db94011d3 704
sahilmgandhi 18:6a4db94011d3 705 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 706 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 707
sahilmgandhi 18:6a4db94011d3 708 return status;
sahilmgandhi 18:6a4db94011d3 709 }
sahilmgandhi 18:6a4db94011d3 710
sahilmgandhi 18:6a4db94011d3 711 /**
sahilmgandhi 18:6a4db94011d3 712 * @brief UnRegister callbacks
sahilmgandhi 18:6a4db94011d3 713 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 714 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 715 * @param CallbackID: User Callback identifer
sahilmgandhi 18:6a4db94011d3 716 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
sahilmgandhi 18:6a4db94011d3 717 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 718 */
sahilmgandhi 18:6a4db94011d3 719 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
sahilmgandhi 18:6a4db94011d3 720 {
sahilmgandhi 18:6a4db94011d3 721 HAL_StatusTypeDef status = HAL_OK;
sahilmgandhi 18:6a4db94011d3 722
sahilmgandhi 18:6a4db94011d3 723 /* Process locked */
sahilmgandhi 18:6a4db94011d3 724 __HAL_LOCK(hdma);
sahilmgandhi 18:6a4db94011d3 725
sahilmgandhi 18:6a4db94011d3 726 if(HAL_DMA_STATE_READY == hdma->State)
sahilmgandhi 18:6a4db94011d3 727 {
sahilmgandhi 18:6a4db94011d3 728 switch (CallbackID)
sahilmgandhi 18:6a4db94011d3 729 {
sahilmgandhi 18:6a4db94011d3 730 case HAL_DMA_XFER_CPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 731 hdma->XferCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 732 break;
sahilmgandhi 18:6a4db94011d3 733
sahilmgandhi 18:6a4db94011d3 734 case HAL_DMA_XFER_HALFCPLT_CB_ID:
sahilmgandhi 18:6a4db94011d3 735 hdma->XferHalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 736 break;
sahilmgandhi 18:6a4db94011d3 737
sahilmgandhi 18:6a4db94011d3 738 case HAL_DMA_XFER_ERROR_CB_ID:
sahilmgandhi 18:6a4db94011d3 739 hdma->XferErrorCallback = NULL;
sahilmgandhi 18:6a4db94011d3 740 break;
sahilmgandhi 18:6a4db94011d3 741
sahilmgandhi 18:6a4db94011d3 742 case HAL_DMA_XFER_ABORT_CB_ID:
sahilmgandhi 18:6a4db94011d3 743 hdma->XferAbortCallback = NULL;
sahilmgandhi 18:6a4db94011d3 744 break;
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 case HAL_DMA_XFER_ALL_CB_ID:
sahilmgandhi 18:6a4db94011d3 747 hdma->XferCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 748 hdma->XferHalfCpltCallback = NULL;
sahilmgandhi 18:6a4db94011d3 749 hdma->XferErrorCallback = NULL;
sahilmgandhi 18:6a4db94011d3 750 hdma->XferAbortCallback = NULL;
sahilmgandhi 18:6a4db94011d3 751 break;
sahilmgandhi 18:6a4db94011d3 752
sahilmgandhi 18:6a4db94011d3 753 default:
sahilmgandhi 18:6a4db94011d3 754 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 755 break;
sahilmgandhi 18:6a4db94011d3 756 }
sahilmgandhi 18:6a4db94011d3 757 }
sahilmgandhi 18:6a4db94011d3 758 else
sahilmgandhi 18:6a4db94011d3 759 {
sahilmgandhi 18:6a4db94011d3 760 status = HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 761 }
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 764 __HAL_UNLOCK(hdma);
sahilmgandhi 18:6a4db94011d3 765
sahilmgandhi 18:6a4db94011d3 766 return status;
sahilmgandhi 18:6a4db94011d3 767 }
sahilmgandhi 18:6a4db94011d3 768
sahilmgandhi 18:6a4db94011d3 769 /**
sahilmgandhi 18:6a4db94011d3 770 * @}
sahilmgandhi 18:6a4db94011d3 771 */
sahilmgandhi 18:6a4db94011d3 772
sahilmgandhi 18:6a4db94011d3 773 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
sahilmgandhi 18:6a4db94011d3 774 * @brief Peripheral State functions
sahilmgandhi 18:6a4db94011d3 775 *
sahilmgandhi 18:6a4db94011d3 776 @verbatim
sahilmgandhi 18:6a4db94011d3 777 ===============================================================================
sahilmgandhi 18:6a4db94011d3 778 ##### State and Errors functions #####
sahilmgandhi 18:6a4db94011d3 779 ===============================================================================
sahilmgandhi 18:6a4db94011d3 780 [..]
sahilmgandhi 18:6a4db94011d3 781 This subsection provides functions allowing to
sahilmgandhi 18:6a4db94011d3 782 (+) Check the DMA state
sahilmgandhi 18:6a4db94011d3 783 (+) Get error code
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 @endverbatim
sahilmgandhi 18:6a4db94011d3 786 * @{
sahilmgandhi 18:6a4db94011d3 787 */
sahilmgandhi 18:6a4db94011d3 788
sahilmgandhi 18:6a4db94011d3 789 /**
sahilmgandhi 18:6a4db94011d3 790 * @brief Returns the DMA state.
sahilmgandhi 18:6a4db94011d3 791 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 792 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 793 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 794 */
sahilmgandhi 18:6a4db94011d3 795 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 796 {
sahilmgandhi 18:6a4db94011d3 797 return hdma->State;
sahilmgandhi 18:6a4db94011d3 798 }
sahilmgandhi 18:6a4db94011d3 799
sahilmgandhi 18:6a4db94011d3 800 /**
sahilmgandhi 18:6a4db94011d3 801 * @brief Return the DMA error code
sahilmgandhi 18:6a4db94011d3 802 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 803 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 804 * @retval DMA Error Code
sahilmgandhi 18:6a4db94011d3 805 */
sahilmgandhi 18:6a4db94011d3 806 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 807 {
sahilmgandhi 18:6a4db94011d3 808 return hdma->ErrorCode;
sahilmgandhi 18:6a4db94011d3 809 }
sahilmgandhi 18:6a4db94011d3 810
sahilmgandhi 18:6a4db94011d3 811 /**
sahilmgandhi 18:6a4db94011d3 812 * @}
sahilmgandhi 18:6a4db94011d3 813 */
sahilmgandhi 18:6a4db94011d3 814
sahilmgandhi 18:6a4db94011d3 815 /**
sahilmgandhi 18:6a4db94011d3 816 * @}
sahilmgandhi 18:6a4db94011d3 817 */
sahilmgandhi 18:6a4db94011d3 818
sahilmgandhi 18:6a4db94011d3 819 /** @addtogroup DMA_Private_Functions
sahilmgandhi 18:6a4db94011d3 820 * @{
sahilmgandhi 18:6a4db94011d3 821 */
sahilmgandhi 18:6a4db94011d3 822
sahilmgandhi 18:6a4db94011d3 823 /**
sahilmgandhi 18:6a4db94011d3 824 * @brief Set the DMA Transfer parameters.
sahilmgandhi 18:6a4db94011d3 825 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 826 * the configuration information for the specified DMA Channel.
sahilmgandhi 18:6a4db94011d3 827 * @param SrcAddress: The source memory Buffer address
sahilmgandhi 18:6a4db94011d3 828 * @param DstAddress: The destination memory Buffer address
sahilmgandhi 18:6a4db94011d3 829 * @param DataLength: The length of data to be transferred from source to destination
sahilmgandhi 18:6a4db94011d3 830 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 831 */
sahilmgandhi 18:6a4db94011d3 832 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
sahilmgandhi 18:6a4db94011d3 833 {
sahilmgandhi 18:6a4db94011d3 834 /* Clear all flags */
sahilmgandhi 18:6a4db94011d3 835 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
sahilmgandhi 18:6a4db94011d3 836
sahilmgandhi 18:6a4db94011d3 837 /* Configure DMA Channel data length */
sahilmgandhi 18:6a4db94011d3 838 hdma->Instance->CNDTR = DataLength;
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 /* Peripheral to Memory */
sahilmgandhi 18:6a4db94011d3 841 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
sahilmgandhi 18:6a4db94011d3 842 {
sahilmgandhi 18:6a4db94011d3 843 /* Configure DMA Channel destination address */
sahilmgandhi 18:6a4db94011d3 844 hdma->Instance->CPAR = DstAddress;
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 /* Configure DMA Channel source address */
sahilmgandhi 18:6a4db94011d3 847 hdma->Instance->CMAR = SrcAddress;
sahilmgandhi 18:6a4db94011d3 848 }
sahilmgandhi 18:6a4db94011d3 849 /* Memory to Peripheral */
sahilmgandhi 18:6a4db94011d3 850 else
sahilmgandhi 18:6a4db94011d3 851 {
sahilmgandhi 18:6a4db94011d3 852 /* Configure DMA Channel source address */
sahilmgandhi 18:6a4db94011d3 853 hdma->Instance->CPAR = SrcAddress;
sahilmgandhi 18:6a4db94011d3 854
sahilmgandhi 18:6a4db94011d3 855 /* Configure DMA Channel destination address */
sahilmgandhi 18:6a4db94011d3 856 hdma->Instance->CMAR = DstAddress;
sahilmgandhi 18:6a4db94011d3 857 }
sahilmgandhi 18:6a4db94011d3 858 }
sahilmgandhi 18:6a4db94011d3 859
sahilmgandhi 18:6a4db94011d3 860 /**
sahilmgandhi 18:6a4db94011d3 861 * @brief set the DMA base address and channel index depending on DMA instance
sahilmgandhi 18:6a4db94011d3 862 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 863 * the configuration information for the specified DMA Stream.
sahilmgandhi 18:6a4db94011d3 864 * @retval None
sahilmgandhi 18:6a4db94011d3 865 */
sahilmgandhi 18:6a4db94011d3 866 static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 867 {
sahilmgandhi 18:6a4db94011d3 868 #if defined (DMA2)
sahilmgandhi 18:6a4db94011d3 869 /* calculation of the channel index */
sahilmgandhi 18:6a4db94011d3 870 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
sahilmgandhi 18:6a4db94011d3 871 {
sahilmgandhi 18:6a4db94011d3 872 /* DMA1 */
sahilmgandhi 18:6a4db94011d3 873 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
sahilmgandhi 18:6a4db94011d3 874 hdma->DmaBaseAddress = DMA1;
sahilmgandhi 18:6a4db94011d3 875 }
sahilmgandhi 18:6a4db94011d3 876 else
sahilmgandhi 18:6a4db94011d3 877 {
sahilmgandhi 18:6a4db94011d3 878 /* DMA2 */
sahilmgandhi 18:6a4db94011d3 879 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
sahilmgandhi 18:6a4db94011d3 880 hdma->DmaBaseAddress = DMA2;
sahilmgandhi 18:6a4db94011d3 881 }
sahilmgandhi 18:6a4db94011d3 882 #else
sahilmgandhi 18:6a4db94011d3 883 /* calculation of the channel index */
sahilmgandhi 18:6a4db94011d3 884 /* DMA1 */
sahilmgandhi 18:6a4db94011d3 885 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
sahilmgandhi 18:6a4db94011d3 886 hdma->DmaBaseAddress = DMA1;
sahilmgandhi 18:6a4db94011d3 887 #endif
sahilmgandhi 18:6a4db94011d3 888 }
sahilmgandhi 18:6a4db94011d3 889
sahilmgandhi 18:6a4db94011d3 890 /**
sahilmgandhi 18:6a4db94011d3 891 * @}
sahilmgandhi 18:6a4db94011d3 892 */
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 /**
sahilmgandhi 18:6a4db94011d3 895 * @}
sahilmgandhi 18:6a4db94011d3 896 */
sahilmgandhi 18:6a4db94011d3 897 #endif /* HAL_DMA_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 898
sahilmgandhi 18:6a4db94011d3 899 /**
sahilmgandhi 18:6a4db94011d3 900 * @}
sahilmgandhi 18:6a4db94011d3 901 */
sahilmgandhi 18:6a4db94011d3 902
sahilmgandhi 18:6a4db94011d3 903 /**
sahilmgandhi 18:6a4db94011d3 904 * @}
sahilmgandhi 18:6a4db94011d3 905 */
sahilmgandhi 18:6a4db94011d3 906
sahilmgandhi 18:6a4db94011d3 907 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/