MacroRat / MouseCode

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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG/device/efm32gg380f1024.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 2 * @file efm32gg380f1024.h
sahilmgandhi 18:6a4db94011d3 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
sahilmgandhi 18:6a4db94011d3 4 * for EFM32GG380F1024
sahilmgandhi 18:6a4db94011d3 5 * @version 5.1.2
sahilmgandhi 18:6a4db94011d3 6 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 7 * @section License
sahilmgandhi 18:6a4db94011d3 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
sahilmgandhi 18:6a4db94011d3 9 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * Permission is granted to anyone to use this software for any purpose,
sahilmgandhi 18:6a4db94011d3 12 * including commercial applications, and to alter it and redistribute it
sahilmgandhi 18:6a4db94011d3 13 * freely, subject to the following restrictions:
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * 1. The origin of this software must not be misrepresented; you must not
sahilmgandhi 18:6a4db94011d3 16 * claim that you wrote the original software.@n
sahilmgandhi 18:6a4db94011d3 17 * 2. Altered source versions must be plainly marked as such, and must not be
sahilmgandhi 18:6a4db94011d3 18 * misrepresented as being the original software.@n
sahilmgandhi 18:6a4db94011d3 19 * 3. This notice may not be removed or altered from any source distribution.
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
sahilmgandhi 18:6a4db94011d3 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
sahilmgandhi 18:6a4db94011d3 23 * providing the Software "AS IS", with no express or implied warranties of any
sahilmgandhi 18:6a4db94011d3 24 * kind, including, but not limited to, any implied warranties of
sahilmgandhi 18:6a4db94011d3 25 * merchantability or fitness for any particular purpose or warranties against
sahilmgandhi 18:6a4db94011d3 26 * infringement of any proprietary rights of a third party.
sahilmgandhi 18:6a4db94011d3 27 *
sahilmgandhi 18:6a4db94011d3 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
sahilmgandhi 18:6a4db94011d3 29 * incidental, or special damages, or any other relief, or for any claim by
sahilmgandhi 18:6a4db94011d3 30 * any third party, arising from your use of this Software.
sahilmgandhi 18:6a4db94011d3 31 *
sahilmgandhi 18:6a4db94011d3 32 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #ifndef EFM32GG380F1024_H
sahilmgandhi 18:6a4db94011d3 35 #define EFM32GG380F1024_H
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 38 extern "C" {
sahilmgandhi 18:6a4db94011d3 39 #endif
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 42 * @addtogroup Parts
sahilmgandhi 18:6a4db94011d3 43 * @{
sahilmgandhi 18:6a4db94011d3 44 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 45
sahilmgandhi 18:6a4db94011d3 46 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 47 * @defgroup EFM32GG380F1024 EFM32GG380F1024
sahilmgandhi 18:6a4db94011d3 48 * @{
sahilmgandhi 18:6a4db94011d3 49 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /** Interrupt Number Definition */
sahilmgandhi 18:6a4db94011d3 52 typedef enum IRQn
sahilmgandhi 18:6a4db94011d3 53 {
sahilmgandhi 18:6a4db94011d3 54 /****** Cortex-M3 Processor Exceptions Numbers ********************************************/
sahilmgandhi 18:6a4db94011d3 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
sahilmgandhi 18:6a4db94011d3 56 HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
sahilmgandhi 18:6a4db94011d3 58 BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
sahilmgandhi 18:6a4db94011d3 60 SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
sahilmgandhi 18:6a4db94011d3 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
sahilmgandhi 18:6a4db94011d3 62 PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
sahilmgandhi 18:6a4db94011d3 63 SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
sahilmgandhi 18:6a4db94011d3 64
sahilmgandhi 18:6a4db94011d3 65 /****** EFM32G Peripheral Interrupt Numbers ***********************************************/
sahilmgandhi 18:6a4db94011d3 66 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
sahilmgandhi 18:6a4db94011d3 67 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
sahilmgandhi 18:6a4db94011d3 68 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
sahilmgandhi 18:6a4db94011d3 69 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
sahilmgandhi 18:6a4db94011d3 70 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
sahilmgandhi 18:6a4db94011d3 71 USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
sahilmgandhi 18:6a4db94011d3 72 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
sahilmgandhi 18:6a4db94011d3 73 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
sahilmgandhi 18:6a4db94011d3 74 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
sahilmgandhi 18:6a4db94011d3 75 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
sahilmgandhi 18:6a4db94011d3 76 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
sahilmgandhi 18:6a4db94011d3 77 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
sahilmgandhi 18:6a4db94011d3 78 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
sahilmgandhi 18:6a4db94011d3 79 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
sahilmgandhi 18:6a4db94011d3 80 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
sahilmgandhi 18:6a4db94011d3 81 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
sahilmgandhi 18:6a4db94011d3 82 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
sahilmgandhi 18:6a4db94011d3 83 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
sahilmgandhi 18:6a4db94011d3 84 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
sahilmgandhi 18:6a4db94011d3 85 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
sahilmgandhi 18:6a4db94011d3 86 UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
sahilmgandhi 18:6a4db94011d3 87 UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
sahilmgandhi 18:6a4db94011d3 88 UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
sahilmgandhi 18:6a4db94011d3 89 UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
sahilmgandhi 18:6a4db94011d3 90 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
sahilmgandhi 18:6a4db94011d3 91 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
sahilmgandhi 18:6a4db94011d3 92 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
sahilmgandhi 18:6a4db94011d3 93 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
sahilmgandhi 18:6a4db94011d3 94 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
sahilmgandhi 18:6a4db94011d3 95 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
sahilmgandhi 18:6a4db94011d3 96 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
sahilmgandhi 18:6a4db94011d3 97 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
sahilmgandhi 18:6a4db94011d3 98 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
sahilmgandhi 18:6a4db94011d3 99 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
sahilmgandhi 18:6a4db94011d3 100 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
sahilmgandhi 18:6a4db94011d3 101 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
sahilmgandhi 18:6a4db94011d3 102 EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
sahilmgandhi 18:6a4db94011d3 103 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
sahilmgandhi 18:6a4db94011d3 104 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 107 * @defgroup EFM32GG380F1024_Core EFM32GG380F1024 Core
sahilmgandhi 18:6a4db94011d3 108 * @{
sahilmgandhi 18:6a4db94011d3 109 * @brief Processor and Core Peripheral Section
sahilmgandhi 18:6a4db94011d3 110 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 111 #define __MPU_PRESENT 1 /**< Presence of MPU */
sahilmgandhi 18:6a4db94011d3 112 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
sahilmgandhi 18:6a4db94011d3 113 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
sahilmgandhi 18:6a4db94011d3 114 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 /** @} End of group EFM32GG380F1024_Core */
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 119 * @defgroup EFM32GG380F1024_Part EFM32GG380F1024 Part
sahilmgandhi 18:6a4db94011d3 120 * @{
sahilmgandhi 18:6a4db94011d3 121 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 122
sahilmgandhi 18:6a4db94011d3 123 /** Part family */
sahilmgandhi 18:6a4db94011d3 124 #define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
sahilmgandhi 18:6a4db94011d3 125 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
sahilmgandhi 18:6a4db94011d3 126 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
sahilmgandhi 18:6a4db94011d3 127 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
sahilmgandhi 18:6a4db94011d3 128 #define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */
sahilmgandhi 18:6a4db94011d3 129 #define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */
sahilmgandhi 18:6a4db94011d3 130 #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */
sahilmgandhi 18:6a4db94011d3 131 #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */
sahilmgandhi 18:6a4db94011d3 132
sahilmgandhi 18:6a4db94011d3 133 /* If part number is not defined as compiler option, define it */
sahilmgandhi 18:6a4db94011d3 134 #if !defined(EFM32GG380F1024)
sahilmgandhi 18:6a4db94011d3 135 #define EFM32GG380F1024 1 /**< Giant/Leopard Gecko Part */
sahilmgandhi 18:6a4db94011d3 136 #endif
sahilmgandhi 18:6a4db94011d3 137
sahilmgandhi 18:6a4db94011d3 138 /** Configure part number */
sahilmgandhi 18:6a4db94011d3 139 #define PART_NUMBER "EFM32GG380F1024" /**< Part Number */
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /** Memory Base addresses and limits */
sahilmgandhi 18:6a4db94011d3 142 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
sahilmgandhi 18:6a4db94011d3 143 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
sahilmgandhi 18:6a4db94011d3 144 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
sahilmgandhi 18:6a4db94011d3 145 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
sahilmgandhi 18:6a4db94011d3 146 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
sahilmgandhi 18:6a4db94011d3 147 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
sahilmgandhi 18:6a4db94011d3 148 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
sahilmgandhi 18:6a4db94011d3 149 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
sahilmgandhi 18:6a4db94011d3 150 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
sahilmgandhi 18:6a4db94011d3 151 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
sahilmgandhi 18:6a4db94011d3 152 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
sahilmgandhi 18:6a4db94011d3 153 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
sahilmgandhi 18:6a4db94011d3 154 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
sahilmgandhi 18:6a4db94011d3 155 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
sahilmgandhi 18:6a4db94011d3 156 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
sahilmgandhi 18:6a4db94011d3 157 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
sahilmgandhi 18:6a4db94011d3 158 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
sahilmgandhi 18:6a4db94011d3 159 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
sahilmgandhi 18:6a4db94011d3 160 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
sahilmgandhi 18:6a4db94011d3 161 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
sahilmgandhi 18:6a4db94011d3 162 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
sahilmgandhi 18:6a4db94011d3 163 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
sahilmgandhi 18:6a4db94011d3 164 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
sahilmgandhi 18:6a4db94011d3 165 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
sahilmgandhi 18:6a4db94011d3 166 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
sahilmgandhi 18:6a4db94011d3 167 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
sahilmgandhi 18:6a4db94011d3 168 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
sahilmgandhi 18:6a4db94011d3 169 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
sahilmgandhi 18:6a4db94011d3 170 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
sahilmgandhi 18:6a4db94011d3 171 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
sahilmgandhi 18:6a4db94011d3 172 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
sahilmgandhi 18:6a4db94011d3 173 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 /** Bit banding area */
sahilmgandhi 18:6a4db94011d3 176 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
sahilmgandhi 18:6a4db94011d3 177 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
sahilmgandhi 18:6a4db94011d3 178
sahilmgandhi 18:6a4db94011d3 179 /** Flash and SRAM limits for EFM32GG380F1024 */
sahilmgandhi 18:6a4db94011d3 180 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
sahilmgandhi 18:6a4db94011d3 181 #define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
sahilmgandhi 18:6a4db94011d3 182 #define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
sahilmgandhi 18:6a4db94011d3 183 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
sahilmgandhi 18:6a4db94011d3 184 #define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
sahilmgandhi 18:6a4db94011d3 185 #define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
sahilmgandhi 18:6a4db94011d3 186 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
sahilmgandhi 18:6a4db94011d3 187 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
sahilmgandhi 18:6a4db94011d3 188 #define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 /** AF channels connect the different on-chip peripherals with the af-mux */
sahilmgandhi 18:6a4db94011d3 191 #define AFCHAN_MAX 163
sahilmgandhi 18:6a4db94011d3 192 #define AFCHANLOC_MAX 7
sahilmgandhi 18:6a4db94011d3 193 /** Analog AF channels */
sahilmgandhi 18:6a4db94011d3 194 #define AFACHAN_MAX 53
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 /* Part number capabilities */
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 #define LETIMER_PRESENT /**< LETIMER is available in this part */
sahilmgandhi 18:6a4db94011d3 199 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
sahilmgandhi 18:6a4db94011d3 200 #define USART_PRESENT /**< USART is available in this part */
sahilmgandhi 18:6a4db94011d3 201 #define USART_COUNT 3 /**< 3 USARTs available */
sahilmgandhi 18:6a4db94011d3 202 #define UART_PRESENT /**< UART is available in this part */
sahilmgandhi 18:6a4db94011d3 203 #define UART_COUNT 2 /**< 2 UARTs available */
sahilmgandhi 18:6a4db94011d3 204 #define TIMER_PRESENT /**< TIMER is available in this part */
sahilmgandhi 18:6a4db94011d3 205 #define TIMER_COUNT 4 /**< 4 TIMERs available */
sahilmgandhi 18:6a4db94011d3 206 #define ACMP_PRESENT /**< ACMP is available in this part */
sahilmgandhi 18:6a4db94011d3 207 #define ACMP_COUNT 2 /**< 2 ACMPs available */
sahilmgandhi 18:6a4db94011d3 208 #define I2C_PRESENT /**< I2C is available in this part */
sahilmgandhi 18:6a4db94011d3 209 #define I2C_COUNT 2 /**< 2 I2Cs available */
sahilmgandhi 18:6a4db94011d3 210 #define LEUART_PRESENT /**< LEUART is available in this part */
sahilmgandhi 18:6a4db94011d3 211 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
sahilmgandhi 18:6a4db94011d3 212 #define PCNT_PRESENT /**< PCNT is available in this part */
sahilmgandhi 18:6a4db94011d3 213 #define PCNT_COUNT 3 /**< 3 PCNTs available */
sahilmgandhi 18:6a4db94011d3 214 #define ADC_PRESENT /**< ADC is available in this part */
sahilmgandhi 18:6a4db94011d3 215 #define ADC_COUNT 1 /**< 1 ADCs available */
sahilmgandhi 18:6a4db94011d3 216 #define DAC_PRESENT /**< DAC is available in this part */
sahilmgandhi 18:6a4db94011d3 217 #define DAC_COUNT 1 /**< 1 DACs available */
sahilmgandhi 18:6a4db94011d3 218 #define DMA_PRESENT
sahilmgandhi 18:6a4db94011d3 219 #define DMA_COUNT 1
sahilmgandhi 18:6a4db94011d3 220 #define AES_PRESENT
sahilmgandhi 18:6a4db94011d3 221 #define AES_COUNT 1
sahilmgandhi 18:6a4db94011d3 222 #define USBC_PRESENT
sahilmgandhi 18:6a4db94011d3 223 #define USBC_COUNT 1
sahilmgandhi 18:6a4db94011d3 224 #define USB_PRESENT
sahilmgandhi 18:6a4db94011d3 225 #define USB_COUNT 1
sahilmgandhi 18:6a4db94011d3 226 #define LE_PRESENT
sahilmgandhi 18:6a4db94011d3 227 #define LE_COUNT 1
sahilmgandhi 18:6a4db94011d3 228 #define MSC_PRESENT
sahilmgandhi 18:6a4db94011d3 229 #define MSC_COUNT 1
sahilmgandhi 18:6a4db94011d3 230 #define EMU_PRESENT
sahilmgandhi 18:6a4db94011d3 231 #define EMU_COUNT 1
sahilmgandhi 18:6a4db94011d3 232 #define RMU_PRESENT
sahilmgandhi 18:6a4db94011d3 233 #define RMU_COUNT 1
sahilmgandhi 18:6a4db94011d3 234 #define CMU_PRESENT
sahilmgandhi 18:6a4db94011d3 235 #define CMU_COUNT 1
sahilmgandhi 18:6a4db94011d3 236 #define LESENSE_PRESENT
sahilmgandhi 18:6a4db94011d3 237 #define LESENSE_COUNT 1
sahilmgandhi 18:6a4db94011d3 238 #define RTC_PRESENT
sahilmgandhi 18:6a4db94011d3 239 #define RTC_COUNT 1
sahilmgandhi 18:6a4db94011d3 240 #define EBI_PRESENT
sahilmgandhi 18:6a4db94011d3 241 #define EBI_COUNT 1
sahilmgandhi 18:6a4db94011d3 242 #define GPIO_PRESENT
sahilmgandhi 18:6a4db94011d3 243 #define GPIO_COUNT 1
sahilmgandhi 18:6a4db94011d3 244 #define VCMP_PRESENT
sahilmgandhi 18:6a4db94011d3 245 #define VCMP_COUNT 1
sahilmgandhi 18:6a4db94011d3 246 #define PRS_PRESENT
sahilmgandhi 18:6a4db94011d3 247 #define PRS_COUNT 1
sahilmgandhi 18:6a4db94011d3 248 #define OPAMP_PRESENT
sahilmgandhi 18:6a4db94011d3 249 #define OPAMP_COUNT 1
sahilmgandhi 18:6a4db94011d3 250 #define BU_PRESENT
sahilmgandhi 18:6a4db94011d3 251 #define BU_COUNT 1
sahilmgandhi 18:6a4db94011d3 252 #define BURTC_PRESENT
sahilmgandhi 18:6a4db94011d3 253 #define BURTC_COUNT 1
sahilmgandhi 18:6a4db94011d3 254 #define HFXTAL_PRESENT
sahilmgandhi 18:6a4db94011d3 255 #define HFXTAL_COUNT 1
sahilmgandhi 18:6a4db94011d3 256 #define LFXTAL_PRESENT
sahilmgandhi 18:6a4db94011d3 257 #define LFXTAL_COUNT 1
sahilmgandhi 18:6a4db94011d3 258 #define WDOG_PRESENT
sahilmgandhi 18:6a4db94011d3 259 #define WDOG_COUNT 1
sahilmgandhi 18:6a4db94011d3 260 #define DBG_PRESENT
sahilmgandhi 18:6a4db94011d3 261 #define DBG_COUNT 1
sahilmgandhi 18:6a4db94011d3 262 #define ETM_PRESENT
sahilmgandhi 18:6a4db94011d3 263 #define ETM_COUNT 1
sahilmgandhi 18:6a4db94011d3 264 #define BOOTLOADER_PRESENT
sahilmgandhi 18:6a4db94011d3 265 #define BOOTLOADER_COUNT 1
sahilmgandhi 18:6a4db94011d3 266 #define ANALOG_PRESENT
sahilmgandhi 18:6a4db94011d3 267 #define ANALOG_COUNT 1
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 270 #include "system_efm32gg.h" /* System Header */
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /** @} End of group EFM32GG380F1024_Part */
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 275 * @defgroup EFM32GG380F1024_Peripheral_TypeDefs EFM32GG380F1024 Peripheral TypeDefs
sahilmgandhi 18:6a4db94011d3 276 * @{
sahilmgandhi 18:6a4db94011d3 277 * @brief Device Specific Peripheral Register Structures
sahilmgandhi 18:6a4db94011d3 278 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 #include "efm32gg_dma_ch.h"
sahilmgandhi 18:6a4db94011d3 281 #include "efm32gg_dma.h"
sahilmgandhi 18:6a4db94011d3 282 #include "efm32gg_aes.h"
sahilmgandhi 18:6a4db94011d3 283 #include "efm32gg_usb_hc.h"
sahilmgandhi 18:6a4db94011d3 284 #include "efm32gg_usb_diep.h"
sahilmgandhi 18:6a4db94011d3 285 #include "efm32gg_usb_doep.h"
sahilmgandhi 18:6a4db94011d3 286 #include "efm32gg_usb.h"
sahilmgandhi 18:6a4db94011d3 287 #include "efm32gg_msc.h"
sahilmgandhi 18:6a4db94011d3 288 #include "efm32gg_emu.h"
sahilmgandhi 18:6a4db94011d3 289 #include "efm32gg_rmu.h"
sahilmgandhi 18:6a4db94011d3 290
sahilmgandhi 18:6a4db94011d3 291 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 292 * @defgroup EFM32GG380F1024_CMU EFM32GG380F1024 CMU
sahilmgandhi 18:6a4db94011d3 293 * @{
sahilmgandhi 18:6a4db94011d3 294 * @brief EFM32GG380F1024_CMU Register Declaration
sahilmgandhi 18:6a4db94011d3 295 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 296 typedef struct
sahilmgandhi 18:6a4db94011d3 297 {
sahilmgandhi 18:6a4db94011d3 298 __IOM uint32_t CTRL; /**< CMU Control Register */
sahilmgandhi 18:6a4db94011d3 299 __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
sahilmgandhi 18:6a4db94011d3 300 __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
sahilmgandhi 18:6a4db94011d3 301 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
sahilmgandhi 18:6a4db94011d3 302 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
sahilmgandhi 18:6a4db94011d3 303 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
sahilmgandhi 18:6a4db94011d3 304 __IOM uint32_t CALCTRL; /**< Calibration Control Register */
sahilmgandhi 18:6a4db94011d3 305 __IOM uint32_t CALCNT; /**< Calibration Counter Register */
sahilmgandhi 18:6a4db94011d3 306 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
sahilmgandhi 18:6a4db94011d3 307 __IOM uint32_t CMD; /**< Command Register */
sahilmgandhi 18:6a4db94011d3 308 __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
sahilmgandhi 18:6a4db94011d3 309 __IM uint32_t STATUS; /**< Status Register */
sahilmgandhi 18:6a4db94011d3 310 __IM uint32_t IF; /**< Interrupt Flag Register */
sahilmgandhi 18:6a4db94011d3 311 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
sahilmgandhi 18:6a4db94011d3 312 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
sahilmgandhi 18:6a4db94011d3 313 __IOM uint32_t IEN; /**< Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 314 __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
sahilmgandhi 18:6a4db94011d3 315 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
sahilmgandhi 18:6a4db94011d3 316 uint32_t RESERVED0[2]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 317 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
sahilmgandhi 18:6a4db94011d3 318 __IOM uint32_t FREEZE; /**< Freeze Register */
sahilmgandhi 18:6a4db94011d3 319 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
sahilmgandhi 18:6a4db94011d3 320 uint32_t RESERVED1[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 321 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 uint32_t RESERVED2[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 324 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
sahilmgandhi 18:6a4db94011d3 325 uint32_t RESERVED3[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 326 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
sahilmgandhi 18:6a4db94011d3 327 uint32_t RESERVED4[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 328 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 uint32_t RESERVED5[1]; /**< Reserved for future use **/
sahilmgandhi 18:6a4db94011d3 331 __IOM uint32_t ROUTE; /**< I/O Routing Register */
sahilmgandhi 18:6a4db94011d3 332 __IOM uint32_t LOCK; /**< Configuration Lock Register */
sahilmgandhi 18:6a4db94011d3 333 } CMU_TypeDef; /** @} */
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 #include "efm32gg_lesense_st.h"
sahilmgandhi 18:6a4db94011d3 336 #include "efm32gg_lesense_buf.h"
sahilmgandhi 18:6a4db94011d3 337 #include "efm32gg_lesense_ch.h"
sahilmgandhi 18:6a4db94011d3 338 #include "efm32gg_lesense.h"
sahilmgandhi 18:6a4db94011d3 339 #include "efm32gg_rtc.h"
sahilmgandhi 18:6a4db94011d3 340 #include "efm32gg_letimer.h"
sahilmgandhi 18:6a4db94011d3 341 #include "efm32gg_ebi.h"
sahilmgandhi 18:6a4db94011d3 342 #include "efm32gg_usart.h"
sahilmgandhi 18:6a4db94011d3 343 #include "efm32gg_timer_cc.h"
sahilmgandhi 18:6a4db94011d3 344 #include "efm32gg_timer.h"
sahilmgandhi 18:6a4db94011d3 345 #include "efm32gg_acmp.h"
sahilmgandhi 18:6a4db94011d3 346 #include "efm32gg_i2c.h"
sahilmgandhi 18:6a4db94011d3 347 #include "efm32gg_gpio_p.h"
sahilmgandhi 18:6a4db94011d3 348 #include "efm32gg_gpio.h"
sahilmgandhi 18:6a4db94011d3 349 #include "efm32gg_vcmp.h"
sahilmgandhi 18:6a4db94011d3 350 #include "efm32gg_prs_ch.h"
sahilmgandhi 18:6a4db94011d3 351 #include "efm32gg_prs.h"
sahilmgandhi 18:6a4db94011d3 352 #include "efm32gg_leuart.h"
sahilmgandhi 18:6a4db94011d3 353 #include "efm32gg_pcnt.h"
sahilmgandhi 18:6a4db94011d3 354 #include "efm32gg_adc.h"
sahilmgandhi 18:6a4db94011d3 355 #include "efm32gg_dac.h"
sahilmgandhi 18:6a4db94011d3 356 #include "efm32gg_burtc_ret.h"
sahilmgandhi 18:6a4db94011d3 357 #include "efm32gg_burtc.h"
sahilmgandhi 18:6a4db94011d3 358 #include "efm32gg_wdog.h"
sahilmgandhi 18:6a4db94011d3 359 #include "efm32gg_etm.h"
sahilmgandhi 18:6a4db94011d3 360 #include "efm32gg_dma_descriptor.h"
sahilmgandhi 18:6a4db94011d3 361 #include "efm32gg_devinfo.h"
sahilmgandhi 18:6a4db94011d3 362 #include "efm32gg_romtable.h"
sahilmgandhi 18:6a4db94011d3 363 #include "efm32gg_calibrate.h"
sahilmgandhi 18:6a4db94011d3 364
sahilmgandhi 18:6a4db94011d3 365 /** @} End of group EFM32GG380F1024_Peripheral_TypeDefs */
sahilmgandhi 18:6a4db94011d3 366
sahilmgandhi 18:6a4db94011d3 367 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 368 * @defgroup EFM32GG380F1024_Peripheral_Base EFM32GG380F1024 Peripheral Memory Map
sahilmgandhi 18:6a4db94011d3 369 * @{
sahilmgandhi 18:6a4db94011d3 370 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
sahilmgandhi 18:6a4db94011d3 373 #define AES_BASE (0x400E0000UL) /**< AES base address */
sahilmgandhi 18:6a4db94011d3 374 #define USB_BASE (0x400C4000UL) /**< USB base address */
sahilmgandhi 18:6a4db94011d3 375 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
sahilmgandhi 18:6a4db94011d3 376 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
sahilmgandhi 18:6a4db94011d3 377 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
sahilmgandhi 18:6a4db94011d3 378 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
sahilmgandhi 18:6a4db94011d3 379 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
sahilmgandhi 18:6a4db94011d3 380 #define RTC_BASE (0x40080000UL) /**< RTC base address */
sahilmgandhi 18:6a4db94011d3 381 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
sahilmgandhi 18:6a4db94011d3 382 #define EBI_BASE (0x40008000UL) /**< EBI base address */
sahilmgandhi 18:6a4db94011d3 383 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
sahilmgandhi 18:6a4db94011d3 384 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
sahilmgandhi 18:6a4db94011d3 385 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
sahilmgandhi 18:6a4db94011d3 386 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */
sahilmgandhi 18:6a4db94011d3 387 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */
sahilmgandhi 18:6a4db94011d3 388 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
sahilmgandhi 18:6a4db94011d3 389 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
sahilmgandhi 18:6a4db94011d3 390 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
sahilmgandhi 18:6a4db94011d3 391 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
sahilmgandhi 18:6a4db94011d3 392 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
sahilmgandhi 18:6a4db94011d3 393 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
sahilmgandhi 18:6a4db94011d3 394 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
sahilmgandhi 18:6a4db94011d3 395 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
sahilmgandhi 18:6a4db94011d3 396 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
sahilmgandhi 18:6a4db94011d3 397 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
sahilmgandhi 18:6a4db94011d3 398 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
sahilmgandhi 18:6a4db94011d3 399 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
sahilmgandhi 18:6a4db94011d3 400 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
sahilmgandhi 18:6a4db94011d3 401 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
sahilmgandhi 18:6a4db94011d3 402 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
sahilmgandhi 18:6a4db94011d3 403 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
sahilmgandhi 18:6a4db94011d3 404 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
sahilmgandhi 18:6a4db94011d3 405 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
sahilmgandhi 18:6a4db94011d3 406 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
sahilmgandhi 18:6a4db94011d3 407 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
sahilmgandhi 18:6a4db94011d3 408 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
sahilmgandhi 18:6a4db94011d3 409 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
sahilmgandhi 18:6a4db94011d3 410 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
sahilmgandhi 18:6a4db94011d3 411 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
sahilmgandhi 18:6a4db94011d3 412 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
sahilmgandhi 18:6a4db94011d3 413 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
sahilmgandhi 18:6a4db94011d3 414
sahilmgandhi 18:6a4db94011d3 415 /** @} End of group EFM32GG380F1024_Peripheral_Base */
sahilmgandhi 18:6a4db94011d3 416
sahilmgandhi 18:6a4db94011d3 417 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 418 * @defgroup EFM32GG380F1024_Peripheral_Declaration EFM32GG380F1024 Peripheral Declarations
sahilmgandhi 18:6a4db94011d3 419 * @{
sahilmgandhi 18:6a4db94011d3 420 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
sahilmgandhi 18:6a4db94011d3 423 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
sahilmgandhi 18:6a4db94011d3 424 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
sahilmgandhi 18:6a4db94011d3 425 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
sahilmgandhi 18:6a4db94011d3 426 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
sahilmgandhi 18:6a4db94011d3 427 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
sahilmgandhi 18:6a4db94011d3 428 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
sahilmgandhi 18:6a4db94011d3 429 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
sahilmgandhi 18:6a4db94011d3 430 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
sahilmgandhi 18:6a4db94011d3 431 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
sahilmgandhi 18:6a4db94011d3 432 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
sahilmgandhi 18:6a4db94011d3 433 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
sahilmgandhi 18:6a4db94011d3 434 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
sahilmgandhi 18:6a4db94011d3 435 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
sahilmgandhi 18:6a4db94011d3 436 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
sahilmgandhi 18:6a4db94011d3 437 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
sahilmgandhi 18:6a4db94011d3 438 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
sahilmgandhi 18:6a4db94011d3 439 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
sahilmgandhi 18:6a4db94011d3 440 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
sahilmgandhi 18:6a4db94011d3 441 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
sahilmgandhi 18:6a4db94011d3 442 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
sahilmgandhi 18:6a4db94011d3 443 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
sahilmgandhi 18:6a4db94011d3 444 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
sahilmgandhi 18:6a4db94011d3 445 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
sahilmgandhi 18:6a4db94011d3 446 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
sahilmgandhi 18:6a4db94011d3 447 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
sahilmgandhi 18:6a4db94011d3 448 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
sahilmgandhi 18:6a4db94011d3 449 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
sahilmgandhi 18:6a4db94011d3 450 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
sahilmgandhi 18:6a4db94011d3 451 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
sahilmgandhi 18:6a4db94011d3 452 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
sahilmgandhi 18:6a4db94011d3 453 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
sahilmgandhi 18:6a4db94011d3 454 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
sahilmgandhi 18:6a4db94011d3 455 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
sahilmgandhi 18:6a4db94011d3 456 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
sahilmgandhi 18:6a4db94011d3 457 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
sahilmgandhi 18:6a4db94011d3 458 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
sahilmgandhi 18:6a4db94011d3 459 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
sahilmgandhi 18:6a4db94011d3 460 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
sahilmgandhi 18:6a4db94011d3 461 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
sahilmgandhi 18:6a4db94011d3 462
sahilmgandhi 18:6a4db94011d3 463 /** @} End of group EFM32GG380F1024_Peripheral_Declaration */
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 466 * @defgroup EFM32GG380F1024_BitFields EFM32GG380F1024 Bit Fields
sahilmgandhi 18:6a4db94011d3 467 * @{
sahilmgandhi 18:6a4db94011d3 468 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 #include "efm32gg_prs_signals.h"
sahilmgandhi 18:6a4db94011d3 471 #include "efm32gg_dmareq.h"
sahilmgandhi 18:6a4db94011d3 472 #include "efm32gg_dmactrl.h"
sahilmgandhi 18:6a4db94011d3 473 #include "efm32gg_uart.h"
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 476 * @defgroup EFM32GG380F1024_CMU_BitFields EFM32GG380F1024_CMU Bit Fields
sahilmgandhi 18:6a4db94011d3 477 * @{
sahilmgandhi 18:6a4db94011d3 478 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /* Bit fields for CMU CTRL */
sahilmgandhi 18:6a4db94011d3 481 #define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 482 #define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 483 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
sahilmgandhi 18:6a4db94011d3 484 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
sahilmgandhi 18:6a4db94011d3 485 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 486 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 487 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 488 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 489 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 490 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 491 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 492 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 493 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
sahilmgandhi 18:6a4db94011d3 494 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
sahilmgandhi 18:6a4db94011d3 495 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 496 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 497 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 498 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 499 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 500 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 501 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 502 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 503 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 504 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 505 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
sahilmgandhi 18:6a4db94011d3 506 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
sahilmgandhi 18:6a4db94011d3 507 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 508 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 509 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 510 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 511 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 512 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 513 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
sahilmgandhi 18:6a4db94011d3 514 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
sahilmgandhi 18:6a4db94011d3 515 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
sahilmgandhi 18:6a4db94011d3 516 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 517 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 518 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
sahilmgandhi 18:6a4db94011d3 519 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
sahilmgandhi 18:6a4db94011d3 520 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 521 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 522 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 523 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 524 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 525 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 526 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 527 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 528 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 529 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 530 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
sahilmgandhi 18:6a4db94011d3 531 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
sahilmgandhi 18:6a4db94011d3 532 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 533 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 534 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 535 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 536 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 537 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 538 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 539 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 540 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
sahilmgandhi 18:6a4db94011d3 541 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
sahilmgandhi 18:6a4db94011d3 542 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
sahilmgandhi 18:6a4db94011d3 543 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 544 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 545 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 546 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 547 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 548 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 549 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */
sahilmgandhi 18:6a4db94011d3 550 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */
sahilmgandhi 18:6a4db94011d3 551 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 552 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 553 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
sahilmgandhi 18:6a4db94011d3 554 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
sahilmgandhi 18:6a4db94011d3 555 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
sahilmgandhi 18:6a4db94011d3 556 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 557 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 558 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
sahilmgandhi 18:6a4db94011d3 559 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
sahilmgandhi 18:6a4db94011d3 560 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 561 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 562 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 563 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 564 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 565 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 566 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 567 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 568 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 569 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 570 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
sahilmgandhi 18:6a4db94011d3 571 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
sahilmgandhi 18:6a4db94011d3 572 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 573 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 574 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 575 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 576 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 577 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 578 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 579 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 580 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 581 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 582 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 583 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 584 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 585 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 586 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 587 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 588 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 589 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 590 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
sahilmgandhi 18:6a4db94011d3 591 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
sahilmgandhi 18:6a4db94011d3 592 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 593 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 594 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 595 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 596 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 597 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 598 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 599 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 600 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 601 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 602 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 603 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 604 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 605 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 606 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 607 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 608 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 609 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 610 #define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */
sahilmgandhi 18:6a4db94011d3 611 #define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */
sahilmgandhi 18:6a4db94011d3 612 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */
sahilmgandhi 18:6a4db94011d3 613 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 614 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 615 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 616 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 617 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 618 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 619 #define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */
sahilmgandhi 18:6a4db94011d3 620 #define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */
sahilmgandhi 18:6a4db94011d3 621 #define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */
sahilmgandhi 18:6a4db94011d3 622 #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 623 #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */
sahilmgandhi 18:6a4db94011d3 624
sahilmgandhi 18:6a4db94011d3 625 /* Bit fields for CMU HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 626 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 627 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 628 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 629 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 630 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 631 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 632 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 633 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 634 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 635 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 636 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 637 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 638 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 639 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 640 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 641 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 642 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 643 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 644 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 645 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 646 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 647 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 648 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 649 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 650 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 651 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 652 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
sahilmgandhi 18:6a4db94011d3 653 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
sahilmgandhi 18:6a4db94011d3 654 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
sahilmgandhi 18:6a4db94011d3 655 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 656 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 657 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 658 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 659 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 660 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
sahilmgandhi 18:6a4db94011d3 661
sahilmgandhi 18:6a4db94011d3 662 /* Bit fields for CMU HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 663 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 664 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 665 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 666 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 667 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 668 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 669 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 670 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 671 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 672 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 673 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 674 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 675 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 676 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 677 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 678 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 679 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 680 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 681 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 682 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 683 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 684 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 685 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 686 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 687 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 688 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 689 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
sahilmgandhi 18:6a4db94011d3 690 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
sahilmgandhi 18:6a4db94011d3 691 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
sahilmgandhi 18:6a4db94011d3 692 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 693 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
sahilmgandhi 18:6a4db94011d3 694
sahilmgandhi 18:6a4db94011d3 695 /* Bit fields for CMU HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 696 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 697 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 698 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
sahilmgandhi 18:6a4db94011d3 699 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
sahilmgandhi 18:6a4db94011d3 700 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 701 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 702 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
sahilmgandhi 18:6a4db94011d3 703 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
sahilmgandhi 18:6a4db94011d3 704 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 705 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 706 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 707 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 708 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 709 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 710 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 711 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 712 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 713 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 714 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 715 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 716 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 717 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 718 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
sahilmgandhi 18:6a4db94011d3 719 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
sahilmgandhi 18:6a4db94011d3 720 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 721 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 722
sahilmgandhi 18:6a4db94011d3 723 /* Bit fields for CMU LFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 724 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 725 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 726 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
sahilmgandhi 18:6a4db94011d3 727 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
sahilmgandhi 18:6a4db94011d3 728 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 729 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 730
sahilmgandhi 18:6a4db94011d3 731 /* Bit fields for CMU AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 732 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 733 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 734 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
sahilmgandhi 18:6a4db94011d3 735 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
sahilmgandhi 18:6a4db94011d3 736 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 737 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 738 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
sahilmgandhi 18:6a4db94011d3 739 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
sahilmgandhi 18:6a4db94011d3 740 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 741 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 742 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 743 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 744 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 745 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 746 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 747 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 748 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 749 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 750 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 751 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 752 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 753 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
sahilmgandhi 18:6a4db94011d3 754
sahilmgandhi 18:6a4db94011d3 755 /* Bit fields for CMU CALCTRL */
sahilmgandhi 18:6a4db94011d3 756 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 757 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 758 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
sahilmgandhi 18:6a4db94011d3 759 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
sahilmgandhi 18:6a4db94011d3 760 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 761 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 762 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 763 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 764 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 765 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 766 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 767 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 768 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 769 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 770 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 771 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 772 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
sahilmgandhi 18:6a4db94011d3 773 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
sahilmgandhi 18:6a4db94011d3 774 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 775 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 776 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 777 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 778 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 779 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 780 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 781 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 782 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 783 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 784 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 785 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 786 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 787 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 788 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
sahilmgandhi 18:6a4db94011d3 789 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
sahilmgandhi 18:6a4db94011d3 790 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
sahilmgandhi 18:6a4db94011d3 791 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 792 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
sahilmgandhi 18:6a4db94011d3 793
sahilmgandhi 18:6a4db94011d3 794 /* Bit fields for CMU CALCNT */
sahilmgandhi 18:6a4db94011d3 795 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
sahilmgandhi 18:6a4db94011d3 796 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
sahilmgandhi 18:6a4db94011d3 797 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
sahilmgandhi 18:6a4db94011d3 798 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
sahilmgandhi 18:6a4db94011d3 799 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
sahilmgandhi 18:6a4db94011d3 800 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
sahilmgandhi 18:6a4db94011d3 801
sahilmgandhi 18:6a4db94011d3 802 /* Bit fields for CMU OSCENCMD */
sahilmgandhi 18:6a4db94011d3 803 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 804 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 805 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
sahilmgandhi 18:6a4db94011d3 806 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
sahilmgandhi 18:6a4db94011d3 807 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
sahilmgandhi 18:6a4db94011d3 808 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 809 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 810 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
sahilmgandhi 18:6a4db94011d3 811 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
sahilmgandhi 18:6a4db94011d3 812 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
sahilmgandhi 18:6a4db94011d3 813 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 814 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 815 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
sahilmgandhi 18:6a4db94011d3 816 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
sahilmgandhi 18:6a4db94011d3 817 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
sahilmgandhi 18:6a4db94011d3 818 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 819 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 820 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
sahilmgandhi 18:6a4db94011d3 821 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
sahilmgandhi 18:6a4db94011d3 822 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
sahilmgandhi 18:6a4db94011d3 823 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 824 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 825 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
sahilmgandhi 18:6a4db94011d3 826 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
sahilmgandhi 18:6a4db94011d3 827 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
sahilmgandhi 18:6a4db94011d3 828 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 829 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 830 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
sahilmgandhi 18:6a4db94011d3 831 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
sahilmgandhi 18:6a4db94011d3 832 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
sahilmgandhi 18:6a4db94011d3 833 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 834 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 835 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
sahilmgandhi 18:6a4db94011d3 836 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
sahilmgandhi 18:6a4db94011d3 837 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
sahilmgandhi 18:6a4db94011d3 838 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 839 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 840 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
sahilmgandhi 18:6a4db94011d3 841 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
sahilmgandhi 18:6a4db94011d3 842 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
sahilmgandhi 18:6a4db94011d3 843 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 844 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 845 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
sahilmgandhi 18:6a4db94011d3 846 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
sahilmgandhi 18:6a4db94011d3 847 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
sahilmgandhi 18:6a4db94011d3 848 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 849 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 850 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
sahilmgandhi 18:6a4db94011d3 851 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
sahilmgandhi 18:6a4db94011d3 852 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
sahilmgandhi 18:6a4db94011d3 853 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 854 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
sahilmgandhi 18:6a4db94011d3 855
sahilmgandhi 18:6a4db94011d3 856 /* Bit fields for CMU CMD */
sahilmgandhi 18:6a4db94011d3 857 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 858 #define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 859 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
sahilmgandhi 18:6a4db94011d3 860 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
sahilmgandhi 18:6a4db94011d3 861 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 862 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 863 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 864 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 865 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 866 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 867 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 868 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 869 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 870 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 871 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
sahilmgandhi 18:6a4db94011d3 872 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
sahilmgandhi 18:6a4db94011d3 873 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
sahilmgandhi 18:6a4db94011d3 874 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 875 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 876 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
sahilmgandhi 18:6a4db94011d3 877 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
sahilmgandhi 18:6a4db94011d3 878 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
sahilmgandhi 18:6a4db94011d3 879 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 880 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 881 #define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */
sahilmgandhi 18:6a4db94011d3 882 #define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */
sahilmgandhi 18:6a4db94011d3 883 #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 884 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL /**< Mode HFCLKNODIV for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 885 #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 886 #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 887 #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 888 #define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) /**< Shifted mode HFCLKNODIV for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 889 #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 890 #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */
sahilmgandhi 18:6a4db94011d3 891
sahilmgandhi 18:6a4db94011d3 892 /* Bit fields for CMU LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 893 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 894 #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 895 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
sahilmgandhi 18:6a4db94011d3 896 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
sahilmgandhi 18:6a4db94011d3 897 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 898 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 899 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 900 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 901 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 902 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 903 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 904 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 905 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 906 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 907 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
sahilmgandhi 18:6a4db94011d3 908 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
sahilmgandhi 18:6a4db94011d3 909 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 910 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 911 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 912 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 913 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 914 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 915 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 916 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 917 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 918 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 919 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
sahilmgandhi 18:6a4db94011d3 920 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
sahilmgandhi 18:6a4db94011d3 921 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
sahilmgandhi 18:6a4db94011d3 922 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 923 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 924 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 925 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 926 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 927 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 928 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
sahilmgandhi 18:6a4db94011d3 929 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
sahilmgandhi 18:6a4db94011d3 930 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
sahilmgandhi 18:6a4db94011d3 931 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 932 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 933 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 934 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 935 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 936 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
sahilmgandhi 18:6a4db94011d3 937
sahilmgandhi 18:6a4db94011d3 938 /* Bit fields for CMU STATUS */
sahilmgandhi 18:6a4db94011d3 939 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 940 #define _CMU_STATUS_MASK 0x0003FFFFUL /**< Mask for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 941 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
sahilmgandhi 18:6a4db94011d3 942 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
sahilmgandhi 18:6a4db94011d3 943 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
sahilmgandhi 18:6a4db94011d3 944 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 945 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 946 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
sahilmgandhi 18:6a4db94011d3 947 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 948 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 949 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 950 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 951 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
sahilmgandhi 18:6a4db94011d3 952 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
sahilmgandhi 18:6a4db94011d3 953 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
sahilmgandhi 18:6a4db94011d3 954 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 955 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 956 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
sahilmgandhi 18:6a4db94011d3 957 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 958 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 959 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 960 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 961 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
sahilmgandhi 18:6a4db94011d3 962 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
sahilmgandhi 18:6a4db94011d3 963 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
sahilmgandhi 18:6a4db94011d3 964 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 965 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 966 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
sahilmgandhi 18:6a4db94011d3 967 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 968 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 969 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 970 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 971 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
sahilmgandhi 18:6a4db94011d3 972 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
sahilmgandhi 18:6a4db94011d3 973 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
sahilmgandhi 18:6a4db94011d3 974 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 975 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 976 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
sahilmgandhi 18:6a4db94011d3 977 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 978 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 979 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 980 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 981 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
sahilmgandhi 18:6a4db94011d3 982 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
sahilmgandhi 18:6a4db94011d3 983 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
sahilmgandhi 18:6a4db94011d3 984 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 985 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 986 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
sahilmgandhi 18:6a4db94011d3 987 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 988 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 989 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 990 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 991 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
sahilmgandhi 18:6a4db94011d3 992 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
sahilmgandhi 18:6a4db94011d3 993 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
sahilmgandhi 18:6a4db94011d3 994 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 995 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 996 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
sahilmgandhi 18:6a4db94011d3 997 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
sahilmgandhi 18:6a4db94011d3 998 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
sahilmgandhi 18:6a4db94011d3 999 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1000 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1001 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
sahilmgandhi 18:6a4db94011d3 1002 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
sahilmgandhi 18:6a4db94011d3 1003 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
sahilmgandhi 18:6a4db94011d3 1004 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1005 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1006 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
sahilmgandhi 18:6a4db94011d3 1007 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
sahilmgandhi 18:6a4db94011d3 1008 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
sahilmgandhi 18:6a4db94011d3 1009 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1010 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1011 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
sahilmgandhi 18:6a4db94011d3 1012 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
sahilmgandhi 18:6a4db94011d3 1013 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
sahilmgandhi 18:6a4db94011d3 1014 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1015 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1016 #define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15) /**< USBC HFCLK Selected */
sahilmgandhi 18:6a4db94011d3 1017 #define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15 /**< Shift value for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1018 #define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL /**< Bit mask for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1019 #define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1020 #define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1021 #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */
sahilmgandhi 18:6a4db94011d3 1022 #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */
sahilmgandhi 18:6a4db94011d3 1023 #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */
sahilmgandhi 18:6a4db94011d3 1024 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1025 #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1026 #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */
sahilmgandhi 18:6a4db94011d3 1027 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */
sahilmgandhi 18:6a4db94011d3 1028 #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */
sahilmgandhi 18:6a4db94011d3 1029 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1030 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */
sahilmgandhi 18:6a4db94011d3 1031
sahilmgandhi 18:6a4db94011d3 1032 /* Bit fields for CMU IF */
sahilmgandhi 18:6a4db94011d3 1033 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1034 #define _CMU_IF_MASK 0x000000FFUL /**< Mask for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1035 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 1036 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 1037 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 1038 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1039 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1040 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 1041 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 1042 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 1043 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1044 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1045 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 1046 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 1047 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 1048 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1049 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1050 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 1051 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 1052 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 1053 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1054 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1055 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 1056 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 1057 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 1058 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1059 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1060 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 1061 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
sahilmgandhi 18:6a4db94011d3 1062 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
sahilmgandhi 18:6a4db94011d3 1063 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1064 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1065 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 1066 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
sahilmgandhi 18:6a4db94011d3 1067 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
sahilmgandhi 18:6a4db94011d3 1068 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1069 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1070 #define CMU_IF_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag */
sahilmgandhi 18:6a4db94011d3 1071 #define _CMU_IF_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1072 #define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1073 #define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1074 #define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IF */
sahilmgandhi 18:6a4db94011d3 1075
sahilmgandhi 18:6a4db94011d3 1076 /* Bit fields for CMU IFS */
sahilmgandhi 18:6a4db94011d3 1077 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1078 #define _CMU_IFS_MASK 0x000000FFUL /**< Mask for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1079 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
sahilmgandhi 18:6a4db94011d3 1080 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 1081 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 1082 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1083 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1084 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
sahilmgandhi 18:6a4db94011d3 1085 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 1086 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 1087 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1088 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1089 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
sahilmgandhi 18:6a4db94011d3 1090 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 1091 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 1092 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1093 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1094 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
sahilmgandhi 18:6a4db94011d3 1095 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 1096 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 1097 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1098 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1099 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
sahilmgandhi 18:6a4db94011d3 1100 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 1101 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 1102 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1103 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1104 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
sahilmgandhi 18:6a4db94011d3 1105 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
sahilmgandhi 18:6a4db94011d3 1106 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
sahilmgandhi 18:6a4db94011d3 1107 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1108 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1109 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
sahilmgandhi 18:6a4db94011d3 1110 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
sahilmgandhi 18:6a4db94011d3 1111 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
sahilmgandhi 18:6a4db94011d3 1112 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1113 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1114 #define CMU_IFS_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Set */
sahilmgandhi 18:6a4db94011d3 1115 #define _CMU_IFS_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1116 #define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1117 #define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1118 #define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFS */
sahilmgandhi 18:6a4db94011d3 1119
sahilmgandhi 18:6a4db94011d3 1120 /* Bit fields for CMU IFC */
sahilmgandhi 18:6a4db94011d3 1121 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1122 #define _CMU_IFC_MASK 0x000000FFUL /**< Mask for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1123 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
sahilmgandhi 18:6a4db94011d3 1124 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 1125 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 1126 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1127 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1128 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
sahilmgandhi 18:6a4db94011d3 1129 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 1130 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 1131 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1132 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1133 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
sahilmgandhi 18:6a4db94011d3 1134 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 1135 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 1136 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1137 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1138 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
sahilmgandhi 18:6a4db94011d3 1139 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 1140 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 1141 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1142 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1143 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
sahilmgandhi 18:6a4db94011d3 1144 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 1145 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 1146 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1147 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1148 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
sahilmgandhi 18:6a4db94011d3 1149 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
sahilmgandhi 18:6a4db94011d3 1150 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
sahilmgandhi 18:6a4db94011d3 1151 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1152 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1153 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
sahilmgandhi 18:6a4db94011d3 1154 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
sahilmgandhi 18:6a4db94011d3 1155 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
sahilmgandhi 18:6a4db94011d3 1156 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1157 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1158 #define CMU_IFC_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Flag Clear */
sahilmgandhi 18:6a4db94011d3 1159 #define _CMU_IFC_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1160 #define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1161 #define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1162 #define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IFC */
sahilmgandhi 18:6a4db94011d3 1163
sahilmgandhi 18:6a4db94011d3 1164 /* Bit fields for CMU IEN */
sahilmgandhi 18:6a4db94011d3 1165 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1166 #define _CMU_IEN_MASK 0x000000FFUL /**< Mask for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1167 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1168 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 1169 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
sahilmgandhi 18:6a4db94011d3 1170 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1171 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1172 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1173 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 1174 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
sahilmgandhi 18:6a4db94011d3 1175 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1176 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1177 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1178 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 1179 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
sahilmgandhi 18:6a4db94011d3 1180 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1181 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1182 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1183 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 1184 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
sahilmgandhi 18:6a4db94011d3 1185 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1186 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1187 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1188 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 1189 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
sahilmgandhi 18:6a4db94011d3 1190 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1191 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1192 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1193 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
sahilmgandhi 18:6a4db94011d3 1194 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
sahilmgandhi 18:6a4db94011d3 1195 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1196 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1197 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1198 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
sahilmgandhi 18:6a4db94011d3 1199 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
sahilmgandhi 18:6a4db94011d3 1200 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1201 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1202 #define CMU_IEN_USBCHFCLKSEL (0x1UL << 7) /**< USBC HFCLK Selected Interrupt Enable */
sahilmgandhi 18:6a4db94011d3 1203 #define _CMU_IEN_USBCHFCLKSEL_SHIFT 7 /**< Shift value for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1204 #define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL /**< Bit mask for CMU_USBCHFCLKSEL */
sahilmgandhi 18:6a4db94011d3 1205 #define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1206 #define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_IEN */
sahilmgandhi 18:6a4db94011d3 1207
sahilmgandhi 18:6a4db94011d3 1208 /* Bit fields for CMU HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1209 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1210 #define _CMU_HFCORECLKEN0_MASK 0x0000003FUL /**< Mask for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1211 #define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */
sahilmgandhi 18:6a4db94011d3 1212 #define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */
sahilmgandhi 18:6a4db94011d3 1213 #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */
sahilmgandhi 18:6a4db94011d3 1214 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1215 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1216 #define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */
sahilmgandhi 18:6a4db94011d3 1217 #define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */
sahilmgandhi 18:6a4db94011d3 1218 #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */
sahilmgandhi 18:6a4db94011d3 1219 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1220 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1221 #define CMU_HFCORECLKEN0_USBC (0x1UL << 2) /**< Universal Serial Bus Interface Core Clock Enable */
sahilmgandhi 18:6a4db94011d3 1222 #define _CMU_HFCORECLKEN0_USBC_SHIFT 2 /**< Shift value for CMU_USBC */
sahilmgandhi 18:6a4db94011d3 1223 #define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL /**< Bit mask for CMU_USBC */
sahilmgandhi 18:6a4db94011d3 1224 #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1225 #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1226 #define CMU_HFCORECLKEN0_USB (0x1UL << 3) /**< Universal Serial Bus Interface Clock Enable */
sahilmgandhi 18:6a4db94011d3 1227 #define _CMU_HFCORECLKEN0_USB_SHIFT 3 /**< Shift value for CMU_USB */
sahilmgandhi 18:6a4db94011d3 1228 #define _CMU_HFCORECLKEN0_USB_MASK 0x8UL /**< Bit mask for CMU_USB */
sahilmgandhi 18:6a4db94011d3 1229 #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1230 #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1231 #define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */
sahilmgandhi 18:6a4db94011d3 1232 #define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */
sahilmgandhi 18:6a4db94011d3 1233 #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */
sahilmgandhi 18:6a4db94011d3 1234 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1235 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1236 #define CMU_HFCORECLKEN0_EBI (0x1UL << 5) /**< External Bus Interface Clock Enable */
sahilmgandhi 18:6a4db94011d3 1237 #define _CMU_HFCORECLKEN0_EBI_SHIFT 5 /**< Shift value for CMU_EBI */
sahilmgandhi 18:6a4db94011d3 1238 #define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL /**< Bit mask for CMU_EBI */
sahilmgandhi 18:6a4db94011d3 1239 #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1240 #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
sahilmgandhi 18:6a4db94011d3 1241
sahilmgandhi 18:6a4db94011d3 1242 /* Bit fields for CMU HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1243 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1244 #define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL /**< Mask for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1245 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1246 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */
sahilmgandhi 18:6a4db94011d3 1247 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */
sahilmgandhi 18:6a4db94011d3 1248 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1249 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1250 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1251 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */
sahilmgandhi 18:6a4db94011d3 1252 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */
sahilmgandhi 18:6a4db94011d3 1253 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1254 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1255 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1256 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */
sahilmgandhi 18:6a4db94011d3 1257 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */
sahilmgandhi 18:6a4db94011d3 1258 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1259 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1260 #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3) /**< Universal Asynchronous Receiver/Transmitter 0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1261 #define _CMU_HFPERCLKEN0_UART0_SHIFT 3 /**< Shift value for CMU_UART0 */
sahilmgandhi 18:6a4db94011d3 1262 #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL /**< Bit mask for CMU_UART0 */
sahilmgandhi 18:6a4db94011d3 1263 #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1264 #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1265 #define CMU_HFPERCLKEN0_UART1 (0x1UL << 4) /**< Universal Asynchronous Receiver/Transmitter 1 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1266 #define _CMU_HFPERCLKEN0_UART1_SHIFT 4 /**< Shift value for CMU_UART1 */
sahilmgandhi 18:6a4db94011d3 1267 #define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL /**< Bit mask for CMU_UART1 */
sahilmgandhi 18:6a4db94011d3 1268 #define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1269 #define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1270 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1271 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */
sahilmgandhi 18:6a4db94011d3 1272 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */
sahilmgandhi 18:6a4db94011d3 1273 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1274 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1275 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1276 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */
sahilmgandhi 18:6a4db94011d3 1277 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */
sahilmgandhi 18:6a4db94011d3 1278 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1279 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1280 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1281 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */
sahilmgandhi 18:6a4db94011d3 1282 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */
sahilmgandhi 18:6a4db94011d3 1283 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1284 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1285 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1286 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */
sahilmgandhi 18:6a4db94011d3 1287 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */
sahilmgandhi 18:6a4db94011d3 1288 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1289 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1290 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1291 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */
sahilmgandhi 18:6a4db94011d3 1292 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */
sahilmgandhi 18:6a4db94011d3 1293 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1294 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1295 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1296 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */
sahilmgandhi 18:6a4db94011d3 1297 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */
sahilmgandhi 18:6a4db94011d3 1298 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1299 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1300 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1301 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
sahilmgandhi 18:6a4db94011d3 1302 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
sahilmgandhi 18:6a4db94011d3 1303 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1304 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1305 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1306 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */
sahilmgandhi 18:6a4db94011d3 1307 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */
sahilmgandhi 18:6a4db94011d3 1308 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1309 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1310 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */
sahilmgandhi 18:6a4db94011d3 1311 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */
sahilmgandhi 18:6a4db94011d3 1312 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */
sahilmgandhi 18:6a4db94011d3 1313 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1314 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1315 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */
sahilmgandhi 18:6a4db94011d3 1316 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */
sahilmgandhi 18:6a4db94011d3 1317 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */
sahilmgandhi 18:6a4db94011d3 1318 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1319 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1320 #define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */
sahilmgandhi 18:6a4db94011d3 1321 #define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */
sahilmgandhi 18:6a4db94011d3 1322 #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */
sahilmgandhi 18:6a4db94011d3 1323 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1324 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1325 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1326 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */
sahilmgandhi 18:6a4db94011d3 1327 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */
sahilmgandhi 18:6a4db94011d3 1328 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1329 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1330 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1331 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */
sahilmgandhi 18:6a4db94011d3 1332 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */
sahilmgandhi 18:6a4db94011d3 1333 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1334 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1335
sahilmgandhi 18:6a4db94011d3 1336 /* Bit fields for CMU SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1337 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1338 #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1339 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
sahilmgandhi 18:6a4db94011d3 1340 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1341 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1342 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1343 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1344 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
sahilmgandhi 18:6a4db94011d3 1345 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1346 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1347 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1348 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1349 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
sahilmgandhi 18:6a4db94011d3 1350 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1351 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1352 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1353 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1354 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
sahilmgandhi 18:6a4db94011d3 1355 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1356 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1357 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1358 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
sahilmgandhi 18:6a4db94011d3 1359
sahilmgandhi 18:6a4db94011d3 1360 /* Bit fields for CMU FREEZE */
sahilmgandhi 18:6a4db94011d3 1361 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
sahilmgandhi 18:6a4db94011d3 1362 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
sahilmgandhi 18:6a4db94011d3 1363 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
sahilmgandhi 18:6a4db94011d3 1364 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
sahilmgandhi 18:6a4db94011d3 1365 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
sahilmgandhi 18:6a4db94011d3 1366 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
sahilmgandhi 18:6a4db94011d3 1367 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
sahilmgandhi 18:6a4db94011d3 1368 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
sahilmgandhi 18:6a4db94011d3 1369 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
sahilmgandhi 18:6a4db94011d3 1370 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
sahilmgandhi 18:6a4db94011d3 1371 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
sahilmgandhi 18:6a4db94011d3 1372
sahilmgandhi 18:6a4db94011d3 1373 /* Bit fields for CMU LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1374 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1375 #define _CMU_LFACLKEN0_MASK 0x00000007UL /**< Mask for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1376 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */
sahilmgandhi 18:6a4db94011d3 1377 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
sahilmgandhi 18:6a4db94011d3 1378 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */
sahilmgandhi 18:6a4db94011d3 1379 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1380 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1381 #define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */
sahilmgandhi 18:6a4db94011d3 1382 #define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */
sahilmgandhi 18:6a4db94011d3 1383 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */
sahilmgandhi 18:6a4db94011d3 1384 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1385 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1386 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1387 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */
sahilmgandhi 18:6a4db94011d3 1388 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */
sahilmgandhi 18:6a4db94011d3 1389 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1390 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
sahilmgandhi 18:6a4db94011d3 1391
sahilmgandhi 18:6a4db94011d3 1392 /* Bit fields for CMU LFBCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1393 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1394 #define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1395 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1396 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
sahilmgandhi 18:6a4db94011d3 1397 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
sahilmgandhi 18:6a4db94011d3 1398 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1399 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1400 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1401 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */
sahilmgandhi 18:6a4db94011d3 1402 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */
sahilmgandhi 18:6a4db94011d3 1403 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1404 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
sahilmgandhi 18:6a4db94011d3 1405
sahilmgandhi 18:6a4db94011d3 1406 /* Bit fields for CMU LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1407 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1408 #define _CMU_LFAPRESC0_MASK 0x00000FF3UL /**< Mask for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1409 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
sahilmgandhi 18:6a4db94011d3 1410 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */
sahilmgandhi 18:6a4db94011d3 1411 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1412 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1413 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1414 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1415 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1416 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1417 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1418 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1419 #define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */
sahilmgandhi 18:6a4db94011d3 1420 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */
sahilmgandhi 18:6a4db94011d3 1421 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1422 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1423 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1424 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1425 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1426 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1427 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1428 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1429 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1430 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1431 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1432 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1433 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1434 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1435 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1436 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1437 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1438 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1439 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1440 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1441 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1442 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1443 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1444 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1445 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1446 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1447 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1448 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1449 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1450 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1451 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1452 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1453 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */
sahilmgandhi 18:6a4db94011d3 1454 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */
sahilmgandhi 18:6a4db94011d3 1455 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1456 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1457 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1458 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1459 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1460 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1461 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1462 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1463 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1464 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1465 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1466 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1467 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1468 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1469 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1470 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1471 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1472 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1473 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1474 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1475 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1476 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1477 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1478 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1479 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1480 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1481 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1482 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1483 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1484 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1485 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1486 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
sahilmgandhi 18:6a4db94011d3 1487
sahilmgandhi 18:6a4db94011d3 1488 /* Bit fields for CMU LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1489 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1490 #define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1491 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
sahilmgandhi 18:6a4db94011d3 1492 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
sahilmgandhi 18:6a4db94011d3 1493 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1494 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1495 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1496 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1497 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1498 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1499 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1500 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1501 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */
sahilmgandhi 18:6a4db94011d3 1502 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */
sahilmgandhi 18:6a4db94011d3 1503 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1504 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1505 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1506 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1507 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1508 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1509 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1510 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
sahilmgandhi 18:6a4db94011d3 1511
sahilmgandhi 18:6a4db94011d3 1512 /* Bit fields for CMU PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1513 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1514 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1515 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1516 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
sahilmgandhi 18:6a4db94011d3 1517 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
sahilmgandhi 18:6a4db94011d3 1518 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1519 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1520 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
sahilmgandhi 18:6a4db94011d3 1521 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
sahilmgandhi 18:6a4db94011d3 1522 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
sahilmgandhi 18:6a4db94011d3 1523 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1524 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1525 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1526 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1527 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1528 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1529 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1530 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */
sahilmgandhi 18:6a4db94011d3 1531 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */
sahilmgandhi 18:6a4db94011d3 1532 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1533 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1534 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */
sahilmgandhi 18:6a4db94011d3 1535 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */
sahilmgandhi 18:6a4db94011d3 1536 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */
sahilmgandhi 18:6a4db94011d3 1537 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1538 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1539 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1540 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1541 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1542 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1543 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */
sahilmgandhi 18:6a4db94011d3 1544 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */
sahilmgandhi 18:6a4db94011d3 1545 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */
sahilmgandhi 18:6a4db94011d3 1546 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1547 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1548 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */
sahilmgandhi 18:6a4db94011d3 1549 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */
sahilmgandhi 18:6a4db94011d3 1550 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */
sahilmgandhi 18:6a4db94011d3 1551 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1552 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1553 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1554 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1555 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1556 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
sahilmgandhi 18:6a4db94011d3 1557
sahilmgandhi 18:6a4db94011d3 1558 /* Bit fields for CMU ROUTE */
sahilmgandhi 18:6a4db94011d3 1559 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1560 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1561 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
sahilmgandhi 18:6a4db94011d3 1562 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
sahilmgandhi 18:6a4db94011d3 1563 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
sahilmgandhi 18:6a4db94011d3 1564 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1565 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1566 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
sahilmgandhi 18:6a4db94011d3 1567 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
sahilmgandhi 18:6a4db94011d3 1568 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
sahilmgandhi 18:6a4db94011d3 1569 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1570 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1571 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
sahilmgandhi 18:6a4db94011d3 1572 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
sahilmgandhi 18:6a4db94011d3 1573 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1574 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1575 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1576 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1577 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1578 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1579 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1580 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
sahilmgandhi 18:6a4db94011d3 1581
sahilmgandhi 18:6a4db94011d3 1582 /* Bit fields for CMU LOCK */
sahilmgandhi 18:6a4db94011d3 1583 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1584 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1585 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 1586 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
sahilmgandhi 18:6a4db94011d3 1587 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1588 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1589 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1590 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1591 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1592 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1593 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1594 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1595 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1596 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
sahilmgandhi 18:6a4db94011d3 1597
sahilmgandhi 18:6a4db94011d3 1598 /** @} End of group EFM32GG380F1024_CMU */
sahilmgandhi 18:6a4db94011d3 1599
sahilmgandhi 18:6a4db94011d3 1600
sahilmgandhi 18:6a4db94011d3 1601
sahilmgandhi 18:6a4db94011d3 1602 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 1603 * @defgroup EFM32GG380F1024_UNLOCK EFM32GG380F1024 Unlock Codes
sahilmgandhi 18:6a4db94011d3 1604 * @{
sahilmgandhi 18:6a4db94011d3 1605 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 1606 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
sahilmgandhi 18:6a4db94011d3 1607 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
sahilmgandhi 18:6a4db94011d3 1608 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
sahilmgandhi 18:6a4db94011d3 1609 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
sahilmgandhi 18:6a4db94011d3 1610 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
sahilmgandhi 18:6a4db94011d3 1611 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
sahilmgandhi 18:6a4db94011d3 1612
sahilmgandhi 18:6a4db94011d3 1613 /** @} End of group EFM32GG380F1024_UNLOCK */
sahilmgandhi 18:6a4db94011d3 1614
sahilmgandhi 18:6a4db94011d3 1615 /** @} End of group EFM32GG380F1024_BitFields */
sahilmgandhi 18:6a4db94011d3 1616
sahilmgandhi 18:6a4db94011d3 1617 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 1618 * @defgroup EFM32GG380F1024_Alternate_Function EFM32GG380F1024 Alternate Function
sahilmgandhi 18:6a4db94011d3 1619 * @{
sahilmgandhi 18:6a4db94011d3 1620 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 1621
sahilmgandhi 18:6a4db94011d3 1622 #include "efm32gg_af_ports.h"
sahilmgandhi 18:6a4db94011d3 1623 #include "efm32gg_af_pins.h"
sahilmgandhi 18:6a4db94011d3 1624
sahilmgandhi 18:6a4db94011d3 1625 /** @} End of group EFM32GG380F1024_Alternate_Function */
sahilmgandhi 18:6a4db94011d3 1626
sahilmgandhi 18:6a4db94011d3 1627 /**************************************************************************//**
sahilmgandhi 18:6a4db94011d3 1628 * @brief Set the value of a bit field within a register.
sahilmgandhi 18:6a4db94011d3 1629 *
sahilmgandhi 18:6a4db94011d3 1630 * @param REG
sahilmgandhi 18:6a4db94011d3 1631 * The register to update
sahilmgandhi 18:6a4db94011d3 1632 * @param MASK
sahilmgandhi 18:6a4db94011d3 1633 * The mask for the bit field to update
sahilmgandhi 18:6a4db94011d3 1634 * @param VALUE
sahilmgandhi 18:6a4db94011d3 1635 * The value to write to the bit field
sahilmgandhi 18:6a4db94011d3 1636 * @param OFFSET
sahilmgandhi 18:6a4db94011d3 1637 * The number of bits that the field is offset within the register.
sahilmgandhi 18:6a4db94011d3 1638 * 0 (zero) means LSB.
sahilmgandhi 18:6a4db94011d3 1639 *****************************************************************************/
sahilmgandhi 18:6a4db94011d3 1640 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
sahilmgandhi 18:6a4db94011d3 1641 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
sahilmgandhi 18:6a4db94011d3 1642
sahilmgandhi 18:6a4db94011d3 1643 /** @} End of group EFM32GG380F1024 */
sahilmgandhi 18:6a4db94011d3 1644
sahilmgandhi 18:6a4db94011d3 1645 /** @} End of group Parts */
sahilmgandhi 18:6a4db94011d3 1646
sahilmgandhi 18:6a4db94011d3 1647 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 1648 }
sahilmgandhi 18:6a4db94011d3 1649 #endif
sahilmgandhi 18:6a4db94011d3 1650 #endif /* EFM32GG380F1024_H */