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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_dma.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32l0xx_ll_dma.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.7.0
sahilmgandhi 18:6a4db94011d3 6 * @date 31-May-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief DMA LL module driver.
sahilmgandhi 18:6a4db94011d3 8 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 9 * @attention
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 12 *
sahilmgandhi 18:6a4db94011d3 13 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 14 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 15 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 16 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 18 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 19 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 21 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 22 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 23 *
sahilmgandhi 18:6a4db94011d3 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 34 *
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 36 */
sahilmgandhi 18:6a4db94011d3 37 #if defined(USE_FULL_LL_DRIVER)
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 40 #include "stm32l0xx_ll_dma.h"
sahilmgandhi 18:6a4db94011d3 41 #include "stm32l0xx_ll_bus.h"
sahilmgandhi 18:6a4db94011d3 42 #ifdef USE_FULL_ASSERT
sahilmgandhi 18:6a4db94011d3 43 #include "stm32_assert.h"
sahilmgandhi 18:6a4db94011d3 44 #else
sahilmgandhi 18:6a4db94011d3 45 #define assert_param(expr) ((void)0U)
sahilmgandhi 18:6a4db94011d3 46 #endif
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 /** @addtogroup STM32L0xx_LL_Driver
sahilmgandhi 18:6a4db94011d3 49 * @{
sahilmgandhi 18:6a4db94011d3 50 */
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 #if defined (DMA1)
sahilmgandhi 18:6a4db94011d3 53
sahilmgandhi 18:6a4db94011d3 54 /** @defgroup DMA_LL DMA
sahilmgandhi 18:6a4db94011d3 55 * @{
sahilmgandhi 18:6a4db94011d3 56 */
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 /* Private types -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 59 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 60 /* Private constants ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 61 /* Private macros ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 62 /** @addtogroup DMA_LL_Private_Macros
sahilmgandhi 18:6a4db94011d3 63 * @{
sahilmgandhi 18:6a4db94011d3 64 */
sahilmgandhi 18:6a4db94011d3 65 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
sahilmgandhi 18:6a4db94011d3 66 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
sahilmgandhi 18:6a4db94011d3 67 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
sahilmgandhi 18:6a4db94011d3 70 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
sahilmgandhi 18:6a4db94011d3 71
sahilmgandhi 18:6a4db94011d3 72 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
sahilmgandhi 18:6a4db94011d3 73 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
sahilmgandhi 18:6a4db94011d3 76 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
sahilmgandhi 18:6a4db94011d3 79 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
sahilmgandhi 18:6a4db94011d3 80 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
sahilmgandhi 18:6a4db94011d3 81
sahilmgandhi 18:6a4db94011d3 82 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
sahilmgandhi 18:6a4db94011d3 83 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
sahilmgandhi 18:6a4db94011d3 84 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
sahilmgandhi 18:6a4db94011d3 85
sahilmgandhi 18:6a4db94011d3 86 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \
sahilmgandhi 18:6a4db94011d3 89 ((__VALUE__) == LL_DMA_REQUEST_1) || \
sahilmgandhi 18:6a4db94011d3 90 ((__VALUE__) == LL_DMA_REQUEST_2) || \
sahilmgandhi 18:6a4db94011d3 91 ((__VALUE__) == LL_DMA_REQUEST_3) || \
sahilmgandhi 18:6a4db94011d3 92 ((__VALUE__) == LL_DMA_REQUEST_4) || \
sahilmgandhi 18:6a4db94011d3 93 ((__VALUE__) == LL_DMA_REQUEST_5) || \
sahilmgandhi 18:6a4db94011d3 94 ((__VALUE__) == LL_DMA_REQUEST_6) || \
sahilmgandhi 18:6a4db94011d3 95 ((__VALUE__) == LL_DMA_REQUEST_7) || \
sahilmgandhi 18:6a4db94011d3 96 ((__VALUE__) == LL_DMA_REQUEST_8) || \
sahilmgandhi 18:6a4db94011d3 97 ((__VALUE__) == LL_DMA_REQUEST_9) || \
sahilmgandhi 18:6a4db94011d3 98 ((__VALUE__) == LL_DMA_REQUEST_10) || \
sahilmgandhi 18:6a4db94011d3 99 ((__VALUE__) == LL_DMA_REQUEST_11) || \
sahilmgandhi 18:6a4db94011d3 100 ((__VALUE__) == LL_DMA_REQUEST_12) || \
sahilmgandhi 18:6a4db94011d3 101 ((__VALUE__) == LL_DMA_REQUEST_13) || \
sahilmgandhi 18:6a4db94011d3 102 ((__VALUE__) == LL_DMA_REQUEST_14) || \
sahilmgandhi 18:6a4db94011d3 103 ((__VALUE__) == LL_DMA_REQUEST_15))
sahilmgandhi 18:6a4db94011d3 104
sahilmgandhi 18:6a4db94011d3 105 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
sahilmgandhi 18:6a4db94011d3 106 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
sahilmgandhi 18:6a4db94011d3 107 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
sahilmgandhi 18:6a4db94011d3 108 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
sahilmgandhi 18:6a4db94011d3 109
sahilmgandhi 18:6a4db94011d3 110 #if defined (DMA1_Channel6) && defined (DMA1_Channel7)
sahilmgandhi 18:6a4db94011d3 111 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
sahilmgandhi 18:6a4db94011d3 112 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
sahilmgandhi 18:6a4db94011d3 113 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 114 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 115 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
sahilmgandhi 18:6a4db94011d3 116 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
sahilmgandhi 18:6a4db94011d3 117 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
sahilmgandhi 18:6a4db94011d3 118 ((CHANNEL) == LL_DMA_CHANNEL_7))))
sahilmgandhi 18:6a4db94011d3 119 #elif defined (DMA1_Channel6)
sahilmgandhi 18:6a4db94011d3 120 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
sahilmgandhi 18:6a4db94011d3 121 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
sahilmgandhi 18:6a4db94011d3 122 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 123 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 124 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
sahilmgandhi 18:6a4db94011d3 125 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
sahilmgandhi 18:6a4db94011d3 126 ((CHANNEL) == LL_DMA_CHANNEL_6))))
sahilmgandhi 18:6a4db94011d3 127 #else
sahilmgandhi 18:6a4db94011d3 128 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
sahilmgandhi 18:6a4db94011d3 129 (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
sahilmgandhi 18:6a4db94011d3 130 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
sahilmgandhi 18:6a4db94011d3 131 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
sahilmgandhi 18:6a4db94011d3 132 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
sahilmgandhi 18:6a4db94011d3 133 ((CHANNEL) == LL_DMA_CHANNEL_5))))
sahilmgandhi 18:6a4db94011d3 134 #endif /* DMA1_Channel6 && DMA1_Channel7 */
sahilmgandhi 18:6a4db94011d3 135 /**
sahilmgandhi 18:6a4db94011d3 136 * @}
sahilmgandhi 18:6a4db94011d3 137 */
sahilmgandhi 18:6a4db94011d3 138
sahilmgandhi 18:6a4db94011d3 139 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /* Exported functions --------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 142 /** @addtogroup DMA_LL_Exported_Functions
sahilmgandhi 18:6a4db94011d3 143 * @{
sahilmgandhi 18:6a4db94011d3 144 */
sahilmgandhi 18:6a4db94011d3 145
sahilmgandhi 18:6a4db94011d3 146 /** @addtogroup DMA_LL_EF_Init
sahilmgandhi 18:6a4db94011d3 147 * @{
sahilmgandhi 18:6a4db94011d3 148 */
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 /**
sahilmgandhi 18:6a4db94011d3 151 * @brief De-initialize the DMA registers to their default reset values.
sahilmgandhi 18:6a4db94011d3 152 * @param DMAx DMAx Instance
sahilmgandhi 18:6a4db94011d3 153 * @param Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 154 * @arg @ref LL_DMA_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 155 * @arg @ref LL_DMA_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 156 * @arg @ref LL_DMA_CHANNEL_3
sahilmgandhi 18:6a4db94011d3 157 * @arg @ref LL_DMA_CHANNEL_4
sahilmgandhi 18:6a4db94011d3 158 * @arg @ref LL_DMA_CHANNEL_5
sahilmgandhi 18:6a4db94011d3 159 * @arg @ref LL_DMA_CHANNEL_6 (*)
sahilmgandhi 18:6a4db94011d3 160 * @arg @ref LL_DMA_CHANNEL_7 (*)
sahilmgandhi 18:6a4db94011d3 161 * @arg @ref LL_DMA_CHANNEL_ALL
sahilmgandhi 18:6a4db94011d3 162 *
sahilmgandhi 18:6a4db94011d3 163 * (*) value not defined in all devices
sahilmgandhi 18:6a4db94011d3 164 * @retval An ErrorStatus enumeration value:
sahilmgandhi 18:6a4db94011d3 165 * - SUCCESS: DMA registers are de-initialized
sahilmgandhi 18:6a4db94011d3 166 * - ERROR: DMA registers are not de-initialized
sahilmgandhi 18:6a4db94011d3 167 */
sahilmgandhi 18:6a4db94011d3 168 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
sahilmgandhi 18:6a4db94011d3 169 {
sahilmgandhi 18:6a4db94011d3 170 DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
sahilmgandhi 18:6a4db94011d3 171 ErrorStatus status = SUCCESS;
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 /* Check the DMA Instance DMAx and Channel parameters*/
sahilmgandhi 18:6a4db94011d3 174 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 if (Channel == LL_DMA_CHANNEL_ALL)
sahilmgandhi 18:6a4db94011d3 177 {
sahilmgandhi 18:6a4db94011d3 178 if (DMAx == DMA1)
sahilmgandhi 18:6a4db94011d3 179 {
sahilmgandhi 18:6a4db94011d3 180 /* Force reset of DMA clock */
sahilmgandhi 18:6a4db94011d3 181 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 /* Release reset of DMA clock */
sahilmgandhi 18:6a4db94011d3 184 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
sahilmgandhi 18:6a4db94011d3 185 }
sahilmgandhi 18:6a4db94011d3 186 #if defined(DMA2)
sahilmgandhi 18:6a4db94011d3 187 else if (DMAx == DMA2)
sahilmgandhi 18:6a4db94011d3 188 {
sahilmgandhi 18:6a4db94011d3 189 /* Force reset of DMA clock */
sahilmgandhi 18:6a4db94011d3 190 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 /* Release reset of DMA clock */
sahilmgandhi 18:6a4db94011d3 193 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
sahilmgandhi 18:6a4db94011d3 194 }
sahilmgandhi 18:6a4db94011d3 195 #endif
sahilmgandhi 18:6a4db94011d3 196 else
sahilmgandhi 18:6a4db94011d3 197 {
sahilmgandhi 18:6a4db94011d3 198 status = ERROR;
sahilmgandhi 18:6a4db94011d3 199 }
sahilmgandhi 18:6a4db94011d3 200 }
sahilmgandhi 18:6a4db94011d3 201 else
sahilmgandhi 18:6a4db94011d3 202 {
sahilmgandhi 18:6a4db94011d3 203 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 /* Disable the selected DMAx_Channely */
sahilmgandhi 18:6a4db94011d3 206 CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
sahilmgandhi 18:6a4db94011d3 207
sahilmgandhi 18:6a4db94011d3 208 /* Reset DMAx_Channely control register */
sahilmgandhi 18:6a4db94011d3 209 LL_DMA_WriteReg(tmp, CCR, 0U);
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 /* Reset DMAx_Channely remaining bytes register */
sahilmgandhi 18:6a4db94011d3 212 LL_DMA_WriteReg(tmp, CNDTR, 0U);
sahilmgandhi 18:6a4db94011d3 213
sahilmgandhi 18:6a4db94011d3 214 /* Reset DMAx_Channely peripheral address register */
sahilmgandhi 18:6a4db94011d3 215 LL_DMA_WriteReg(tmp, CPAR, 0U);
sahilmgandhi 18:6a4db94011d3 216
sahilmgandhi 18:6a4db94011d3 217 /* Reset DMAx_Channely memory address register */
sahilmgandhi 18:6a4db94011d3 218 LL_DMA_WriteReg(tmp, CMAR, 0U);
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 /* Reset Request register field for DMAx Channel */
sahilmgandhi 18:6a4db94011d3 221 LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 if (Channel == LL_DMA_CHANNEL_1)
sahilmgandhi 18:6a4db94011d3 224 {
sahilmgandhi 18:6a4db94011d3 225 /* Reset interrupt pending bits for DMAx Channel1 */
sahilmgandhi 18:6a4db94011d3 226 LL_DMA_ClearFlag_GI1(DMAx);
sahilmgandhi 18:6a4db94011d3 227 }
sahilmgandhi 18:6a4db94011d3 228 else if (Channel == LL_DMA_CHANNEL_2)
sahilmgandhi 18:6a4db94011d3 229 {
sahilmgandhi 18:6a4db94011d3 230 /* Reset interrupt pending bits for DMAx Channel2 */
sahilmgandhi 18:6a4db94011d3 231 LL_DMA_ClearFlag_GI2(DMAx);
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233 else if (Channel == LL_DMA_CHANNEL_3)
sahilmgandhi 18:6a4db94011d3 234 {
sahilmgandhi 18:6a4db94011d3 235 /* Reset interrupt pending bits for DMAx Channel3 */
sahilmgandhi 18:6a4db94011d3 236 LL_DMA_ClearFlag_GI3(DMAx);
sahilmgandhi 18:6a4db94011d3 237 }
sahilmgandhi 18:6a4db94011d3 238 else if (Channel == LL_DMA_CHANNEL_4)
sahilmgandhi 18:6a4db94011d3 239 {
sahilmgandhi 18:6a4db94011d3 240 /* Reset interrupt pending bits for DMAx Channel4 */
sahilmgandhi 18:6a4db94011d3 241 LL_DMA_ClearFlag_GI4(DMAx);
sahilmgandhi 18:6a4db94011d3 242 }
sahilmgandhi 18:6a4db94011d3 243 else if (Channel == LL_DMA_CHANNEL_5)
sahilmgandhi 18:6a4db94011d3 244 {
sahilmgandhi 18:6a4db94011d3 245 /* Reset interrupt pending bits for DMAx Channel5 */
sahilmgandhi 18:6a4db94011d3 246 LL_DMA_ClearFlag_GI5(DMAx);
sahilmgandhi 18:6a4db94011d3 247 }
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 #if defined(DMA1_Channel6)
sahilmgandhi 18:6a4db94011d3 250 else if (Channel == LL_DMA_CHANNEL_6)
sahilmgandhi 18:6a4db94011d3 251 {
sahilmgandhi 18:6a4db94011d3 252 /* Reset interrupt pending bits for DMAx Channel6 */
sahilmgandhi 18:6a4db94011d3 253 LL_DMA_ClearFlag_GI6(DMAx);
sahilmgandhi 18:6a4db94011d3 254 }
sahilmgandhi 18:6a4db94011d3 255 #endif
sahilmgandhi 18:6a4db94011d3 256 #if defined(DMA1_Channel7)
sahilmgandhi 18:6a4db94011d3 257 else if (Channel == LL_DMA_CHANNEL_7)
sahilmgandhi 18:6a4db94011d3 258 {
sahilmgandhi 18:6a4db94011d3 259 /* Reset interrupt pending bits for DMAx Channel7 */
sahilmgandhi 18:6a4db94011d3 260 LL_DMA_ClearFlag_GI7(DMAx);
sahilmgandhi 18:6a4db94011d3 261 }
sahilmgandhi 18:6a4db94011d3 262 #endif
sahilmgandhi 18:6a4db94011d3 263 else
sahilmgandhi 18:6a4db94011d3 264 {
sahilmgandhi 18:6a4db94011d3 265 status = ERROR;
sahilmgandhi 18:6a4db94011d3 266 }
sahilmgandhi 18:6a4db94011d3 267 }
sahilmgandhi 18:6a4db94011d3 268
sahilmgandhi 18:6a4db94011d3 269 return status;
sahilmgandhi 18:6a4db94011d3 270 }
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /**
sahilmgandhi 18:6a4db94011d3 273 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
sahilmgandhi 18:6a4db94011d3 274 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
sahilmgandhi 18:6a4db94011d3 275 * @arg @ref __LL_DMA_GET_INSTANCE
sahilmgandhi 18:6a4db94011d3 276 * @arg @ref __LL_DMA_GET_CHANNEL
sahilmgandhi 18:6a4db94011d3 277 * @param DMAx DMAx Instance
sahilmgandhi 18:6a4db94011d3 278 * @param Channel This parameter can be one of the following values:
sahilmgandhi 18:6a4db94011d3 279 * @arg @ref LL_DMA_CHANNEL_1
sahilmgandhi 18:6a4db94011d3 280 * @arg @ref LL_DMA_CHANNEL_2
sahilmgandhi 18:6a4db94011d3 281 * @arg @ref LL_DMA_CHANNEL_3
sahilmgandhi 18:6a4db94011d3 282 * @arg @ref LL_DMA_CHANNEL_4
sahilmgandhi 18:6a4db94011d3 283 * @arg @ref LL_DMA_CHANNEL_5
sahilmgandhi 18:6a4db94011d3 284 * @arg @ref LL_DMA_CHANNEL_6 (*)
sahilmgandhi 18:6a4db94011d3 285 * @arg @ref LL_DMA_CHANNEL_7 (*)
sahilmgandhi 18:6a4db94011d3 286 *
sahilmgandhi 18:6a4db94011d3 287 * (*) value not defined in all devices
sahilmgandhi 18:6a4db94011d3 288 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
sahilmgandhi 18:6a4db94011d3 289 * @retval An ErrorStatus enumeration value:
sahilmgandhi 18:6a4db94011d3 290 * - SUCCESS: DMA registers are initialized
sahilmgandhi 18:6a4db94011d3 291 * - ERROR: Not applicable
sahilmgandhi 18:6a4db94011d3 292 */
sahilmgandhi 18:6a4db94011d3 293 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
sahilmgandhi 18:6a4db94011d3 294 {
sahilmgandhi 18:6a4db94011d3 295 /* Check the DMA Instance DMAx and Channel parameters*/
sahilmgandhi 18:6a4db94011d3 296 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 /* Check the DMA parameters from DMA_InitStruct */
sahilmgandhi 18:6a4db94011d3 299 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
sahilmgandhi 18:6a4db94011d3 300 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
sahilmgandhi 18:6a4db94011d3 301 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
sahilmgandhi 18:6a4db94011d3 302 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
sahilmgandhi 18:6a4db94011d3 303 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
sahilmgandhi 18:6a4db94011d3 304 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
sahilmgandhi 18:6a4db94011d3 305 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
sahilmgandhi 18:6a4db94011d3 306 assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
sahilmgandhi 18:6a4db94011d3 307 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
sahilmgandhi 18:6a4db94011d3 308
sahilmgandhi 18:6a4db94011d3 309 /*---------------------------- DMAx CCR Configuration ------------------------
sahilmgandhi 18:6a4db94011d3 310 * Configure DMAx_Channely: data transfer direction, data transfer mode,
sahilmgandhi 18:6a4db94011d3 311 * peripheral and memory increment mode,
sahilmgandhi 18:6a4db94011d3 312 * data size alignment and priority level with parameters :
sahilmgandhi 18:6a4db94011d3 313 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
sahilmgandhi 18:6a4db94011d3 314 * - Mode: DMA_CCR_CIRC bit
sahilmgandhi 18:6a4db94011d3 315 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
sahilmgandhi 18:6a4db94011d3 316 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
sahilmgandhi 18:6a4db94011d3 317 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
sahilmgandhi 18:6a4db94011d3 318 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
sahilmgandhi 18:6a4db94011d3 319 * - Priority: DMA_CCR_PL[1:0] bits
sahilmgandhi 18:6a4db94011d3 320 */
sahilmgandhi 18:6a4db94011d3 321 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
sahilmgandhi 18:6a4db94011d3 322 DMA_InitStruct->Mode | \
sahilmgandhi 18:6a4db94011d3 323 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
sahilmgandhi 18:6a4db94011d3 324 DMA_InitStruct->MemoryOrM2MDstIncMode | \
sahilmgandhi 18:6a4db94011d3 325 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
sahilmgandhi 18:6a4db94011d3 326 DMA_InitStruct->MemoryOrM2MDstDataSize | \
sahilmgandhi 18:6a4db94011d3 327 DMA_InitStruct->Priority);
sahilmgandhi 18:6a4db94011d3 328
sahilmgandhi 18:6a4db94011d3 329 /*-------------------------- DMAx CMAR Configuration -------------------------
sahilmgandhi 18:6a4db94011d3 330 * Configure the memory or destination base address with parameter :
sahilmgandhi 18:6a4db94011d3 331 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
sahilmgandhi 18:6a4db94011d3 332 */
sahilmgandhi 18:6a4db94011d3 333 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 /*-------------------------- DMAx CPAR Configuration -------------------------
sahilmgandhi 18:6a4db94011d3 336 * Configure the peripheral or source base address with parameter :
sahilmgandhi 18:6a4db94011d3 337 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
sahilmgandhi 18:6a4db94011d3 338 */
sahilmgandhi 18:6a4db94011d3 339 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 /*--------------------------- DMAx CNDTR Configuration -----------------------
sahilmgandhi 18:6a4db94011d3 342 * Configure the peripheral base address with parameter :
sahilmgandhi 18:6a4db94011d3 343 * - NbData: DMA_CNDTR_NDT[15:0] bits
sahilmgandhi 18:6a4db94011d3 344 */
sahilmgandhi 18:6a4db94011d3 345 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 /*--------------------------- DMAx CSELR Configuration -----------------------
sahilmgandhi 18:6a4db94011d3 348 * Configure the peripheral base address with parameter :
sahilmgandhi 18:6a4db94011d3 349 * - PeriphRequest: DMA_CSELR[31:0] bits
sahilmgandhi 18:6a4db94011d3 350 */
sahilmgandhi 18:6a4db94011d3 351 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 return SUCCESS;
sahilmgandhi 18:6a4db94011d3 354 }
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 /**
sahilmgandhi 18:6a4db94011d3 357 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
sahilmgandhi 18:6a4db94011d3 358 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
sahilmgandhi 18:6a4db94011d3 359 * @retval None
sahilmgandhi 18:6a4db94011d3 360 */
sahilmgandhi 18:6a4db94011d3 361 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
sahilmgandhi 18:6a4db94011d3 362 {
sahilmgandhi 18:6a4db94011d3 363 /* Set DMA_InitStruct fields to default values */
sahilmgandhi 18:6a4db94011d3 364 DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U;
sahilmgandhi 18:6a4db94011d3 365 DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U;
sahilmgandhi 18:6a4db94011d3 366 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
sahilmgandhi 18:6a4db94011d3 367 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
sahilmgandhi 18:6a4db94011d3 368 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
sahilmgandhi 18:6a4db94011d3 369 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
sahilmgandhi 18:6a4db94011d3 370 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
sahilmgandhi 18:6a4db94011d3 371 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
sahilmgandhi 18:6a4db94011d3 372 DMA_InitStruct->NbData = (uint32_t)0x00000000U;
sahilmgandhi 18:6a4db94011d3 373 DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0;
sahilmgandhi 18:6a4db94011d3 374 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
sahilmgandhi 18:6a4db94011d3 375 }
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 /**
sahilmgandhi 18:6a4db94011d3 378 * @}
sahilmgandhi 18:6a4db94011d3 379 */
sahilmgandhi 18:6a4db94011d3 380
sahilmgandhi 18:6a4db94011d3 381 /**
sahilmgandhi 18:6a4db94011d3 382 * @}
sahilmgandhi 18:6a4db94011d3 383 */
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 /**
sahilmgandhi 18:6a4db94011d3 386 * @}
sahilmgandhi 18:6a4db94011d3 387 */
sahilmgandhi 18:6a4db94011d3 388
sahilmgandhi 18:6a4db94011d3 389 #endif /* DMA1 */
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 /**
sahilmgandhi 18:6a4db94011d3 392 * @}
sahilmgandhi 18:6a4db94011d3 393 */
sahilmgandhi 18:6a4db94011d3 394
sahilmgandhi 18:6a4db94011d3 395 #endif /* USE_FULL_LL_DRIVER */
sahilmgandhi 18:6a4db94011d3 396
sahilmgandhi 18:6a4db94011d3 397 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/