MacroRat / MouseCode

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_NXP/TARGET_LPC43XX/device/LPC43xx.h@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 * LPC43xx/LPC18xx MCU header
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Copyright(C) NXP Semiconductors, 2012
sahilmgandhi 18:6a4db94011d3 5 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 6 *
sahilmgandhi 18:6a4db94011d3 7 * Software that is described herein is for illustrative purposes only
sahilmgandhi 18:6a4db94011d3 8 * which provides customers with programming information regarding the
sahilmgandhi 18:6a4db94011d3 9 * LPC products. This software is supplied "AS IS" without any warranties of
sahilmgandhi 18:6a4db94011d3 10 * any kind, and NXP Semiconductors and its licensor disclaim any and
sahilmgandhi 18:6a4db94011d3 11 * all warranties, express or implied, including all implied warranties of
sahilmgandhi 18:6a4db94011d3 12 * merchantability, fitness for a particular purpose and non-infringement of
sahilmgandhi 18:6a4db94011d3 13 * intellectual property rights. NXP Semiconductors assumes no responsibility
sahilmgandhi 18:6a4db94011d3 14 * or liability for the use of the software, conveys no license or rights under any
sahilmgandhi 18:6a4db94011d3 15 * patent, copyright, mask work right, or any other intellectual property rights in
sahilmgandhi 18:6a4db94011d3 16 * or to any products. NXP Semiconductors reserves the right to make changes
sahilmgandhi 18:6a4db94011d3 17 * in the software without notification. NXP Semiconductors also makes no
sahilmgandhi 18:6a4db94011d3 18 * representation or warranty that such application will be suitable for the
sahilmgandhi 18:6a4db94011d3 19 * specified use without further testing or modification.
sahilmgandhi 18:6a4db94011d3 20 *
sahilmgandhi 18:6a4db94011d3 21 * Permission to use, copy, modify, and distribute this software and its
sahilmgandhi 18:6a4db94011d3 22 * documentation is hereby granted, under NXP Semiconductors' and its
sahilmgandhi 18:6a4db94011d3 23 * licensor's relevant copyrights in the software, without fee, provided that it
sahilmgandhi 18:6a4db94011d3 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
sahilmgandhi 18:6a4db94011d3 25 * copyright, permission, and disclaimer notice must appear in all copies of
sahilmgandhi 18:6a4db94011d3 26 * this code.
sahilmgandhi 18:6a4db94011d3 27 *
sahilmgandhi 18:6a4db94011d3 28 * Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
sahilmgandhi 18:6a4db94011d3 29 * 05/15/13 Micromint USA <support@micromint.com>
sahilmgandhi 18:6a4db94011d3 30 */
sahilmgandhi 18:6a4db94011d3 31
sahilmgandhi 18:6a4db94011d3 32 #ifndef __LPC43XX_H
sahilmgandhi 18:6a4db94011d3 33 #define __LPC43XX_H
sahilmgandhi 18:6a4db94011d3 34
sahilmgandhi 18:6a4db94011d3 35 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 36 extern "C" {
sahilmgandhi 18:6a4db94011d3 37 #endif
sahilmgandhi 18:6a4db94011d3 38
sahilmgandhi 18:6a4db94011d3 39 /* Treat __CORE_Mx as CORE_Mx */
sahilmgandhi 18:6a4db94011d3 40 #if defined(__CORTEX_M0) && !defined(CORE_M0)
sahilmgandhi 18:6a4db94011d3 41 #define CORE_M0
sahilmgandhi 18:6a4db94011d3 42 #endif
sahilmgandhi 18:6a4db94011d3 43 #if defined(__CORTEX_M3) && !defined(CORE_M3)
sahilmgandhi 18:6a4db94011d3 44 #define CORE_M3
sahilmgandhi 18:6a4db94011d3 45 #endif
sahilmgandhi 18:6a4db94011d3 46 /* Default to M4 core if no core explicitly declared */
sahilmgandhi 18:6a4db94011d3 47 #if !defined(CORE_M0) && !defined(CORE_M3)
sahilmgandhi 18:6a4db94011d3 48 #define CORE_M4
sahilmgandhi 18:6a4db94011d3 49 #endif
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /* Define LPC18XX or LPC43XX according to core type */
sahilmgandhi 18:6a4db94011d3 52 #if (defined(CORE_M4) || defined(CORE_M0)) && !defined(__LPC43XX__)
sahilmgandhi 18:6a4db94011d3 53 #define __LPC43XX__
sahilmgandhi 18:6a4db94011d3 54 #endif
sahilmgandhi 18:6a4db94011d3 55 #if defined(CORE_M3) && !defined(__LPC18XX__)
sahilmgandhi 18:6a4db94011d3 56 #define __LPC18XX__
sahilmgandhi 18:6a4db94011d3 57 #endif
sahilmgandhi 18:6a4db94011d3 58
sahilmgandhi 18:6a4db94011d3 59 /* Start of section using anonymous unions */
sahilmgandhi 18:6a4db94011d3 60 #if defined(__ARMCC_VERSION)
sahilmgandhi 18:6a4db94011d3 61 // Kill warning "#pragma push with no matching #pragma pop"
sahilmgandhi 18:6a4db94011d3 62 #pragma diag_suppress 2525
sahilmgandhi 18:6a4db94011d3 63 #pragma push
sahilmgandhi 18:6a4db94011d3 64 #pragma anon_unions
sahilmgandhi 18:6a4db94011d3 65 #elif defined(__CWCC__)
sahilmgandhi 18:6a4db94011d3 66 #pragma push
sahilmgandhi 18:6a4db94011d3 67 #pragma cpp_extensions on
sahilmgandhi 18:6a4db94011d3 68 #elif defined(__IAR_SYSTEMS_ICC__)
sahilmgandhi 18:6a4db94011d3 69 //#pragma push // FIXME not usable for IAR
sahilmgandhi 18:6a4db94011d3 70 #pragma language=extended
sahilmgandhi 18:6a4db94011d3 71 #else /* defined(__GNUC__) and others */
sahilmgandhi 18:6a4db94011d3 72 /* Assume anonymous unions are enabled by default */
sahilmgandhi 18:6a4db94011d3 73 #endif
sahilmgandhi 18:6a4db94011d3 74
sahilmgandhi 18:6a4db94011d3 75 #if defined(CORE_M4)
sahilmgandhi 18:6a4db94011d3 76 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 77 * LPC43xx (M4 Core) Cortex CMSIS definitions
sahilmgandhi 18:6a4db94011d3 78 */
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 #define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
sahilmgandhi 18:6a4db94011d3 81 #define __MPU_PRESENT 1 /* MPU present or not */
sahilmgandhi 18:6a4db94011d3 82 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 83 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 84 #define __FPU_PRESENT 1 /* FPU present or not */
sahilmgandhi 18:6a4db94011d3 85 #define CHIP_LPC43XX /* LPCOPEN compatibility */
sahilmgandhi 18:6a4db94011d3 86
sahilmgandhi 18:6a4db94011d3 87 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 88 * LPC43xx peripheral interrupt numbers
sahilmgandhi 18:6a4db94011d3 89 */
sahilmgandhi 18:6a4db94011d3 90
sahilmgandhi 18:6a4db94011d3 91 typedef enum {
sahilmgandhi 18:6a4db94011d3 92 /* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
sahilmgandhi 18:6a4db94011d3 93 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
sahilmgandhi 18:6a4db94011d3 94 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
sahilmgandhi 18:6a4db94011d3 95 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
sahilmgandhi 18:6a4db94011d3 96 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
sahilmgandhi 18:6a4db94011d3 97 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
sahilmgandhi 18:6a4db94011d3 98 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
sahilmgandhi 18:6a4db94011d3 99 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
sahilmgandhi 18:6a4db94011d3 100 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
sahilmgandhi 18:6a4db94011d3 101 PendSV_IRQn = -2,/* 14 Pendable request for system service */
sahilmgandhi 18:6a4db94011d3 102 SysTick_IRQn = -1,/* 15 System Tick Timer */
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
sahilmgandhi 18:6a4db94011d3 105 DAC_IRQn = 0,/* 0 DAC */
sahilmgandhi 18:6a4db94011d3 106 M0CORE_IRQn = 1,/* 1 M0a */
sahilmgandhi 18:6a4db94011d3 107 DMA_IRQn = 2,/* 2 DMA */
sahilmgandhi 18:6a4db94011d3 108 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
sahilmgandhi 18:6a4db94011d3 109 RESERVED2_IRQn = 4,
sahilmgandhi 18:6a4db94011d3 110 ETHERNET_IRQn = 5,/* 5 ETHERNET */
sahilmgandhi 18:6a4db94011d3 111 SDIO_IRQn = 6,/* 6 SDIO */
sahilmgandhi 18:6a4db94011d3 112 LCD_IRQn = 7,/* 7 LCD */
sahilmgandhi 18:6a4db94011d3 113 USB0_IRQn = 8,/* 8 USB0 */
sahilmgandhi 18:6a4db94011d3 114 USB1_IRQn = 9,/* 9 USB1 */
sahilmgandhi 18:6a4db94011d3 115 SCT_IRQn = 10,/* 10 SCT */
sahilmgandhi 18:6a4db94011d3 116 RITIMER_IRQn = 11,/* 11 RITIMER */
sahilmgandhi 18:6a4db94011d3 117 TIMER0_IRQn = 12,/* 12 TIMER0 */
sahilmgandhi 18:6a4db94011d3 118 TIMER1_IRQn = 13,/* 13 TIMER1 */
sahilmgandhi 18:6a4db94011d3 119 TIMER2_IRQn = 14,/* 14 TIMER2 */
sahilmgandhi 18:6a4db94011d3 120 TIMER3_IRQn = 15,/* 15 TIMER3 */
sahilmgandhi 18:6a4db94011d3 121 MCPWM_IRQn = 16,/* 16 MCPWM */
sahilmgandhi 18:6a4db94011d3 122 ADC0_IRQn = 17,/* 17 ADC0 */
sahilmgandhi 18:6a4db94011d3 123 I2C0_IRQn = 18,/* 18 I2C0 */
sahilmgandhi 18:6a4db94011d3 124 I2C1_IRQn = 19,/* 19 I2C1 */
sahilmgandhi 18:6a4db94011d3 125 SPI_INT_IRQn = 20,/* 20 SPI_INT */
sahilmgandhi 18:6a4db94011d3 126 ADC1_IRQn = 21,/* 21 ADC1 */
sahilmgandhi 18:6a4db94011d3 127 SSP0_IRQn = 22,/* 22 SSP0 */
sahilmgandhi 18:6a4db94011d3 128 SSP1_IRQn = 23,/* 23 SSP1 */
sahilmgandhi 18:6a4db94011d3 129 USART0_IRQn = 24,/* 24 USART0 */
sahilmgandhi 18:6a4db94011d3 130 UART1_IRQn = 25,/* 25 UART1 */
sahilmgandhi 18:6a4db94011d3 131 USART2_IRQn = 26,/* 26 USART2 */
sahilmgandhi 18:6a4db94011d3 132 USART3_IRQn = 27,/* 27 USART3 */
sahilmgandhi 18:6a4db94011d3 133 I2S0_IRQn = 28,/* 28 I2S0 */
sahilmgandhi 18:6a4db94011d3 134 I2S1_IRQn = 29,/* 29 I2S1 */
sahilmgandhi 18:6a4db94011d3 135 RESERVED4_IRQn = 30,
sahilmgandhi 18:6a4db94011d3 136 SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
sahilmgandhi 18:6a4db94011d3 137 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
sahilmgandhi 18:6a4db94011d3 138 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
sahilmgandhi 18:6a4db94011d3 139 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
sahilmgandhi 18:6a4db94011d3 140 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
sahilmgandhi 18:6a4db94011d3 141 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
sahilmgandhi 18:6a4db94011d3 142 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
sahilmgandhi 18:6a4db94011d3 143 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
sahilmgandhi 18:6a4db94011d3 144 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
sahilmgandhi 18:6a4db94011d3 145 GINT0_IRQn = 40,/* 40 GINT0 */
sahilmgandhi 18:6a4db94011d3 146 GINT1_IRQn = 41,/* 41 GINT1 */
sahilmgandhi 18:6a4db94011d3 147 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
sahilmgandhi 18:6a4db94011d3 148 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
sahilmgandhi 18:6a4db94011d3 149 RESERVED6_IRQn = 44,
sahilmgandhi 18:6a4db94011d3 150 RESERVED7_IRQn = 45,/* 45 VADC */
sahilmgandhi 18:6a4db94011d3 151 ATIMER_IRQn = 46,/* 46 ATIMER */
sahilmgandhi 18:6a4db94011d3 152 RTC_IRQn = 47,/* 47 RTC */
sahilmgandhi 18:6a4db94011d3 153 RESERVED8_IRQn = 48,
sahilmgandhi 18:6a4db94011d3 154 WWDT_IRQn = 49,/* 49 WWDT */
sahilmgandhi 18:6a4db94011d3 155 RESERVED9_IRQn = 50,
sahilmgandhi 18:6a4db94011d3 156 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
sahilmgandhi 18:6a4db94011d3 157 QEI_IRQn = 52,/* 52 QEI */
sahilmgandhi 18:6a4db94011d3 158 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 161
sahilmgandhi 18:6a4db94011d3 162 #elif defined(CORE_M3)
sahilmgandhi 18:6a4db94011d3 163 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 164 * LPC18xx (M3 Core) Cortex CMSIS definitions
sahilmgandhi 18:6a4db94011d3 165 */
sahilmgandhi 18:6a4db94011d3 166 #define __MPU_PRESENT 1 /* MPU present or not */
sahilmgandhi 18:6a4db94011d3 167 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 168 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 169 #define __FPU_PRESENT 0 /* FPU present or not */
sahilmgandhi 18:6a4db94011d3 170 #define CHIP_LPC18XX /* LPCOPEN compatibility */
sahilmgandhi 18:6a4db94011d3 171
sahilmgandhi 18:6a4db94011d3 172 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 173 * LPC18xx peripheral interrupt numbers
sahilmgandhi 18:6a4db94011d3 174 */
sahilmgandhi 18:6a4db94011d3 175
sahilmgandhi 18:6a4db94011d3 176 typedef enum {
sahilmgandhi 18:6a4db94011d3 177 /* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
sahilmgandhi 18:6a4db94011d3 178 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
sahilmgandhi 18:6a4db94011d3 179 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
sahilmgandhi 18:6a4db94011d3 180 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
sahilmgandhi 18:6a4db94011d3 181 MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
sahilmgandhi 18:6a4db94011d3 182 BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
sahilmgandhi 18:6a4db94011d3 183 UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
sahilmgandhi 18:6a4db94011d3 184 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
sahilmgandhi 18:6a4db94011d3 185 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
sahilmgandhi 18:6a4db94011d3 186 PendSV_IRQn = -2,/* 14 Pendable request for system service */
sahilmgandhi 18:6a4db94011d3 187 SysTick_IRQn = -1,/* 15 System Tick Timer */
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
sahilmgandhi 18:6a4db94011d3 190 DAC_IRQn = 0,/* 0 DAC */
sahilmgandhi 18:6a4db94011d3 191 RESERVED0_IRQn = 1,
sahilmgandhi 18:6a4db94011d3 192 DMA_IRQn = 2,/* 2 DMA */
sahilmgandhi 18:6a4db94011d3 193 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
sahilmgandhi 18:6a4db94011d3 194 RESERVED2_IRQn = 4,
sahilmgandhi 18:6a4db94011d3 195 ETHERNET_IRQn = 5,/* 5 ETHERNET */
sahilmgandhi 18:6a4db94011d3 196 SDIO_IRQn = 6,/* 6 SDIO */
sahilmgandhi 18:6a4db94011d3 197 LCD_IRQn = 7,/* 7 LCD */
sahilmgandhi 18:6a4db94011d3 198 USB0_IRQn = 8,/* 8 USB0 */
sahilmgandhi 18:6a4db94011d3 199 USB1_IRQn = 9,/* 9 USB1 */
sahilmgandhi 18:6a4db94011d3 200 SCT_IRQn = 10,/* 10 SCT */
sahilmgandhi 18:6a4db94011d3 201 RITIMER_IRQn = 11,/* 11 RITIMER */
sahilmgandhi 18:6a4db94011d3 202 TIMER0_IRQn = 12,/* 12 TIMER0 */
sahilmgandhi 18:6a4db94011d3 203 TIMER1_IRQn = 13,/* 13 TIMER1 */
sahilmgandhi 18:6a4db94011d3 204 TIMER2_IRQn = 14,/* 14 TIMER2 */
sahilmgandhi 18:6a4db94011d3 205 TIMER3_IRQn = 15,/* 15 TIMER3 */
sahilmgandhi 18:6a4db94011d3 206 MCPWM_IRQn = 16,/* 16 MCPWM */
sahilmgandhi 18:6a4db94011d3 207 ADC0_IRQn = 17,/* 17 ADC0 */
sahilmgandhi 18:6a4db94011d3 208 I2C0_IRQn = 18,/* 18 I2C0 */
sahilmgandhi 18:6a4db94011d3 209 I2C1_IRQn = 19,/* 19 I2C1 */
sahilmgandhi 18:6a4db94011d3 210 RESERVED3_IRQn = 20,
sahilmgandhi 18:6a4db94011d3 211 ADC1_IRQn = 21,/* 21 ADC1 */
sahilmgandhi 18:6a4db94011d3 212 SSP0_IRQn = 22,/* 22 SSP0 */
sahilmgandhi 18:6a4db94011d3 213 SSP1_IRQn = 23,/* 23 SSP1 */
sahilmgandhi 18:6a4db94011d3 214 USART0_IRQn = 24,/* 24 USART0 */
sahilmgandhi 18:6a4db94011d3 215 UART1_IRQn = 25,/* 25 UART1 */
sahilmgandhi 18:6a4db94011d3 216 USART2_IRQn = 26,/* 26 USART2 */
sahilmgandhi 18:6a4db94011d3 217 USART3_IRQn = 27,/* 27 USART3 */
sahilmgandhi 18:6a4db94011d3 218 I2S0_IRQn = 28,/* 28 I2S0 */
sahilmgandhi 18:6a4db94011d3 219 I2S1_IRQn = 29,/* 29 I2S1 */
sahilmgandhi 18:6a4db94011d3 220 RESERVED4_IRQn = 30,
sahilmgandhi 18:6a4db94011d3 221 RESERVED5_IRQn = 31,
sahilmgandhi 18:6a4db94011d3 222 PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
sahilmgandhi 18:6a4db94011d3 223 PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
sahilmgandhi 18:6a4db94011d3 224 PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
sahilmgandhi 18:6a4db94011d3 225 PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
sahilmgandhi 18:6a4db94011d3 226 PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
sahilmgandhi 18:6a4db94011d3 227 PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
sahilmgandhi 18:6a4db94011d3 228 PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
sahilmgandhi 18:6a4db94011d3 229 PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
sahilmgandhi 18:6a4db94011d3 230 GINT0_IRQn = 40,/* 40 GINT0 */
sahilmgandhi 18:6a4db94011d3 231 GINT1_IRQn = 41,/* 41 GINT1 */
sahilmgandhi 18:6a4db94011d3 232 EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
sahilmgandhi 18:6a4db94011d3 233 C_CAN1_IRQn = 43,/* 43 C_CAN1 */
sahilmgandhi 18:6a4db94011d3 234 RESERVED6_IRQn = 44,
sahilmgandhi 18:6a4db94011d3 235 RESERVED7_IRQn = 45,/* 45 VADC */
sahilmgandhi 18:6a4db94011d3 236 ATIMER_IRQn = 46,/* 46 ATIMER */
sahilmgandhi 18:6a4db94011d3 237 RTC_IRQn = 47,/* 47 RTC */
sahilmgandhi 18:6a4db94011d3 238 RESERVED8_IRQn = 48,
sahilmgandhi 18:6a4db94011d3 239 WWDT_IRQn = 49,/* 49 WWDT */
sahilmgandhi 18:6a4db94011d3 240 RESERVED9_IRQn = 50,
sahilmgandhi 18:6a4db94011d3 241 C_CAN0_IRQn = 51,/* 51 C_CAN0 */
sahilmgandhi 18:6a4db94011d3 242 QEI_IRQn = 52,/* 52 QEI */
sahilmgandhi 18:6a4db94011d3 243 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 #elif defined(CORE_M0)
sahilmgandhi 18:6a4db94011d3 248 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 249 * LPC43xx (M0 Core) Cortex CMSIS definitions
sahilmgandhi 18:6a4db94011d3 250 */
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 #define __MPU_PRESENT 0 /* MPU present or not */
sahilmgandhi 18:6a4db94011d3 253 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
sahilmgandhi 18:6a4db94011d3 254 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
sahilmgandhi 18:6a4db94011d3 255 #define __FPU_PRESENT 0 /* FPU present or not */
sahilmgandhi 18:6a4db94011d3 256 #define CHIP_LPC43XX /* LPCOPEN compatibility */
sahilmgandhi 18:6a4db94011d3 257
sahilmgandhi 18:6a4db94011d3 258 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 259 * LPC43xx (M0 Core) peripheral interrupt numbers
sahilmgandhi 18:6a4db94011d3 260 */
sahilmgandhi 18:6a4db94011d3 261
sahilmgandhi 18:6a4db94011d3 262 typedef enum {
sahilmgandhi 18:6a4db94011d3 263 /* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
sahilmgandhi 18:6a4db94011d3 264 Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
sahilmgandhi 18:6a4db94011d3 265 NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
sahilmgandhi 18:6a4db94011d3 266 HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
sahilmgandhi 18:6a4db94011d3 267 SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
sahilmgandhi 18:6a4db94011d3 268 DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
sahilmgandhi 18:6a4db94011d3 269 PendSV_IRQn = -2,/* 14 Pendable request for system service */
sahilmgandhi 18:6a4db94011d3 270 SysTick_IRQn = -1,/* 15 System Tick Timer */
sahilmgandhi 18:6a4db94011d3 271
sahilmgandhi 18:6a4db94011d3 272 /* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
sahilmgandhi 18:6a4db94011d3 273 DAC_IRQn = 0,/* 0 DAC */
sahilmgandhi 18:6a4db94011d3 274 M0_M4CORE_IRQn = 1,/* 1 M0a */
sahilmgandhi 18:6a4db94011d3 275 DMA_IRQn = 2,/* 2 DMA r */
sahilmgandhi 18:6a4db94011d3 276 RESERVED1_IRQn = 3,/* 3 EZH/EDM */
sahilmgandhi 18:6a4db94011d3 277 FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
sahilmgandhi 18:6a4db94011d3 278 ETHERNET_IRQn = 5,/* 5 ETHERNET */
sahilmgandhi 18:6a4db94011d3 279 SDIO_IRQn = 6,/* 6 SDIO */
sahilmgandhi 18:6a4db94011d3 280 LCD_IRQn = 7,/* 7 LCD */
sahilmgandhi 18:6a4db94011d3 281 USB0_IRQn = 8,/* 8 USB0 */
sahilmgandhi 18:6a4db94011d3 282 USB1_IRQn = 9,/* 9 USB1 */
sahilmgandhi 18:6a4db94011d3 283 SCT_IRQn = 10,/* 10 SCT */
sahilmgandhi 18:6a4db94011d3 284 RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
sahilmgandhi 18:6a4db94011d3 285 TIMER0_IRQn = 12,/* 12 TIMER0 */
sahilmgandhi 18:6a4db94011d3 286 GINT1_IRQn = 13,/* 13 GINT1 */
sahilmgandhi 18:6a4db94011d3 287 PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
sahilmgandhi 18:6a4db94011d3 288 TIMER3_IRQn = 15,/* 15 TIMER3 */
sahilmgandhi 18:6a4db94011d3 289 MCPWM_IRQn = 16,/* 16 MCPWM */
sahilmgandhi 18:6a4db94011d3 290 ADC0_IRQn = 17,/* 17 ADC0 */
sahilmgandhi 18:6a4db94011d3 291 I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
sahilmgandhi 18:6a4db94011d3 292 SGPIO_INT_IRQn = 19,/* 19 SGPIO */
sahilmgandhi 18:6a4db94011d3 293 SPI_INT_IRQn = 20,/* 20 SPI_INT */
sahilmgandhi 18:6a4db94011d3 294 ADC1_IRQn = 21,/* 21 ADC1 */
sahilmgandhi 18:6a4db94011d3 295 SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
sahilmgandhi 18:6a4db94011d3 296 EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
sahilmgandhi 18:6a4db94011d3 297 USART0_IRQn = 24,/* 24 USART0 */
sahilmgandhi 18:6a4db94011d3 298 UART1_IRQn = 25,/* 25 UART1 */
sahilmgandhi 18:6a4db94011d3 299 USART2_IRQn = 26,/* 26 USART2 */
sahilmgandhi 18:6a4db94011d3 300 USART3_IRQn = 27,/* 27 USART3 */
sahilmgandhi 18:6a4db94011d3 301 I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
sahilmgandhi 18:6a4db94011d3 302 C_CAN0_IRQn = 29,/* 29 C_CAN0 */
sahilmgandhi 18:6a4db94011d3 303 I2S1_IRQn = 29,/* 29 I2S1 */
sahilmgandhi 18:6a4db94011d3 304 RESERVED2_IRQn = 30,
sahilmgandhi 18:6a4db94011d3 305 RESERVED3_IRQn = 31,
sahilmgandhi 18:6a4db94011d3 306 } IRQn_Type;
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 #include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
sahilmgandhi 18:6a4db94011d3 309 #else
sahilmgandhi 18:6a4db94011d3 310 #error Please #define CORE_M0, CORE_M3 or CORE_M4
sahilmgandhi 18:6a4db94011d3 311 #endif
sahilmgandhi 18:6a4db94011d3 312
sahilmgandhi 18:6a4db94011d3 313 #include "system_LPC43xx.h"
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 316 * State Configurable Timer register block structure
sahilmgandhi 18:6a4db94011d3 317 */
sahilmgandhi 18:6a4db94011d3 318 #define LPC_SCT_BASE 0x40000000
sahilmgandhi 18:6a4db94011d3 319 #define CONFIG_SCT_nEV (16) /* Number of events */
sahilmgandhi 18:6a4db94011d3 320 #define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
sahilmgandhi 18:6a4db94011d3 321 #define CONFIG_SCT_nOU (16) /* Number of outputs */
sahilmgandhi 18:6a4db94011d3 322
sahilmgandhi 18:6a4db94011d3 323 typedef struct {
sahilmgandhi 18:6a4db94011d3 324 __IO uint32_t CONFIG; /* Configuration Register */
sahilmgandhi 18:6a4db94011d3 325 union {
sahilmgandhi 18:6a4db94011d3 326 __IO uint32_t CTRL_U; /* Control Register */
sahilmgandhi 18:6a4db94011d3 327 struct {
sahilmgandhi 18:6a4db94011d3 328 __IO uint16_t CTRL_L; /* Low control register */
sahilmgandhi 18:6a4db94011d3 329 __IO uint16_t CTRL_H; /* High control register */
sahilmgandhi 18:6a4db94011d3 330 };
sahilmgandhi 18:6a4db94011d3 331
sahilmgandhi 18:6a4db94011d3 332 };
sahilmgandhi 18:6a4db94011d3 333
sahilmgandhi 18:6a4db94011d3 334 __IO uint16_t LIMIT_L; /* limit register for counter L */
sahilmgandhi 18:6a4db94011d3 335 __IO uint16_t LIMIT_H; /* limit register for counter H */
sahilmgandhi 18:6a4db94011d3 336 __IO uint16_t HALT_L; /* halt register for counter L */
sahilmgandhi 18:6a4db94011d3 337 __IO uint16_t HALT_H; /* halt register for counter H */
sahilmgandhi 18:6a4db94011d3 338 __IO uint16_t STOP_L; /* stop register for counter L */
sahilmgandhi 18:6a4db94011d3 339 __IO uint16_t STOP_H; /* stop register for counter H */
sahilmgandhi 18:6a4db94011d3 340 __IO uint16_t START_L; /* start register for counter L */
sahilmgandhi 18:6a4db94011d3 341 __IO uint16_t START_H; /* start register for counter H */
sahilmgandhi 18:6a4db94011d3 342 uint32_t RESERVED1[10]; /* 0x03C reserved */
sahilmgandhi 18:6a4db94011d3 343 union {
sahilmgandhi 18:6a4db94011d3 344 __IO uint32_t COUNT_U; /* counter register */
sahilmgandhi 18:6a4db94011d3 345 struct {
sahilmgandhi 18:6a4db94011d3 346 __IO uint16_t COUNT_L; /* counter register for counter L */
sahilmgandhi 18:6a4db94011d3 347 __IO uint16_t COUNT_H; /* counter register for counter H */
sahilmgandhi 18:6a4db94011d3 348 };
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 };
sahilmgandhi 18:6a4db94011d3 351
sahilmgandhi 18:6a4db94011d3 352 __IO uint16_t STATE_L; /* state register for counter L */
sahilmgandhi 18:6a4db94011d3 353 __IO uint16_t STATE_H; /* state register for counter H */
sahilmgandhi 18:6a4db94011d3 354 __I uint32_t INPUT; /* input register */
sahilmgandhi 18:6a4db94011d3 355 __IO uint16_t REGMODE_L; /* match - capture registers mode register L */
sahilmgandhi 18:6a4db94011d3 356 __IO uint16_t REGMODE_H; /* match - capture registers mode register H */
sahilmgandhi 18:6a4db94011d3 357 __IO uint32_t OUTPUT; /* output register */
sahilmgandhi 18:6a4db94011d3 358 __IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
sahilmgandhi 18:6a4db94011d3 359 __IO uint32_t RES; /* conflict resolution register */
sahilmgandhi 18:6a4db94011d3 360 __IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
sahilmgandhi 18:6a4db94011d3 361 __IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
sahilmgandhi 18:6a4db94011d3 362 uint32_t RESERVED2[35];
sahilmgandhi 18:6a4db94011d3 363 __IO uint32_t EVEN; /* event enable register */
sahilmgandhi 18:6a4db94011d3 364 __IO uint32_t EVFLAG; /* event flag register */
sahilmgandhi 18:6a4db94011d3 365 __IO uint32_t CONEN; /* conflict enable register */
sahilmgandhi 18:6a4db94011d3 366 __IO uint32_t CONFLAG; /* conflict flag register */
sahilmgandhi 18:6a4db94011d3 367 union {
sahilmgandhi 18:6a4db94011d3 368 __IO union { /* ... Match / Capture value */
sahilmgandhi 18:6a4db94011d3 369 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
sahilmgandhi 18:6a4db94011d3 370 struct {
sahilmgandhi 18:6a4db94011d3 371 uint16_t L; /* SCTMATCH[i].L Access to L value */
sahilmgandhi 18:6a4db94011d3 372 uint16_t H; /* SCTMATCH[i].H Access to H value */
sahilmgandhi 18:6a4db94011d3 373 };
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 } MATCH[CONFIG_SCT_nRG];
sahilmgandhi 18:6a4db94011d3 376
sahilmgandhi 18:6a4db94011d3 377 __I union {
sahilmgandhi 18:6a4db94011d3 378 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
sahilmgandhi 18:6a4db94011d3 379 struct {
sahilmgandhi 18:6a4db94011d3 380 uint16_t L; /* SCTCAP[i].L Access to L value */
sahilmgandhi 18:6a4db94011d3 381 uint16_t H; /* SCTCAP[i].H Access to H value */
sahilmgandhi 18:6a4db94011d3 382 };
sahilmgandhi 18:6a4db94011d3 383
sahilmgandhi 18:6a4db94011d3 384 } CAP[CONFIG_SCT_nRG];
sahilmgandhi 18:6a4db94011d3 385
sahilmgandhi 18:6a4db94011d3 386 };
sahilmgandhi 18:6a4db94011d3 387
sahilmgandhi 18:6a4db94011d3 388 uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
sahilmgandhi 18:6a4db94011d3 389 union {
sahilmgandhi 18:6a4db94011d3 390 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
sahilmgandhi 18:6a4db94011d3 391 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
sahilmgandhi 18:6a4db94011d3 392 };
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
sahilmgandhi 18:6a4db94011d3 395 union {
sahilmgandhi 18:6a4db94011d3 396 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
sahilmgandhi 18:6a4db94011d3 397 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
sahilmgandhi 18:6a4db94011d3 398 };
sahilmgandhi 18:6a4db94011d3 399
sahilmgandhi 18:6a4db94011d3 400 uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
sahilmgandhi 18:6a4db94011d3 401 union {
sahilmgandhi 18:6a4db94011d3 402 __IO union { /* 0x200-... Match Reload / Capture Control value */
sahilmgandhi 18:6a4db94011d3 403 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
sahilmgandhi 18:6a4db94011d3 404 struct {
sahilmgandhi 18:6a4db94011d3 405 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
sahilmgandhi 18:6a4db94011d3 406 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
sahilmgandhi 18:6a4db94011d3 407 };
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 } MATCHREL[CONFIG_SCT_nRG];
sahilmgandhi 18:6a4db94011d3 410
sahilmgandhi 18:6a4db94011d3 411 __IO union {
sahilmgandhi 18:6a4db94011d3 412 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
sahilmgandhi 18:6a4db94011d3 413 struct {
sahilmgandhi 18:6a4db94011d3 414 uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
sahilmgandhi 18:6a4db94011d3 415 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
sahilmgandhi 18:6a4db94011d3 416 };
sahilmgandhi 18:6a4db94011d3 417
sahilmgandhi 18:6a4db94011d3 418 } CAPCTRL[CONFIG_SCT_nRG];
sahilmgandhi 18:6a4db94011d3 419
sahilmgandhi 18:6a4db94011d3 420 };
sahilmgandhi 18:6a4db94011d3 421
sahilmgandhi 18:6a4db94011d3 422 uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
sahilmgandhi 18:6a4db94011d3 423 union {
sahilmgandhi 18:6a4db94011d3 424 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
sahilmgandhi 18:6a4db94011d3 425 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
sahilmgandhi 18:6a4db94011d3 426 };
sahilmgandhi 18:6a4db94011d3 427
sahilmgandhi 18:6a4db94011d3 428 uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
sahilmgandhi 18:6a4db94011d3 429 union {
sahilmgandhi 18:6a4db94011d3 430 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
sahilmgandhi 18:6a4db94011d3 431 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
sahilmgandhi 18:6a4db94011d3 432 };
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
sahilmgandhi 18:6a4db94011d3 435 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
sahilmgandhi 18:6a4db94011d3 436 uint32_t STATE; /* Event State Register */
sahilmgandhi 18:6a4db94011d3 437 uint32_t CTRL; /* Event Control Register */
sahilmgandhi 18:6a4db94011d3 438 } EVENT[CONFIG_SCT_nEV];
sahilmgandhi 18:6a4db94011d3 439
sahilmgandhi 18:6a4db94011d3 440 uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
sahilmgandhi 18:6a4db94011d3 441 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
sahilmgandhi 18:6a4db94011d3 442 uint32_t SET; /* Output n Set Register */
sahilmgandhi 18:6a4db94011d3 443 uint32_t CLR; /* Output n Clear Register */
sahilmgandhi 18:6a4db94011d3 444 } OUT[CONFIG_SCT_nOU];
sahilmgandhi 18:6a4db94011d3 445
sahilmgandhi 18:6a4db94011d3 446 uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
sahilmgandhi 18:6a4db94011d3 447 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
sahilmgandhi 18:6a4db94011d3 448 } LPC_SCT_T;
sahilmgandhi 18:6a4db94011d3 449
sahilmgandhi 18:6a4db94011d3 450 /* Macro defines for SCT configuration register */
sahilmgandhi 18:6a4db94011d3 451 #define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
sahilmgandhi 18:6a4db94011d3 452 #define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
sahilmgandhi 18:6a4db94011d3 453
sahilmgandhi 18:6a4db94011d3 454 #define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
sahilmgandhi 18:6a4db94011d3 455 #define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
sahilmgandhi 18:6a4db94011d3 456 #define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
sahilmgandhi 18:6a4db94011d3 457 #define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
sahilmgandhi 18:6a4db94011d3 458
sahilmgandhi 18:6a4db94011d3 459 #define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
sahilmgandhi 18:6a4db94011d3 460 #define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462 /* Macro defines for SCT control register */
sahilmgandhi 18:6a4db94011d3 463 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
sahilmgandhi 18:6a4db94011d3 464 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 #define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
sahilmgandhi 18:6a4db94011d3 467 #define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
sahilmgandhi 18:6a4db94011d3 468 #define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
sahilmgandhi 18:6a4db94011d3 469 #define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
sahilmgandhi 18:6a4db94011d3 470 #define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
sahilmgandhi 18:6a4db94011d3 473 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
sahilmgandhi 18:6a4db94011d3 474 #define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
sahilmgandhi 18:6a4db94011d3 475 #define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
sahilmgandhi 18:6a4db94011d3 476 #define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
sahilmgandhi 18:6a4db94011d3 477 #define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
sahilmgandhi 18:6a4db94011d3 478 #define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
sahilmgandhi 18:6a4db94011d3 479
sahilmgandhi 18:6a4db94011d3 480 /* Macro defines for SCT Conflict resolution register */
sahilmgandhi 18:6a4db94011d3 481 #define SCT_RES_NOCHANGE (0)
sahilmgandhi 18:6a4db94011d3 482 #define SCT_RES_SET_OUTPUT (1)
sahilmgandhi 18:6a4db94011d3 483 #define SCT_RES_CLEAR_OUTPUT (2)
sahilmgandhi 18:6a4db94011d3 484 #define SCT_RES_TOGGLE_OUTPUT (3)
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 487 * GPDMA Channel register block structure
sahilmgandhi 18:6a4db94011d3 488 */
sahilmgandhi 18:6a4db94011d3 489 #define LPC_GPDMA_BASE 0x40002000
sahilmgandhi 18:6a4db94011d3 490
sahilmgandhi 18:6a4db94011d3 491 typedef struct {
sahilmgandhi 18:6a4db94011d3 492 __IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
sahilmgandhi 18:6a4db94011d3 493 __IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
sahilmgandhi 18:6a4db94011d3 494 __IO uint32_t LLI; /* DMA Channel Linked List Item Register */
sahilmgandhi 18:6a4db94011d3 495 __IO uint32_t CONTROL; /* DMA Channel Control Register */
sahilmgandhi 18:6a4db94011d3 496 __IO uint32_t CONFIG; /* DMA Channel Configuration Register */
sahilmgandhi 18:6a4db94011d3 497 __I uint32_t RESERVED1[3];
sahilmgandhi 18:6a4db94011d3 498 } LPC_GPDMA_CH_T;
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 #define GPDMA_CHANNELS 8
sahilmgandhi 18:6a4db94011d3 501
sahilmgandhi 18:6a4db94011d3 502 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 503 * GPDMA register block
sahilmgandhi 18:6a4db94011d3 504 */
sahilmgandhi 18:6a4db94011d3 505 typedef struct { /* GPDMA Structure */
sahilmgandhi 18:6a4db94011d3 506 __I uint32_t INTSTAT; /* DMA Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 507 __I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
sahilmgandhi 18:6a4db94011d3 508 __O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
sahilmgandhi 18:6a4db94011d3 509 __I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
sahilmgandhi 18:6a4db94011d3 510 __O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
sahilmgandhi 18:6a4db94011d3 511 __I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
sahilmgandhi 18:6a4db94011d3 512 __I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 513 __I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
sahilmgandhi 18:6a4db94011d3 514 __IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
sahilmgandhi 18:6a4db94011d3 515 __IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
sahilmgandhi 18:6a4db94011d3 516 __IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
sahilmgandhi 18:6a4db94011d3 517 __IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
sahilmgandhi 18:6a4db94011d3 518 __IO uint32_t CONFIG; /* DMA Configuration Register */
sahilmgandhi 18:6a4db94011d3 519 __IO uint32_t SYNC; /* DMA Synchronization Register */
sahilmgandhi 18:6a4db94011d3 520 __I uint32_t RESERVED0[50];
sahilmgandhi 18:6a4db94011d3 521 LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
sahilmgandhi 18:6a4db94011d3 522 } LPC_GPDMA_T;
sahilmgandhi 18:6a4db94011d3 523
sahilmgandhi 18:6a4db94011d3 524 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 525 * SPIFI register block structure
sahilmgandhi 18:6a4db94011d3 526 */
sahilmgandhi 18:6a4db94011d3 527 #define LPC_SPIFI_BASE 0x40003000
sahilmgandhi 18:6a4db94011d3 528
sahilmgandhi 18:6a4db94011d3 529 typedef struct { /* SPIFI Structure */
sahilmgandhi 18:6a4db94011d3 530 __IO uint32_t CTRL; /* Control register */
sahilmgandhi 18:6a4db94011d3 531 __IO uint32_t CMD; /* Command register */
sahilmgandhi 18:6a4db94011d3 532 __IO uint32_t ADDR; /* Address register */
sahilmgandhi 18:6a4db94011d3 533 __IO uint32_t IDATA; /* Intermediate data register */
sahilmgandhi 18:6a4db94011d3 534 __IO uint32_t CLIMIT; /* Cache limit register */
sahilmgandhi 18:6a4db94011d3 535 union {
sahilmgandhi 18:6a4db94011d3 536 __IO uint32_t DATA;
sahilmgandhi 18:6a4db94011d3 537 __IO uint16_t DATA_HWORD;
sahilmgandhi 18:6a4db94011d3 538 __IO uint8_t DATA_BYTE;
sahilmgandhi 18:6a4db94011d3 539 }; /* Data register */
sahilmgandhi 18:6a4db94011d3 540 __IO uint32_t MCMD; /* Memory command register */
sahilmgandhi 18:6a4db94011d3 541 __IO uint32_t STAT; /* Status register */
sahilmgandhi 18:6a4db94011d3 542 } LPC_SPIFI_T;
sahilmgandhi 18:6a4db94011d3 543
sahilmgandhi 18:6a4db94011d3 544 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 545 * SD/MMC & SDIO register block structure
sahilmgandhi 18:6a4db94011d3 546 */
sahilmgandhi 18:6a4db94011d3 547 #define LPC_SDMMC_BASE 0x40004000
sahilmgandhi 18:6a4db94011d3 548
sahilmgandhi 18:6a4db94011d3 549 typedef struct { /* SDMMC Structure */
sahilmgandhi 18:6a4db94011d3 550 __IO uint32_t CTRL; /* Control Register */
sahilmgandhi 18:6a4db94011d3 551 __IO uint32_t PWREN; /* Power Enable Register */
sahilmgandhi 18:6a4db94011d3 552 __IO uint32_t CLKDIV; /* Clock Divider Register */
sahilmgandhi 18:6a4db94011d3 553 __IO uint32_t CLKSRC; /* SD Clock Source Register */
sahilmgandhi 18:6a4db94011d3 554 __IO uint32_t CLKENA; /* Clock Enable Register */
sahilmgandhi 18:6a4db94011d3 555 __IO uint32_t TMOUT; /* Timeout Register */
sahilmgandhi 18:6a4db94011d3 556 __IO uint32_t CTYPE; /* Card Type Register */
sahilmgandhi 18:6a4db94011d3 557 __IO uint32_t BLKSIZ; /* Block Size Register */
sahilmgandhi 18:6a4db94011d3 558 __IO uint32_t BYTCNT; /* Byte Count Register */
sahilmgandhi 18:6a4db94011d3 559 __IO uint32_t INTMASK; /* Interrupt Mask Register */
sahilmgandhi 18:6a4db94011d3 560 __IO uint32_t CMDARG; /* Command Argument Register */
sahilmgandhi 18:6a4db94011d3 561 __IO uint32_t CMD; /* Command Register */
sahilmgandhi 18:6a4db94011d3 562 __I uint32_t RESP0; /* Response Register 0 */
sahilmgandhi 18:6a4db94011d3 563 __I uint32_t RESP1; /* Response Register 1 */
sahilmgandhi 18:6a4db94011d3 564 __I uint32_t RESP2; /* Response Register 2 */
sahilmgandhi 18:6a4db94011d3 565 __I uint32_t RESP3; /* Response Register 3 */
sahilmgandhi 18:6a4db94011d3 566 __I uint32_t MINTSTS; /* Masked Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 567 __IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 568 __I uint32_t STATUS; /* Status Register */
sahilmgandhi 18:6a4db94011d3 569 __IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
sahilmgandhi 18:6a4db94011d3 570 __I uint32_t CDETECT; /* Card Detect Register */
sahilmgandhi 18:6a4db94011d3 571 __I uint32_t WRTPRT; /* Write Protect Register */
sahilmgandhi 18:6a4db94011d3 572 __IO uint32_t GPIO; /* General Purpose Input/Output Register */
sahilmgandhi 18:6a4db94011d3 573 __I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
sahilmgandhi 18:6a4db94011d3 574 __I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
sahilmgandhi 18:6a4db94011d3 575 __IO uint32_t DEBNCE; /* Debounce Count Register */
sahilmgandhi 18:6a4db94011d3 576 __IO uint32_t USRID; /* User ID Register */
sahilmgandhi 18:6a4db94011d3 577 __I uint32_t VERID; /* Version ID Register */
sahilmgandhi 18:6a4db94011d3 578 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 579 __IO uint32_t UHS_REG; /* UHS-1 Register */
sahilmgandhi 18:6a4db94011d3 580 __IO uint32_t RST_N; /* Hardware Reset */
sahilmgandhi 18:6a4db94011d3 581 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 582 __IO uint32_t BMOD; /* Bus Mode Register */
sahilmgandhi 18:6a4db94011d3 583 __O uint32_t PLDMND; /* Poll Demand Register */
sahilmgandhi 18:6a4db94011d3 584 __IO uint32_t DBADDR; /* Descriptor List Base Address Register */
sahilmgandhi 18:6a4db94011d3 585 __IO uint32_t IDSTS; /* Internal DMAC Status Register */
sahilmgandhi 18:6a4db94011d3 586 __IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
sahilmgandhi 18:6a4db94011d3 587 __I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
sahilmgandhi 18:6a4db94011d3 588 __I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
sahilmgandhi 18:6a4db94011d3 589 } LPC_SDMMC_T;
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 592 * External Memory Controller (EMC) register block structure
sahilmgandhi 18:6a4db94011d3 593 */
sahilmgandhi 18:6a4db94011d3 594 #define LPC_EMC_BASE 0x40005000
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 typedef struct { /* EMC Structure */
sahilmgandhi 18:6a4db94011d3 597 __IO uint32_t CONTROL; /* Controls operation of the memory controller. */
sahilmgandhi 18:6a4db94011d3 598 __I uint32_t STATUS; /* Provides EMC status information. */
sahilmgandhi 18:6a4db94011d3 599 __IO uint32_t CONFIG; /* Configures operation of the memory controller. */
sahilmgandhi 18:6a4db94011d3 600 __I uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 601 __IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
sahilmgandhi 18:6a4db94011d3 602 __IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
sahilmgandhi 18:6a4db94011d3 603 __IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
sahilmgandhi 18:6a4db94011d3 604 __I uint32_t RESERVED1;
sahilmgandhi 18:6a4db94011d3 605 __IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
sahilmgandhi 18:6a4db94011d3 606 __IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
sahilmgandhi 18:6a4db94011d3 607 __IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
sahilmgandhi 18:6a4db94011d3 608 __IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
sahilmgandhi 18:6a4db94011d3 609 __IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
sahilmgandhi 18:6a4db94011d3 610 __IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
sahilmgandhi 18:6a4db94011d3 611 __IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
sahilmgandhi 18:6a4db94011d3 612 __IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
sahilmgandhi 18:6a4db94011d3 613 __IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
sahilmgandhi 18:6a4db94011d3 614 __IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
sahilmgandhi 18:6a4db94011d3 615 __IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
sahilmgandhi 18:6a4db94011d3 616 __I uint32_t RESERVED2[9];
sahilmgandhi 18:6a4db94011d3 617 __IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
sahilmgandhi 18:6a4db94011d3 618 __I uint32_t RESERVED3[31];
sahilmgandhi 18:6a4db94011d3 619 __IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
sahilmgandhi 18:6a4db94011d3 620 __IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
sahilmgandhi 18:6a4db94011d3 621 __I uint32_t RESERVED4[6];
sahilmgandhi 18:6a4db94011d3 622 __IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
sahilmgandhi 18:6a4db94011d3 623 __IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
sahilmgandhi 18:6a4db94011d3 624 __I uint32_t RESERVED5[6];
sahilmgandhi 18:6a4db94011d3 625 __IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
sahilmgandhi 18:6a4db94011d3 626 __IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
sahilmgandhi 18:6a4db94011d3 627 __I uint32_t RESERVED6[6];
sahilmgandhi 18:6a4db94011d3 628 __IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
sahilmgandhi 18:6a4db94011d3 629 __IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
sahilmgandhi 18:6a4db94011d3 630 __I uint32_t RESERVED7[38];
sahilmgandhi 18:6a4db94011d3 631 __IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
sahilmgandhi 18:6a4db94011d3 632 __IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
sahilmgandhi 18:6a4db94011d3 633 __IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
sahilmgandhi 18:6a4db94011d3 634 __IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
sahilmgandhi 18:6a4db94011d3 635 __IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
sahilmgandhi 18:6a4db94011d3 636 __IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
sahilmgandhi 18:6a4db94011d3 637 __IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
sahilmgandhi 18:6a4db94011d3 638 __I uint32_t RESERVED8;
sahilmgandhi 18:6a4db94011d3 639 __IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
sahilmgandhi 18:6a4db94011d3 640 __IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
sahilmgandhi 18:6a4db94011d3 641 __IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
sahilmgandhi 18:6a4db94011d3 642 __IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
sahilmgandhi 18:6a4db94011d3 643 __IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
sahilmgandhi 18:6a4db94011d3 644 __IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
sahilmgandhi 18:6a4db94011d3 645 __IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
sahilmgandhi 18:6a4db94011d3 646 __I uint32_t RESERVED9;
sahilmgandhi 18:6a4db94011d3 647 __IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
sahilmgandhi 18:6a4db94011d3 648 __IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
sahilmgandhi 18:6a4db94011d3 649 __IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
sahilmgandhi 18:6a4db94011d3 650 __IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
sahilmgandhi 18:6a4db94011d3 651 __IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
sahilmgandhi 18:6a4db94011d3 652 __IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
sahilmgandhi 18:6a4db94011d3 653 __IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
sahilmgandhi 18:6a4db94011d3 654 __I uint32_t RESERVED10;
sahilmgandhi 18:6a4db94011d3 655 __IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
sahilmgandhi 18:6a4db94011d3 656 __IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
sahilmgandhi 18:6a4db94011d3 657 __IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
sahilmgandhi 18:6a4db94011d3 658 __IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
sahilmgandhi 18:6a4db94011d3 659 __IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
sahilmgandhi 18:6a4db94011d3 660 __IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
sahilmgandhi 18:6a4db94011d3 661 __IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
sahilmgandhi 18:6a4db94011d3 662 } LPC_EMC_T;
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 665 * USB High-Speed register block structure
sahilmgandhi 18:6a4db94011d3 666 */
sahilmgandhi 18:6a4db94011d3 667 #define LPC_USB0_BASE 0x40006000
sahilmgandhi 18:6a4db94011d3 668 #define LPC_USB1_BASE 0x40007000
sahilmgandhi 18:6a4db94011d3 669
sahilmgandhi 18:6a4db94011d3 670 typedef struct { /* USB Structure */
sahilmgandhi 18:6a4db94011d3 671 __I uint32_t RESERVED0[64];
sahilmgandhi 18:6a4db94011d3 672 __I uint32_t CAPLENGTH; /* Capability register length */
sahilmgandhi 18:6a4db94011d3 673 __I uint32_t HCSPARAMS; /* Host controller structural parameters */
sahilmgandhi 18:6a4db94011d3 674 __I uint32_t HCCPARAMS; /* Host controller capability parameters */
sahilmgandhi 18:6a4db94011d3 675 __I uint32_t RESERVED1[5];
sahilmgandhi 18:6a4db94011d3 676 __I uint32_t DCIVERSION; /* Device interface version number */
sahilmgandhi 18:6a4db94011d3 677 __I uint32_t RESERVED2[7];
sahilmgandhi 18:6a4db94011d3 678 union {
sahilmgandhi 18:6a4db94011d3 679 __IO uint32_t USBCMD_H; /* USB command (host mode) */
sahilmgandhi 18:6a4db94011d3 680 __IO uint32_t USBCMD_D; /* USB command (device mode) */
sahilmgandhi 18:6a4db94011d3 681 };
sahilmgandhi 18:6a4db94011d3 682
sahilmgandhi 18:6a4db94011d3 683 union {
sahilmgandhi 18:6a4db94011d3 684 __IO uint32_t USBSTS_H; /* USB status (host mode) */
sahilmgandhi 18:6a4db94011d3 685 __IO uint32_t USBSTS_D; /* USB status (device mode) */
sahilmgandhi 18:6a4db94011d3 686 };
sahilmgandhi 18:6a4db94011d3 687
sahilmgandhi 18:6a4db94011d3 688 union {
sahilmgandhi 18:6a4db94011d3 689 __IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
sahilmgandhi 18:6a4db94011d3 690 __IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
sahilmgandhi 18:6a4db94011d3 691 };
sahilmgandhi 18:6a4db94011d3 692
sahilmgandhi 18:6a4db94011d3 693 union {
sahilmgandhi 18:6a4db94011d3 694 __IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
sahilmgandhi 18:6a4db94011d3 695 __I uint32_t FRINDEX_D; /* USB frame index (device mode) */
sahilmgandhi 18:6a4db94011d3 696 };
sahilmgandhi 18:6a4db94011d3 697
sahilmgandhi 18:6a4db94011d3 698 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 699 union {
sahilmgandhi 18:6a4db94011d3 700 __IO uint32_t PERIODICLISTBASE; /* Frame list base address */
sahilmgandhi 18:6a4db94011d3 701 __IO uint32_t DEVICEADDR; /* USB device address */
sahilmgandhi 18:6a4db94011d3 702 };
sahilmgandhi 18:6a4db94011d3 703
sahilmgandhi 18:6a4db94011d3 704 union {
sahilmgandhi 18:6a4db94011d3 705 __IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
sahilmgandhi 18:6a4db94011d3 706 __IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
sahilmgandhi 18:6a4db94011d3 707 };
sahilmgandhi 18:6a4db94011d3 708
sahilmgandhi 18:6a4db94011d3 709 __IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
sahilmgandhi 18:6a4db94011d3 710 __IO uint32_t BURSTSIZE; /* Programmable burst size */
sahilmgandhi 18:6a4db94011d3 711 __IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
sahilmgandhi 18:6a4db94011d3 712 __I uint32_t RESERVED4[2];
sahilmgandhi 18:6a4db94011d3 713 __IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
sahilmgandhi 18:6a4db94011d3 714 __IO uint32_t BINTERVAL; /* Length of virtual frame */
sahilmgandhi 18:6a4db94011d3 715 __IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
sahilmgandhi 18:6a4db94011d3 716 __IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
sahilmgandhi 18:6a4db94011d3 717 __I uint32_t RESERVED5;
sahilmgandhi 18:6a4db94011d3 718 union {
sahilmgandhi 18:6a4db94011d3 719 __IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
sahilmgandhi 18:6a4db94011d3 720 __IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
sahilmgandhi 18:6a4db94011d3 721 };
sahilmgandhi 18:6a4db94011d3 722
sahilmgandhi 18:6a4db94011d3 723 __I uint32_t RESERVED6[7];
sahilmgandhi 18:6a4db94011d3 724 __IO uint32_t OTGSC; /* OTG status and control */
sahilmgandhi 18:6a4db94011d3 725 union {
sahilmgandhi 18:6a4db94011d3 726 __IO uint32_t USBMODE_H; /* USB mode (host mode) */
sahilmgandhi 18:6a4db94011d3 727 __IO uint32_t USBMODE_D; /* USB mode (device mode) */
sahilmgandhi 18:6a4db94011d3 728 };
sahilmgandhi 18:6a4db94011d3 729
sahilmgandhi 18:6a4db94011d3 730 __IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
sahilmgandhi 18:6a4db94011d3 731 __IO uint32_t ENDPTPRIME; /* Endpoint initialization */
sahilmgandhi 18:6a4db94011d3 732 __IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
sahilmgandhi 18:6a4db94011d3 733 __I uint32_t ENDPTSTAT; /* Endpoint status */
sahilmgandhi 18:6a4db94011d3 734 __IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
sahilmgandhi 18:6a4db94011d3 735 __IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
sahilmgandhi 18:6a4db94011d3 736 } LPC_USBHS_T;
sahilmgandhi 18:6a4db94011d3 737
sahilmgandhi 18:6a4db94011d3 738 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 739 * LCD Controller register block structure
sahilmgandhi 18:6a4db94011d3 740 */
sahilmgandhi 18:6a4db94011d3 741 #define LPC_LCD_BASE 0x40008000
sahilmgandhi 18:6a4db94011d3 742
sahilmgandhi 18:6a4db94011d3 743 typedef struct { /* LCD Structure */
sahilmgandhi 18:6a4db94011d3 744 __IO uint32_t TIMH; /* Horizontal Timing Control register */
sahilmgandhi 18:6a4db94011d3 745 __IO uint32_t TIMV; /* Vertical Timing Control register */
sahilmgandhi 18:6a4db94011d3 746 __IO uint32_t POL; /* Clock and Signal Polarity Control register */
sahilmgandhi 18:6a4db94011d3 747 __IO uint32_t LE; /* Line End Control register */
sahilmgandhi 18:6a4db94011d3 748 __IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
sahilmgandhi 18:6a4db94011d3 749 __IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
sahilmgandhi 18:6a4db94011d3 750 __IO uint32_t CTRL; /* LCD Control register */
sahilmgandhi 18:6a4db94011d3 751 __IO uint32_t INTMSK; /* Interrupt Mask register */
sahilmgandhi 18:6a4db94011d3 752 __I uint32_t INTRAW; /* Raw Interrupt Status register */
sahilmgandhi 18:6a4db94011d3 753 __I uint32_t INTSTAT; /* Masked Interrupt Status register */
sahilmgandhi 18:6a4db94011d3 754 __O uint32_t INTCLR; /* Interrupt Clear register */
sahilmgandhi 18:6a4db94011d3 755 __I uint32_t UPCURR; /* Upper Panel Current Address Value register */
sahilmgandhi 18:6a4db94011d3 756 __I uint32_t LPCURR; /* Lower Panel Current Address Value register */
sahilmgandhi 18:6a4db94011d3 757 __I uint32_t RESERVED0[115];
sahilmgandhi 18:6a4db94011d3 758 __IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
sahilmgandhi 18:6a4db94011d3 759 __I uint32_t RESERVED1[256];
sahilmgandhi 18:6a4db94011d3 760 __IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
sahilmgandhi 18:6a4db94011d3 761 __IO uint32_t CRSR_CTRL; /* Cursor Control register */
sahilmgandhi 18:6a4db94011d3 762 __IO uint32_t CRSR_CFG; /* Cursor Configuration register */
sahilmgandhi 18:6a4db94011d3 763 __IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
sahilmgandhi 18:6a4db94011d3 764 __IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
sahilmgandhi 18:6a4db94011d3 765 __IO uint32_t CRSR_XY; /* Cursor XY Position register */
sahilmgandhi 18:6a4db94011d3 766 __IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
sahilmgandhi 18:6a4db94011d3 767 __I uint32_t RESERVED2[2];
sahilmgandhi 18:6a4db94011d3 768 __IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
sahilmgandhi 18:6a4db94011d3 769 __O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
sahilmgandhi 18:6a4db94011d3 770 __I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
sahilmgandhi 18:6a4db94011d3 771 __I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
sahilmgandhi 18:6a4db94011d3 772 } LPC_LCD_T;
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 775 * EEPROM register block structure
sahilmgandhi 18:6a4db94011d3 776 */
sahilmgandhi 18:6a4db94011d3 777 #define LPC_EEPROM_BASE 0x4000E000
sahilmgandhi 18:6a4db94011d3 778
sahilmgandhi 18:6a4db94011d3 779 typedef struct { /* EEPROM Structure */
sahilmgandhi 18:6a4db94011d3 780 __IO uint32_t CMD; /* EEPROM command register */
sahilmgandhi 18:6a4db94011d3 781 uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 782 __IO uint32_t RWSTATE; /* EEPROM read wait state register */
sahilmgandhi 18:6a4db94011d3 783 __IO uint32_t AUTOPROG; /* EEPROM auto programming register */
sahilmgandhi 18:6a4db94011d3 784 __IO uint32_t WSTATE; /* EEPROM wait state register */
sahilmgandhi 18:6a4db94011d3 785 __IO uint32_t CLKDIV; /* EEPROM clock divider register */
sahilmgandhi 18:6a4db94011d3 786 __IO uint32_t PWRDWN; /* EEPROM power-down register */
sahilmgandhi 18:6a4db94011d3 787 uint32_t RESERVED2[1007];
sahilmgandhi 18:6a4db94011d3 788 __O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
sahilmgandhi 18:6a4db94011d3 789 __O uint32_t INTENSET; /* EEPROM interrupt enable set */
sahilmgandhi 18:6a4db94011d3 790 __I uint32_t INTSTAT; /* EEPROM interrupt status */
sahilmgandhi 18:6a4db94011d3 791 __I uint32_t INTEN; /* EEPROM interrupt enable */
sahilmgandhi 18:6a4db94011d3 792 __O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
sahilmgandhi 18:6a4db94011d3 793 __O uint32_t INTSTATSET; /* EEPROM interrupt status set */
sahilmgandhi 18:6a4db94011d3 794 } LPC_EEPROM_T;
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 797 * 10/100 MII & RMII Ethernet with timestamping register block structure
sahilmgandhi 18:6a4db94011d3 798 */
sahilmgandhi 18:6a4db94011d3 799 #define LPC_ETHERNET_BASE 0x40010000
sahilmgandhi 18:6a4db94011d3 800
sahilmgandhi 18:6a4db94011d3 801 typedef struct { /* ETHERNET Structure */
sahilmgandhi 18:6a4db94011d3 802 __IO uint32_t MAC_CONFIG; /* MAC configuration register */
sahilmgandhi 18:6a4db94011d3 803 __IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
sahilmgandhi 18:6a4db94011d3 804 __IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
sahilmgandhi 18:6a4db94011d3 805 __IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
sahilmgandhi 18:6a4db94011d3 806 __IO uint32_t MAC_MII_ADDR; /* MII address register */
sahilmgandhi 18:6a4db94011d3 807 __IO uint32_t MAC_MII_DATA; /* MII data register */
sahilmgandhi 18:6a4db94011d3 808 __IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
sahilmgandhi 18:6a4db94011d3 809 __IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
sahilmgandhi 18:6a4db94011d3 810 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 811 __I uint32_t MAC_DEBUG; /* Debug register */
sahilmgandhi 18:6a4db94011d3 812 __IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
sahilmgandhi 18:6a4db94011d3 813 __IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
sahilmgandhi 18:6a4db94011d3 814 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 815 __I uint32_t MAC_INTR; /* Interrupt status register */
sahilmgandhi 18:6a4db94011d3 816 __IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
sahilmgandhi 18:6a4db94011d3 817 __IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
sahilmgandhi 18:6a4db94011d3 818 __IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
sahilmgandhi 18:6a4db94011d3 819 __I uint32_t RESERVED2[430];
sahilmgandhi 18:6a4db94011d3 820 __IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
sahilmgandhi 18:6a4db94011d3 821 __IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
sahilmgandhi 18:6a4db94011d3 822 __I uint32_t SECONDS; /* System time seconds register */
sahilmgandhi 18:6a4db94011d3 823 __I uint32_t NANOSECONDS; /* System time nanoseconds register */
sahilmgandhi 18:6a4db94011d3 824 __IO uint32_t SECONDSUPDATE; /* System time seconds update register */
sahilmgandhi 18:6a4db94011d3 825 __IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
sahilmgandhi 18:6a4db94011d3 826 __IO uint32_t ADDEND; /* Time stamp addend register */
sahilmgandhi 18:6a4db94011d3 827 __IO uint32_t TARGETSECONDS; /* Target time seconds register */
sahilmgandhi 18:6a4db94011d3 828 __IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
sahilmgandhi 18:6a4db94011d3 829 __IO uint32_t HIGHWORD; /* System time higher word seconds register */
sahilmgandhi 18:6a4db94011d3 830 __I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
sahilmgandhi 18:6a4db94011d3 831 __IO uint32_t PPSCTRL; /* PPS control register */
sahilmgandhi 18:6a4db94011d3 832 __I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
sahilmgandhi 18:6a4db94011d3 833 __I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
sahilmgandhi 18:6a4db94011d3 834 __I uint32_t RESERVED3[562];
sahilmgandhi 18:6a4db94011d3 835 __IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
sahilmgandhi 18:6a4db94011d3 836 __IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
sahilmgandhi 18:6a4db94011d3 837 __IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
sahilmgandhi 18:6a4db94011d3 838 __IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
sahilmgandhi 18:6a4db94011d3 839 __IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
sahilmgandhi 18:6a4db94011d3 840 __IO uint32_t DMA_STAT; /* Status register */
sahilmgandhi 18:6a4db94011d3 841 __IO uint32_t DMA_OP_MODE; /* Operation mode register */
sahilmgandhi 18:6a4db94011d3 842 __IO uint32_t DMA_INT_EN; /* Interrupt enable register */
sahilmgandhi 18:6a4db94011d3 843 __I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
sahilmgandhi 18:6a4db94011d3 844 __IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
sahilmgandhi 18:6a4db94011d3 845 __I uint32_t RESERVED4[8];
sahilmgandhi 18:6a4db94011d3 846 __I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
sahilmgandhi 18:6a4db94011d3 847 __I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
sahilmgandhi 18:6a4db94011d3 848 __I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
sahilmgandhi 18:6a4db94011d3 849 __I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
sahilmgandhi 18:6a4db94011d3 850 } LPC_ENET_T;
sahilmgandhi 18:6a4db94011d3 851
sahilmgandhi 18:6a4db94011d3 852 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 853 * Alarm Timer register block structure
sahilmgandhi 18:6a4db94011d3 854 */
sahilmgandhi 18:6a4db94011d3 855 #define LPC_ATIMER_BASE 0x40040000
sahilmgandhi 18:6a4db94011d3 856
sahilmgandhi 18:6a4db94011d3 857 typedef struct { /* ATIMER Structure */
sahilmgandhi 18:6a4db94011d3 858 __IO uint32_t DOWNCOUNTER; /* Downcounter register */
sahilmgandhi 18:6a4db94011d3 859 __IO uint32_t PRESET; /* Preset value register */
sahilmgandhi 18:6a4db94011d3 860 __I uint32_t RESERVED0[1012];
sahilmgandhi 18:6a4db94011d3 861 __O uint32_t CLR_EN; /* Interrupt clear enable register */
sahilmgandhi 18:6a4db94011d3 862 __O uint32_t SET_EN; /* Interrupt set enable register */
sahilmgandhi 18:6a4db94011d3 863 __I uint32_t STATUS; /* Status register */
sahilmgandhi 18:6a4db94011d3 864 __I uint32_t ENABLE; /* Enable register */
sahilmgandhi 18:6a4db94011d3 865 __O uint32_t CLR_STAT; /* Clear register */
sahilmgandhi 18:6a4db94011d3 866 __O uint32_t SET_STAT; /* Set register */
sahilmgandhi 18:6a4db94011d3 867 } LPC_ATIMER_T;
sahilmgandhi 18:6a4db94011d3 868
sahilmgandhi 18:6a4db94011d3 869 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 870 * Register File register block structure
sahilmgandhi 18:6a4db94011d3 871 */
sahilmgandhi 18:6a4db94011d3 872 #define LPC_REGFILE_BASE 0x40041000
sahilmgandhi 18:6a4db94011d3 873
sahilmgandhi 18:6a4db94011d3 874 typedef struct {
sahilmgandhi 18:6a4db94011d3 875 __IO uint32_t REGFILE[64]; /* General purpose storage register */
sahilmgandhi 18:6a4db94011d3 876 } LPC_REGFILE_T;
sahilmgandhi 18:6a4db94011d3 877
sahilmgandhi 18:6a4db94011d3 878 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 879 * Power Management Controller register block structure
sahilmgandhi 18:6a4db94011d3 880 */
sahilmgandhi 18:6a4db94011d3 881 #define LPC_PMC_BASE 0x40042000
sahilmgandhi 18:6a4db94011d3 882
sahilmgandhi 18:6a4db94011d3 883 typedef struct { /* PMC Structure */
sahilmgandhi 18:6a4db94011d3 884 __IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
sahilmgandhi 18:6a4db94011d3 885 __I uint32_t RESERVED0[6];
sahilmgandhi 18:6a4db94011d3 886 __IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
sahilmgandhi 18:6a4db94011d3 887 } LPC_PMC_T;
sahilmgandhi 18:6a4db94011d3 888
sahilmgandhi 18:6a4db94011d3 889 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 890 * CREG Register Block
sahilmgandhi 18:6a4db94011d3 891 */
sahilmgandhi 18:6a4db94011d3 892 #define LPC_CREG_BASE 0x40043000
sahilmgandhi 18:6a4db94011d3 893
sahilmgandhi 18:6a4db94011d3 894 typedef struct { /* CREG Structure */
sahilmgandhi 18:6a4db94011d3 895 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 896 __IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
sahilmgandhi 18:6a4db94011d3 897 __I uint32_t RESERVED1[62];
sahilmgandhi 18:6a4db94011d3 898 __IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
sahilmgandhi 18:6a4db94011d3 899 #if defined(CHIP_LPC18XX)
sahilmgandhi 18:6a4db94011d3 900 __I uint32_t RESERVED2[5];
sahilmgandhi 18:6a4db94011d3 901 #else
sahilmgandhi 18:6a4db94011d3 902 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 903 __I uint32_t CREG1; /* Configuration Register 1 */
sahilmgandhi 18:6a4db94011d3 904 __I uint32_t CREG2; /* Configuration Register 2 */
sahilmgandhi 18:6a4db94011d3 905 __I uint32_t CREG3; /* Configuration Register 3 */
sahilmgandhi 18:6a4db94011d3 906 __I uint32_t CREG4; /* Configuration Register 4 */
sahilmgandhi 18:6a4db94011d3 907 #endif
sahilmgandhi 18:6a4db94011d3 908 __IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
sahilmgandhi 18:6a4db94011d3 909 __IO uint32_t DMAMUX; /* DMA muxing control */
sahilmgandhi 18:6a4db94011d3 910 __IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
sahilmgandhi 18:6a4db94011d3 911 __IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
sahilmgandhi 18:6a4db94011d3 912 __IO uint32_t ETBCFG; /* ETB RAM configuration */
sahilmgandhi 18:6a4db94011d3 913 __IO uint32_t CREG6; /* Chip configuration register 6. */
sahilmgandhi 18:6a4db94011d3 914 #if defined(CHIP_LPC18XX)
sahilmgandhi 18:6a4db94011d3 915 __I uint32_t RESERVED4[52];
sahilmgandhi 18:6a4db94011d3 916 #else
sahilmgandhi 18:6a4db94011d3 917 __IO uint32_t M4TXEVENT; /* M4 IPC event register */
sahilmgandhi 18:6a4db94011d3 918 __I uint32_t RESERVED4[51];
sahilmgandhi 18:6a4db94011d3 919 #endif
sahilmgandhi 18:6a4db94011d3 920 __I uint32_t CHIPID; /* Part ID */
sahilmgandhi 18:6a4db94011d3 921 #if defined(CHIP_LPC18XX)
sahilmgandhi 18:6a4db94011d3 922 __I uint32_t RESERVED5[191];
sahilmgandhi 18:6a4db94011d3 923 #else
sahilmgandhi 18:6a4db94011d3 924 __I uint32_t RESERVED5[127];
sahilmgandhi 18:6a4db94011d3 925 __IO uint32_t M0TXEVENT; /* M0 IPC Event register */
sahilmgandhi 18:6a4db94011d3 926 __IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
sahilmgandhi 18:6a4db94011d3 927 __I uint32_t RESERVED6[62];
sahilmgandhi 18:6a4db94011d3 928 #endif
sahilmgandhi 18:6a4db94011d3 929 __IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
sahilmgandhi 18:6a4db94011d3 930 __I uint32_t RESERVED7[63];
sahilmgandhi 18:6a4db94011d3 931 __IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
sahilmgandhi 18:6a4db94011d3 932 } LPC_CREG_T;
sahilmgandhi 18:6a4db94011d3 933
sahilmgandhi 18:6a4db94011d3 934 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 935 * Event Router register structure
sahilmgandhi 18:6a4db94011d3 936 */
sahilmgandhi 18:6a4db94011d3 937 #define LPC_EVRT_BASE 0x40044000
sahilmgandhi 18:6a4db94011d3 938
sahilmgandhi 18:6a4db94011d3 939 typedef struct { /* EVENTROUTER Structure */
sahilmgandhi 18:6a4db94011d3 940 __IO uint32_t HILO; /* Level configuration register */
sahilmgandhi 18:6a4db94011d3 941 __IO uint32_t EDGE; /* Edge configuration */
sahilmgandhi 18:6a4db94011d3 942 __I uint32_t RESERVED0[1012];
sahilmgandhi 18:6a4db94011d3 943 __O uint32_t CLR_EN; /* Event clear enable register */
sahilmgandhi 18:6a4db94011d3 944 __O uint32_t SET_EN; /* Event set enable register */
sahilmgandhi 18:6a4db94011d3 945 __I uint32_t STATUS; /* Status register */
sahilmgandhi 18:6a4db94011d3 946 __I uint32_t ENABLE; /* Enable register */
sahilmgandhi 18:6a4db94011d3 947 __O uint32_t CLR_STAT; /* Clear register */
sahilmgandhi 18:6a4db94011d3 948 __O uint32_t SET_STAT; /* Set register */
sahilmgandhi 18:6a4db94011d3 949 } LPC_EVRT_T;
sahilmgandhi 18:6a4db94011d3 950
sahilmgandhi 18:6a4db94011d3 951 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 952 * Real Time Clock register block structure
sahilmgandhi 18:6a4db94011d3 953 */
sahilmgandhi 18:6a4db94011d3 954 #define LPC_RTC_BASE 0x40046000
sahilmgandhi 18:6a4db94011d3 955 #define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
sahilmgandhi 18:6a4db94011d3 956
sahilmgandhi 18:6a4db94011d3 957 typedef enum RTC_TIMEINDEX {
sahilmgandhi 18:6a4db94011d3 958 RTC_TIMETYPE_SECOND, /* Second */
sahilmgandhi 18:6a4db94011d3 959 RTC_TIMETYPE_MINUTE, /* Month */
sahilmgandhi 18:6a4db94011d3 960 RTC_TIMETYPE_HOUR, /* Hour */
sahilmgandhi 18:6a4db94011d3 961 RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
sahilmgandhi 18:6a4db94011d3 962 RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
sahilmgandhi 18:6a4db94011d3 963 RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
sahilmgandhi 18:6a4db94011d3 964 RTC_TIMETYPE_MONTH, /* Month */
sahilmgandhi 18:6a4db94011d3 965 RTC_TIMETYPE_YEAR, /* Year */
sahilmgandhi 18:6a4db94011d3 966 RTC_TIMETYPE_LAST
sahilmgandhi 18:6a4db94011d3 967 } RTC_TIMEINDEX_T;
sahilmgandhi 18:6a4db94011d3 968
sahilmgandhi 18:6a4db94011d3 969 #if RTC_EV_SUPPORT
sahilmgandhi 18:6a4db94011d3 970 typedef enum LPC_RTC_EV_CHANNEL {
sahilmgandhi 18:6a4db94011d3 971 RTC_EV_CHANNEL_1 = 0,
sahilmgandhi 18:6a4db94011d3 972 RTC_EV_CHANNEL_2,
sahilmgandhi 18:6a4db94011d3 973 RTC_EV_CHANNEL_3,
sahilmgandhi 18:6a4db94011d3 974 RTC_EV_CHANNEL_NUM,
sahilmgandhi 18:6a4db94011d3 975 } LPC_RTC_EV_CHANNEL_T;
sahilmgandhi 18:6a4db94011d3 976 #endif /*RTC_EV_SUPPORT*/
sahilmgandhi 18:6a4db94011d3 977
sahilmgandhi 18:6a4db94011d3 978 typedef struct { /* RTC Structure */
sahilmgandhi 18:6a4db94011d3 979 __IO uint32_t ILR; /* Interrupt Location Register */
sahilmgandhi 18:6a4db94011d3 980 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 981 __IO uint32_t CCR; /* Clock Control Register */
sahilmgandhi 18:6a4db94011d3 982 __IO uint32_t CIIR; /* Counter Increment Interrupt Register */
sahilmgandhi 18:6a4db94011d3 983 __IO uint32_t AMR; /* Alarm Mask Register */
sahilmgandhi 18:6a4db94011d3 984 __I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
sahilmgandhi 18:6a4db94011d3 985 __IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
sahilmgandhi 18:6a4db94011d3 986 __IO uint32_t CALIBRATION; /* Calibration Value Register */
sahilmgandhi 18:6a4db94011d3 987 __I uint32_t RESERVED1[7];
sahilmgandhi 18:6a4db94011d3 988 __IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
sahilmgandhi 18:6a4db94011d3 989 #if RTC_EV_SUPPORT
sahilmgandhi 18:6a4db94011d3 990 __IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
sahilmgandhi 18:6a4db94011d3 991 __IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
sahilmgandhi 18:6a4db94011d3 992 __I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
sahilmgandhi 18:6a4db94011d3 993 __I uint32_t RESERVED2;
sahilmgandhi 18:6a4db94011d3 994 __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
sahilmgandhi 18:6a4db94011d3 995 __I uint32_t RESERVED3;
sahilmgandhi 18:6a4db94011d3 996 __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
sahilmgandhi 18:6a4db94011d3 997 #endif /*RTC_EV_SUPPORT*/
sahilmgandhi 18:6a4db94011d3 998 } LPC_RTC_T;
sahilmgandhi 18:6a4db94011d3 999
sahilmgandhi 18:6a4db94011d3 1000 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1001 * LPC18XX/43XX CGU register block structure
sahilmgandhi 18:6a4db94011d3 1002 */
sahilmgandhi 18:6a4db94011d3 1003 #define LPC_CGU_BASE 0x40050000
sahilmgandhi 18:6a4db94011d3 1004 #define LPC_CCU1_BASE 0x40051000
sahilmgandhi 18:6a4db94011d3 1005 #define LPC_CCU2_BASE 0x40052000
sahilmgandhi 18:6a4db94011d3 1006 /*
sahilmgandhi 18:6a4db94011d3 1007 * Input clocks for the CGU and can come from both external (crystal) and
sahilmgandhi 18:6a4db94011d3 1008 * internal (PLL) sources. Can be routed to the base clocks.
sahilmgandhi 18:6a4db94011d3 1009 */
sahilmgandhi 18:6a4db94011d3 1010 typedef enum CGU_CLKIN {
sahilmgandhi 18:6a4db94011d3 1011 CLKIN_32K, /* External 32KHz input */
sahilmgandhi 18:6a4db94011d3 1012 CLKIN_IRC, /* Internal IRC (12MHz) input */
sahilmgandhi 18:6a4db94011d3 1013 CLKIN_ENET_RX, /* External ENET_RX pin input */
sahilmgandhi 18:6a4db94011d3 1014 CLKIN_ENET_TX, /* External ENET_TX pin input */
sahilmgandhi 18:6a4db94011d3 1015 CLKIN_CLKIN, /* External GPCLKIN pin input */
sahilmgandhi 18:6a4db94011d3 1016 CLKIN_RESERVED1,
sahilmgandhi 18:6a4db94011d3 1017 CLKIN_CRYSTAL, /* External (main) crystal pin input */
sahilmgandhi 18:6a4db94011d3 1018 CLKIN_USBPLL, /* Internal USB PLL input */
sahilmgandhi 18:6a4db94011d3 1019 CLKIN_AUDIOPLL, /* Internal Audio PLL input */
sahilmgandhi 18:6a4db94011d3 1020 CLKIN_MAINPLL, /* Internal Main PLL input */
sahilmgandhi 18:6a4db94011d3 1021 CLKIN_RESERVED2,
sahilmgandhi 18:6a4db94011d3 1022 CLKIN_RESERVED3,
sahilmgandhi 18:6a4db94011d3 1023 CLKIN_IDIVA, /* Internal divider A input */
sahilmgandhi 18:6a4db94011d3 1024 CLKIN_IDIVB, /* Internal divider B input */
sahilmgandhi 18:6a4db94011d3 1025 CLKIN_IDIVC, /* Internal divider C input */
sahilmgandhi 18:6a4db94011d3 1026 CLKIN_IDIVD, /* Internal divider D input */
sahilmgandhi 18:6a4db94011d3 1027 CLKIN_IDIVE, /* Internal divider E input */
sahilmgandhi 18:6a4db94011d3 1028 CLKINPUT_PD /* External 32KHz input */
sahilmgandhi 18:6a4db94011d3 1029 } CGU_CLKIN_T;
sahilmgandhi 18:6a4db94011d3 1030
sahilmgandhi 18:6a4db94011d3 1031 #define CLKIN_PLL0USB CLKIN_USBPLL
sahilmgandhi 18:6a4db94011d3 1032 #define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
sahilmgandhi 18:6a4db94011d3 1033 #define CLKIN_PLL1 CLKIN_MAINPLL
sahilmgandhi 18:6a4db94011d3 1034
sahilmgandhi 18:6a4db94011d3 1035 /*
sahilmgandhi 18:6a4db94011d3 1036 * CGU base clocks are clocks that are associated with a single input clock
sahilmgandhi 18:6a4db94011d3 1037 * and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
sahilmgandhi 18:6a4db94011d3 1038 * clock can be configured to use the CLKIN_MAINPLL input clock, which will in
sahilmgandhi 18:6a4db94011d3 1039 * turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
sahilmgandhi 18:6a4db94011d3 1040 * CLK_PERIPH_SGPIO periphral clocks.
sahilmgandhi 18:6a4db94011d3 1041 */
sahilmgandhi 18:6a4db94011d3 1042 typedef enum CGU_BASE_CLK {
sahilmgandhi 18:6a4db94011d3 1043 CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
sahilmgandhi 18:6a4db94011d3 1044 CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
sahilmgandhi 18:6a4db94011d3 1045 #if defined(CHIP_LPC43XX)
sahilmgandhi 18:6a4db94011d3 1046 CLK_BASE_PERIPH, /* Base clock for SGPIO */
sahilmgandhi 18:6a4db94011d3 1047 #else
sahilmgandhi 18:6a4db94011d3 1048 CLK_BASE_RESERVED1,
sahilmgandhi 18:6a4db94011d3 1049 #endif
sahilmgandhi 18:6a4db94011d3 1050 CLK_BASE_USB1, /* Base USB clock for USB1 */
sahilmgandhi 18:6a4db94011d3 1051 CLK_BASE_MX, /* Base clock for CPU core */
sahilmgandhi 18:6a4db94011d3 1052 CLK_BASE_SPIFI, /* Base clock for SPIFI */
sahilmgandhi 18:6a4db94011d3 1053 #if defined(CHIP_LPC43XX)
sahilmgandhi 18:6a4db94011d3 1054 CLK_BASE_SPI, /* Base clock for SPI */
sahilmgandhi 18:6a4db94011d3 1055 #else
sahilmgandhi 18:6a4db94011d3 1056 CLK_BASE_RESERVED2,
sahilmgandhi 18:6a4db94011d3 1057 #endif
sahilmgandhi 18:6a4db94011d3 1058 CLK_BASE_PHY_RX, /* Base clock for PHY RX */
sahilmgandhi 18:6a4db94011d3 1059 CLK_BASE_PHY_TX, /* Base clock for PHY TX */
sahilmgandhi 18:6a4db94011d3 1060 CLK_BASE_APB1, /* Base clock for APB1 group */
sahilmgandhi 18:6a4db94011d3 1061 CLK_BASE_APB3, /* Base clock for APB3 group */
sahilmgandhi 18:6a4db94011d3 1062 CLK_BASE_LCD, /* Base clock for LCD pixel clock */
sahilmgandhi 18:6a4db94011d3 1063 #if defined(CHIP_LPC43XX)
sahilmgandhi 18:6a4db94011d3 1064 CLK_BASE_VADC, /* Base clock for VADC */
sahilmgandhi 18:6a4db94011d3 1065 #else
sahilmgandhi 18:6a4db94011d3 1066 CLK_BASE_RESERVED3,
sahilmgandhi 18:6a4db94011d3 1067 #endif
sahilmgandhi 18:6a4db94011d3 1068 CLK_BASE_SDIO, /* Base clock for SDIO */
sahilmgandhi 18:6a4db94011d3 1069 CLK_BASE_SSP0, /* Base clock for SSP0 */
sahilmgandhi 18:6a4db94011d3 1070 CLK_BASE_SSP1, /* Base clock for SSP1 */
sahilmgandhi 18:6a4db94011d3 1071 CLK_BASE_UART0, /* Base clock for UART0 */
sahilmgandhi 18:6a4db94011d3 1072 CLK_BASE_UART1, /* Base clock for UART1 */
sahilmgandhi 18:6a4db94011d3 1073 CLK_BASE_UART2, /* Base clock for UART2 */
sahilmgandhi 18:6a4db94011d3 1074 CLK_BASE_UART3, /* Base clock for UART3 */
sahilmgandhi 18:6a4db94011d3 1075 CLK_BASE_OUT, /* Base clock for CLKOUT pin */
sahilmgandhi 18:6a4db94011d3 1076 CLK_BASE_RESERVED4,
sahilmgandhi 18:6a4db94011d3 1077 CLK_BASE_RESERVED5,
sahilmgandhi 18:6a4db94011d3 1078 CLK_BASE_RESERVED6,
sahilmgandhi 18:6a4db94011d3 1079 CLK_BASE_RESERVED7,
sahilmgandhi 18:6a4db94011d3 1080 CLK_BASE_APLL, /* Base clock for audio PLL */
sahilmgandhi 18:6a4db94011d3 1081 CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
sahilmgandhi 18:6a4db94011d3 1082 CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
sahilmgandhi 18:6a4db94011d3 1083 CLK_BASE_LAST,
sahilmgandhi 18:6a4db94011d3 1084 CLK_BASE_NONE = CLK_BASE_LAST
sahilmgandhi 18:6a4db94011d3 1085 } CGU_BASE_CLK_T;
sahilmgandhi 18:6a4db94011d3 1086
sahilmgandhi 18:6a4db94011d3 1087 /*
sahilmgandhi 18:6a4db94011d3 1088 * CGU dividers provide an extra clock state where a specific clock can be
sahilmgandhi 18:6a4db94011d3 1089 * divided before being routed to a peripheral group. A divider accepts an
sahilmgandhi 18:6a4db94011d3 1090 * input clock and then divides it. To use the divided clock for a base clock
sahilmgandhi 18:6a4db94011d3 1091 * group, use the divider as the input clock for the base clock (for example,
sahilmgandhi 18:6a4db94011d3 1092 * use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
sahilmgandhi 18:6a4db94011d3 1093 */
sahilmgandhi 18:6a4db94011d3 1094 typedef enum CGU_IDIV {
sahilmgandhi 18:6a4db94011d3 1095 CLK_IDIV_A, /* CGU clock divider A */
sahilmgandhi 18:6a4db94011d3 1096 CLK_IDIV_B, /* CGU clock divider B */
sahilmgandhi 18:6a4db94011d3 1097 CLK_IDIV_C, /* CGU clock divider A */
sahilmgandhi 18:6a4db94011d3 1098 CLK_IDIV_D, /* CGU clock divider D */
sahilmgandhi 18:6a4db94011d3 1099 CLK_IDIV_E, /* CGU clock divider E */
sahilmgandhi 18:6a4db94011d3 1100 CLK_IDIV_LAST
sahilmgandhi 18:6a4db94011d3 1101 } CGU_IDIV_T;
sahilmgandhi 18:6a4db94011d3 1102
sahilmgandhi 18:6a4db94011d3 1103 /*
sahilmgandhi 18:6a4db94011d3 1104 * Peripheral clocks are individual clocks routed to peripherals. Although
sahilmgandhi 18:6a4db94011d3 1105 * multiple peripherals may share a same base clock, each peripheral's clock
sahilmgandhi 18:6a4db94011d3 1106 * can be enabled or disabled individually. Some peripheral clocks also have
sahilmgandhi 18:6a4db94011d3 1107 * additional dividers associated with them.
sahilmgandhi 18:6a4db94011d3 1108 */
sahilmgandhi 18:6a4db94011d3 1109 typedef enum CCU_CLK {
sahilmgandhi 18:6a4db94011d3 1110 /* CCU1 clocks */
sahilmgandhi 18:6a4db94011d3 1111 CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
sahilmgandhi 18:6a4db94011d3 1112 CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
sahilmgandhi 18:6a4db94011d3 1113 CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
sahilmgandhi 18:6a4db94011d3 1114 CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
sahilmgandhi 18:6a4db94011d3 1115 CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
sahilmgandhi 18:6a4db94011d3 1116 CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
sahilmgandhi 18:6a4db94011d3 1117 CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
sahilmgandhi 18:6a4db94011d3 1118 CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
sahilmgandhi 18:6a4db94011d3 1119 CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
sahilmgandhi 18:6a4db94011d3 1120 CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
sahilmgandhi 18:6a4db94011d3 1121 CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
sahilmgandhi 18:6a4db94011d3 1122 CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
sahilmgandhi 18:6a4db94011d3 1123 CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1124 CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1125 CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1126 CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1127 CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1128 CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1129 CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1130 CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1131 CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1132 CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1133 RESERVED_ALIGN = CLK_MX_MXCORE + 3,
sahilmgandhi 18:6a4db94011d3 1134 CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1135 CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1136 CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1137 CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1138 CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1139 #if defined(CHIP_LPC43XX)
sahilmgandhi 18:6a4db94011d3 1140 CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1141 CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1142 #else
sahilmgandhi 18:6a4db94011d3 1143 CLK_RESERVED1,
sahilmgandhi 18:6a4db94011d3 1144 CLK_RESERVED2,
sahilmgandhi 18:6a4db94011d3 1145 #endif
sahilmgandhi 18:6a4db94011d3 1146 CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1147 CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1148 CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1149 CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1150 CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1151 CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1152 CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1153 CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1154 CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1155 CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1156 CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1157 CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1158 CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1159 CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1160 CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1161 CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
sahilmgandhi 18:6a4db94011d3 1162 #if defined(CHIP_LPC43XX)
sahilmgandhi 18:6a4db94011d3 1163 CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
sahilmgandhi 18:6a4db94011d3 1164 CLK_RESERVED3,
sahilmgandhi 18:6a4db94011d3 1165 CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
sahilmgandhi 18:6a4db94011d3 1166 CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
sahilmgandhi 18:6a4db94011d3 1167 #else
sahilmgandhi 18:6a4db94011d3 1168 CLK_RESERVED3 = 192,
sahilmgandhi 18:6a4db94011d3 1169 CLK_RESERVED3A,
sahilmgandhi 18:6a4db94011d3 1170 CLK_RESERVED4,
sahilmgandhi 18:6a4db94011d3 1171 CLK_RESERVED5,
sahilmgandhi 18:6a4db94011d3 1172 #endif
sahilmgandhi 18:6a4db94011d3 1173 CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
sahilmgandhi 18:6a4db94011d3 1174 CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
sahilmgandhi 18:6a4db94011d3 1175 #if defined(CHIP_LPC43XX)
sahilmgandhi 18:6a4db94011d3 1176 CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
sahilmgandhi 18:6a4db94011d3 1177 CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
sahilmgandhi 18:6a4db94011d3 1178 #else
sahilmgandhi 18:6a4db94011d3 1179 CLK_RESERVED7 = 320,
sahilmgandhi 18:6a4db94011d3 1180 CLK_RESERVED8,
sahilmgandhi 18:6a4db94011d3 1181 #endif
sahilmgandhi 18:6a4db94011d3 1182 CLK_CCU1_LAST,
sahilmgandhi 18:6a4db94011d3 1183
sahilmgandhi 18:6a4db94011d3 1184 /* CCU2 clocks */
sahilmgandhi 18:6a4db94011d3 1185 CLK_CCU2_START,
sahilmgandhi 18:6a4db94011d3 1186 CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
sahilmgandhi 18:6a4db94011d3 1187 RESERVED_ALIGNB = CLK_CCU2_START + 31,
sahilmgandhi 18:6a4db94011d3 1188 CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
sahilmgandhi 18:6a4db94011d3 1189 RESERVED_ALIGNC = CLK_CCU2_START + 63,
sahilmgandhi 18:6a4db94011d3 1190 CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
sahilmgandhi 18:6a4db94011d3 1191 RESERVED_ALIGND = CLK_CCU2_START + 95,
sahilmgandhi 18:6a4db94011d3 1192 CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
sahilmgandhi 18:6a4db94011d3 1193 RESERVED_ALIGNE = CLK_CCU2_START + 127,
sahilmgandhi 18:6a4db94011d3 1194 CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
sahilmgandhi 18:6a4db94011d3 1195 RESERVED_ALIGNF = CLK_CCU2_START + 159,
sahilmgandhi 18:6a4db94011d3 1196 CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
sahilmgandhi 18:6a4db94011d3 1197 RESERVED_ALIGNG = CLK_CCU2_START + 191,
sahilmgandhi 18:6a4db94011d3 1198 CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
sahilmgandhi 18:6a4db94011d3 1199 RESERVED_ALIGNH = CLK_CCU2_START + 223,
sahilmgandhi 18:6a4db94011d3 1200 CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
sahilmgandhi 18:6a4db94011d3 1201 CLK_CCU2_LAST
sahilmgandhi 18:6a4db94011d3 1202 } CCU_CLK_T;
sahilmgandhi 18:6a4db94011d3 1203
sahilmgandhi 18:6a4db94011d3 1204 /*
sahilmgandhi 18:6a4db94011d3 1205 * Audio or USB PLL selection
sahilmgandhi 18:6a4db94011d3 1206 */
sahilmgandhi 18:6a4db94011d3 1207 typedef enum CGU_USB_AUDIO_PLL {
sahilmgandhi 18:6a4db94011d3 1208 CGU_USB_PLL,
sahilmgandhi 18:6a4db94011d3 1209 CGU_AUDIO_PLL
sahilmgandhi 18:6a4db94011d3 1210 } CGU_USB_AUDIO_PLL_T;
sahilmgandhi 18:6a4db94011d3 1211
sahilmgandhi 18:6a4db94011d3 1212 /*
sahilmgandhi 18:6a4db94011d3 1213 * PLL register block
sahilmgandhi 18:6a4db94011d3 1214 */
sahilmgandhi 18:6a4db94011d3 1215 typedef struct {
sahilmgandhi 18:6a4db94011d3 1216 __I uint32_t PLL_STAT; /* PLL status register */
sahilmgandhi 18:6a4db94011d3 1217 __IO uint32_t PLL_CTRL; /* PLL control register */
sahilmgandhi 18:6a4db94011d3 1218 __IO uint32_t PLL_MDIV; /* PLL M-divider register */
sahilmgandhi 18:6a4db94011d3 1219 __IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
sahilmgandhi 18:6a4db94011d3 1220 } CGU_PLL_REG_T;
sahilmgandhi 18:6a4db94011d3 1221
sahilmgandhi 18:6a4db94011d3 1222 typedef struct { /* (@ 0x40050000) CGU Structure */
sahilmgandhi 18:6a4db94011d3 1223 __I uint32_t RESERVED0[5];
sahilmgandhi 18:6a4db94011d3 1224 __IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
sahilmgandhi 18:6a4db94011d3 1225 __IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
sahilmgandhi 18:6a4db94011d3 1226 CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
sahilmgandhi 18:6a4db94011d3 1227 __IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
sahilmgandhi 18:6a4db94011d3 1228 __I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
sahilmgandhi 18:6a4db94011d3 1229 __IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
sahilmgandhi 18:6a4db94011d3 1230 __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
sahilmgandhi 18:6a4db94011d3 1231 __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
sahilmgandhi 18:6a4db94011d3 1232 } LPC_CGU_T;
sahilmgandhi 18:6a4db94011d3 1233
sahilmgandhi 18:6a4db94011d3 1234 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1235 * CCU clock config/status register pair
sahilmgandhi 18:6a4db94011d3 1236 */
sahilmgandhi 18:6a4db94011d3 1237 typedef struct {
sahilmgandhi 18:6a4db94011d3 1238 __IO uint32_t CFG; /* CCU clock configuration register */
sahilmgandhi 18:6a4db94011d3 1239 __I uint32_t STAT; /* CCU clock status register */
sahilmgandhi 18:6a4db94011d3 1240 } CCU_CFGSTAT_T;
sahilmgandhi 18:6a4db94011d3 1241
sahilmgandhi 18:6a4db94011d3 1242 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1243 * CCU1 register block structure
sahilmgandhi 18:6a4db94011d3 1244 */
sahilmgandhi 18:6a4db94011d3 1245 typedef struct { /* (@ 0x40051000) CCU1 Structure */
sahilmgandhi 18:6a4db94011d3 1246 __IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
sahilmgandhi 18:6a4db94011d3 1247 __I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
sahilmgandhi 18:6a4db94011d3 1248 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 1249 CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
sahilmgandhi 18:6a4db94011d3 1250 } LPC_CCU1_T;
sahilmgandhi 18:6a4db94011d3 1251
sahilmgandhi 18:6a4db94011d3 1252 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1253 * CCU2 register block structure
sahilmgandhi 18:6a4db94011d3 1254 */
sahilmgandhi 18:6a4db94011d3 1255 typedef struct { /* (@ 0x40052000) CCU2 Structure */
sahilmgandhi 18:6a4db94011d3 1256 __IO uint32_t PM; /* (@ 0x40052000) Power mode register */
sahilmgandhi 18:6a4db94011d3 1257 __I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
sahilmgandhi 18:6a4db94011d3 1258 __I uint32_t RESERVED0[62];
sahilmgandhi 18:6a4db94011d3 1259 CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
sahilmgandhi 18:6a4db94011d3 1260 } LPC_CCU2_T;
sahilmgandhi 18:6a4db94011d3 1261
sahilmgandhi 18:6a4db94011d3 1262 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1263 * RGU register structure
sahilmgandhi 18:6a4db94011d3 1264 */
sahilmgandhi 18:6a4db94011d3 1265 #define LPC_RGU_BASE 0x40053000
sahilmgandhi 18:6a4db94011d3 1266
sahilmgandhi 18:6a4db94011d3 1267 typedef enum RGU_RST {
sahilmgandhi 18:6a4db94011d3 1268 RGU_CORE_RST,
sahilmgandhi 18:6a4db94011d3 1269 RGU_PERIPH_RST,
sahilmgandhi 18:6a4db94011d3 1270 RGU_MASTER_RST,
sahilmgandhi 18:6a4db94011d3 1271 RGU_WWDT_RST = 4,
sahilmgandhi 18:6a4db94011d3 1272 RGU_CREG_RST,
sahilmgandhi 18:6a4db94011d3 1273 RGU_BUS_RST = 8,
sahilmgandhi 18:6a4db94011d3 1274 RGU_SCU_RST,
sahilmgandhi 18:6a4db94011d3 1275 RGU_M3_RST = 13,
sahilmgandhi 18:6a4db94011d3 1276 RGU_LCD_RST = 16,
sahilmgandhi 18:6a4db94011d3 1277 RGU_USB0_RST,
sahilmgandhi 18:6a4db94011d3 1278 RGU_USB1_RST,
sahilmgandhi 18:6a4db94011d3 1279 RGU_DMA_RST,
sahilmgandhi 18:6a4db94011d3 1280 RGU_SDIO_RST,
sahilmgandhi 18:6a4db94011d3 1281 RGU_EMC_RST,
sahilmgandhi 18:6a4db94011d3 1282 RGU_ETHERNET_RST,
sahilmgandhi 18:6a4db94011d3 1283 RGU_FLASHA_RST = 25,
sahilmgandhi 18:6a4db94011d3 1284 RGU_EEPROM_RST = 27,
sahilmgandhi 18:6a4db94011d3 1285 RGU_GPIO_RST,
sahilmgandhi 18:6a4db94011d3 1286 RGU_FLASHB_RST,
sahilmgandhi 18:6a4db94011d3 1287 RGU_TIMER0_RST = 32,
sahilmgandhi 18:6a4db94011d3 1288 RGU_TIMER1_RST,
sahilmgandhi 18:6a4db94011d3 1289 RGU_TIMER2_RST,
sahilmgandhi 18:6a4db94011d3 1290 RGU_TIMER3_RST,
sahilmgandhi 18:6a4db94011d3 1291 RGU_RITIMER_RST,
sahilmgandhi 18:6a4db94011d3 1292 RGU_SCT_RST,
sahilmgandhi 18:6a4db94011d3 1293 RGU_MOTOCONPWM_RST,
sahilmgandhi 18:6a4db94011d3 1294 RGU_QEI_RST,
sahilmgandhi 18:6a4db94011d3 1295 RGU_ADC0_RST,
sahilmgandhi 18:6a4db94011d3 1296 RGU_ADC1_RST,
sahilmgandhi 18:6a4db94011d3 1297 RGU_DAC_RST,
sahilmgandhi 18:6a4db94011d3 1298 RGU_UART0_RST = 44,
sahilmgandhi 18:6a4db94011d3 1299 RGU_UART1_RST,
sahilmgandhi 18:6a4db94011d3 1300 RGU_UART2_RST,
sahilmgandhi 18:6a4db94011d3 1301 RGU_UART3_RST,
sahilmgandhi 18:6a4db94011d3 1302 RGU_I2C0_RST,
sahilmgandhi 18:6a4db94011d3 1303 RGU_I2C1_RST,
sahilmgandhi 18:6a4db94011d3 1304 RGU_SSP0_RST,
sahilmgandhi 18:6a4db94011d3 1305 RGU_SSP1_RST,
sahilmgandhi 18:6a4db94011d3 1306 RGU_I2S_RST,
sahilmgandhi 18:6a4db94011d3 1307 RGU_SPIFI_RST,
sahilmgandhi 18:6a4db94011d3 1308 RGU_CAN1_RST,
sahilmgandhi 18:6a4db94011d3 1309 RGU_CAN0_RST,
sahilmgandhi 18:6a4db94011d3 1310 #ifdef CHIP_LPC43XX
sahilmgandhi 18:6a4db94011d3 1311 RGU_M0APP_RST,
sahilmgandhi 18:6a4db94011d3 1312 RGU_SGPIO_RST,
sahilmgandhi 18:6a4db94011d3 1313 RGU_SPI_RST,
sahilmgandhi 18:6a4db94011d3 1314 #endif
sahilmgandhi 18:6a4db94011d3 1315 RGU_LAST_RST = 63,
sahilmgandhi 18:6a4db94011d3 1316 } RGU_RST_T;
sahilmgandhi 18:6a4db94011d3 1317
sahilmgandhi 18:6a4db94011d3 1318 typedef struct { /* RGU Structure */
sahilmgandhi 18:6a4db94011d3 1319 __I uint32_t RESERVED0[64];
sahilmgandhi 18:6a4db94011d3 1320 __O uint32_t RESET_CTRL0; /* Reset control register 0 */
sahilmgandhi 18:6a4db94011d3 1321 __O uint32_t RESET_CTRL1; /* Reset control register 1 */
sahilmgandhi 18:6a4db94011d3 1322 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 1323 __IO uint32_t RESET_STATUS0; /* Reset status register 0 */
sahilmgandhi 18:6a4db94011d3 1324 __IO uint32_t RESET_STATUS1; /* Reset status register 1 */
sahilmgandhi 18:6a4db94011d3 1325 __IO uint32_t RESET_STATUS2; /* Reset status register 2 */
sahilmgandhi 18:6a4db94011d3 1326 __IO uint32_t RESET_STATUS3; /* Reset status register 3 */
sahilmgandhi 18:6a4db94011d3 1327 __I uint32_t RESERVED2[12];
sahilmgandhi 18:6a4db94011d3 1328 __I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
sahilmgandhi 18:6a4db94011d3 1329 __I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
sahilmgandhi 18:6a4db94011d3 1330 __I uint32_t RESERVED3[170];
sahilmgandhi 18:6a4db94011d3 1331 __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
sahilmgandhi 18:6a4db94011d3 1332 } LPC_RGU_T;
sahilmgandhi 18:6a4db94011d3 1333
sahilmgandhi 18:6a4db94011d3 1334 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1335 * Windowed Watchdog register block structure
sahilmgandhi 18:6a4db94011d3 1336 */
sahilmgandhi 18:6a4db94011d3 1337 #define LPC_WWDT_BASE 0x40080000
sahilmgandhi 18:6a4db94011d3 1338
sahilmgandhi 18:6a4db94011d3 1339 typedef struct { /* WWDT Structure */
sahilmgandhi 18:6a4db94011d3 1340 __IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
sahilmgandhi 18:6a4db94011d3 1341 __IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
sahilmgandhi 18:6a4db94011d3 1342 __O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
sahilmgandhi 18:6a4db94011d3 1343 __I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
sahilmgandhi 18:6a4db94011d3 1344 #ifdef WATCHDOG_CLKSEL_SUPPORT
sahilmgandhi 18:6a4db94011d3 1345 __IO uint32_t CLKSEL; /* Watchdog clock select register. */
sahilmgandhi 18:6a4db94011d3 1346 #else
sahilmgandhi 18:6a4db94011d3 1347 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1348 #endif
sahilmgandhi 18:6a4db94011d3 1349 #ifdef WATCHDOG_WINDOW_SUPPORT
sahilmgandhi 18:6a4db94011d3 1350 __IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
sahilmgandhi 18:6a4db94011d3 1351 __IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
sahilmgandhi 18:6a4db94011d3 1352 #endif
sahilmgandhi 18:6a4db94011d3 1353 } LPC_WWDT_T;
sahilmgandhi 18:6a4db94011d3 1354
sahilmgandhi 18:6a4db94011d3 1355 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1356 * USART register block structure
sahilmgandhi 18:6a4db94011d3 1357 */
sahilmgandhi 18:6a4db94011d3 1358 #define LPC_USART0_BASE 0x40081000
sahilmgandhi 18:6a4db94011d3 1359 #define LPC_UART1_BASE 0x40082000
sahilmgandhi 18:6a4db94011d3 1360 #define LPC_USART2_BASE 0x400C1000
sahilmgandhi 18:6a4db94011d3 1361 #define LPC_USART3_BASE 0x400C2000
sahilmgandhi 18:6a4db94011d3 1362
sahilmgandhi 18:6a4db94011d3 1363 typedef struct { /* USARTn Structure */
sahilmgandhi 18:6a4db94011d3 1364
sahilmgandhi 18:6a4db94011d3 1365 union {
sahilmgandhi 18:6a4db94011d3 1366 __IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
sahilmgandhi 18:6a4db94011d3 1367 __O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
sahilmgandhi 18:6a4db94011d3 1368 __I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
sahilmgandhi 18:6a4db94011d3 1369 };
sahilmgandhi 18:6a4db94011d3 1370
sahilmgandhi 18:6a4db94011d3 1371 union {
sahilmgandhi 18:6a4db94011d3 1372 __IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
sahilmgandhi 18:6a4db94011d3 1373 __IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
sahilmgandhi 18:6a4db94011d3 1374 };
sahilmgandhi 18:6a4db94011d3 1375
sahilmgandhi 18:6a4db94011d3 1376 union {
sahilmgandhi 18:6a4db94011d3 1377 __O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
sahilmgandhi 18:6a4db94011d3 1378 __I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
sahilmgandhi 18:6a4db94011d3 1379 };
sahilmgandhi 18:6a4db94011d3 1380
sahilmgandhi 18:6a4db94011d3 1381 __IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
sahilmgandhi 18:6a4db94011d3 1382 __IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
sahilmgandhi 18:6a4db94011d3 1383 __I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
sahilmgandhi 18:6a4db94011d3 1384 __I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
sahilmgandhi 18:6a4db94011d3 1385 __IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
sahilmgandhi 18:6a4db94011d3 1386 __IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
sahilmgandhi 18:6a4db94011d3 1387 __IO uint32_t ICR; /* IrDA control register (not all UARTS) */
sahilmgandhi 18:6a4db94011d3 1388 __IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
sahilmgandhi 18:6a4db94011d3 1389 __IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
sahilmgandhi 18:6a4db94011d3 1390 __IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
sahilmgandhi 18:6a4db94011d3 1391 uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 1392 __IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
sahilmgandhi 18:6a4db94011d3 1393 __I uint32_t RESERVED1[1];
sahilmgandhi 18:6a4db94011d3 1394 __IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
sahilmgandhi 18:6a4db94011d3 1395 __IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
sahilmgandhi 18:6a4db94011d3 1396 __IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
sahilmgandhi 18:6a4db94011d3 1397 __IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
sahilmgandhi 18:6a4db94011d3 1398 union {
sahilmgandhi 18:6a4db94011d3 1399 __IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
sahilmgandhi 18:6a4db94011d3 1400 __I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
sahilmgandhi 18:6a4db94011d3 1401 };
sahilmgandhi 18:6a4db94011d3 1402
sahilmgandhi 18:6a4db94011d3 1403 __IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
sahilmgandhi 18:6a4db94011d3 1404 } LPC_USART_T;
sahilmgandhi 18:6a4db94011d3 1405
sahilmgandhi 18:6a4db94011d3 1406 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1407 * SSP register block structure
sahilmgandhi 18:6a4db94011d3 1408 */
sahilmgandhi 18:6a4db94011d3 1409 #define LPC_SSP0_BASE 0x40083000
sahilmgandhi 18:6a4db94011d3 1410 #define LPC_SSP1_BASE 0x400C5000
sahilmgandhi 18:6a4db94011d3 1411
sahilmgandhi 18:6a4db94011d3 1412 typedef struct { /* SSPn Structure */
sahilmgandhi 18:6a4db94011d3 1413 __IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
sahilmgandhi 18:6a4db94011d3 1414 __IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
sahilmgandhi 18:6a4db94011d3 1415 __IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
sahilmgandhi 18:6a4db94011d3 1416 __I uint32_t SR; /* Status Register */
sahilmgandhi 18:6a4db94011d3 1417 __IO uint32_t CPSR; /* Clock Prescale Register */
sahilmgandhi 18:6a4db94011d3 1418 __IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
sahilmgandhi 18:6a4db94011d3 1419 __I uint32_t RIS; /* Raw Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 1420 __I uint32_t MIS; /* Masked Interrupt Status Register */
sahilmgandhi 18:6a4db94011d3 1421 __O uint32_t ICR; /* SSPICR Interrupt Clear Register */
sahilmgandhi 18:6a4db94011d3 1422 __IO uint32_t DMACR; /* SSPn DMA control register */
sahilmgandhi 18:6a4db94011d3 1423 } LPC_SSP_T;
sahilmgandhi 18:6a4db94011d3 1424
sahilmgandhi 18:6a4db94011d3 1425 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1426 * 32-bit Standard timer register block structure
sahilmgandhi 18:6a4db94011d3 1427 */
sahilmgandhi 18:6a4db94011d3 1428 #define LPC_TIMER0_BASE 0x40084000
sahilmgandhi 18:6a4db94011d3 1429 #define LPC_TIMER1_BASE 0x40085000
sahilmgandhi 18:6a4db94011d3 1430 #define LPC_TIMER2_BASE 0x400C3000
sahilmgandhi 18:6a4db94011d3 1431 #define LPC_TIMER3_BASE 0x400C4000
sahilmgandhi 18:6a4db94011d3 1432
sahilmgandhi 18:6a4db94011d3 1433 typedef struct { /* TIMERn Structure */
sahilmgandhi 18:6a4db94011d3 1434 __IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
sahilmgandhi 18:6a4db94011d3 1435 __IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
sahilmgandhi 18:6a4db94011d3 1436 __IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
sahilmgandhi 18:6a4db94011d3 1437 __IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
sahilmgandhi 18:6a4db94011d3 1438 __IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
sahilmgandhi 18:6a4db94011d3 1439 __IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
sahilmgandhi 18:6a4db94011d3 1440 __IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
sahilmgandhi 18:6a4db94011d3 1441 __IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
sahilmgandhi 18:6a4db94011d3 1442 __IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
sahilmgandhi 18:6a4db94011d3 1443 __IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
sahilmgandhi 18:6a4db94011d3 1444 __I uint32_t RESERVED0[12];
sahilmgandhi 18:6a4db94011d3 1445 __IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
sahilmgandhi 18:6a4db94011d3 1446 } LPC_TIMER_T;
sahilmgandhi 18:6a4db94011d3 1447
sahilmgandhi 18:6a4db94011d3 1448 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1449 * System Control Unit register block
sahilmgandhi 18:6a4db94011d3 1450 */
sahilmgandhi 18:6a4db94011d3 1451 #define LPC_SCU_BASE 0x40086000
sahilmgandhi 18:6a4db94011d3 1452
sahilmgandhi 18:6a4db94011d3 1453 typedef struct {
sahilmgandhi 18:6a4db94011d3 1454 __IO uint32_t SFSP[16][32];
sahilmgandhi 18:6a4db94011d3 1455 __I uint32_t RESERVED0[256];
sahilmgandhi 18:6a4db94011d3 1456 __IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
sahilmgandhi 18:6a4db94011d3 1457 __I uint32_t RESERVED16[28];
sahilmgandhi 18:6a4db94011d3 1458 __IO uint32_t SFSUSB; /* Pin configuration register for USB */
sahilmgandhi 18:6a4db94011d3 1459 __IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
sahilmgandhi 18:6a4db94011d3 1460 __IO uint32_t ENAIO[3]; /* Analog function select registers */
sahilmgandhi 18:6a4db94011d3 1461 __I uint32_t RESERVED17[27];
sahilmgandhi 18:6a4db94011d3 1462 __IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
sahilmgandhi 18:6a4db94011d3 1463 __I uint32_t RESERVED18[63];
sahilmgandhi 18:6a4db94011d3 1464 __IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
sahilmgandhi 18:6a4db94011d3 1465 __IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
sahilmgandhi 18:6a4db94011d3 1466 } LPC_SCU_T;
sahilmgandhi 18:6a4db94011d3 1467
sahilmgandhi 18:6a4db94011d3 1468 /*
sahilmgandhi 18:6a4db94011d3 1469 * SCU function and mode selection definitions
sahilmgandhi 18:6a4db94011d3 1470 * See the User Manual for specific modes and functions supoprted by the
sahilmgandhi 18:6a4db94011d3 1471 * various LPC18xx/43xx devices. Functionality can vary per device.
sahilmgandhi 18:6a4db94011d3 1472 */
sahilmgandhi 18:6a4db94011d3 1473 #define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
sahilmgandhi 18:6a4db94011d3 1474 #define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
sahilmgandhi 18:6a4db94011d3 1475 #define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
sahilmgandhi 18:6a4db94011d3 1476 #define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
sahilmgandhi 18:6a4db94011d3 1477 #define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
sahilmgandhi 18:6a4db94011d3 1478 #define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
sahilmgandhi 18:6a4db94011d3 1479 #define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
sahilmgandhi 18:6a4db94011d3 1480 #define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
sahilmgandhi 18:6a4db94011d3 1481 #define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
sahilmgandhi 18:6a4db94011d3 1482 #define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
sahilmgandhi 18:6a4db94011d3 1483 #define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
sahilmgandhi 18:6a4db94011d3 1484
sahilmgandhi 18:6a4db94011d3 1485 #define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
sahilmgandhi 18:6a4db94011d3 1486 #define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
sahilmgandhi 18:6a4db94011d3 1487 #define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
sahilmgandhi 18:6a4db94011d3 1488 #define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
sahilmgandhi 18:6a4db94011d3 1489 #define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
sahilmgandhi 18:6a4db94011d3 1490 #define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
sahilmgandhi 18:6a4db94011d3 1491 #define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
sahilmgandhi 18:6a4db94011d3 1492 #define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
sahilmgandhi 18:6a4db94011d3 1493
sahilmgandhi 18:6a4db94011d3 1494 /* Common SCU configurations */
sahilmgandhi 18:6a4db94011d3 1495 #define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
sahilmgandhi 18:6a4db94011d3 1496 #define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
sahilmgandhi 18:6a4db94011d3 1497 #define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
sahilmgandhi 18:6a4db94011d3 1498 #define SCU_PINIO_PULLNONE (SCU_MODE_INACT | SCU_MODE_INBUFF_EN)
sahilmgandhi 18:6a4db94011d3 1499
sahilmgandhi 18:6a4db94011d3 1500 /* Calculate SCU offset and register address from group and pin number */
sahilmgandhi 18:6a4db94011d3 1501 #define SCU_OFF(group, num) ((group << 7) + (num << 2))
sahilmgandhi 18:6a4db94011d3 1502 #define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
sahilmgandhi 18:6a4db94011d3 1503
sahilmgandhi 18:6a4db94011d3 1504 /**
sahilmgandhi 18:6a4db94011d3 1505 * SCU function and mode selection definitions (old)
sahilmgandhi 18:6a4db94011d3 1506 * For backwards compatibility.
sahilmgandhi 18:6a4db94011d3 1507 */
sahilmgandhi 18:6a4db94011d3 1508 #define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
sahilmgandhi 18:6a4db94011d3 1509 #define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
sahilmgandhi 18:6a4db94011d3 1510 #define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
sahilmgandhi 18:6a4db94011d3 1511 #define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
sahilmgandhi 18:6a4db94011d3 1512 #define MD_EHS (0x1 << 5) /* Enable fast slew rate */
sahilmgandhi 18:6a4db94011d3 1513 #define MD_EZI (0x1 << 6) /* Input buffer enable */
sahilmgandhi 18:6a4db94011d3 1514 #define MD_ZI (0x1 << 7) /* Disable input glitch filter */
sahilmgandhi 18:6a4db94011d3 1515 #define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
sahilmgandhi 18:6a4db94011d3 1516 #define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
sahilmgandhi 18:6a4db94011d3 1517 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
sahilmgandhi 18:6a4db94011d3 1518 #define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
sahilmgandhi 18:6a4db94011d3 1519 #define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
sahilmgandhi 18:6a4db94011d3 1520
sahilmgandhi 18:6a4db94011d3 1521 #define FUNC0 0x0 /* Pin function 0 */
sahilmgandhi 18:6a4db94011d3 1522 #define FUNC1 0x1 /* Pin function 1 */
sahilmgandhi 18:6a4db94011d3 1523 #define FUNC2 0x2 /* Pin function 2 */
sahilmgandhi 18:6a4db94011d3 1524 #define FUNC3 0x3 /* Pin function 3 */
sahilmgandhi 18:6a4db94011d3 1525 #define FUNC4 0x4 /* Pin function 4 */
sahilmgandhi 18:6a4db94011d3 1526 #define FUNC5 0x5 /* Pin function 5 */
sahilmgandhi 18:6a4db94011d3 1527 #define FUNC6 0x6 /* Pin function 6 */
sahilmgandhi 18:6a4db94011d3 1528 #define FUNC7 0x7 /* Pin function 7 */
sahilmgandhi 18:6a4db94011d3 1529
sahilmgandhi 18:6a4db94011d3 1530 #define PORT_OFFSET 0x80 /* Port offset definition */
sahilmgandhi 18:6a4db94011d3 1531 #define PIN_OFFSET 0x04 /* Pin offset definition */
sahilmgandhi 18:6a4db94011d3 1532
sahilmgandhi 18:6a4db94011d3 1533 /* Returns the SFSP register address in the SCU for a pin and port,
sahilmgandhi 18:6a4db94011d3 1534 recommend using (*(volatile int *) &LPC_SCU->SFSP[po][pi];) */
sahilmgandhi 18:6a4db94011d3 1535 #define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
sahilmgandhi 18:6a4db94011d3 1536 (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
sahilmgandhi 18:6a4db94011d3 1537
sahilmgandhi 18:6a4db94011d3 1538 /* Returns the address in the SCU for a SFSCLK clock register,
sahilmgandhi 18:6a4db94011d3 1539 recommend using (*(volatile int *) &LPC_SCU->SFSCLK[c];) */
sahilmgandhi 18:6a4db94011d3 1540 #define LPC_SCU_CLK(LPC_SCU_BASE, c) \
sahilmgandhi 18:6a4db94011d3 1541 (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
sahilmgandhi 18:6a4db94011d3 1542
sahilmgandhi 18:6a4db94011d3 1543 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1544 * GPIO pin interrupt register block structure
sahilmgandhi 18:6a4db94011d3 1545 */
sahilmgandhi 18:6a4db94011d3 1546 #define LPC_GPIO_PIN_INT_BASE 0x40087000
sahilmgandhi 18:6a4db94011d3 1547
sahilmgandhi 18:6a4db94011d3 1548 typedef struct { /* GPIO_PIN_INT Structure */
sahilmgandhi 18:6a4db94011d3 1549 __IO uint32_t ISEL; /* Pin Interrupt Mode register */
sahilmgandhi 18:6a4db94011d3 1550 __IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
sahilmgandhi 18:6a4db94011d3 1551 __O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
sahilmgandhi 18:6a4db94011d3 1552 __O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
sahilmgandhi 18:6a4db94011d3 1553 __IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
sahilmgandhi 18:6a4db94011d3 1554 __O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
sahilmgandhi 18:6a4db94011d3 1555 __O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
sahilmgandhi 18:6a4db94011d3 1556 __IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
sahilmgandhi 18:6a4db94011d3 1557 __IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
sahilmgandhi 18:6a4db94011d3 1558 __IO uint32_t IST; /* Pin Interrupt Status register */
sahilmgandhi 18:6a4db94011d3 1559 } LPC_GPIOPININT_T;
sahilmgandhi 18:6a4db94011d3 1560
sahilmgandhi 18:6a4db94011d3 1561 typedef enum LPC_GPIOPININT_MODE {
sahilmgandhi 18:6a4db94011d3 1562 GPIOPININT_RISING_EDGE = 0x01,
sahilmgandhi 18:6a4db94011d3 1563 GPIOPININT_FALLING_EDGE = 0x02,
sahilmgandhi 18:6a4db94011d3 1564 GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
sahilmgandhi 18:6a4db94011d3 1565 GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
sahilmgandhi 18:6a4db94011d3 1566 } LPC_GPIOPININT_MODE_T;
sahilmgandhi 18:6a4db94011d3 1567
sahilmgandhi 18:6a4db94011d3 1568 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1569 * GPIO grouped interrupt register block structure
sahilmgandhi 18:6a4db94011d3 1570 */
sahilmgandhi 18:6a4db94011d3 1571 #define LPC_GPIO_GROUP_INT0_BASE 0x40088000
sahilmgandhi 18:6a4db94011d3 1572 #define LPC_GPIO_GROUP_INT1_BASE 0x40089000
sahilmgandhi 18:6a4db94011d3 1573
sahilmgandhi 18:6a4db94011d3 1574 typedef struct { /* GPIO_GROUP_INTn Structure */
sahilmgandhi 18:6a4db94011d3 1575 __IO uint32_t CTRL; /* GPIO grouped interrupt control register */
sahilmgandhi 18:6a4db94011d3 1576 __I uint32_t RESERVED0[7];
sahilmgandhi 18:6a4db94011d3 1577 __IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
sahilmgandhi 18:6a4db94011d3 1578 __IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
sahilmgandhi 18:6a4db94011d3 1579 } LPC_GPIOGROUPINT_T;
sahilmgandhi 18:6a4db94011d3 1580
sahilmgandhi 18:6a4db94011d3 1581 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1582 * Motor Control PWM register block structure
sahilmgandhi 18:6a4db94011d3 1583 */
sahilmgandhi 18:6a4db94011d3 1584 #define LPC_MCPWM_BASE 0x400A0000
sahilmgandhi 18:6a4db94011d3 1585
sahilmgandhi 18:6a4db94011d3 1586 typedef struct { /* MCPWM Structure */
sahilmgandhi 18:6a4db94011d3 1587 __I uint32_t CON; /* PWM Control read address */
sahilmgandhi 18:6a4db94011d3 1588 __O uint32_t CON_SET; /* PWM Control set address */
sahilmgandhi 18:6a4db94011d3 1589 __O uint32_t CON_CLR; /* PWM Control clear address */
sahilmgandhi 18:6a4db94011d3 1590 __I uint32_t CAPCON; /* Capture Control read address */
sahilmgandhi 18:6a4db94011d3 1591 __O uint32_t CAPCON_SET; /* Capture Control set address */
sahilmgandhi 18:6a4db94011d3 1592 __O uint32_t CAPCON_CLR; /* Event Control clear address */
sahilmgandhi 18:6a4db94011d3 1593 __IO uint32_t TC[3]; /* Timer Counter register */
sahilmgandhi 18:6a4db94011d3 1594 __IO uint32_t LIM[3]; /* Limit register */
sahilmgandhi 18:6a4db94011d3 1595 __IO uint32_t MAT[3]; /* Match register */
sahilmgandhi 18:6a4db94011d3 1596 __IO uint32_t DT; /* Dead time register */
sahilmgandhi 18:6a4db94011d3 1597 __IO uint32_t CCP; /* Communication Pattern register */
sahilmgandhi 18:6a4db94011d3 1598 __I uint32_t CAP[3]; /* Capture register */
sahilmgandhi 18:6a4db94011d3 1599 __I uint32_t INTEN; /* Interrupt Enable read address */
sahilmgandhi 18:6a4db94011d3 1600 __O uint32_t INTEN_SET; /* Interrupt Enable set address */
sahilmgandhi 18:6a4db94011d3 1601 __O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
sahilmgandhi 18:6a4db94011d3 1602 __I uint32_t CNTCON; /* Count Control read address */
sahilmgandhi 18:6a4db94011d3 1603 __O uint32_t CNTCON_SET; /* Count Control set address */
sahilmgandhi 18:6a4db94011d3 1604 __O uint32_t CNTCON_CLR; /* Count Control clear address */
sahilmgandhi 18:6a4db94011d3 1605 __I uint32_t INTF; /* Interrupt flags read address */
sahilmgandhi 18:6a4db94011d3 1606 __O uint32_t INTF_SET; /* Interrupt flags set address */
sahilmgandhi 18:6a4db94011d3 1607 __O uint32_t INTF_CLR; /* Interrupt flags clear address */
sahilmgandhi 18:6a4db94011d3 1608 __O uint32_t CAP_CLR; /* Capture clear address */
sahilmgandhi 18:6a4db94011d3 1609 } LPC_MCPWM_T;
sahilmgandhi 18:6a4db94011d3 1610
sahilmgandhi 18:6a4db94011d3 1611 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1612 * I2C register block structure
sahilmgandhi 18:6a4db94011d3 1613 */
sahilmgandhi 18:6a4db94011d3 1614 #define LPC_I2C0_BASE 0x400A1000
sahilmgandhi 18:6a4db94011d3 1615 #define LPC_I2C1_BASE 0x400E0000
sahilmgandhi 18:6a4db94011d3 1616
sahilmgandhi 18:6a4db94011d3 1617 typedef struct { /* I2C0 Structure */
sahilmgandhi 18:6a4db94011d3 1618 __IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
sahilmgandhi 18:6a4db94011d3 1619 __I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
sahilmgandhi 18:6a4db94011d3 1620 __IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
sahilmgandhi 18:6a4db94011d3 1621 __IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 1622 __IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
sahilmgandhi 18:6a4db94011d3 1623 __IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
sahilmgandhi 18:6a4db94011d3 1624 __O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
sahilmgandhi 18:6a4db94011d3 1625 __IO uint32_t MMCTRL; /* Monitor mode control register. */
sahilmgandhi 18:6a4db94011d3 1626 __IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 1627 __IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 1628 __IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
sahilmgandhi 18:6a4db94011d3 1629 __I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
sahilmgandhi 18:6a4db94011d3 1630 __IO uint32_t MASK[4]; /* I2C Slave address mask register */
sahilmgandhi 18:6a4db94011d3 1631 } LPC_I2C_T;
sahilmgandhi 18:6a4db94011d3 1632
sahilmgandhi 18:6a4db94011d3 1633 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1634 * I2S register block structure
sahilmgandhi 18:6a4db94011d3 1635 */
sahilmgandhi 18:6a4db94011d3 1636 #define LPC_I2S0_BASE 0x400A2000
sahilmgandhi 18:6a4db94011d3 1637 #define LPC_I2S1_BASE 0x400A3000
sahilmgandhi 18:6a4db94011d3 1638
sahilmgandhi 18:6a4db94011d3 1639 typedef struct { /* I2S Structure */
sahilmgandhi 18:6a4db94011d3 1640 __IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
sahilmgandhi 18:6a4db94011d3 1641 __IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
sahilmgandhi 18:6a4db94011d3 1642 __O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
sahilmgandhi 18:6a4db94011d3 1643 __I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
sahilmgandhi 18:6a4db94011d3 1644 __I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
sahilmgandhi 18:6a4db94011d3 1645 __IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
sahilmgandhi 18:6a4db94011d3 1646 __IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
sahilmgandhi 18:6a4db94011d3 1647 __IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
sahilmgandhi 18:6a4db94011d3 1648 __IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
sahilmgandhi 18:6a4db94011d3 1649 __IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
sahilmgandhi 18:6a4db94011d3 1650 __IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
sahilmgandhi 18:6a4db94011d3 1651 __IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
sahilmgandhi 18:6a4db94011d3 1652 __IO uint32_t TXMODE; /* I2S Transmit mode control */
sahilmgandhi 18:6a4db94011d3 1653 __IO uint32_t RXMODE; /* I2S Receive mode control */
sahilmgandhi 18:6a4db94011d3 1654 } LPC_I2S_T;
sahilmgandhi 18:6a4db94011d3 1655
sahilmgandhi 18:6a4db94011d3 1656 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1657 * CCAN Controller Area Network register block structure
sahilmgandhi 18:6a4db94011d3 1658 */
sahilmgandhi 18:6a4db94011d3 1659 #define LPC_C_CAN1_BASE 0x400A4000
sahilmgandhi 18:6a4db94011d3 1660 #define LPC_C_CAN0_BASE 0x400E2000
sahilmgandhi 18:6a4db94011d3 1661
sahilmgandhi 18:6a4db94011d3 1662 typedef struct { /* C_CAN message interface Structure */
sahilmgandhi 18:6a4db94011d3 1663 __IO uint32_t IF_CMDREQ; /* Message interface command request */
sahilmgandhi 18:6a4db94011d3 1664 union {
sahilmgandhi 18:6a4db94011d3 1665 __IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
sahilmgandhi 18:6a4db94011d3 1666 __IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
sahilmgandhi 18:6a4db94011d3 1667 };
sahilmgandhi 18:6a4db94011d3 1668
sahilmgandhi 18:6a4db94011d3 1669 __IO uint32_t IF_MSK1; /* Message interface mask 1 */
sahilmgandhi 18:6a4db94011d3 1670 __IO uint32_t IF_MSK2; /* Message interface mask 2 */
sahilmgandhi 18:6a4db94011d3 1671 __IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
sahilmgandhi 18:6a4db94011d3 1672 __IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
sahilmgandhi 18:6a4db94011d3 1673 __IO uint32_t IF_MCTRL; /* Message interface message control */
sahilmgandhi 18:6a4db94011d3 1674 __IO uint32_t IF_DA1; /* Message interface data A1 */
sahilmgandhi 18:6a4db94011d3 1675 __IO uint32_t IF_DA2; /* Message interface data A2 */
sahilmgandhi 18:6a4db94011d3 1676 __IO uint32_t IF_DB1; /* Message interface data B1 */
sahilmgandhi 18:6a4db94011d3 1677 __IO uint32_t IF_DB2; /* Message interface data B2 */
sahilmgandhi 18:6a4db94011d3 1678 __I uint32_t RESERVED[13];
sahilmgandhi 18:6a4db94011d3 1679 } LPC_CCAN_IF_T;
sahilmgandhi 18:6a4db94011d3 1680
sahilmgandhi 18:6a4db94011d3 1681 typedef struct { /* C_CAN Structure */
sahilmgandhi 18:6a4db94011d3 1682 __IO uint32_t CNTL; /* CAN control */
sahilmgandhi 18:6a4db94011d3 1683 __IO uint32_t STAT; /* Status register */
sahilmgandhi 18:6a4db94011d3 1684 __I uint32_t EC; /* Error counter */
sahilmgandhi 18:6a4db94011d3 1685 __IO uint32_t BT; /* Bit timing register */
sahilmgandhi 18:6a4db94011d3 1686 __I uint32_t INT; /* Interrupt register */
sahilmgandhi 18:6a4db94011d3 1687 __IO uint32_t TEST; /* Test register */
sahilmgandhi 18:6a4db94011d3 1688 __IO uint32_t BRPE; /* Baud rate prescaler extension register */
sahilmgandhi 18:6a4db94011d3 1689 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1690 LPC_CCAN_IF_T IF[2];
sahilmgandhi 18:6a4db94011d3 1691 __I uint32_t RESERVED2[8];
sahilmgandhi 18:6a4db94011d3 1692 __I uint32_t TXREQ1; /* Transmission request 1 */
sahilmgandhi 18:6a4db94011d3 1693 __I uint32_t TXREQ2; /* Transmission request 2 */
sahilmgandhi 18:6a4db94011d3 1694 __I uint32_t RESERVED3[6];
sahilmgandhi 18:6a4db94011d3 1695 __I uint32_t ND1; /* New data 1 */
sahilmgandhi 18:6a4db94011d3 1696 __I uint32_t ND2; /* New data 2 */
sahilmgandhi 18:6a4db94011d3 1697 __I uint32_t RESERVED4[6];
sahilmgandhi 18:6a4db94011d3 1698 __I uint32_t IR1; /* Interrupt pending 1 */
sahilmgandhi 18:6a4db94011d3 1699 __I uint32_t IR2; /* Interrupt pending 2 */
sahilmgandhi 18:6a4db94011d3 1700 __I uint32_t RESERVED5[6];
sahilmgandhi 18:6a4db94011d3 1701 __I uint32_t MSGV1; /* Message valid 1 */
sahilmgandhi 18:6a4db94011d3 1702 __I uint32_t MSGV2; /* Message valid 2 */
sahilmgandhi 18:6a4db94011d3 1703 __I uint32_t RESERVED6[6];
sahilmgandhi 18:6a4db94011d3 1704 __IO uint32_t CLKDIV; /* CAN clock divider register */
sahilmgandhi 18:6a4db94011d3 1705 } LPC_CCAN_T;
sahilmgandhi 18:6a4db94011d3 1706
sahilmgandhi 18:6a4db94011d3 1707 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1708 * Repetitive Interrupt Timer register block structure
sahilmgandhi 18:6a4db94011d3 1709 */
sahilmgandhi 18:6a4db94011d3 1710 #define LPC_RITIMER_BASE 0x400C0000
sahilmgandhi 18:6a4db94011d3 1711
sahilmgandhi 18:6a4db94011d3 1712 typedef struct { /* RITIMER Structure */
sahilmgandhi 18:6a4db94011d3 1713 __IO uint32_t COMPVAL; /* Compare register */
sahilmgandhi 18:6a4db94011d3 1714 __IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
sahilmgandhi 18:6a4db94011d3 1715 __IO uint32_t CTRL; /* Control register. */
sahilmgandhi 18:6a4db94011d3 1716 __IO uint32_t COUNTER; /* 32-bit counter */
sahilmgandhi 18:6a4db94011d3 1717 } LPC_RITIMER_T;
sahilmgandhi 18:6a4db94011d3 1718
sahilmgandhi 18:6a4db94011d3 1719 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1720 * Quadrature Encoder Interface register block structure
sahilmgandhi 18:6a4db94011d3 1721 */
sahilmgandhi 18:6a4db94011d3 1722 #define LPC_QEI_BASE 0x400C6000
sahilmgandhi 18:6a4db94011d3 1723
sahilmgandhi 18:6a4db94011d3 1724 typedef struct { /* QEI Structure */
sahilmgandhi 18:6a4db94011d3 1725 __O uint32_t CON; /* Control register */
sahilmgandhi 18:6a4db94011d3 1726 __I uint32_t STAT; /* Encoder status register */
sahilmgandhi 18:6a4db94011d3 1727 __IO uint32_t CONF; /* Configuration register */
sahilmgandhi 18:6a4db94011d3 1728 __I uint32_t POS; /* Position register */
sahilmgandhi 18:6a4db94011d3 1729 __IO uint32_t MAXPOS; /* Maximum position register */
sahilmgandhi 18:6a4db94011d3 1730 __IO uint32_t CMPOS0; /* position compare register 0 */
sahilmgandhi 18:6a4db94011d3 1731 __IO uint32_t CMPOS1; /* position compare register 1 */
sahilmgandhi 18:6a4db94011d3 1732 __IO uint32_t CMPOS2; /* position compare register 2 */
sahilmgandhi 18:6a4db94011d3 1733 __I uint32_t INXCNT; /* Index count register */
sahilmgandhi 18:6a4db94011d3 1734 __IO uint32_t INXCMP0; /* Index compare register 0 */
sahilmgandhi 18:6a4db94011d3 1735 __IO uint32_t LOAD; /* Velocity timer reload register */
sahilmgandhi 18:6a4db94011d3 1736 __I uint32_t TIME; /* Velocity timer register */
sahilmgandhi 18:6a4db94011d3 1737 __I uint32_t VEL; /* Velocity counter register */
sahilmgandhi 18:6a4db94011d3 1738 __I uint32_t CAP; /* Velocity capture register */
sahilmgandhi 18:6a4db94011d3 1739 __IO uint32_t VELCOMP; /* Velocity compare register */
sahilmgandhi 18:6a4db94011d3 1740 __IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
sahilmgandhi 18:6a4db94011d3 1741 __IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
sahilmgandhi 18:6a4db94011d3 1742 __IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
sahilmgandhi 18:6a4db94011d3 1743 __IO uint32_t WINDOW; /* Index acceptance window register */
sahilmgandhi 18:6a4db94011d3 1744 __IO uint32_t INXCMP1; /* Index compare register 1 */
sahilmgandhi 18:6a4db94011d3 1745 __IO uint32_t INXCMP2; /* Index compare register 2 */
sahilmgandhi 18:6a4db94011d3 1746 __I uint32_t RESERVED0[993];
sahilmgandhi 18:6a4db94011d3 1747 __O uint32_t IEC; /* Interrupt enable clear register */
sahilmgandhi 18:6a4db94011d3 1748 __O uint32_t IES; /* Interrupt enable set register */
sahilmgandhi 18:6a4db94011d3 1749 __I uint32_t INTSTAT; /* Interrupt status register */
sahilmgandhi 18:6a4db94011d3 1750 __I uint32_t IE; /* Interrupt enable register */
sahilmgandhi 18:6a4db94011d3 1751 __O uint32_t CLR; /* Interrupt status clear register */
sahilmgandhi 18:6a4db94011d3 1752 __O uint32_t SET; /* Interrupt status set register */
sahilmgandhi 18:6a4db94011d3 1753 } LPC_QEI_T;
sahilmgandhi 18:6a4db94011d3 1754
sahilmgandhi 18:6a4db94011d3 1755 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1756 * Global Input Multiplexer Array (GIMA) register block structure
sahilmgandhi 18:6a4db94011d3 1757 */
sahilmgandhi 18:6a4db94011d3 1758 #define LPC_GIMA_BASE 0x400C7000
sahilmgandhi 18:6a4db94011d3 1759
sahilmgandhi 18:6a4db94011d3 1760 typedef struct { /* GIMA Structure */
sahilmgandhi 18:6a4db94011d3 1761 __IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x*4)+y)) */
sahilmgandhi 18:6a4db94011d3 1762 __IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
sahilmgandhi 18:6a4db94011d3 1763 __IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
sahilmgandhi 18:6a4db94011d3 1764 __IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
sahilmgandhi 18:6a4db94011d3 1765 __IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
sahilmgandhi 18:6a4db94011d3 1766 __IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
sahilmgandhi 18:6a4db94011d3 1767 __IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
sahilmgandhi 18:6a4db94011d3 1768 __IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
sahilmgandhi 18:6a4db94011d3 1769 } LPC_GIMA_T;
sahilmgandhi 18:6a4db94011d3 1770
sahilmgandhi 18:6a4db94011d3 1771 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1772 * DAC register block structure
sahilmgandhi 18:6a4db94011d3 1773 */
sahilmgandhi 18:6a4db94011d3 1774 #define LPC_DAC_BASE 0x400E1000
sahilmgandhi 18:6a4db94011d3 1775
sahilmgandhi 18:6a4db94011d3 1776 typedef struct { /* DAC Structure */
sahilmgandhi 18:6a4db94011d3 1777 __IO uint32_t CR; /* DAC register. Holds the conversion data. */
sahilmgandhi 18:6a4db94011d3 1778 __IO uint32_t CTRL; /* DAC control register. */
sahilmgandhi 18:6a4db94011d3 1779 __IO uint32_t CNTVAL; /* DAC counter value register. */
sahilmgandhi 18:6a4db94011d3 1780 } LPC_DAC_T;
sahilmgandhi 18:6a4db94011d3 1781
sahilmgandhi 18:6a4db94011d3 1782 /* After the selected settling time after this field is written with a
sahilmgandhi 18:6a4db94011d3 1783 * new VALUE, the voltage on the AOUT pin (with respect to VSSA)
sahilmgandhi 18:6a4db94011d3 1784 * is VALUE/1024 ? VREF
sahilmgandhi 18:6a4db94011d3 1785 */
sahilmgandhi 18:6a4db94011d3 1786 #define DAC_RANGE 0x3FF
sahilmgandhi 18:6a4db94011d3 1787 #define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
sahilmgandhi 18:6a4db94011d3 1788 #define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
sahilmgandhi 18:6a4db94011d3 1789 #define DAC_VALUE(n) DAC_SET(n)
sahilmgandhi 18:6a4db94011d3 1790 /* If this bit = 0: The settling time of the DAC is 1 microsecond max,
sahilmgandhi 18:6a4db94011d3 1791 * and the maximum current is 700 microAmpere
sahilmgandhi 18:6a4db94011d3 1792 * If this bit = 1: The settling time of the DAC is 2.5 microsecond
sahilmgandhi 18:6a4db94011d3 1793 * and the maximum current is 350 microAmpere
sahilmgandhi 18:6a4db94011d3 1794 */
sahilmgandhi 18:6a4db94011d3 1795 #define DAC_BIAS_EN ((uint32_t) (1 << 16))
sahilmgandhi 18:6a4db94011d3 1796 /* Value to reload interrupt DMA counter */
sahilmgandhi 18:6a4db94011d3 1797 #define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
sahilmgandhi 18:6a4db94011d3 1798
sahilmgandhi 18:6a4db94011d3 1799 #define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
sahilmgandhi 18:6a4db94011d3 1800 #define DAC_CNT_ENA ((uint32_t) (1 << 2))
sahilmgandhi 18:6a4db94011d3 1801 #define DAC_DMA_ENA ((uint32_t) (1 << 3))
sahilmgandhi 18:6a4db94011d3 1802 #define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
sahilmgandhi 18:6a4db94011d3 1803
sahilmgandhi 18:6a4db94011d3 1804 /* Current option in DAC configuration option */
sahilmgandhi 18:6a4db94011d3 1805 typedef enum DAC_CURRENT_OPT {
sahilmgandhi 18:6a4db94011d3 1806 DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
sahilmgandhi 18:6a4db94011d3 1807 allows for a maximum update rate of 1 MHz */
sahilmgandhi 18:6a4db94011d3 1808 DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
sahilmgandhi 18:6a4db94011d3 1809 allows for a maximum update rate of 400 kHz */
sahilmgandhi 18:6a4db94011d3 1810 } DAC_CURRENT_OPT_T;
sahilmgandhi 18:6a4db94011d3 1811
sahilmgandhi 18:6a4db94011d3 1812 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1813 * ADC register block structure
sahilmgandhi 18:6a4db94011d3 1814 */
sahilmgandhi 18:6a4db94011d3 1815 #define LPC_ADC0_BASE 0x400E3000
sahilmgandhi 18:6a4db94011d3 1816 #define LPC_ADC1_BASE 0x400E4000
sahilmgandhi 18:6a4db94011d3 1817 #define ADC_ACC_10BITS
sahilmgandhi 18:6a4db94011d3 1818
sahilmgandhi 18:6a4db94011d3 1819 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1820 * 10 or 12-bit ADC register block structure
sahilmgandhi 18:6a4db94011d3 1821 */
sahilmgandhi 18:6a4db94011d3 1822 typedef struct { /* ADCn Structure */
sahilmgandhi 18:6a4db94011d3 1823 __IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
sahilmgandhi 18:6a4db94011d3 1824 __I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
sahilmgandhi 18:6a4db94011d3 1825 __I uint32_t RESERVED0;
sahilmgandhi 18:6a4db94011d3 1826 __IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
sahilmgandhi 18:6a4db94011d3 1827 __I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
sahilmgandhi 18:6a4db94011d3 1828 __I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
sahilmgandhi 18:6a4db94011d3 1829 } LPC_ADC_T;
sahilmgandhi 18:6a4db94011d3 1830
sahilmgandhi 18:6a4db94011d3 1831 /* ADC register support bitfields and mask */
sahilmgandhi 18:6a4db94011d3 1832 #define ADC_RANGE 0x3FF
sahilmgandhi 18:6a4db94011d3 1833 #define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
sahilmgandhi 18:6a4db94011d3 1834 #define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
sahilmgandhi 18:6a4db94011d3 1835 #define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
sahilmgandhi 18:6a4db94011d3 1836 #define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
sahilmgandhi 18:6a4db94011d3 1837 #define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
sahilmgandhi 18:6a4db94011d3 1838 #define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
sahilmgandhi 18:6a4db94011d3 1839 #define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
sahilmgandhi 18:6a4db94011d3 1840 #define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
sahilmgandhi 18:6a4db94011d3 1841 #define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
sahilmgandhi 18:6a4db94011d3 1842 #define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
sahilmgandhi 18:6a4db94011d3 1843 #define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
sahilmgandhi 18:6a4db94011d3 1844 #define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
sahilmgandhi 18:6a4db94011d3 1845 #define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
sahilmgandhi 18:6a4db94011d3 1846 #define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
sahilmgandhi 18:6a4db94011d3 1847 #define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
sahilmgandhi 18:6a4db94011d3 1848 #define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
sahilmgandhi 18:6a4db94011d3 1849 #define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
sahilmgandhi 18:6a4db94011d3 1850 #define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07) | ADC_CR_PDN)
sahilmgandhi 18:6a4db94011d3 1851
sahilmgandhi 18:6a4db94011d3 1852 /* ADC status register used for IP drivers */
sahilmgandhi 18:6a4db94011d3 1853 typedef enum ADC_STATUS {
sahilmgandhi 18:6a4db94011d3 1854 ADC_DR_DONE_STAT, /* ADC data register staus */
sahilmgandhi 18:6a4db94011d3 1855 ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
sahilmgandhi 18:6a4db94011d3 1856 ADC_DR_ADINT_STAT /* ADC interrupt status */
sahilmgandhi 18:6a4db94011d3 1857 } ADC_STATUS_T;
sahilmgandhi 18:6a4db94011d3 1858
sahilmgandhi 18:6a4db94011d3 1859 /** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
sahilmgandhi 18:6a4db94011d3 1860 typedef enum ADC_START_MODE {
sahilmgandhi 18:6a4db94011d3 1861 ADC_NO_START = 0,
sahilmgandhi 18:6a4db94011d3 1862 ADC_START_NOW, /* Start conversion now */
sahilmgandhi 18:6a4db94011d3 1863 ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
sahilmgandhi 18:6a4db94011d3 1864 ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
sahilmgandhi 18:6a4db94011d3 1865 ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
sahilmgandhi 18:6a4db94011d3 1866 ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
sahilmgandhi 18:6a4db94011d3 1867 ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
sahilmgandhi 18:6a4db94011d3 1868 } ADC_START_MODE_T;
sahilmgandhi 18:6a4db94011d3 1869
sahilmgandhi 18:6a4db94011d3 1870 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1871 * GPIO port register block structure
sahilmgandhi 18:6a4db94011d3 1872 */
sahilmgandhi 18:6a4db94011d3 1873 #define LPC_GPIO_PORT_BASE 0x400F4000
sahilmgandhi 18:6a4db94011d3 1874 #define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
sahilmgandhi 18:6a4db94011d3 1875 #define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
sahilmgandhi 18:6a4db94011d3 1876 #define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
sahilmgandhi 18:6a4db94011d3 1877 #define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
sahilmgandhi 18:6a4db94011d3 1878 #define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
sahilmgandhi 18:6a4db94011d3 1879 #define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
sahilmgandhi 18:6a4db94011d3 1880 #define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
sahilmgandhi 18:6a4db94011d3 1881 #define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
sahilmgandhi 18:6a4db94011d3 1882
sahilmgandhi 18:6a4db94011d3 1883 typedef struct { /* GPIO_PORT Structure */
sahilmgandhi 18:6a4db94011d3 1884 __IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
sahilmgandhi 18:6a4db94011d3 1885 __IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
sahilmgandhi 18:6a4db94011d3 1886 __IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
sahilmgandhi 18:6a4db94011d3 1887 __IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
sahilmgandhi 18:6a4db94011d3 1888 __IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
sahilmgandhi 18:6a4db94011d3 1889 __IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
sahilmgandhi 18:6a4db94011d3 1890 __IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
sahilmgandhi 18:6a4db94011d3 1891 __O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
sahilmgandhi 18:6a4db94011d3 1892 __O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
sahilmgandhi 18:6a4db94011d3 1893 } LPC_GPIO_T;
sahilmgandhi 18:6a4db94011d3 1894
sahilmgandhi 18:6a4db94011d3 1895 /* Calculate GPIO offset and port register address from group and pin number */
sahilmgandhi 18:6a4db94011d3 1896 #define GPIO_OFF(port, pin) ((port << 5) + pin)
sahilmgandhi 18:6a4db94011d3 1897 #define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
sahilmgandhi 18:6a4db94011d3 1898
sahilmgandhi 18:6a4db94011d3 1899 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1900 * SPI register block structure
sahilmgandhi 18:6a4db94011d3 1901 */
sahilmgandhi 18:6a4db94011d3 1902 #define LPC_SPI_BASE 0x40100000
sahilmgandhi 18:6a4db94011d3 1903
sahilmgandhi 18:6a4db94011d3 1904 typedef struct { /* SPI Structure */
sahilmgandhi 18:6a4db94011d3 1905 __IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
sahilmgandhi 18:6a4db94011d3 1906 __I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
sahilmgandhi 18:6a4db94011d3 1907 __IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
sahilmgandhi 18:6a4db94011d3 1908 __IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
sahilmgandhi 18:6a4db94011d3 1909 __I uint32_t RESERVED0[3];
sahilmgandhi 18:6a4db94011d3 1910 __IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
sahilmgandhi 18:6a4db94011d3 1911 } LPC_SPI_T;
sahilmgandhi 18:6a4db94011d3 1912
sahilmgandhi 18:6a4db94011d3 1913 /* SPI CFG Register BitMask */
sahilmgandhi 18:6a4db94011d3 1914 #define SPI_CR_BITMASK ((uint32_t) 0xFFC)
sahilmgandhi 18:6a4db94011d3 1915 /* Enable of controlling the number of bits per transfer */
sahilmgandhi 18:6a4db94011d3 1916 #define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
sahilmgandhi 18:6a4db94011d3 1917 /* Mask of field of bit controlling */
sahilmgandhi 18:6a4db94011d3 1918 #define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
sahilmgandhi 18:6a4db94011d3 1919 /* Set the number of bits per a transfer */
sahilmgandhi 18:6a4db94011d3 1920 #define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
sahilmgandhi 18:6a4db94011d3 1921 /* SPI Clock Phase Select*/
sahilmgandhi 18:6a4db94011d3 1922 #define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
sahilmgandhi 18:6a4db94011d3 1923 #define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
sahilmgandhi 18:6a4db94011d3 1924 /* SPI Clock Polarity Select*/
sahilmgandhi 18:6a4db94011d3 1925 #define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
sahilmgandhi 18:6a4db94011d3 1926 #define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
sahilmgandhi 18:6a4db94011d3 1927 /* SPI Slave Mode Select */
sahilmgandhi 18:6a4db94011d3 1928 #define SPI_CR_SLAVE_EN ((uint32_t) 0)
sahilmgandhi 18:6a4db94011d3 1929 /* SPI Master Mode Select */
sahilmgandhi 18:6a4db94011d3 1930 #define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
sahilmgandhi 18:6a4db94011d3 1931 /* SPI MSB First mode enable */
sahilmgandhi 18:6a4db94011d3 1932 #define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
sahilmgandhi 18:6a4db94011d3 1933 /* SPI LSB First mode enable */
sahilmgandhi 18:6a4db94011d3 1934 #define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
sahilmgandhi 18:6a4db94011d3 1935 /* SPI interrupt enable */
sahilmgandhi 18:6a4db94011d3 1936 #define SPI_CR_INT_EN ((uint32_t) (1 << 7))
sahilmgandhi 18:6a4db94011d3 1937 /* SPI STAT Register BitMask */
sahilmgandhi 18:6a4db94011d3 1938 #define SPI_SR_BITMASK ((uint32_t) 0xF8)
sahilmgandhi 18:6a4db94011d3 1939 /* Slave abort Flag */
sahilmgandhi 18:6a4db94011d3 1940 #define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
sahilmgandhi 18:6a4db94011d3 1941 /* Mode fault Flag */
sahilmgandhi 18:6a4db94011d3 1942 #define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
sahilmgandhi 18:6a4db94011d3 1943 /* Read overrun flag*/
sahilmgandhi 18:6a4db94011d3 1944 #define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
sahilmgandhi 18:6a4db94011d3 1945 /* Write collision flag. */
sahilmgandhi 18:6a4db94011d3 1946 #define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
sahilmgandhi 18:6a4db94011d3 1947 /* SPI transfer complete flag. */
sahilmgandhi 18:6a4db94011d3 1948 #define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
sahilmgandhi 18:6a4db94011d3 1949 /* SPI error flag */
sahilmgandhi 18:6a4db94011d3 1950 #define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
sahilmgandhi 18:6a4db94011d3 1951 /* Enable SPI Test Mode */
sahilmgandhi 18:6a4db94011d3 1952 #define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
sahilmgandhi 18:6a4db94011d3 1953 /* SPI interrupt flag */
sahilmgandhi 18:6a4db94011d3 1954 #define SPI_INT_SPIF ((uint32_t) (1 << 0))
sahilmgandhi 18:6a4db94011d3 1955 /* Receiver Data */
sahilmgandhi 18:6a4db94011d3 1956 #define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
sahilmgandhi 18:6a4db94011d3 1957
sahilmgandhi 18:6a4db94011d3 1958 /* SPI Mode*/
sahilmgandhi 18:6a4db94011d3 1959 typedef enum LPC_SPI_MODE {
sahilmgandhi 18:6a4db94011d3 1960 SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
sahilmgandhi 18:6a4db94011d3 1961 SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
sahilmgandhi 18:6a4db94011d3 1962 } LPC_SPI_MODE_T;
sahilmgandhi 18:6a4db94011d3 1963
sahilmgandhi 18:6a4db94011d3 1964 /* SPI Clock Mode*/
sahilmgandhi 18:6a4db94011d3 1965 typedef enum LPC_SPI_CLOCK_MODE {
sahilmgandhi 18:6a4db94011d3 1966 SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
sahilmgandhi 18:6a4db94011d3 1967 SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
sahilmgandhi 18:6a4db94011d3 1968 SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
sahilmgandhi 18:6a4db94011d3 1969 SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
sahilmgandhi 18:6a4db94011d3 1970 SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
sahilmgandhi 18:6a4db94011d3 1971 SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
sahilmgandhi 18:6a4db94011d3 1972 SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
sahilmgandhi 18:6a4db94011d3 1973 SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
sahilmgandhi 18:6a4db94011d3 1974 } LPC_SPI_CLOCK_MODE_T;
sahilmgandhi 18:6a4db94011d3 1975
sahilmgandhi 18:6a4db94011d3 1976 /* SPI Data Order Mode*/
sahilmgandhi 18:6a4db94011d3 1977 typedef enum LPC_SPI_DATA_ORDER {
sahilmgandhi 18:6a4db94011d3 1978 SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
sahilmgandhi 18:6a4db94011d3 1979 SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
sahilmgandhi 18:6a4db94011d3 1980 } LPC_SPI_DATA_ORDER_T;
sahilmgandhi 18:6a4db94011d3 1981
sahilmgandhi 18:6a4db94011d3 1982 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 1983 * Serial GPIO register block structure
sahilmgandhi 18:6a4db94011d3 1984 */
sahilmgandhi 18:6a4db94011d3 1985 #define LPC_SGPIO_BASE 0x40101000
sahilmgandhi 18:6a4db94011d3 1986
sahilmgandhi 18:6a4db94011d3 1987 typedef struct { /* SGPIO Structure */
sahilmgandhi 18:6a4db94011d3 1988 __IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
sahilmgandhi 18:6a4db94011d3 1989 __IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
sahilmgandhi 18:6a4db94011d3 1990 __IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
sahilmgandhi 18:6a4db94011d3 1991 __IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
sahilmgandhi 18:6a4db94011d3 1992 __IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
sahilmgandhi 18:6a4db94011d3 1993 __IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
sahilmgandhi 18:6a4db94011d3 1994 __IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
sahilmgandhi 18:6a4db94011d3 1995 __IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
sahilmgandhi 18:6a4db94011d3 1996 __IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
sahilmgandhi 18:6a4db94011d3 1997 __IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
sahilmgandhi 18:6a4db94011d3 1998 __IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
sahilmgandhi 18:6a4db94011d3 1999 __IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
sahilmgandhi 18:6a4db94011d3 2000 __I uint32_t GPIO_INREG; /* GPIO input status register */
sahilmgandhi 18:6a4db94011d3 2001 __IO uint32_t GPIO_OUTREG; /* GPIO output control register */
sahilmgandhi 18:6a4db94011d3 2002 __IO uint32_t GPIO_OENREG; /* GPIO OE control register */
sahilmgandhi 18:6a4db94011d3 2003 __IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
sahilmgandhi 18:6a4db94011d3 2004 __IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
sahilmgandhi 18:6a4db94011d3 2005 __I uint32_t RESERVED0[823];
sahilmgandhi 18:6a4db94011d3 2006 __O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
sahilmgandhi 18:6a4db94011d3 2007 __O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
sahilmgandhi 18:6a4db94011d3 2008 __I uint32_t ENABLE_0; /* Shift clock interrupt enable */
sahilmgandhi 18:6a4db94011d3 2009 __I uint32_t STATUS_0; /* Shift clock interrupt status */
sahilmgandhi 18:6a4db94011d3 2010 __O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
sahilmgandhi 18:6a4db94011d3 2011 __O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
sahilmgandhi 18:6a4db94011d3 2012 __I uint32_t RESERVED1[2];
sahilmgandhi 18:6a4db94011d3 2013 __O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
sahilmgandhi 18:6a4db94011d3 2014 __O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
sahilmgandhi 18:6a4db94011d3 2015 __I uint32_t ENABLE_1; /* Capture clock interrupt enable */
sahilmgandhi 18:6a4db94011d3 2016 __I uint32_t STATUS_1; /* Capture clock interrupt status */
sahilmgandhi 18:6a4db94011d3 2017 __O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
sahilmgandhi 18:6a4db94011d3 2018 __O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
sahilmgandhi 18:6a4db94011d3 2019 __I uint32_t RESERVED2[2];
sahilmgandhi 18:6a4db94011d3 2020 __O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
sahilmgandhi 18:6a4db94011d3 2021 __O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
sahilmgandhi 18:6a4db94011d3 2022 __I uint32_t ENABLE_2; /* Pattern match interrupt enable */
sahilmgandhi 18:6a4db94011d3 2023 __I uint32_t STATUS_2; /* Pattern match interrupt status */
sahilmgandhi 18:6a4db94011d3 2024 __O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
sahilmgandhi 18:6a4db94011d3 2025 __O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
sahilmgandhi 18:6a4db94011d3 2026 __I uint32_t RESERVED3[2];
sahilmgandhi 18:6a4db94011d3 2027 __O uint32_t CLR_EN_3; /* Input interrupt clear mask */
sahilmgandhi 18:6a4db94011d3 2028 __O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
sahilmgandhi 18:6a4db94011d3 2029 __I uint32_t ENABLE_3; /* Input bit match interrupt enable */
sahilmgandhi 18:6a4db94011d3 2030 __I uint32_t STATUS_3; /* Input bit match interrupt status */
sahilmgandhi 18:6a4db94011d3 2031 __O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
sahilmgandhi 18:6a4db94011d3 2032 __O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
sahilmgandhi 18:6a4db94011d3 2033 } LPC_SGPIO_T;
sahilmgandhi 18:6a4db94011d3 2034
sahilmgandhi 18:6a4db94011d3 2035 /* End of section using anonymous unions */
sahilmgandhi 18:6a4db94011d3 2036 #if defined(__ARMCC_VERSION)
sahilmgandhi 18:6a4db94011d3 2037 #pragma pop
sahilmgandhi 18:6a4db94011d3 2038 #elif defined(__CWCC__)
sahilmgandhi 18:6a4db94011d3 2039 #pragma pop
sahilmgandhi 18:6a4db94011d3 2040 #elif defined(__IAR_SYSTEMS_ICC__)
sahilmgandhi 18:6a4db94011d3 2041 //#pragma pop // FIXME not usable for IAR
sahilmgandhi 18:6a4db94011d3 2042 #else /* defined(__GNUC__) and others */
sahilmgandhi 18:6a4db94011d3 2043 /* Leave anonymous unions enabled */
sahilmgandhi 18:6a4db94011d3 2044 #endif
sahilmgandhi 18:6a4db94011d3 2045
sahilmgandhi 18:6a4db94011d3 2046 /* ---------------------------------------------------------------------------
sahilmgandhi 18:6a4db94011d3 2047 * LPC43xx Peripheral register set declarations
sahilmgandhi 18:6a4db94011d3 2048 */
sahilmgandhi 18:6a4db94011d3 2049 #define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
sahilmgandhi 18:6a4db94011d3 2050 #define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
sahilmgandhi 18:6a4db94011d3 2051 #define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
sahilmgandhi 18:6a4db94011d3 2052 #define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
sahilmgandhi 18:6a4db94011d3 2053 #define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
sahilmgandhi 18:6a4db94011d3 2054 #define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
sahilmgandhi 18:6a4db94011d3 2055 #define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
sahilmgandhi 18:6a4db94011d3 2056 #define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
sahilmgandhi 18:6a4db94011d3 2057 #define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
sahilmgandhi 18:6a4db94011d3 2058 #define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
sahilmgandhi 18:6a4db94011d3 2059 #define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
sahilmgandhi 18:6a4db94011d3 2060 #define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
sahilmgandhi 18:6a4db94011d3 2061 #define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
sahilmgandhi 18:6a4db94011d3 2062 #define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
sahilmgandhi 18:6a4db94011d3 2063 #define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
sahilmgandhi 18:6a4db94011d3 2064 #define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
sahilmgandhi 18:6a4db94011d3 2065 #define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
sahilmgandhi 18:6a4db94011d3 2066 #define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
sahilmgandhi 18:6a4db94011d3 2067 #define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
sahilmgandhi 18:6a4db94011d3 2068 #define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
sahilmgandhi 18:6a4db94011d3 2069 #define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
sahilmgandhi 18:6a4db94011d3 2070 #define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
sahilmgandhi 18:6a4db94011d3 2071 #define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
sahilmgandhi 18:6a4db94011d3 2072 #define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
sahilmgandhi 18:6a4db94011d3 2073 #define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
sahilmgandhi 18:6a4db94011d3 2074 #define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
sahilmgandhi 18:6a4db94011d3 2075 #define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
sahilmgandhi 18:6a4db94011d3 2076 #define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
sahilmgandhi 18:6a4db94011d3 2077 #define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
sahilmgandhi 18:6a4db94011d3 2078 #define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
sahilmgandhi 18:6a4db94011d3 2079 #define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
sahilmgandhi 18:6a4db94011d3 2080 #define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
sahilmgandhi 18:6a4db94011d3 2081 #define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
sahilmgandhi 18:6a4db94011d3 2082 #define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
sahilmgandhi 18:6a4db94011d3 2083 #define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
sahilmgandhi 18:6a4db94011d3 2084 #define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
sahilmgandhi 18:6a4db94011d3 2085 #define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
sahilmgandhi 18:6a4db94011d3 2086 #define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
sahilmgandhi 18:6a4db94011d3 2087 #define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
sahilmgandhi 18:6a4db94011d3 2088 #define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
sahilmgandhi 18:6a4db94011d3 2089 #define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
sahilmgandhi 18:6a4db94011d3 2090 #define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
sahilmgandhi 18:6a4db94011d3 2091 #define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
sahilmgandhi 18:6a4db94011d3 2092 #define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
sahilmgandhi 18:6a4db94011d3 2093 #define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
sahilmgandhi 18:6a4db94011d3 2094 #define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
sahilmgandhi 18:6a4db94011d3 2095 #define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
sahilmgandhi 18:6a4db94011d3 2096 #define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
sahilmgandhi 18:6a4db94011d3 2097 #define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
sahilmgandhi 18:6a4db94011d3 2098 #define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
sahilmgandhi 18:6a4db94011d3 2099 #define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
sahilmgandhi 18:6a4db94011d3 2100 #define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
sahilmgandhi 18:6a4db94011d3 2101 #define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
sahilmgandhi 18:6a4db94011d3 2102 #define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
sahilmgandhi 18:6a4db94011d3 2103 #define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
sahilmgandhi 18:6a4db94011d3 2104 #define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
sahilmgandhi 18:6a4db94011d3 2105 #define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
sahilmgandhi 18:6a4db94011d3 2106 #define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
sahilmgandhi 18:6a4db94011d3 2107 #define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
sahilmgandhi 18:6a4db94011d3 2108
sahilmgandhi 18:6a4db94011d3 2109 #ifdef __cplusplus
sahilmgandhi 18:6a4db94011d3 2110 }
sahilmgandhi 18:6a4db94011d3 2111 #endif
sahilmgandhi 18:6a4db94011d3 2112
sahilmgandhi 18:6a4db94011d3 2113 #endif /* __LPC43XX_H */