MacroRat / MouseCode

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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32600/serial_api.c@46:b156ef445742, 2017-06-03 (annotated)

Committer:
sahilmgandhi
Date:
Sat Jun 03 00:22:44 2017 +0000
Revision:
46:b156ef445742
Parent:
18:6a4db94011d3 
Final code for internal battlebot competition.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
sahilmgandhi 18:6a4db94011d3 5 * copy of this software and associated documentation files (the "Software"),
sahilmgandhi 18:6a4db94011d3 6 * to deal in the Software without restriction, including without limitation
sahilmgandhi 18:6a4db94011d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
sahilmgandhi 18:6a4db94011d3 8 * and/or sell copies of the Software, and to permit persons to whom the
sahilmgandhi 18:6a4db94011d3 9 * Software is furnished to do so, subject to the following conditions:
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * The above copyright notice and this permission notice shall be included
sahilmgandhi 18:6a4db94011d3 12 * in all copies or substantial portions of the Software.
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
sahilmgandhi 18:6a4db94011d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
sahilmgandhi 18:6a4db94011d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
sahilmgandhi 18:6a4db94011d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
sahilmgandhi 18:6a4db94011d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
sahilmgandhi 18:6a4db94011d3 20 * OTHER DEALINGS IN THE SOFTWARE.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * Except as contained in this notice, the name of Maxim Integrated
sahilmgandhi 18:6a4db94011d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
sahilmgandhi 18:6a4db94011d3 24 * Products, Inc. Branding Policy.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * The mere transfer of this software does not imply any licenses
sahilmgandhi 18:6a4db94011d3 27 * of trade secrets, proprietary technology, copyrights, patents,
sahilmgandhi 18:6a4db94011d3 28 * trademarks, maskwork rights, or any other form of intellectual
sahilmgandhi 18:6a4db94011d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
sahilmgandhi 18:6a4db94011d3 30 * ownership rights.
sahilmgandhi 18:6a4db94011d3 31 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #include <string.h>
sahilmgandhi 18:6a4db94011d3 35 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 36 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 37 #include "serial_api.h"
sahilmgandhi 18:6a4db94011d3 38 #include "gpio_api.h"
sahilmgandhi 18:6a4db94011d3 39 #include "uart_regs.h"
sahilmgandhi 18:6a4db94011d3 40 #include "ioman_regs.h"
sahilmgandhi 18:6a4db94011d3 41 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 42
sahilmgandhi 18:6a4db94011d3 43 #define UART_NUM 2
sahilmgandhi 18:6a4db94011d3 44 #define DEFAULT_BAUD 9600
sahilmgandhi 18:6a4db94011d3 45 #define DEFAULT_STOP 1
sahilmgandhi 18:6a4db94011d3 46 #define DEFAULT_PARITY ParityNone
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 #define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAME_ERROR | \
sahilmgandhi 18:6a4db94011d3 49 MXC_F_UART_INTFL_RX_PARITY_ERROR | \
sahilmgandhi 18:6a4db94011d3 50 MXC_F_UART_INTFL_RX_OVERRUN)
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 // Variables for managing the stdio UART
sahilmgandhi 18:6a4db94011d3 53 int stdio_uart_inited;
sahilmgandhi 18:6a4db94011d3 54 serial_t stdio_uart;
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56 // Variables for interrupt driven
sahilmgandhi 18:6a4db94011d3 57 static uart_irq_handler irq_handler;
sahilmgandhi 18:6a4db94011d3 58 static uint32_t serial_irq_ids[UART_NUM];
sahilmgandhi 18:6a4db94011d3 59
sahilmgandhi 18:6a4db94011d3 60 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 61 void serial_init(serial_t *obj, PinName tx, PinName rx)
sahilmgandhi 18:6a4db94011d3 62 {
sahilmgandhi 18:6a4db94011d3 63 // Determine which uart is associated with each pin
sahilmgandhi 18:6a4db94011d3 64 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 65 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
sahilmgandhi 18:6a4db94011d3 66 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
sahilmgandhi 18:6a4db94011d3 67
sahilmgandhi 18:6a4db94011d3 68 // Make sure that both pins are pointing to the same uart
sahilmgandhi 18:6a4db94011d3 69 MBED_ASSERT(uart != (UARTName)NC);
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 // Set the obj pointer to the proper uart
sahilmgandhi 18:6a4db94011d3 72 obj->uart = (mxc_uart_regs_t*)uart;
sahilmgandhi 18:6a4db94011d3 73
sahilmgandhi 18:6a4db94011d3 74 // Set the uart index
sahilmgandhi 18:6a4db94011d3 75 obj->index = MXC_UART_BASE_TO_INSTANCE(obj->uart);
sahilmgandhi 18:6a4db94011d3 76
sahilmgandhi 18:6a4db94011d3 77 // Configure the pins
sahilmgandhi 18:6a4db94011d3 78 pinmap_pinout(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 79 pinmap_pinout(rx, PinMap_UART_RX);
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 // Flush the RX and TX FIFOs, clear the settings
sahilmgandhi 18:6a4db94011d3 82 obj->uart->ctrl = ( MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH);
sahilmgandhi 18:6a4db94011d3 83
sahilmgandhi 18:6a4db94011d3 84 // Disable interrupts
sahilmgandhi 18:6a4db94011d3 85 obj->uart->inten = 0;
sahilmgandhi 18:6a4db94011d3 86 obj->uart->intfl = 0;
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 // Configure to default settings
sahilmgandhi 18:6a4db94011d3 89 serial_baud(obj, DEFAULT_BAUD);
sahilmgandhi 18:6a4db94011d3 90 serial_format(obj, 8, ParityNone, 1);
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 // Manage stdio UART
sahilmgandhi 18:6a4db94011d3 93 if(uart == STDIO_UART) {
sahilmgandhi 18:6a4db94011d3 94 stdio_uart_inited = 1;
sahilmgandhi 18:6a4db94011d3 95 memcpy(&stdio_uart, obj, sizeof(serial_t));
sahilmgandhi 18:6a4db94011d3 96 }
sahilmgandhi 18:6a4db94011d3 97 }
sahilmgandhi 18:6a4db94011d3 98
sahilmgandhi 18:6a4db94011d3 99 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 100 void serial_baud(serial_t *obj, int baudrate)
sahilmgandhi 18:6a4db94011d3 101 {
sahilmgandhi 18:6a4db94011d3 102 uint32_t idiv = 0, ddiv = 0, div = 0;
sahilmgandhi 18:6a4db94011d3 103
sahilmgandhi 18:6a4db94011d3 104 // Calculate the integer and decimal portions
sahilmgandhi 18:6a4db94011d3 105 div = SystemCoreClock / ((baudrate / 100) * 128);
sahilmgandhi 18:6a4db94011d3 106 idiv = (div / 100);
sahilmgandhi 18:6a4db94011d3 107 ddiv = (div - idiv * 100) * 128 / 100;
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 obj->uart->baud_int = idiv;
sahilmgandhi 18:6a4db94011d3 110 obj->uart->baud_div_128 = ddiv;
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 // Enable the baud clock
sahilmgandhi 18:6a4db94011d3 113 obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN;
sahilmgandhi 18:6a4db94011d3 114 }
sahilmgandhi 18:6a4db94011d3 115
sahilmgandhi 18:6a4db94011d3 116 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 117 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
sahilmgandhi 18:6a4db94011d3 118 {
sahilmgandhi 18:6a4db94011d3 119
sahilmgandhi 18:6a4db94011d3 120 // Check the validity of the inputs
sahilmgandhi 18:6a4db94011d3 121 MBED_ASSERT((data_bits > 4) && (data_bits < 9));
sahilmgandhi 18:6a4db94011d3 122 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) ||
sahilmgandhi 18:6a4db94011d3 123 (parity == ParityEven) || (parity == ParityForced1) ||
sahilmgandhi 18:6a4db94011d3 124 (parity == ParityForced0));
sahilmgandhi 18:6a4db94011d3 125 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
sahilmgandhi 18:6a4db94011d3 126
sahilmgandhi 18:6a4db94011d3 127 // Adjust the stop and data bits
sahilmgandhi 18:6a4db94011d3 128 stop_bits -= 1;
sahilmgandhi 18:6a4db94011d3 129 data_bits -= 5;
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 // Adjust the parity setting
sahilmgandhi 18:6a4db94011d3 132 int paren = 0, mode = 0;
sahilmgandhi 18:6a4db94011d3 133 switch (parity) {
sahilmgandhi 18:6a4db94011d3 134 case ParityNone:
sahilmgandhi 18:6a4db94011d3 135 paren = 0;
sahilmgandhi 18:6a4db94011d3 136 mode = 0;
sahilmgandhi 18:6a4db94011d3 137 break;
sahilmgandhi 18:6a4db94011d3 138 case ParityOdd :
sahilmgandhi 18:6a4db94011d3 139 paren = 1;
sahilmgandhi 18:6a4db94011d3 140 mode = 0;
sahilmgandhi 18:6a4db94011d3 141 break;
sahilmgandhi 18:6a4db94011d3 142 case ParityEven:
sahilmgandhi 18:6a4db94011d3 143 paren = 1;
sahilmgandhi 18:6a4db94011d3 144 mode = 1;
sahilmgandhi 18:6a4db94011d3 145 break;
sahilmgandhi 18:6a4db94011d3 146 case ParityForced1:
sahilmgandhi 18:6a4db94011d3 147 // Hardware does not support forced parity
sahilmgandhi 18:6a4db94011d3 148 MBED_ASSERT(0);
sahilmgandhi 18:6a4db94011d3 149 break;
sahilmgandhi 18:6a4db94011d3 150 case ParityForced0:
sahilmgandhi 18:6a4db94011d3 151 // Hardware does not support forced parity
sahilmgandhi 18:6a4db94011d3 152 MBED_ASSERT(0);
sahilmgandhi 18:6a4db94011d3 153 break;
sahilmgandhi 18:6a4db94011d3 154 default:
sahilmgandhi 18:6a4db94011d3 155 paren = 1;
sahilmgandhi 18:6a4db94011d3 156 mode = 0;
sahilmgandhi 18:6a4db94011d3 157 break;
sahilmgandhi 18:6a4db94011d3 158 }
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 obj->uart->ctrl |= ((data_bits << MXC_F_UART_CTRL_CHAR_LENGTH_POS) |
sahilmgandhi 18:6a4db94011d3 161 (stop_bits << MXC_F_UART_CTRL_STOP_BIT_MODE_POS) |
sahilmgandhi 18:6a4db94011d3 162 (paren << MXC_F_UART_CTRL_PARITY_ENABLE_POS) |
sahilmgandhi 18:6a4db94011d3 163 (mode << MXC_F_UART_CTRL_PARITY_MODE_POS));
sahilmgandhi 18:6a4db94011d3 164 }
sahilmgandhi 18:6a4db94011d3 165
sahilmgandhi 18:6a4db94011d3 166 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 167 void uart_handler(mxc_uart_regs_t* uart, int id)
sahilmgandhi 18:6a4db94011d3 168 {
sahilmgandhi 18:6a4db94011d3 169 // Check for errors or RX Threshold
sahilmgandhi 18:6a4db94011d3 170 if(uart->intfl & (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS)) {
sahilmgandhi 18:6a4db94011d3 171 irq_handler(serial_irq_ids[id], RxIrq);
sahilmgandhi 18:6a4db94011d3 172 uart->intfl &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS);
sahilmgandhi 18:6a4db94011d3 173 }
sahilmgandhi 18:6a4db94011d3 174
sahilmgandhi 18:6a4db94011d3 175 // Check for TX Threshold
sahilmgandhi 18:6a4db94011d3 176 if(uart->intfl & MXC_F_UART_INTFL_TX_ALMOST_EMPTY) {
sahilmgandhi 18:6a4db94011d3 177 irq_handler(serial_irq_ids[id], TxIrq);
sahilmgandhi 18:6a4db94011d3 178 uart->intfl &= ~(MXC_F_UART_INTFL_TX_ALMOST_EMPTY);
sahilmgandhi 18:6a4db94011d3 179 }
sahilmgandhi 18:6a4db94011d3 180 }
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 void uart0_handler(void)
sahilmgandhi 18:6a4db94011d3 183 {
sahilmgandhi 18:6a4db94011d3 184 uart_handler(MXC_UART0, 0);
sahilmgandhi 18:6a4db94011d3 185 }
sahilmgandhi 18:6a4db94011d3 186 void uart1_handler(void)
sahilmgandhi 18:6a4db94011d3 187 {
sahilmgandhi 18:6a4db94011d3 188 uart_handler(MXC_UART1, 1);
sahilmgandhi 18:6a4db94011d3 189 }
sahilmgandhi 18:6a4db94011d3 190
sahilmgandhi 18:6a4db94011d3 191 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 192 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
sahilmgandhi 18:6a4db94011d3 193 {
sahilmgandhi 18:6a4db94011d3 194 irq_handler = handler;
sahilmgandhi 18:6a4db94011d3 195 serial_irq_ids[obj->index] = id;
sahilmgandhi 18:6a4db94011d3 196 }
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 199 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
sahilmgandhi 18:6a4db94011d3 200 {
sahilmgandhi 18:6a4db94011d3 201 if(obj->index == 0) {
sahilmgandhi 18:6a4db94011d3 202 NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
sahilmgandhi 18:6a4db94011d3 203 NVIC_EnableIRQ(UART0_IRQn);
sahilmgandhi 18:6a4db94011d3 204 } else {
sahilmgandhi 18:6a4db94011d3 205 NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler);
sahilmgandhi 18:6a4db94011d3 206 NVIC_EnableIRQ(UART1_IRQn);
sahilmgandhi 18:6a4db94011d3 207 }
sahilmgandhi 18:6a4db94011d3 208
sahilmgandhi 18:6a4db94011d3 209 if(irq == RxIrq) {
sahilmgandhi 18:6a4db94011d3 210 // Set the RX FIFO Threshold to 1
sahilmgandhi 18:6a4db94011d3 211 obj->uart->ctrl &= ~MXC_F_UART_CTRL_RX_THRESHOLD;
sahilmgandhi 18:6a4db94011d3 212 obj->uart->ctrl |= 0x1;
sahilmgandhi 18:6a4db94011d3 213 // Enable RX FIFO Threshold Interrupt
sahilmgandhi 18:6a4db94011d3 214 if(enable) {
sahilmgandhi 18:6a4db94011d3 215 // Clear pending interrupts
sahilmgandhi 18:6a4db94011d3 216 obj->uart->intfl = 0;
sahilmgandhi 18:6a4db94011d3 217 obj->uart->inten |= (MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
sahilmgandhi 18:6a4db94011d3 218 UART_ERRORS);
sahilmgandhi 18:6a4db94011d3 219 } else {
sahilmgandhi 18:6a4db94011d3 220 // Clear pending interrupts
sahilmgandhi 18:6a4db94011d3 221 obj->uart->intfl = 0;
sahilmgandhi 18:6a4db94011d3 222 obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
sahilmgandhi 18:6a4db94011d3 223 UART_ERRORS);
sahilmgandhi 18:6a4db94011d3 224 }
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 } else if (irq == TxIrq) {
sahilmgandhi 18:6a4db94011d3 227 // Enable TX Almost empty Interrupt
sahilmgandhi 18:6a4db94011d3 228 if(enable) {
sahilmgandhi 18:6a4db94011d3 229 // Clear pending interrupts
sahilmgandhi 18:6a4db94011d3 230 obj->uart->intfl = 0;
sahilmgandhi 18:6a4db94011d3 231 obj->uart->inten |= MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
sahilmgandhi 18:6a4db94011d3 232 } else {
sahilmgandhi 18:6a4db94011d3 233 // Clear pending interrupts
sahilmgandhi 18:6a4db94011d3 234 obj->uart->intfl = 0;
sahilmgandhi 18:6a4db94011d3 235 obj->uart->inten &= ~MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
sahilmgandhi 18:6a4db94011d3 236 }
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 } else {
sahilmgandhi 18:6a4db94011d3 239 MBED_ASSERT(0);
sahilmgandhi 18:6a4db94011d3 240 }
sahilmgandhi 18:6a4db94011d3 241 }
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243
sahilmgandhi 18:6a4db94011d3 244 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 245 int serial_getc(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 246 {
sahilmgandhi 18:6a4db94011d3 247 int c;
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 // Wait for data to be available
sahilmgandhi 18:6a4db94011d3 250 while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {}
sahilmgandhi 18:6a4db94011d3 251 c = obj->uart->tx_rx_fifo & 0xFF;
sahilmgandhi 18:6a4db94011d3 252
sahilmgandhi 18:6a4db94011d3 253 return c;
sahilmgandhi 18:6a4db94011d3 254 }
sahilmgandhi 18:6a4db94011d3 255
sahilmgandhi 18:6a4db94011d3 256 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 257 void serial_putc(serial_t *obj, int c)
sahilmgandhi 18:6a4db94011d3 258 {
sahilmgandhi 18:6a4db94011d3 259 // Wait for TXFIFO to not be full
sahilmgandhi 18:6a4db94011d3 260 while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
sahilmgandhi 18:6a4db94011d3 261 obj->uart->tx_rx_fifo = c;
sahilmgandhi 18:6a4db94011d3 262 }
sahilmgandhi 18:6a4db94011d3 263
sahilmgandhi 18:6a4db94011d3 264 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 265 int serial_readable(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 266 {
sahilmgandhi 18:6a4db94011d3 267 return (!(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY));
sahilmgandhi 18:6a4db94011d3 268 }
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 271 int serial_writable(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 272 {
sahilmgandhi 18:6a4db94011d3 273 return (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL));
sahilmgandhi 18:6a4db94011d3 274 }
sahilmgandhi 18:6a4db94011d3 275
sahilmgandhi 18:6a4db94011d3 276 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 277 void serial_clear(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 278 {
sahilmgandhi 18:6a4db94011d3 279 // Clear the rx and tx fifos
sahilmgandhi 18:6a4db94011d3 280 obj->uart->ctrl |= (MXC_F_UART_CTRL_TX_FIFO_FLUSH | MXC_F_UART_CTRL_RX_FIFO_FLUSH );
sahilmgandhi 18:6a4db94011d3 281 }
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 284 void serial_break_set(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 285 {
sahilmgandhi 18:6a4db94011d3 286 // Make sure that nothing is being sent
sahilmgandhi 18:6a4db94011d3 287 while (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_EMPTY));
sahilmgandhi 18:6a4db94011d3 288 while (obj->uart->status & MXC_F_UART_STATUS_TX_BUSY);
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 // Configure the GPIO to outpu 0
sahilmgandhi 18:6a4db94011d3 291 gpio_t tx_gpio;
sahilmgandhi 18:6a4db94011d3 292 switch (((UARTName)(obj->uart))) {
sahilmgandhi 18:6a4db94011d3 293 case UART_0:
sahilmgandhi 18:6a4db94011d3 294 gpio_init_out(&tx_gpio, UART0_TX);
sahilmgandhi 18:6a4db94011d3 295 break;
sahilmgandhi 18:6a4db94011d3 296 case UART_1:
sahilmgandhi 18:6a4db94011d3 297 gpio_init_out(&tx_gpio, UART1_TX);
sahilmgandhi 18:6a4db94011d3 298 break;
sahilmgandhi 18:6a4db94011d3 299 default:
sahilmgandhi 18:6a4db94011d3 300 gpio_init_out(&tx_gpio, (PinName)NC);
sahilmgandhi 18:6a4db94011d3 301 break;
sahilmgandhi 18:6a4db94011d3 302 }
sahilmgandhi 18:6a4db94011d3 303
sahilmgandhi 18:6a4db94011d3 304 gpio_write(&tx_gpio, 0);
sahilmgandhi 18:6a4db94011d3 305
sahilmgandhi 18:6a4db94011d3 306 // GPIO is setup now, but we need to maps gpio to the pin
sahilmgandhi 18:6a4db94011d3 307 switch (((UARTName)(obj->uart))) {
sahilmgandhi 18:6a4db94011d3 308 case UART_0:
sahilmgandhi 18:6a4db94011d3 309 MXC_IOMAN->uart0_req &= ~MXC_F_IOMAN_UART_CORE_IO;
sahilmgandhi 18:6a4db94011d3 310 MBED_ASSERT((MXC_IOMAN->uart0_ack & (MXC_F_IOMAN_UART_CORE_IO | MXC_F_IOMAN_UART_CORE_IO)) == 0);
sahilmgandhi 18:6a4db94011d3 311 break;
sahilmgandhi 18:6a4db94011d3 312 case UART_1:
sahilmgandhi 18:6a4db94011d3 313 MXC_IOMAN->uart1_req &= ~MXC_F_IOMAN_UART_CORE_IO;
sahilmgandhi 18:6a4db94011d3 314 MBED_ASSERT((MXC_IOMAN->uart1_ack & (MXC_F_IOMAN_UART_CORE_IO | MXC_F_IOMAN_UART_CORE_IO)) == 0);
sahilmgandhi 18:6a4db94011d3 315 break;
sahilmgandhi 18:6a4db94011d3 316 default:
sahilmgandhi 18:6a4db94011d3 317 break;
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319 }
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 322 void serial_break_clear(serial_t *obj)
sahilmgandhi 18:6a4db94011d3 323 {
sahilmgandhi 18:6a4db94011d3 324 // Configure the GPIO to output 1
sahilmgandhi 18:6a4db94011d3 325 gpio_t tx_gpio;
sahilmgandhi 18:6a4db94011d3 326 switch (((UARTName)(obj->uart))) {
sahilmgandhi 18:6a4db94011d3 327 case UART_0:
sahilmgandhi 18:6a4db94011d3 328 gpio_init_out(&tx_gpio, UART0_TX);
sahilmgandhi 18:6a4db94011d3 329 break;
sahilmgandhi 18:6a4db94011d3 330 case UART_1:
sahilmgandhi 18:6a4db94011d3 331 gpio_init_out(&tx_gpio, UART1_TX);
sahilmgandhi 18:6a4db94011d3 332 break;
sahilmgandhi 18:6a4db94011d3 333 default:
sahilmgandhi 18:6a4db94011d3 334 gpio_init_out(&tx_gpio, (PinName)NC);
sahilmgandhi 18:6a4db94011d3 335 break;
sahilmgandhi 18:6a4db94011d3 336 }
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 gpio_write(&tx_gpio, 1);
sahilmgandhi 18:6a4db94011d3 339
sahilmgandhi 18:6a4db94011d3 340 // Renable UART
sahilmgandhi 18:6a4db94011d3 341 switch (((UARTName)(obj->uart))) {
sahilmgandhi 18:6a4db94011d3 342 case UART_0:
sahilmgandhi 18:6a4db94011d3 343 serial_pinout_tx(UART0_TX);
sahilmgandhi 18:6a4db94011d3 344 break;
sahilmgandhi 18:6a4db94011d3 345 case UART_1:
sahilmgandhi 18:6a4db94011d3 346 serial_pinout_tx(UART1_TX);
sahilmgandhi 18:6a4db94011d3 347 break;
sahilmgandhi 18:6a4db94011d3 348 default:
sahilmgandhi 18:6a4db94011d3 349 serial_pinout_tx((PinName)NC);
sahilmgandhi 18:6a4db94011d3 350 break;
sahilmgandhi 18:6a4db94011d3 351 }
sahilmgandhi 18:6a4db94011d3 352 }
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 355 void serial_pinout_tx(PinName tx)
sahilmgandhi 18:6a4db94011d3 356 {
sahilmgandhi 18:6a4db94011d3 357 pinmap_pinout(tx, PinMap_UART_TX);
sahilmgandhi 18:6a4db94011d3 358 }
sahilmgandhi 18:6a4db94011d3 359
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 362 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
sahilmgandhi 18:6a4db94011d3 363 {
sahilmgandhi 18:6a4db94011d3 364 if(FlowControlNone == type) {
sahilmgandhi 18:6a4db94011d3 365 // Disable hardware flow control
sahilmgandhi 18:6a4db94011d3 366 obj->uart->ctrl &= ~(MXC_F_UART_CTRL_HW_FLOW_CTRL_EN);
sahilmgandhi 18:6a4db94011d3 367 return;
sahilmgandhi 18:6a4db94011d3 368 }
sahilmgandhi 18:6a4db94011d3 369
sahilmgandhi 18:6a4db94011d3 370 // Check to see if we can use HW flow control
sahilmgandhi 18:6a4db94011d3 371 UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
sahilmgandhi 18:6a4db94011d3 372 UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
sahilmgandhi 18:6a4db94011d3 373 UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
sahilmgandhi 18:6a4db94011d3 374
sahilmgandhi 18:6a4db94011d3 375 if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) {
sahilmgandhi 18:6a4db94011d3 376 // Make sure pin is in the PinMap
sahilmgandhi 18:6a4db94011d3 377 MBED_ASSERT(uart_cts != (UARTName)NC);
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 // Enable the pin for CTS function
sahilmgandhi 18:6a4db94011d3 380 pinmap_pinout(txflow, PinMap_UART_CTS);
sahilmgandhi 18:6a4db94011d3 381 }
sahilmgandhi 18:6a4db94011d3 382
sahilmgandhi 18:6a4db94011d3 383 if((FlowControlRTS == type) || (FlowControlRTSCTS== type)) {
sahilmgandhi 18:6a4db94011d3 384 // Make sure pin is in the PinMap
sahilmgandhi 18:6a4db94011d3 385 MBED_ASSERT(uart_rts != (UARTName)NC);
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 // Enable the pin for RTS function
sahilmgandhi 18:6a4db94011d3 388 pinmap_pinout(rxflow, PinMap_UART_RTS);
sahilmgandhi 18:6a4db94011d3 389 }
sahilmgandhi 18:6a4db94011d3 390
sahilmgandhi 18:6a4db94011d3 391 if(FlowControlRTSCTS == type){
sahilmgandhi 18:6a4db94011d3 392 // Make sure that the pins are pointing to the same UART
sahilmgandhi 18:6a4db94011d3 393 MBED_ASSERT(uart != (UARTName)NC);
sahilmgandhi 18:6a4db94011d3 394 }
sahilmgandhi 18:6a4db94011d3 395
sahilmgandhi 18:6a4db94011d3 396 // Enable hardware flow control
sahilmgandhi 18:6a4db94011d3 397 obj->uart->ctrl |= MXC_F_UART_CTRL_HW_FLOW_CTRL_EN;
sahilmgandhi 18:6a4db94011d3 398 }