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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /**
sahilmgandhi 18:6a4db94011d3 2 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 3 * @file stm32l1xx_hal_spi.c
sahilmgandhi 18:6a4db94011d3 4 * @author MCD Application Team
sahilmgandhi 18:6a4db94011d3 5 * @version V1.2.0
sahilmgandhi 18:6a4db94011d3 6 * @date 01-July-2016
sahilmgandhi 18:6a4db94011d3 7 * @brief SPI HAL module driver.
sahilmgandhi 18:6a4db94011d3 8 *
sahilmgandhi 18:6a4db94011d3 9 * This file provides firmware functions to manage the following
sahilmgandhi 18:6a4db94011d3 10 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
sahilmgandhi 18:6a4db94011d3 11 * + Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 12 * + IO operation functions
sahilmgandhi 18:6a4db94011d3 13 * + Peripheral Control functions
sahilmgandhi 18:6a4db94011d3 14 * + Peripheral State functions
sahilmgandhi 18:6a4db94011d3 15 @verbatim
sahilmgandhi 18:6a4db94011d3 16 ==============================================================================
sahilmgandhi 18:6a4db94011d3 17 ##### How to use this driver #####
sahilmgandhi 18:6a4db94011d3 18 ==============================================================================
sahilmgandhi 18:6a4db94011d3 19 [..]
sahilmgandhi 18:6a4db94011d3 20 The SPI HAL driver can be used as follows:
sahilmgandhi 18:6a4db94011d3 21
sahilmgandhi 18:6a4db94011d3 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
sahilmgandhi 18:6a4db94011d3 23 SPI_HandleTypeDef hspi;
sahilmgandhi 18:6a4db94011d3 24
sahilmgandhi 18:6a4db94011d3 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
sahilmgandhi 18:6a4db94011d3 26 (##) Enable the SPIx interface clock
sahilmgandhi 18:6a4db94011d3 27 (##) SPI pins configuration
sahilmgandhi 18:6a4db94011d3 28 (+++) Enable the clock for the SPI GPIOs
sahilmgandhi 18:6a4db94011d3 29 (+++) Configure these SPI pins as alternate function push-pull
sahilmgandhi 18:6a4db94011d3 30 (##) NVIC configuration if you need to use interrupt process
sahilmgandhi 18:6a4db94011d3 31 (+++) Configure the SPIx interrupt priority
sahilmgandhi 18:6a4db94011d3 32 (+++) Enable the NVIC SPI IRQ handle
sahilmgandhi 18:6a4db94011d3 33 (##) DMA Configuration if you need to use DMA process
sahilmgandhi 18:6a4db94011d3 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
sahilmgandhi 18:6a4db94011d3 35 (+++) Enable the DMAx clock
sahilmgandhi 18:6a4db94011d3 36 (+++) Configure the DMA handle parameters
sahilmgandhi 18:6a4db94011d3 37 (+++) Configure the DMA Tx or Rx Channel
sahilmgandhi 18:6a4db94011d3 38 (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
sahilmgandhi 18:6a4db94011d3 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
sahilmgandhi 18:6a4db94011d3 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
sahilmgandhi 18:6a4db94011d3 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
sahilmgandhi 18:6a4db94011d3 46 by calling the customed HAL_SPI_MspInit() API.
sahilmgandhi 18:6a4db94011d3 47 [..]
sahilmgandhi 18:6a4db94011d3 48 Circular mode restriction:
sahilmgandhi 18:6a4db94011d3 49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
sahilmgandhi 18:6a4db94011d3 50 (##) Master 2Lines RxOnly
sahilmgandhi 18:6a4db94011d3 51 (##) Master 1Line Rx
sahilmgandhi 18:6a4db94011d3 52 (#) The CRC feature is not managed when the DMA circular mode is enabled
sahilmgandhi 18:6a4db94011d3 53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
sahilmgandhi 18:6a4db94011d3 54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
sahilmgandhi 18:6a4db94011d3 55
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57
sahilmgandhi 18:6a4db94011d3 58 @endverbatim
sahilmgandhi 18:6a4db94011d3 59 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 60 * @attention
sahilmgandhi 18:6a4db94011d3 61 *
sahilmgandhi 18:6a4db94011d3 62 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
sahilmgandhi 18:6a4db94011d3 63 *
sahilmgandhi 18:6a4db94011d3 64 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 65 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 66 * 1. Redistributions of source code must retain the above copyright notice,
sahilmgandhi 18:6a4db94011d3 67 * this list of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 68 * 2. Redistributions in binary form must reproduce the above copyright notice,
sahilmgandhi 18:6a4db94011d3 69 * this list of conditions and the following disclaimer in the documentation
sahilmgandhi 18:6a4db94011d3 70 * and/or other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 71 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sahilmgandhi 18:6a4db94011d3 72 * may be used to endorse or promote products derived from this software
sahilmgandhi 18:6a4db94011d3 73 * without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 74 *
sahilmgandhi 18:6a4db94011d3 75 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sahilmgandhi 18:6a4db94011d3 76 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sahilmgandhi 18:6a4db94011d3 77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 78 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sahilmgandhi 18:6a4db94011d3 79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sahilmgandhi 18:6a4db94011d3 80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sahilmgandhi 18:6a4db94011d3 81 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sahilmgandhi 18:6a4db94011d3 82 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sahilmgandhi 18:6a4db94011d3 83 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sahilmgandhi 18:6a4db94011d3 84 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 85 *
sahilmgandhi 18:6a4db94011d3 86 ******************************************************************************
sahilmgandhi 18:6a4db94011d3 87 */
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 /* Includes ------------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 90 #include "stm32l1xx_hal.h"
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /** @addtogroup STM32L1xx_HAL_Driver
sahilmgandhi 18:6a4db94011d3 93 * @{
sahilmgandhi 18:6a4db94011d3 94 */
sahilmgandhi 18:6a4db94011d3 95
sahilmgandhi 18:6a4db94011d3 96 /** @defgroup SPI SPI
sahilmgandhi 18:6a4db94011d3 97 * @brief SPI HAL module driver
sahilmgandhi 18:6a4db94011d3 98 * @{
sahilmgandhi 18:6a4db94011d3 99 */
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 #ifdef HAL_SPI_MODULE_ENABLED
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 /* Private typedef -----------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 104 /* Private define ------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 105 /** @defgroup SPI_Private_Constants SPI Private Constants
sahilmgandhi 18:6a4db94011d3 106 * @{
sahilmgandhi 18:6a4db94011d3 107 */
sahilmgandhi 18:6a4db94011d3 108 #define SPI_TIMEOUT_VALUE 10
sahilmgandhi 18:6a4db94011d3 109 #define SPI_DEFAULT_TIMEOUT 100U
sahilmgandhi 18:6a4db94011d3 110
sahilmgandhi 18:6a4db94011d3 111 /**
sahilmgandhi 18:6a4db94011d3 112 * @}
sahilmgandhi 18:6a4db94011d3 113 */
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 /* Private macro -------------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 116 /* Private variables ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 117 /* Private function prototypes -----------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 118 /** @defgroup SPI_Private_Functions SPI Private Functions
sahilmgandhi 18:6a4db94011d3 119 * @{
sahilmgandhi 18:6a4db94011d3 120 */
sahilmgandhi 18:6a4db94011d3 121 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
sahilmgandhi 18:6a4db94011d3 122 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 123 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 124 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 125 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 126 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 127 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 128 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 129 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 130 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 131 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 132 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 133 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 134 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 135 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 136 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 137 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 138 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
sahilmgandhi 18:6a4db94011d3 139 static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 140 static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 141 static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 142 static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 143 static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 144 static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 145 static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma);
sahilmgandhi 18:6a4db94011d3 146 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
sahilmgandhi 18:6a4db94011d3 147 /**
sahilmgandhi 18:6a4db94011d3 148 * @}
sahilmgandhi 18:6a4db94011d3 149 */
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /* Exported functions ---------------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 152
sahilmgandhi 18:6a4db94011d3 153 /** @defgroup SPI_Exported_Functions SPI Exported Functions
sahilmgandhi 18:6a4db94011d3 154 * @{
sahilmgandhi 18:6a4db94011d3 155 */
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
sahilmgandhi 18:6a4db94011d3 158 * @brief Initialization and Configuration functions
sahilmgandhi 18:6a4db94011d3 159 *
sahilmgandhi 18:6a4db94011d3 160 @verbatim
sahilmgandhi 18:6a4db94011d3 161 ===============================================================================
sahilmgandhi 18:6a4db94011d3 162 ##### Initialization and de-initialization functions #####
sahilmgandhi 18:6a4db94011d3 163 ===============================================================================
sahilmgandhi 18:6a4db94011d3 164 [..] This subsection provides a set of functions allowing to initialize and
sahilmgandhi 18:6a4db94011d3 165 de-initialiaze the SPIx peripheral:
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 (+) User must implement HAL_SPI_MspInit() function in which he configures
sahilmgandhi 18:6a4db94011d3 168 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
sahilmgandhi 18:6a4db94011d3 169
sahilmgandhi 18:6a4db94011d3 170 (+) Call the function HAL_SPI_Init() to configure the selected device with
sahilmgandhi 18:6a4db94011d3 171 the selected configuration:
sahilmgandhi 18:6a4db94011d3 172 (++) Mode
sahilmgandhi 18:6a4db94011d3 173 (++) Direction
sahilmgandhi 18:6a4db94011d3 174 (++) Data Size
sahilmgandhi 18:6a4db94011d3 175 (++) Clock Polarity and Phase
sahilmgandhi 18:6a4db94011d3 176 (++) NSS Management
sahilmgandhi 18:6a4db94011d3 177 (++) BaudRate Prescaler
sahilmgandhi 18:6a4db94011d3 178 (++) FirstBit
sahilmgandhi 18:6a4db94011d3 179 (++) TIMode
sahilmgandhi 18:6a4db94011d3 180 (++) CRC Calculation
sahilmgandhi 18:6a4db94011d3 181 (++) CRC Polynomial if CRC enabled
sahilmgandhi 18:6a4db94011d3 182
sahilmgandhi 18:6a4db94011d3 183 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
sahilmgandhi 18:6a4db94011d3 184 of the selected SPIx periperal.
sahilmgandhi 18:6a4db94011d3 185
sahilmgandhi 18:6a4db94011d3 186 @endverbatim
sahilmgandhi 18:6a4db94011d3 187 * @{
sahilmgandhi 18:6a4db94011d3 188 */
sahilmgandhi 18:6a4db94011d3 189
sahilmgandhi 18:6a4db94011d3 190 /**
sahilmgandhi 18:6a4db94011d3 191 * @brief Initializes the SPI according to the specified parameters
sahilmgandhi 18:6a4db94011d3 192 * in the SPI_InitTypeDef and create the associated handle.
sahilmgandhi 18:6a4db94011d3 193 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 194 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 195 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 196 */
sahilmgandhi 18:6a4db94011d3 197 __weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 198 {
sahilmgandhi 18:6a4db94011d3 199 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 200 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 203 }
sahilmgandhi 18:6a4db94011d3 204
sahilmgandhi 18:6a4db94011d3 205 /**
sahilmgandhi 18:6a4db94011d3 206 * @brief DeInitializes the SPI peripheral
sahilmgandhi 18:6a4db94011d3 207 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 208 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 209 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 210 */
sahilmgandhi 18:6a4db94011d3 211 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 212 {
sahilmgandhi 18:6a4db94011d3 213 /* Check the SPI handle allocation */
sahilmgandhi 18:6a4db94011d3 214 if(hspi == NULL)
sahilmgandhi 18:6a4db94011d3 215 {
sahilmgandhi 18:6a4db94011d3 216 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 217 }
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 /* Disable the SPI Peripheral Clock */
sahilmgandhi 18:6a4db94011d3 220 __HAL_SPI_DISABLE(hspi);
sahilmgandhi 18:6a4db94011d3 221
sahilmgandhi 18:6a4db94011d3 222 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
sahilmgandhi 18:6a4db94011d3 223 HAL_SPI_MspDeInit(hspi);
sahilmgandhi 18:6a4db94011d3 224
sahilmgandhi 18:6a4db94011d3 225 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 226 hspi->State = HAL_SPI_STATE_RESET;
sahilmgandhi 18:6a4db94011d3 227
sahilmgandhi 18:6a4db94011d3 228 /* Release Lock */
sahilmgandhi 18:6a4db94011d3 229 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 230
sahilmgandhi 18:6a4db94011d3 231 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 /**
sahilmgandhi 18:6a4db94011d3 235 * @brief SPI MSP Init
sahilmgandhi 18:6a4db94011d3 236 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 237 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 238 * @retval None
sahilmgandhi 18:6a4db94011d3 239 */
sahilmgandhi 18:6a4db94011d3 240 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 241 {
sahilmgandhi 18:6a4db94011d3 242 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 243 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 244
sahilmgandhi 18:6a4db94011d3 245 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 246 the HAL_SPI_MspInit could be implenetd in the user file
sahilmgandhi 18:6a4db94011d3 247 */
sahilmgandhi 18:6a4db94011d3 248 }
sahilmgandhi 18:6a4db94011d3 249
sahilmgandhi 18:6a4db94011d3 250 /**
sahilmgandhi 18:6a4db94011d3 251 * @brief SPI MSP DeInit
sahilmgandhi 18:6a4db94011d3 252 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 253 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 254 * @retval None
sahilmgandhi 18:6a4db94011d3 255 */
sahilmgandhi 18:6a4db94011d3 256 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 257 {
sahilmgandhi 18:6a4db94011d3 258 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 259 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 260
sahilmgandhi 18:6a4db94011d3 261 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 262 the HAL_SPI_MspDeInit could be implenetd in the user file
sahilmgandhi 18:6a4db94011d3 263 */
sahilmgandhi 18:6a4db94011d3 264 }
sahilmgandhi 18:6a4db94011d3 265
sahilmgandhi 18:6a4db94011d3 266 /**
sahilmgandhi 18:6a4db94011d3 267 * @}
sahilmgandhi 18:6a4db94011d3 268 */
sahilmgandhi 18:6a4db94011d3 269
sahilmgandhi 18:6a4db94011d3 270 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
sahilmgandhi 18:6a4db94011d3 271 * @brief Data transfers functions
sahilmgandhi 18:6a4db94011d3 272 *
sahilmgandhi 18:6a4db94011d3 273 @verbatim
sahilmgandhi 18:6a4db94011d3 274 ==============================================================================
sahilmgandhi 18:6a4db94011d3 275 ##### IO operation functions #####
sahilmgandhi 18:6a4db94011d3 276 ===============================================================================
sahilmgandhi 18:6a4db94011d3 277 This subsection provides a set of functions allowing to manage the SPI
sahilmgandhi 18:6a4db94011d3 278 data transfers.
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 [..] The SPI supports master and slave mode :
sahilmgandhi 18:6a4db94011d3 281
sahilmgandhi 18:6a4db94011d3 282 (#) There are two modes of transfer:
sahilmgandhi 18:6a4db94011d3 283 (++) Blocking mode: The communication is performed in polling mode.
sahilmgandhi 18:6a4db94011d3 284 The HAL status of all data processing is returned by the same function
sahilmgandhi 18:6a4db94011d3 285 after finishing transfer.
sahilmgandhi 18:6a4db94011d3 286 (++) No-Blocking mode: The communication is performed using Interrupts
sahilmgandhi 18:6a4db94011d3 287 or DMA, These APIs return the HAL status.
sahilmgandhi 18:6a4db94011d3 288 The end of the data processing will be indicated through the
sahilmgandhi 18:6a4db94011d3 289 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
sahilmgandhi 18:6a4db94011d3 290 using DMA mode.
sahilmgandhi 18:6a4db94011d3 291 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
sahilmgandhi 18:6a4db94011d3 292 will be executed respectivelly at the end of the transmit or Receive process
sahilmgandhi 18:6a4db94011d3 293 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
sahilmgandhi 18:6a4db94011d3 296 exist for 1Line (simplex) and 2Lines (full duplex) modes.
sahilmgandhi 18:6a4db94011d3 297
sahilmgandhi 18:6a4db94011d3 298 @endverbatim
sahilmgandhi 18:6a4db94011d3 299 * @{
sahilmgandhi 18:6a4db94011d3 300 */
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 /**
sahilmgandhi 18:6a4db94011d3 303 * @brief Transmit an amount of data in blocking mode
sahilmgandhi 18:6a4db94011d3 304 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 305 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 306 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 307 * @param Size: amount of data to be sent
sahilmgandhi 18:6a4db94011d3 308 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 309 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 310 */
sahilmgandhi 18:6a4db94011d3 311 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 312 {
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 315 {
sahilmgandhi 18:6a4db94011d3 316 if((pData == NULL ) || (Size == 0))
sahilmgandhi 18:6a4db94011d3 317 {
sahilmgandhi 18:6a4db94011d3 318 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 319 }
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 322 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
sahilmgandhi 18:6a4db94011d3 323
sahilmgandhi 18:6a4db94011d3 324 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 325 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 326
sahilmgandhi 18:6a4db94011d3 327 /* Configure communication */
sahilmgandhi 18:6a4db94011d3 328 hspi->State = HAL_SPI_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 329 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 330
sahilmgandhi 18:6a4db94011d3 331 hspi->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 332 hspi->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 333 hspi->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 334
sahilmgandhi 18:6a4db94011d3 335 /*Init field not used in handle to zero */
sahilmgandhi 18:6a4db94011d3 336 hspi->TxISR = 0;
sahilmgandhi 18:6a4db94011d3 337 hspi->RxISR = 0;
sahilmgandhi 18:6a4db94011d3 338 hspi->pRxBuffPtr = NULL;
sahilmgandhi 18:6a4db94011d3 339 hspi->RxXferSize = 0;
sahilmgandhi 18:6a4db94011d3 340 hspi->RxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 341
sahilmgandhi 18:6a4db94011d3 342 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 343 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 344 {
sahilmgandhi 18:6a4db94011d3 345 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 346 }
sahilmgandhi 18:6a4db94011d3 347
sahilmgandhi 18:6a4db94011d3 348 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi 18:6a4db94011d3 349 {
sahilmgandhi 18:6a4db94011d3 350 /* Configure communication direction : 1Line */
sahilmgandhi 18:6a4db94011d3 351 SPI_1LINE_TX(hspi);
sahilmgandhi 18:6a4db94011d3 352 }
sahilmgandhi 18:6a4db94011d3 353
sahilmgandhi 18:6a4db94011d3 354 /* Check if the SPI is already enabled */
sahilmgandhi 18:6a4db94011d3 355 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 356 {
sahilmgandhi 18:6a4db94011d3 357 /* Enable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 358 __HAL_SPI_ENABLE(hspi);
sahilmgandhi 18:6a4db94011d3 359 }
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 /* Transmit data in 8 Bit mode */
sahilmgandhi 18:6a4db94011d3 362 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
sahilmgandhi 18:6a4db94011d3 363 {
sahilmgandhi 18:6a4db94011d3 364 if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
sahilmgandhi 18:6a4db94011d3 365 {
sahilmgandhi 18:6a4db94011d3 366 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 367 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 368 }
sahilmgandhi 18:6a4db94011d3 369 while(hspi->TxXferCount > 0)
sahilmgandhi 18:6a4db94011d3 370 {
sahilmgandhi 18:6a4db94011d3 371 /* Wait until TXE flag is set to send data */
sahilmgandhi 18:6a4db94011d3 372 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 373 {
sahilmgandhi 18:6a4db94011d3 374 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 375 }
sahilmgandhi 18:6a4db94011d3 376 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 377 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 378 }
sahilmgandhi 18:6a4db94011d3 379 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 380 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 381 {
sahilmgandhi 18:6a4db94011d3 382 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384 }
sahilmgandhi 18:6a4db94011d3 385 /* Transmit data in 16 Bit mode */
sahilmgandhi 18:6a4db94011d3 386 else
sahilmgandhi 18:6a4db94011d3 387 {
sahilmgandhi 18:6a4db94011d3 388 if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
sahilmgandhi 18:6a4db94011d3 389 {
sahilmgandhi 18:6a4db94011d3 390 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
sahilmgandhi 18:6a4db94011d3 391 hspi->pTxBuffPtr+=2;
sahilmgandhi 18:6a4db94011d3 392 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 393 }
sahilmgandhi 18:6a4db94011d3 394 while(hspi->TxXferCount > 0)
sahilmgandhi 18:6a4db94011d3 395 {
sahilmgandhi 18:6a4db94011d3 396 /* Wait until TXE flag is set to send data */
sahilmgandhi 18:6a4db94011d3 397 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 398 {
sahilmgandhi 18:6a4db94011d3 399 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 400 }
sahilmgandhi 18:6a4db94011d3 401 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
sahilmgandhi 18:6a4db94011d3 402 hspi->pTxBuffPtr+=2;
sahilmgandhi 18:6a4db94011d3 403 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 404 }
sahilmgandhi 18:6a4db94011d3 405 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 406 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 407 {
sahilmgandhi 18:6a4db94011d3 408 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 409 }
sahilmgandhi 18:6a4db94011d3 410 }
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 /* Wait until TXE flag is set to send data */
sahilmgandhi 18:6a4db94011d3 413 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 414 {
sahilmgandhi 18:6a4db94011d3 415 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 416 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 417 }
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 /* Wait until Busy flag is reset before disabling SPI */
sahilmgandhi 18:6a4db94011d3 420 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 421 {
sahilmgandhi 18:6a4db94011d3 422 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 423 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 424 }
sahilmgandhi 18:6a4db94011d3 425
sahilmgandhi 18:6a4db94011d3 426 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
sahilmgandhi 18:6a4db94011d3 427 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi 18:6a4db94011d3 428 {
sahilmgandhi 18:6a4db94011d3 429 __HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 430 }
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 433
sahilmgandhi 18:6a4db94011d3 434 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 435 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 436
sahilmgandhi 18:6a4db94011d3 437 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 438 }
sahilmgandhi 18:6a4db94011d3 439 else
sahilmgandhi 18:6a4db94011d3 440 {
sahilmgandhi 18:6a4db94011d3 441 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 442 }
sahilmgandhi 18:6a4db94011d3 443 }
sahilmgandhi 18:6a4db94011d3 444
sahilmgandhi 18:6a4db94011d3 445 /**
sahilmgandhi 18:6a4db94011d3 446 * @brief Receive an amount of data in blocking mode
sahilmgandhi 18:6a4db94011d3 447 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 448 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 449 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 450 * @param Size: amount of data to be sent
sahilmgandhi 18:6a4db94011d3 451 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 452 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 453 */
sahilmgandhi 18:6a4db94011d3 454 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 455 {
sahilmgandhi 18:6a4db94011d3 456 __IO uint16_t tmpreg = 0;
sahilmgandhi 18:6a4db94011d3 457
sahilmgandhi 18:6a4db94011d3 458 if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 459 {
sahilmgandhi 18:6a4db94011d3 460 if((pData == NULL ) || (Size == 0))
sahilmgandhi 18:6a4db94011d3 461 {
sahilmgandhi 18:6a4db94011d3 462 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 463 }
sahilmgandhi 18:6a4db94011d3 464
sahilmgandhi 18:6a4db94011d3 465 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 466 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 /* Configure communication */
sahilmgandhi 18:6a4db94011d3 469 hspi->State = HAL_SPI_STATE_BUSY_RX;
sahilmgandhi 18:6a4db94011d3 470 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 hspi->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 473 hspi->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 474 hspi->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 475
sahilmgandhi 18:6a4db94011d3 476 /*Init field not used in handle to zero */
sahilmgandhi 18:6a4db94011d3 477 hspi->RxISR = 0;
sahilmgandhi 18:6a4db94011d3 478 hspi->TxISR = 0;
sahilmgandhi 18:6a4db94011d3 479 hspi->pTxBuffPtr = NULL;
sahilmgandhi 18:6a4db94011d3 480 hspi->TxXferSize = 0;
sahilmgandhi 18:6a4db94011d3 481 hspi->TxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 482
sahilmgandhi 18:6a4db94011d3 483 /* Configure communication direction : 1Line */
sahilmgandhi 18:6a4db94011d3 484 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi 18:6a4db94011d3 485 {
sahilmgandhi 18:6a4db94011d3 486 SPI_1LINE_RX(hspi);
sahilmgandhi 18:6a4db94011d3 487 }
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 490 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 491 {
sahilmgandhi 18:6a4db94011d3 492 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 493 }
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
sahilmgandhi 18:6a4db94011d3 496 {
sahilmgandhi 18:6a4db94011d3 497 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 498 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
sahilmgandhi 18:6a4db94011d3 501 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
sahilmgandhi 18:6a4db94011d3 502 }
sahilmgandhi 18:6a4db94011d3 503
sahilmgandhi 18:6a4db94011d3 504 /* Check if the SPI is already enabled */
sahilmgandhi 18:6a4db94011d3 505 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 506 {
sahilmgandhi 18:6a4db94011d3 507 /* Enable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 508 __HAL_SPI_ENABLE(hspi);
sahilmgandhi 18:6a4db94011d3 509 }
sahilmgandhi 18:6a4db94011d3 510
sahilmgandhi 18:6a4db94011d3 511 /* Receive data in 8 Bit mode */
sahilmgandhi 18:6a4db94011d3 512 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
sahilmgandhi 18:6a4db94011d3 513 {
sahilmgandhi 18:6a4db94011d3 514 while(hspi->RxXferCount > 1)
sahilmgandhi 18:6a4db94011d3 515 {
sahilmgandhi 18:6a4db94011d3 516 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 517 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 518 {
sahilmgandhi 18:6a4db94011d3 519 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 520 }
sahilmgandhi 18:6a4db94011d3 521
sahilmgandhi 18:6a4db94011d3 522 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 523 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 524 }
sahilmgandhi 18:6a4db94011d3 525 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 526 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 527 {
sahilmgandhi 18:6a4db94011d3 528 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 529 }
sahilmgandhi 18:6a4db94011d3 530 }
sahilmgandhi 18:6a4db94011d3 531 /* Receive data in 16 Bit mode */
sahilmgandhi 18:6a4db94011d3 532 else
sahilmgandhi 18:6a4db94011d3 533 {
sahilmgandhi 18:6a4db94011d3 534 while(hspi->RxXferCount > 1)
sahilmgandhi 18:6a4db94011d3 535 {
sahilmgandhi 18:6a4db94011d3 536 /* Wait until RXNE flag is set to read data */
sahilmgandhi 18:6a4db94011d3 537 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 538 {
sahilmgandhi 18:6a4db94011d3 539 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 540 }
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 543 hspi->pRxBuffPtr+=2;
sahilmgandhi 18:6a4db94011d3 544 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 545 }
sahilmgandhi 18:6a4db94011d3 546 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 547 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 548 {
sahilmgandhi 18:6a4db94011d3 549 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 550 }
sahilmgandhi 18:6a4db94011d3 551 }
sahilmgandhi 18:6a4db94011d3 552
sahilmgandhi 18:6a4db94011d3 553 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 554 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 555 {
sahilmgandhi 18:6a4db94011d3 556 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 557 }
sahilmgandhi 18:6a4db94011d3 558
sahilmgandhi 18:6a4db94011d3 559 /* Receive last data in 8 Bit mode */
sahilmgandhi 18:6a4db94011d3 560 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
sahilmgandhi 18:6a4db94011d3 561 {
sahilmgandhi 18:6a4db94011d3 562 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 563 }
sahilmgandhi 18:6a4db94011d3 564 /* Receive last data in 16 Bit mode */
sahilmgandhi 18:6a4db94011d3 565 else
sahilmgandhi 18:6a4db94011d3 566 {
sahilmgandhi 18:6a4db94011d3 567 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 568 hspi->pRxBuffPtr+=2;
sahilmgandhi 18:6a4db94011d3 569 }
sahilmgandhi 18:6a4db94011d3 570 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 571
sahilmgandhi 18:6a4db94011d3 572 /* Wait until RXNE flag is set: CRC Received */
sahilmgandhi 18:6a4db94011d3 573 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 574 {
sahilmgandhi 18:6a4db94011d3 575 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 576 {
sahilmgandhi 18:6a4db94011d3 577 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi 18:6a4db94011d3 578 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 579 }
sahilmgandhi 18:6a4db94011d3 580
sahilmgandhi 18:6a4db94011d3 581 /* Read CRC to Flush RXNE flag */
sahilmgandhi 18:6a4db94011d3 582 tmpreg = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 583 UNUSED(tmpreg);
sahilmgandhi 18:6a4db94011d3 584 }
sahilmgandhi 18:6a4db94011d3 585
sahilmgandhi 18:6a4db94011d3 586 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
sahilmgandhi 18:6a4db94011d3 587 {
sahilmgandhi 18:6a4db94011d3 588 /* Disable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 589 __HAL_SPI_DISABLE(hspi);
sahilmgandhi 18:6a4db94011d3 590 }
sahilmgandhi 18:6a4db94011d3 591
sahilmgandhi 18:6a4db94011d3 592 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 593
sahilmgandhi 18:6a4db94011d3 594 /* Check if CRC error occurred */
sahilmgandhi 18:6a4db94011d3 595 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
sahilmgandhi 18:6a4db94011d3 596 {
sahilmgandhi 18:6a4db94011d3 597 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi 18:6a4db94011d3 598
sahilmgandhi 18:6a4db94011d3 599 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 600 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 601
sahilmgandhi 18:6a4db94011d3 602 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 603 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 604
sahilmgandhi 18:6a4db94011d3 605 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 606 }
sahilmgandhi 18:6a4db94011d3 607
sahilmgandhi 18:6a4db94011d3 608 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 609 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 610
sahilmgandhi 18:6a4db94011d3 611 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 612 }
sahilmgandhi 18:6a4db94011d3 613 else
sahilmgandhi 18:6a4db94011d3 614 {
sahilmgandhi 18:6a4db94011d3 615 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 616 }
sahilmgandhi 18:6a4db94011d3 617 }
sahilmgandhi 18:6a4db94011d3 618
sahilmgandhi 18:6a4db94011d3 619 /**
sahilmgandhi 18:6a4db94011d3 620 * @brief Transmit and Receive an amount of data in blocking mode
sahilmgandhi 18:6a4db94011d3 621 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 622 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 623 * @param pTxData: pointer to transmission data buffer
sahilmgandhi 18:6a4db94011d3 624 * @param pRxData: pointer to reception data buffer to be
sahilmgandhi 18:6a4db94011d3 625 * @param Size: amount of data to be sent
sahilmgandhi 18:6a4db94011d3 626 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 627 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 628 */
sahilmgandhi 18:6a4db94011d3 629 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 630 {
sahilmgandhi 18:6a4db94011d3 631 __IO uint16_t tmpreg = 0;
sahilmgandhi 18:6a4db94011d3 632
sahilmgandhi 18:6a4db94011d3 633 if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX))
sahilmgandhi 18:6a4db94011d3 634 {
sahilmgandhi 18:6a4db94011d3 635 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
sahilmgandhi 18:6a4db94011d3 636 {
sahilmgandhi 18:6a4db94011d3 637 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 638 }
sahilmgandhi 18:6a4db94011d3 639
sahilmgandhi 18:6a4db94011d3 640 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 641 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
sahilmgandhi 18:6a4db94011d3 642
sahilmgandhi 18:6a4db94011d3 643 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 644 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
sahilmgandhi 18:6a4db94011d3 647 if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 648 {
sahilmgandhi 18:6a4db94011d3 649 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
sahilmgandhi 18:6a4db94011d3 650 }
sahilmgandhi 18:6a4db94011d3 651
sahilmgandhi 18:6a4db94011d3 652 /* Configure communication */
sahilmgandhi 18:6a4db94011d3 653 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 654
sahilmgandhi 18:6a4db94011d3 655 hspi->pRxBuffPtr = pRxData;
sahilmgandhi 18:6a4db94011d3 656 hspi->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 657 hspi->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 658
sahilmgandhi 18:6a4db94011d3 659 hspi->pTxBuffPtr = pTxData;
sahilmgandhi 18:6a4db94011d3 660 hspi->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 661 hspi->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 662
sahilmgandhi 18:6a4db94011d3 663 /*Init field not used in handle to zero */
sahilmgandhi 18:6a4db94011d3 664 hspi->RxISR = 0;
sahilmgandhi 18:6a4db94011d3 665 hspi->TxISR = 0;
sahilmgandhi 18:6a4db94011d3 666
sahilmgandhi 18:6a4db94011d3 667 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 668 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 669 {
sahilmgandhi 18:6a4db94011d3 670 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 671 }
sahilmgandhi 18:6a4db94011d3 672
sahilmgandhi 18:6a4db94011d3 673 /* Check if the SPI is already enabled */
sahilmgandhi 18:6a4db94011d3 674 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 675 {
sahilmgandhi 18:6a4db94011d3 676 /* Enable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 677 __HAL_SPI_ENABLE(hspi);
sahilmgandhi 18:6a4db94011d3 678 }
sahilmgandhi 18:6a4db94011d3 679
sahilmgandhi 18:6a4db94011d3 680 /* Transmit and Receive data in 16 Bit mode */
sahilmgandhi 18:6a4db94011d3 681 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
sahilmgandhi 18:6a4db94011d3 682 {
sahilmgandhi 18:6a4db94011d3 683 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
sahilmgandhi 18:6a4db94011d3 684 {
sahilmgandhi 18:6a4db94011d3 685 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
sahilmgandhi 18:6a4db94011d3 686 hspi->pTxBuffPtr+=2;
sahilmgandhi 18:6a4db94011d3 687 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 688 }
sahilmgandhi 18:6a4db94011d3 689 if(hspi->TxXferCount == 0)
sahilmgandhi 18:6a4db94011d3 690 {
sahilmgandhi 18:6a4db94011d3 691 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 692 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 693 {
sahilmgandhi 18:6a4db94011d3 694 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 695 }
sahilmgandhi 18:6a4db94011d3 696
sahilmgandhi 18:6a4db94011d3 697 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 698 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 699 {
sahilmgandhi 18:6a4db94011d3 700 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 701 }
sahilmgandhi 18:6a4db94011d3 702
sahilmgandhi 18:6a4db94011d3 703 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 704 hspi->pRxBuffPtr+=2;
sahilmgandhi 18:6a4db94011d3 705 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 706 }
sahilmgandhi 18:6a4db94011d3 707 else
sahilmgandhi 18:6a4db94011d3 708 {
sahilmgandhi 18:6a4db94011d3 709 while(hspi->TxXferCount > 0)
sahilmgandhi 18:6a4db94011d3 710 {
sahilmgandhi 18:6a4db94011d3 711 /* Wait until TXE flag is set to send data */
sahilmgandhi 18:6a4db94011d3 712 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 713 {
sahilmgandhi 18:6a4db94011d3 714 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 715 }
sahilmgandhi 18:6a4db94011d3 716
sahilmgandhi 18:6a4db94011d3 717 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
sahilmgandhi 18:6a4db94011d3 718 hspi->pTxBuffPtr+=2;
sahilmgandhi 18:6a4db94011d3 719 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 720
sahilmgandhi 18:6a4db94011d3 721 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 722 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
sahilmgandhi 18:6a4db94011d3 723 {
sahilmgandhi 18:6a4db94011d3 724 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 725 }
sahilmgandhi 18:6a4db94011d3 726
sahilmgandhi 18:6a4db94011d3 727 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 728 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 729 {
sahilmgandhi 18:6a4db94011d3 730 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 731 }
sahilmgandhi 18:6a4db94011d3 732
sahilmgandhi 18:6a4db94011d3 733 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 734 hspi->pRxBuffPtr+=2;
sahilmgandhi 18:6a4db94011d3 735 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 736 }
sahilmgandhi 18:6a4db94011d3 737 /* Receive the last byte */
sahilmgandhi 18:6a4db94011d3 738 if(hspi->Init.Mode == SPI_MODE_SLAVE)
sahilmgandhi 18:6a4db94011d3 739 {
sahilmgandhi 18:6a4db94011d3 740 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 741 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 742 {
sahilmgandhi 18:6a4db94011d3 743 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 744 }
sahilmgandhi 18:6a4db94011d3 745
sahilmgandhi 18:6a4db94011d3 746 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 747 hspi->pRxBuffPtr+=2;
sahilmgandhi 18:6a4db94011d3 748 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 749 }
sahilmgandhi 18:6a4db94011d3 750 }
sahilmgandhi 18:6a4db94011d3 751 }
sahilmgandhi 18:6a4db94011d3 752 /* Transmit and Receive data in 8 Bit mode */
sahilmgandhi 18:6a4db94011d3 753 else
sahilmgandhi 18:6a4db94011d3 754 {
sahilmgandhi 18:6a4db94011d3 755 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
sahilmgandhi 18:6a4db94011d3 756 {
sahilmgandhi 18:6a4db94011d3 757 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 758 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 759 }
sahilmgandhi 18:6a4db94011d3 760 if(hspi->TxXferCount == 0)
sahilmgandhi 18:6a4db94011d3 761 {
sahilmgandhi 18:6a4db94011d3 762 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 763 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 764 {
sahilmgandhi 18:6a4db94011d3 765 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 766 }
sahilmgandhi 18:6a4db94011d3 767
sahilmgandhi 18:6a4db94011d3 768 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 769 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 770 {
sahilmgandhi 18:6a4db94011d3 771 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 772 }
sahilmgandhi 18:6a4db94011d3 773
sahilmgandhi 18:6a4db94011d3 774 (*hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 775 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 776 }
sahilmgandhi 18:6a4db94011d3 777 else
sahilmgandhi 18:6a4db94011d3 778 {
sahilmgandhi 18:6a4db94011d3 779 while(hspi->TxXferCount > 0)
sahilmgandhi 18:6a4db94011d3 780 {
sahilmgandhi 18:6a4db94011d3 781 /* Wait until TXE flag is set to send data */
sahilmgandhi 18:6a4db94011d3 782 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 783 {
sahilmgandhi 18:6a4db94011d3 784 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 785 }
sahilmgandhi 18:6a4db94011d3 786
sahilmgandhi 18:6a4db94011d3 787 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 788 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 789
sahilmgandhi 18:6a4db94011d3 790 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 791 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
sahilmgandhi 18:6a4db94011d3 792 {
sahilmgandhi 18:6a4db94011d3 793 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 794 }
sahilmgandhi 18:6a4db94011d3 795
sahilmgandhi 18:6a4db94011d3 796 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 797 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 798 {
sahilmgandhi 18:6a4db94011d3 799 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 800 }
sahilmgandhi 18:6a4db94011d3 801
sahilmgandhi 18:6a4db94011d3 802 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 803 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 804 }
sahilmgandhi 18:6a4db94011d3 805 if(hspi->Init.Mode == SPI_MODE_SLAVE)
sahilmgandhi 18:6a4db94011d3 806 {
sahilmgandhi 18:6a4db94011d3 807 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 808 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 809 {
sahilmgandhi 18:6a4db94011d3 810 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 811 }
sahilmgandhi 18:6a4db94011d3 812
sahilmgandhi 18:6a4db94011d3 813 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 814 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 815 }
sahilmgandhi 18:6a4db94011d3 816 }
sahilmgandhi 18:6a4db94011d3 817 }
sahilmgandhi 18:6a4db94011d3 818
sahilmgandhi 18:6a4db94011d3 819 /* Read CRC from DR to close CRC calculation process */
sahilmgandhi 18:6a4db94011d3 820 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 821 {
sahilmgandhi 18:6a4db94011d3 822 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 823 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 824 {
sahilmgandhi 18:6a4db94011d3 825 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi 18:6a4db94011d3 826 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 827 }
sahilmgandhi 18:6a4db94011d3 828 /* Read CRC */
sahilmgandhi 18:6a4db94011d3 829 tmpreg = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 830 UNUSED(tmpreg);
sahilmgandhi 18:6a4db94011d3 831 }
sahilmgandhi 18:6a4db94011d3 832
sahilmgandhi 18:6a4db94011d3 833 /* Wait until Busy flag is reset before disabling SPI */
sahilmgandhi 18:6a4db94011d3 834 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 835 {
sahilmgandhi 18:6a4db94011d3 836 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 837 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 838 }
sahilmgandhi 18:6a4db94011d3 839
sahilmgandhi 18:6a4db94011d3 840 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 841
sahilmgandhi 18:6a4db94011d3 842 /* Check if CRC error occurred */
sahilmgandhi 18:6a4db94011d3 843 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
sahilmgandhi 18:6a4db94011d3 844 {
sahilmgandhi 18:6a4db94011d3 845 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi 18:6a4db94011d3 846
sahilmgandhi 18:6a4db94011d3 847 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 848 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 849 {
sahilmgandhi 18:6a4db94011d3 850 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 851 }
sahilmgandhi 18:6a4db94011d3 852
sahilmgandhi 18:6a4db94011d3 853 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 854 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 855
sahilmgandhi 18:6a4db94011d3 856 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 857 }
sahilmgandhi 18:6a4db94011d3 858
sahilmgandhi 18:6a4db94011d3 859 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 860 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 861
sahilmgandhi 18:6a4db94011d3 862 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 863 }
sahilmgandhi 18:6a4db94011d3 864 else
sahilmgandhi 18:6a4db94011d3 865 {
sahilmgandhi 18:6a4db94011d3 866 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 867 }
sahilmgandhi 18:6a4db94011d3 868 }
sahilmgandhi 18:6a4db94011d3 869
sahilmgandhi 18:6a4db94011d3 870 /**
sahilmgandhi 18:6a4db94011d3 871 * @brief Transmit an amount of data in no-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 872 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 873 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 874 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 875 * @param Size: amount of data to be sent
sahilmgandhi 18:6a4db94011d3 876 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 877 */
sahilmgandhi 18:6a4db94011d3 878 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 879 {
sahilmgandhi 18:6a4db94011d3 880 if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 881 {
sahilmgandhi 18:6a4db94011d3 882 if((pData == NULL) || (Size == 0))
sahilmgandhi 18:6a4db94011d3 883 {
sahilmgandhi 18:6a4db94011d3 884 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 885 }
sahilmgandhi 18:6a4db94011d3 886
sahilmgandhi 18:6a4db94011d3 887 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 888 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
sahilmgandhi 18:6a4db94011d3 889
sahilmgandhi 18:6a4db94011d3 890 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 891 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 892
sahilmgandhi 18:6a4db94011d3 893 /* Configure communication */
sahilmgandhi 18:6a4db94011d3 894 hspi->State = HAL_SPI_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 895 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 896
sahilmgandhi 18:6a4db94011d3 897 /* Set the function for IT treatment */
sahilmgandhi 18:6a4db94011d3 898 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
sahilmgandhi 18:6a4db94011d3 899 {
sahilmgandhi 18:6a4db94011d3 900 hspi->TxISR = SPI_TxISR_16BIT;
sahilmgandhi 18:6a4db94011d3 901 }
sahilmgandhi 18:6a4db94011d3 902 else
sahilmgandhi 18:6a4db94011d3 903 {
sahilmgandhi 18:6a4db94011d3 904 hspi->TxISR = SPI_TxISR_8BIT;
sahilmgandhi 18:6a4db94011d3 905 }
sahilmgandhi 18:6a4db94011d3 906
sahilmgandhi 18:6a4db94011d3 907 hspi->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 908 hspi->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 909 hspi->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 910
sahilmgandhi 18:6a4db94011d3 911 /*Init field not used in handle to zero */
sahilmgandhi 18:6a4db94011d3 912 hspi->RxISR = 0;
sahilmgandhi 18:6a4db94011d3 913 hspi->pRxBuffPtr = NULL;
sahilmgandhi 18:6a4db94011d3 914 hspi->RxXferSize = 0;
sahilmgandhi 18:6a4db94011d3 915 hspi->RxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 916
sahilmgandhi 18:6a4db94011d3 917 /* Configure communication direction : 1Line */
sahilmgandhi 18:6a4db94011d3 918 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi 18:6a4db94011d3 919 {
sahilmgandhi 18:6a4db94011d3 920 SPI_1LINE_TX(hspi);
sahilmgandhi 18:6a4db94011d3 921 }
sahilmgandhi 18:6a4db94011d3 922
sahilmgandhi 18:6a4db94011d3 923 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 924 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 925 {
sahilmgandhi 18:6a4db94011d3 926 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 927 }
sahilmgandhi 18:6a4db94011d3 928
sahilmgandhi 18:6a4db94011d3 929 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi 18:6a4db94011d3 930 {
sahilmgandhi 18:6a4db94011d3 931 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
sahilmgandhi 18:6a4db94011d3 932 }else
sahilmgandhi 18:6a4db94011d3 933 {
sahilmgandhi 18:6a4db94011d3 934 /* Enable TXE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 935 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 936 }
sahilmgandhi 18:6a4db94011d3 937 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 938 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 939
sahilmgandhi 18:6a4db94011d3 940 /* Check if the SPI is already enabled */
sahilmgandhi 18:6a4db94011d3 941 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 942 {
sahilmgandhi 18:6a4db94011d3 943 /* Enable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 944 __HAL_SPI_ENABLE(hspi);
sahilmgandhi 18:6a4db94011d3 945 }
sahilmgandhi 18:6a4db94011d3 946
sahilmgandhi 18:6a4db94011d3 947 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 948 }
sahilmgandhi 18:6a4db94011d3 949 else
sahilmgandhi 18:6a4db94011d3 950 {
sahilmgandhi 18:6a4db94011d3 951 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 952 }
sahilmgandhi 18:6a4db94011d3 953 }
sahilmgandhi 18:6a4db94011d3 954
sahilmgandhi 18:6a4db94011d3 955 /**
sahilmgandhi 18:6a4db94011d3 956 * @brief Receive an amount of data in no-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 957 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 958 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 959 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 960 * @param Size: amount of data to be sent
sahilmgandhi 18:6a4db94011d3 961 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 962 */
sahilmgandhi 18:6a4db94011d3 963 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 964 {
sahilmgandhi 18:6a4db94011d3 965 if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 966 {
sahilmgandhi 18:6a4db94011d3 967 if((pData == NULL) || (Size == 0))
sahilmgandhi 18:6a4db94011d3 968 {
sahilmgandhi 18:6a4db94011d3 969 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 970 }
sahilmgandhi 18:6a4db94011d3 971
sahilmgandhi 18:6a4db94011d3 972 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 973 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 974
sahilmgandhi 18:6a4db94011d3 975 /* Configure communication */
sahilmgandhi 18:6a4db94011d3 976 hspi->State = HAL_SPI_STATE_BUSY_RX;
sahilmgandhi 18:6a4db94011d3 977 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 978
sahilmgandhi 18:6a4db94011d3 979 /* Set the function for IT treatment */
sahilmgandhi 18:6a4db94011d3 980 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
sahilmgandhi 18:6a4db94011d3 981 {
sahilmgandhi 18:6a4db94011d3 982 hspi->RxISR = SPI_RxISR_16BIT;
sahilmgandhi 18:6a4db94011d3 983 }
sahilmgandhi 18:6a4db94011d3 984 else
sahilmgandhi 18:6a4db94011d3 985 {
sahilmgandhi 18:6a4db94011d3 986 hspi->RxISR = SPI_RxISR_8BIT;
sahilmgandhi 18:6a4db94011d3 987 }
sahilmgandhi 18:6a4db94011d3 988 hspi->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 989 hspi->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 990 hspi->RxXferCount = Size ;
sahilmgandhi 18:6a4db94011d3 991
sahilmgandhi 18:6a4db94011d3 992 /*Init field not used in handle to zero */
sahilmgandhi 18:6a4db94011d3 993 hspi->TxISR = 0;
sahilmgandhi 18:6a4db94011d3 994 hspi->pTxBuffPtr = NULL;
sahilmgandhi 18:6a4db94011d3 995 hspi->TxXferSize = 0;
sahilmgandhi 18:6a4db94011d3 996 hspi->TxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 997
sahilmgandhi 18:6a4db94011d3 998 /* Configure communication direction : 1Line */
sahilmgandhi 18:6a4db94011d3 999 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi 18:6a4db94011d3 1000 {
sahilmgandhi 18:6a4db94011d3 1001 SPI_1LINE_RX(hspi);
sahilmgandhi 18:6a4db94011d3 1002 }
sahilmgandhi 18:6a4db94011d3 1003 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
sahilmgandhi 18:6a4db94011d3 1004 {
sahilmgandhi 18:6a4db94011d3 1005 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1006 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1007
sahilmgandhi 18:6a4db94011d3 1008 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
sahilmgandhi 18:6a4db94011d3 1009 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
sahilmgandhi 18:6a4db94011d3 1010 }
sahilmgandhi 18:6a4db94011d3 1011
sahilmgandhi 18:6a4db94011d3 1012 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 1013 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1014 {
sahilmgandhi 18:6a4db94011d3 1015 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 1016 }
sahilmgandhi 18:6a4db94011d3 1017
sahilmgandhi 18:6a4db94011d3 1018 /* Enable TXE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 1019 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 1020
sahilmgandhi 18:6a4db94011d3 1021 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1022 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1023
sahilmgandhi 18:6a4db94011d3 1024 /* Note : The SPI must be enabled after unlocking current process
sahilmgandhi 18:6a4db94011d3 1025 to avoid the risk of SPI interrupt handle execution before current
sahilmgandhi 18:6a4db94011d3 1026 process unlock */
sahilmgandhi 18:6a4db94011d3 1027
sahilmgandhi 18:6a4db94011d3 1028 /* Check if the SPI is already enabled */
sahilmgandhi 18:6a4db94011d3 1029 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 1030 {
sahilmgandhi 18:6a4db94011d3 1031 /* Enable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 1032 __HAL_SPI_ENABLE(hspi);
sahilmgandhi 18:6a4db94011d3 1033 }
sahilmgandhi 18:6a4db94011d3 1034
sahilmgandhi 18:6a4db94011d3 1035 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1036 }
sahilmgandhi 18:6a4db94011d3 1037 else
sahilmgandhi 18:6a4db94011d3 1038 {
sahilmgandhi 18:6a4db94011d3 1039 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1040 }
sahilmgandhi 18:6a4db94011d3 1041 }
sahilmgandhi 18:6a4db94011d3 1042
sahilmgandhi 18:6a4db94011d3 1043 /**
sahilmgandhi 18:6a4db94011d3 1044 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
sahilmgandhi 18:6a4db94011d3 1045 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1046 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1047 * @param pTxData: pointer to transmission data buffer
sahilmgandhi 18:6a4db94011d3 1048 * @param pRxData: pointer to reception data buffer to be
sahilmgandhi 18:6a4db94011d3 1049 * @param Size: amount of data to be sent
sahilmgandhi 18:6a4db94011d3 1050 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1051 */
sahilmgandhi 18:6a4db94011d3 1052 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 1053 {
sahilmgandhi 18:6a4db94011d3 1054
sahilmgandhi 18:6a4db94011d3 1055 if((hspi->State == HAL_SPI_STATE_READY) || \
sahilmgandhi 18:6a4db94011d3 1056 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
sahilmgandhi 18:6a4db94011d3 1057 {
sahilmgandhi 18:6a4db94011d3 1058 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
sahilmgandhi 18:6a4db94011d3 1059 {
sahilmgandhi 18:6a4db94011d3 1060 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1061 }
sahilmgandhi 18:6a4db94011d3 1062
sahilmgandhi 18:6a4db94011d3 1063 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1064 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
sahilmgandhi 18:6a4db94011d3 1065
sahilmgandhi 18:6a4db94011d3 1066 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1067 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1068
sahilmgandhi 18:6a4db94011d3 1069 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
sahilmgandhi 18:6a4db94011d3 1070 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 1071 {
sahilmgandhi 18:6a4db94011d3 1072 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
sahilmgandhi 18:6a4db94011d3 1073 }
sahilmgandhi 18:6a4db94011d3 1074
sahilmgandhi 18:6a4db94011d3 1075 /* Configure communication */
sahilmgandhi 18:6a4db94011d3 1076 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1077
sahilmgandhi 18:6a4db94011d3 1078 hspi->pTxBuffPtr = pTxData;
sahilmgandhi 18:6a4db94011d3 1079 hspi->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 1080 hspi->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 1081
sahilmgandhi 18:6a4db94011d3 1082 hspi->pRxBuffPtr = pRxData;
sahilmgandhi 18:6a4db94011d3 1083 hspi->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 1084 hspi->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 1085
sahilmgandhi 18:6a4db94011d3 1086 /* Set the function for IT treatment */
sahilmgandhi 18:6a4db94011d3 1087 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
sahilmgandhi 18:6a4db94011d3 1088 {
sahilmgandhi 18:6a4db94011d3 1089 hspi->RxISR = SPI_2linesRxISR_16BIT;
sahilmgandhi 18:6a4db94011d3 1090 hspi->TxISR = SPI_2linesTxISR_16BIT;
sahilmgandhi 18:6a4db94011d3 1091 }
sahilmgandhi 18:6a4db94011d3 1092 else
sahilmgandhi 18:6a4db94011d3 1093 {
sahilmgandhi 18:6a4db94011d3 1094 hspi->RxISR = SPI_2linesRxISR_8BIT;
sahilmgandhi 18:6a4db94011d3 1095 hspi->TxISR = SPI_2linesTxISR_8BIT;
sahilmgandhi 18:6a4db94011d3 1096 }
sahilmgandhi 18:6a4db94011d3 1097
sahilmgandhi 18:6a4db94011d3 1098 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 1099 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1100 {
sahilmgandhi 18:6a4db94011d3 1101 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 1102 }
sahilmgandhi 18:6a4db94011d3 1103
sahilmgandhi 18:6a4db94011d3 1104 /* Enable TXE, RXNE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 1105 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 1106
sahilmgandhi 18:6a4db94011d3 1107 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1108 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1109
sahilmgandhi 18:6a4db94011d3 1110 /* Check if the SPI is already enabled */
sahilmgandhi 18:6a4db94011d3 1111 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 1112 {
sahilmgandhi 18:6a4db94011d3 1113 /* Enable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 1114 __HAL_SPI_ENABLE(hspi);
sahilmgandhi 18:6a4db94011d3 1115 }
sahilmgandhi 18:6a4db94011d3 1116
sahilmgandhi 18:6a4db94011d3 1117 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1118 }
sahilmgandhi 18:6a4db94011d3 1119 else
sahilmgandhi 18:6a4db94011d3 1120 {
sahilmgandhi 18:6a4db94011d3 1121 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1122 }
sahilmgandhi 18:6a4db94011d3 1123 }
sahilmgandhi 18:6a4db94011d3 1124
sahilmgandhi 18:6a4db94011d3 1125 /**
sahilmgandhi 18:6a4db94011d3 1126 * @brief Transmit an amount of data in no-blocking mode with DMA
sahilmgandhi 18:6a4db94011d3 1127 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1128 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1129 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 1130 * @param Size: amount of data to be sent
sahilmgandhi 18:6a4db94011d3 1131 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1132 */
sahilmgandhi 18:6a4db94011d3 1133 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 1134 {
sahilmgandhi 18:6a4db94011d3 1135 if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 1136 {
sahilmgandhi 18:6a4db94011d3 1137 if((pData == NULL) || (Size == 0))
sahilmgandhi 18:6a4db94011d3 1138 {
sahilmgandhi 18:6a4db94011d3 1139 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1140 }
sahilmgandhi 18:6a4db94011d3 1141
sahilmgandhi 18:6a4db94011d3 1142 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1143 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
sahilmgandhi 18:6a4db94011d3 1144
sahilmgandhi 18:6a4db94011d3 1145 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1146 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1147
sahilmgandhi 18:6a4db94011d3 1148 /* Configure communication */
sahilmgandhi 18:6a4db94011d3 1149 hspi->State = HAL_SPI_STATE_BUSY_TX;
sahilmgandhi 18:6a4db94011d3 1150 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1151
sahilmgandhi 18:6a4db94011d3 1152 hspi->pTxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 1153 hspi->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 1154 hspi->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 1155
sahilmgandhi 18:6a4db94011d3 1156 /*Init field not used in handle to zero */
sahilmgandhi 18:6a4db94011d3 1157 hspi->TxISR = 0;
sahilmgandhi 18:6a4db94011d3 1158 hspi->RxISR = 0;
sahilmgandhi 18:6a4db94011d3 1159 hspi->pRxBuffPtr = NULL;
sahilmgandhi 18:6a4db94011d3 1160 hspi->RxXferSize = 0;
sahilmgandhi 18:6a4db94011d3 1161 hspi->RxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 1162
sahilmgandhi 18:6a4db94011d3 1163 /* Configure communication direction : 1Line */
sahilmgandhi 18:6a4db94011d3 1164 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi 18:6a4db94011d3 1165 {
sahilmgandhi 18:6a4db94011d3 1166 SPI_1LINE_TX(hspi);
sahilmgandhi 18:6a4db94011d3 1167 }
sahilmgandhi 18:6a4db94011d3 1168
sahilmgandhi 18:6a4db94011d3 1169 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 1170 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1171 {
sahilmgandhi 18:6a4db94011d3 1172 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 1173 }
sahilmgandhi 18:6a4db94011d3 1174
sahilmgandhi 18:6a4db94011d3 1175 /* Set the SPI TxDMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1176 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
sahilmgandhi 18:6a4db94011d3 1177
sahilmgandhi 18:6a4db94011d3 1178 /* Set the SPI TxDMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1179 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
sahilmgandhi 18:6a4db94011d3 1180
sahilmgandhi 18:6a4db94011d3 1181 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 1182 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
sahilmgandhi 18:6a4db94011d3 1183
sahilmgandhi 18:6a4db94011d3 1184 /* Enable the Tx DMA Channel */
sahilmgandhi 18:6a4db94011d3 1185 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
sahilmgandhi 18:6a4db94011d3 1186
sahilmgandhi 18:6a4db94011d3 1187 /* Enable Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 1188 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 1189
sahilmgandhi 18:6a4db94011d3 1190 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1191 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1192
sahilmgandhi 18:6a4db94011d3 1193 /* Check if the SPI is already enabled */
sahilmgandhi 18:6a4db94011d3 1194 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 1195 {
sahilmgandhi 18:6a4db94011d3 1196 /* Enable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 1197 __HAL_SPI_ENABLE(hspi);
sahilmgandhi 18:6a4db94011d3 1198 }
sahilmgandhi 18:6a4db94011d3 1199
sahilmgandhi 18:6a4db94011d3 1200 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1201 }
sahilmgandhi 18:6a4db94011d3 1202 else
sahilmgandhi 18:6a4db94011d3 1203 {
sahilmgandhi 18:6a4db94011d3 1204 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1205 }
sahilmgandhi 18:6a4db94011d3 1206 }
sahilmgandhi 18:6a4db94011d3 1207
sahilmgandhi 18:6a4db94011d3 1208 /**
sahilmgandhi 18:6a4db94011d3 1209 * @brief Receive an amount of data in no-blocking mode with DMA
sahilmgandhi 18:6a4db94011d3 1210 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1211 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1212 * @param pData: pointer to data buffer
sahilmgandhi 18:6a4db94011d3 1213 * @note When the CRC feature is enabled the pData Length must be Size + 1.
sahilmgandhi 18:6a4db94011d3 1214 * @param Size: amount of data to be sent
sahilmgandhi 18:6a4db94011d3 1215 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1216 */
sahilmgandhi 18:6a4db94011d3 1217 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 1218 {
sahilmgandhi 18:6a4db94011d3 1219 if(hspi->State == HAL_SPI_STATE_READY)
sahilmgandhi 18:6a4db94011d3 1220 {
sahilmgandhi 18:6a4db94011d3 1221 if((pData == NULL) || (Size == 0))
sahilmgandhi 18:6a4db94011d3 1222 {
sahilmgandhi 18:6a4db94011d3 1223 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1224 }
sahilmgandhi 18:6a4db94011d3 1225
sahilmgandhi 18:6a4db94011d3 1226 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1227 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1228
sahilmgandhi 18:6a4db94011d3 1229 /* Configure communication */
sahilmgandhi 18:6a4db94011d3 1230 hspi->State = HAL_SPI_STATE_BUSY_RX;
sahilmgandhi 18:6a4db94011d3 1231 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1232
sahilmgandhi 18:6a4db94011d3 1233 hspi->pRxBuffPtr = pData;
sahilmgandhi 18:6a4db94011d3 1234 hspi->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 1235 hspi->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 1236
sahilmgandhi 18:6a4db94011d3 1237 /*Init field not used in handle to zero */
sahilmgandhi 18:6a4db94011d3 1238 hspi->RxISR = 0;
sahilmgandhi 18:6a4db94011d3 1239 hspi->TxISR = 0;
sahilmgandhi 18:6a4db94011d3 1240 hspi->pTxBuffPtr = NULL;
sahilmgandhi 18:6a4db94011d3 1241 hspi->TxXferSize = 0;
sahilmgandhi 18:6a4db94011d3 1242 hspi->TxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 1243
sahilmgandhi 18:6a4db94011d3 1244 /* Configure communication direction : 1Line */
sahilmgandhi 18:6a4db94011d3 1245 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
sahilmgandhi 18:6a4db94011d3 1246 {
sahilmgandhi 18:6a4db94011d3 1247 SPI_1LINE_RX(hspi);
sahilmgandhi 18:6a4db94011d3 1248 }
sahilmgandhi 18:6a4db94011d3 1249 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
sahilmgandhi 18:6a4db94011d3 1250 {
sahilmgandhi 18:6a4db94011d3 1251 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1252 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1253
sahilmgandhi 18:6a4db94011d3 1254 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
sahilmgandhi 18:6a4db94011d3 1255 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
sahilmgandhi 18:6a4db94011d3 1256 }
sahilmgandhi 18:6a4db94011d3 1257
sahilmgandhi 18:6a4db94011d3 1258 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 1259 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1260 {
sahilmgandhi 18:6a4db94011d3 1261 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 1262 }
sahilmgandhi 18:6a4db94011d3 1263
sahilmgandhi 18:6a4db94011d3 1264 /* Set the SPI RxDMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1265 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
sahilmgandhi 18:6a4db94011d3 1266
sahilmgandhi 18:6a4db94011d3 1267 /* Set the SPI Rx DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1268 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
sahilmgandhi 18:6a4db94011d3 1269
sahilmgandhi 18:6a4db94011d3 1270 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 1271 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
sahilmgandhi 18:6a4db94011d3 1272
sahilmgandhi 18:6a4db94011d3 1273 /* Enable the Rx DMA Channel */
sahilmgandhi 18:6a4db94011d3 1274 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
sahilmgandhi 18:6a4db94011d3 1275
sahilmgandhi 18:6a4db94011d3 1276 /* Enable Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 1277 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 1278
sahilmgandhi 18:6a4db94011d3 1279 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1280 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1281
sahilmgandhi 18:6a4db94011d3 1282 /* Check if the SPI is already enabled */
sahilmgandhi 18:6a4db94011d3 1283 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 1284 {
sahilmgandhi 18:6a4db94011d3 1285 /* Enable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 1286 __HAL_SPI_ENABLE(hspi);
sahilmgandhi 18:6a4db94011d3 1287 }
sahilmgandhi 18:6a4db94011d3 1288
sahilmgandhi 18:6a4db94011d3 1289 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1290 }
sahilmgandhi 18:6a4db94011d3 1291 else
sahilmgandhi 18:6a4db94011d3 1292 {
sahilmgandhi 18:6a4db94011d3 1293 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1294 }
sahilmgandhi 18:6a4db94011d3 1295 }
sahilmgandhi 18:6a4db94011d3 1296
sahilmgandhi 18:6a4db94011d3 1297 /**
sahilmgandhi 18:6a4db94011d3 1298 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
sahilmgandhi 18:6a4db94011d3 1299 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1300 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1301 * @param pTxData: pointer to transmission data buffer
sahilmgandhi 18:6a4db94011d3 1302 * @param pRxData: pointer to reception data buffer
sahilmgandhi 18:6a4db94011d3 1303 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
sahilmgandhi 18:6a4db94011d3 1304 * @param Size: amount of data to be sent
sahilmgandhi 18:6a4db94011d3 1305 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1306 */
sahilmgandhi 18:6a4db94011d3 1307 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
sahilmgandhi 18:6a4db94011d3 1308 {
sahilmgandhi 18:6a4db94011d3 1309 if((hspi->State == HAL_SPI_STATE_READY) || \
sahilmgandhi 18:6a4db94011d3 1310 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
sahilmgandhi 18:6a4db94011d3 1311 {
sahilmgandhi 18:6a4db94011d3 1312 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
sahilmgandhi 18:6a4db94011d3 1313 {
sahilmgandhi 18:6a4db94011d3 1314 return HAL_ERROR;
sahilmgandhi 18:6a4db94011d3 1315 }
sahilmgandhi 18:6a4db94011d3 1316
sahilmgandhi 18:6a4db94011d3 1317 /* Check the parameters */
sahilmgandhi 18:6a4db94011d3 1318 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
sahilmgandhi 18:6a4db94011d3 1319
sahilmgandhi 18:6a4db94011d3 1320 /* Process locked */
sahilmgandhi 18:6a4db94011d3 1321 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1322
sahilmgandhi 18:6a4db94011d3 1323 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
sahilmgandhi 18:6a4db94011d3 1324 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 1325 {
sahilmgandhi 18:6a4db94011d3 1326 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
sahilmgandhi 18:6a4db94011d3 1327 }
sahilmgandhi 18:6a4db94011d3 1328
sahilmgandhi 18:6a4db94011d3 1329 /* Configure communication */
sahilmgandhi 18:6a4db94011d3 1330 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
sahilmgandhi 18:6a4db94011d3 1331
sahilmgandhi 18:6a4db94011d3 1332 hspi->pTxBuffPtr = (uint8_t*)pTxData;
sahilmgandhi 18:6a4db94011d3 1333 hspi->TxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 1334 hspi->TxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 1335
sahilmgandhi 18:6a4db94011d3 1336 hspi->pRxBuffPtr = (uint8_t*)pRxData;
sahilmgandhi 18:6a4db94011d3 1337 hspi->RxXferSize = Size;
sahilmgandhi 18:6a4db94011d3 1338 hspi->RxXferCount = Size;
sahilmgandhi 18:6a4db94011d3 1339
sahilmgandhi 18:6a4db94011d3 1340 /*Init field not used in handle to zero */
sahilmgandhi 18:6a4db94011d3 1341 hspi->RxISR = 0;
sahilmgandhi 18:6a4db94011d3 1342 hspi->TxISR = 0;
sahilmgandhi 18:6a4db94011d3 1343
sahilmgandhi 18:6a4db94011d3 1344 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 1345 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1346 {
sahilmgandhi 18:6a4db94011d3 1347 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 1348 }
sahilmgandhi 18:6a4db94011d3 1349
sahilmgandhi 18:6a4db94011d3 1350 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1351 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 1352 {
sahilmgandhi 18:6a4db94011d3 1353 /* Set the SPI Rx DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1354 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
sahilmgandhi 18:6a4db94011d3 1355
sahilmgandhi 18:6a4db94011d3 1356 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
sahilmgandhi 18:6a4db94011d3 1357 }
sahilmgandhi 18:6a4db94011d3 1358 else
sahilmgandhi 18:6a4db94011d3 1359 {
sahilmgandhi 18:6a4db94011d3 1360 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
sahilmgandhi 18:6a4db94011d3 1361 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
sahilmgandhi 18:6a4db94011d3 1362
sahilmgandhi 18:6a4db94011d3 1363 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
sahilmgandhi 18:6a4db94011d3 1364 }
sahilmgandhi 18:6a4db94011d3 1365
sahilmgandhi 18:6a4db94011d3 1366 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 1367 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
sahilmgandhi 18:6a4db94011d3 1368
sahilmgandhi 18:6a4db94011d3 1369 /* Enable the Rx DMA Channel */
sahilmgandhi 18:6a4db94011d3 1370 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
sahilmgandhi 18:6a4db94011d3 1371
sahilmgandhi 18:6a4db94011d3 1372 /* Enable Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 1373 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 1374
sahilmgandhi 18:6a4db94011d3 1375 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
sahilmgandhi 18:6a4db94011d3 1376 is performed in DMA reception complete callback */
sahilmgandhi 18:6a4db94011d3 1377 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
sahilmgandhi 18:6a4db94011d3 1378 {
sahilmgandhi 18:6a4db94011d3 1379 /* Set the DMA error callback */
sahilmgandhi 18:6a4db94011d3 1380 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
sahilmgandhi 18:6a4db94011d3 1381 }
sahilmgandhi 18:6a4db94011d3 1382 else
sahilmgandhi 18:6a4db94011d3 1383 {
sahilmgandhi 18:6a4db94011d3 1384 hspi->hdmatx->XferErrorCallback = NULL;
sahilmgandhi 18:6a4db94011d3 1385 }
sahilmgandhi 18:6a4db94011d3 1386
sahilmgandhi 18:6a4db94011d3 1387 /* Enable the Tx DMA Channel */
sahilmgandhi 18:6a4db94011d3 1388 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
sahilmgandhi 18:6a4db94011d3 1389
sahilmgandhi 18:6a4db94011d3 1390 /* Check if the SPI is already enabled */
sahilmgandhi 18:6a4db94011d3 1391 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
sahilmgandhi 18:6a4db94011d3 1392 {
sahilmgandhi 18:6a4db94011d3 1393 /* Enable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 1394 __HAL_SPI_ENABLE(hspi);
sahilmgandhi 18:6a4db94011d3 1395 }
sahilmgandhi 18:6a4db94011d3 1396
sahilmgandhi 18:6a4db94011d3 1397 /* Enable Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 1398 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 1399
sahilmgandhi 18:6a4db94011d3 1400 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1401 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1402
sahilmgandhi 18:6a4db94011d3 1403 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1404 }
sahilmgandhi 18:6a4db94011d3 1405 else
sahilmgandhi 18:6a4db94011d3 1406 {
sahilmgandhi 18:6a4db94011d3 1407 return HAL_BUSY;
sahilmgandhi 18:6a4db94011d3 1408 }
sahilmgandhi 18:6a4db94011d3 1409 }
sahilmgandhi 18:6a4db94011d3 1410
sahilmgandhi 18:6a4db94011d3 1411
sahilmgandhi 18:6a4db94011d3 1412 /**
sahilmgandhi 18:6a4db94011d3 1413 * @brief Pauses the DMA Transfer.
sahilmgandhi 18:6a4db94011d3 1414 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1415 * the configuration information for the specified SPI module.
sahilmgandhi 18:6a4db94011d3 1416 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1417 */
sahilmgandhi 18:6a4db94011d3 1418 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1419 {
sahilmgandhi 18:6a4db94011d3 1420 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1421 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1422
sahilmgandhi 18:6a4db94011d3 1423 /* Disable the SPI DMA Tx & Rx requests */
sahilmgandhi 18:6a4db94011d3 1424 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 1425 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 1426
sahilmgandhi 18:6a4db94011d3 1427 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1428 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1429
sahilmgandhi 18:6a4db94011d3 1430 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1431 }
sahilmgandhi 18:6a4db94011d3 1432
sahilmgandhi 18:6a4db94011d3 1433 /**
sahilmgandhi 18:6a4db94011d3 1434 * @brief Resumes the DMA Transfer.
sahilmgandhi 18:6a4db94011d3 1435 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1436 * the configuration information for the specified SPI module.
sahilmgandhi 18:6a4db94011d3 1437 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1438 */
sahilmgandhi 18:6a4db94011d3 1439 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1440 {
sahilmgandhi 18:6a4db94011d3 1441 /* Process Locked */
sahilmgandhi 18:6a4db94011d3 1442 __HAL_LOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1443
sahilmgandhi 18:6a4db94011d3 1444 /* Enable the SPI DMA Tx & Rx requests */
sahilmgandhi 18:6a4db94011d3 1445 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 1446 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 1447
sahilmgandhi 18:6a4db94011d3 1448 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 1449 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 1450
sahilmgandhi 18:6a4db94011d3 1451 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1452 }
sahilmgandhi 18:6a4db94011d3 1453
sahilmgandhi 18:6a4db94011d3 1454 /**
sahilmgandhi 18:6a4db94011d3 1455 * @brief Stops the DMA Transfer.
sahilmgandhi 18:6a4db94011d3 1456 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1457 * the configuration information for the specified UART module.
sahilmgandhi 18:6a4db94011d3 1458 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1459 */
sahilmgandhi 18:6a4db94011d3 1460 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1461 {
sahilmgandhi 18:6a4db94011d3 1462 /* The Lock is not implemented on this API to allow the user application
sahilmgandhi 18:6a4db94011d3 1463 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
sahilmgandhi 18:6a4db94011d3 1464 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
sahilmgandhi 18:6a4db94011d3 1465 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
sahilmgandhi 18:6a4db94011d3 1466 */
sahilmgandhi 18:6a4db94011d3 1467
sahilmgandhi 18:6a4db94011d3 1468 /* Abort the SPI DMA tx Channel */
sahilmgandhi 18:6a4db94011d3 1469 if(hspi->hdmatx != NULL)
sahilmgandhi 18:6a4db94011d3 1470 {
sahilmgandhi 18:6a4db94011d3 1471 HAL_DMA_Abort(hspi->hdmatx);
sahilmgandhi 18:6a4db94011d3 1472 }
sahilmgandhi 18:6a4db94011d3 1473 /* Abort the SPI DMA rx Channel */
sahilmgandhi 18:6a4db94011d3 1474 if(hspi->hdmarx != NULL)
sahilmgandhi 18:6a4db94011d3 1475 {
sahilmgandhi 18:6a4db94011d3 1476 HAL_DMA_Abort(hspi->hdmarx);
sahilmgandhi 18:6a4db94011d3 1477 }
sahilmgandhi 18:6a4db94011d3 1478
sahilmgandhi 18:6a4db94011d3 1479 /* Disable the SPI DMA Tx & Rx requests */
sahilmgandhi 18:6a4db94011d3 1480 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 1481 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 1482
sahilmgandhi 18:6a4db94011d3 1483 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1484
sahilmgandhi 18:6a4db94011d3 1485 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 1486 }
sahilmgandhi 18:6a4db94011d3 1487
sahilmgandhi 18:6a4db94011d3 1488 /**
sahilmgandhi 18:6a4db94011d3 1489 * @brief This function handles SPI interrupt request.
sahilmgandhi 18:6a4db94011d3 1490 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1491 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1492 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 1493 */
sahilmgandhi 18:6a4db94011d3 1494 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1495 {
sahilmgandhi 18:6a4db94011d3 1496 /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
sahilmgandhi 18:6a4db94011d3 1497 if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
sahilmgandhi 18:6a4db94011d3 1498 {
sahilmgandhi 18:6a4db94011d3 1499 hspi->RxISR(hspi);
sahilmgandhi 18:6a4db94011d3 1500 return;
sahilmgandhi 18:6a4db94011d3 1501 }
sahilmgandhi 18:6a4db94011d3 1502
sahilmgandhi 18:6a4db94011d3 1503 /* SPI in mode Tramitter ---------------------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1504 if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
sahilmgandhi 18:6a4db94011d3 1505 {
sahilmgandhi 18:6a4db94011d3 1506 hspi->TxISR(hspi);
sahilmgandhi 18:6a4db94011d3 1507 return;
sahilmgandhi 18:6a4db94011d3 1508 }
sahilmgandhi 18:6a4db94011d3 1509
sahilmgandhi 18:6a4db94011d3 1510 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
sahilmgandhi 18:6a4db94011d3 1511 {
sahilmgandhi 18:6a4db94011d3 1512 /* SPI CRC error interrupt occurred ---------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1513 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
sahilmgandhi 18:6a4db94011d3 1514 {
sahilmgandhi 18:6a4db94011d3 1515 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi 18:6a4db94011d3 1516 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 1517 }
sahilmgandhi 18:6a4db94011d3 1518 /* SPI Mode Fault error interrupt occurred --------------------------------*/
sahilmgandhi 18:6a4db94011d3 1519 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
sahilmgandhi 18:6a4db94011d3 1520 {
sahilmgandhi 18:6a4db94011d3 1521 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
sahilmgandhi 18:6a4db94011d3 1522 __HAL_SPI_CLEAR_MODFFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 1523 }
sahilmgandhi 18:6a4db94011d3 1524
sahilmgandhi 18:6a4db94011d3 1525 /* SPI Overrun error interrupt occurred -----------------------------------*/
sahilmgandhi 18:6a4db94011d3 1526 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
sahilmgandhi 18:6a4db94011d3 1527 {
sahilmgandhi 18:6a4db94011d3 1528 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
sahilmgandhi 18:6a4db94011d3 1529 {
sahilmgandhi 18:6a4db94011d3 1530 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
sahilmgandhi 18:6a4db94011d3 1531 __HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 1532 }
sahilmgandhi 18:6a4db94011d3 1533 }
sahilmgandhi 18:6a4db94011d3 1534
sahilmgandhi 18:6a4db94011d3 1535 /* SPI Frame error interrupt occurred -------------------------------------*/
sahilmgandhi 18:6a4db94011d3 1536 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
sahilmgandhi 18:6a4db94011d3 1537 {
sahilmgandhi 18:6a4db94011d3 1538 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
sahilmgandhi 18:6a4db94011d3 1539 __HAL_SPI_CLEAR_FREFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 1540 }
sahilmgandhi 18:6a4db94011d3 1541
sahilmgandhi 18:6a4db94011d3 1542 /* Call the Error call Back in case of Errors */
sahilmgandhi 18:6a4db94011d3 1543 if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 1544 {
sahilmgandhi 18:6a4db94011d3 1545 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
sahilmgandhi 18:6a4db94011d3 1546 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 1547 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 1548 }
sahilmgandhi 18:6a4db94011d3 1549 }
sahilmgandhi 18:6a4db94011d3 1550 }
sahilmgandhi 18:6a4db94011d3 1551
sahilmgandhi 18:6a4db94011d3 1552 /**
sahilmgandhi 18:6a4db94011d3 1553 * @brief Tx Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1554 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1555 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1556 * @retval None
sahilmgandhi 18:6a4db94011d3 1557 */
sahilmgandhi 18:6a4db94011d3 1558 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1559 {
sahilmgandhi 18:6a4db94011d3 1560 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1561 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 1562
sahilmgandhi 18:6a4db94011d3 1563 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1564 the HAL_SPI_TxCpltCallback could be implenetd in the user file
sahilmgandhi 18:6a4db94011d3 1565 */
sahilmgandhi 18:6a4db94011d3 1566 }
sahilmgandhi 18:6a4db94011d3 1567
sahilmgandhi 18:6a4db94011d3 1568 /**
sahilmgandhi 18:6a4db94011d3 1569 * @brief Rx Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1570 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1571 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1572 * @retval None
sahilmgandhi 18:6a4db94011d3 1573 */
sahilmgandhi 18:6a4db94011d3 1574 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1575 {
sahilmgandhi 18:6a4db94011d3 1576 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1577 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 1578
sahilmgandhi 18:6a4db94011d3 1579 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1580 the HAL_SPI_RxCpltCallback() could be implenetd in the user file
sahilmgandhi 18:6a4db94011d3 1581 */
sahilmgandhi 18:6a4db94011d3 1582 }
sahilmgandhi 18:6a4db94011d3 1583
sahilmgandhi 18:6a4db94011d3 1584 /**
sahilmgandhi 18:6a4db94011d3 1585 * @brief Tx and Rx Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1586 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1587 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1588 * @retval None
sahilmgandhi 18:6a4db94011d3 1589 */
sahilmgandhi 18:6a4db94011d3 1590 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1591 {
sahilmgandhi 18:6a4db94011d3 1592 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1593 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 1594
sahilmgandhi 18:6a4db94011d3 1595 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1596 the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
sahilmgandhi 18:6a4db94011d3 1597 */
sahilmgandhi 18:6a4db94011d3 1598 }
sahilmgandhi 18:6a4db94011d3 1599
sahilmgandhi 18:6a4db94011d3 1600 /**
sahilmgandhi 18:6a4db94011d3 1601 * @brief Tx Half Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1602 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1603 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1604 * @retval None
sahilmgandhi 18:6a4db94011d3 1605 */
sahilmgandhi 18:6a4db94011d3 1606 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1607 {
sahilmgandhi 18:6a4db94011d3 1608 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1609 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 1610
sahilmgandhi 18:6a4db94011d3 1611 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1612 the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
sahilmgandhi 18:6a4db94011d3 1613 */
sahilmgandhi 18:6a4db94011d3 1614 }
sahilmgandhi 18:6a4db94011d3 1615
sahilmgandhi 18:6a4db94011d3 1616 /**
sahilmgandhi 18:6a4db94011d3 1617 * @brief Rx Half Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1618 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1619 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1620 * @retval None
sahilmgandhi 18:6a4db94011d3 1621 */
sahilmgandhi 18:6a4db94011d3 1622 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1623 {
sahilmgandhi 18:6a4db94011d3 1624 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1625 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 1626
sahilmgandhi 18:6a4db94011d3 1627 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1628 the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
sahilmgandhi 18:6a4db94011d3 1629 */
sahilmgandhi 18:6a4db94011d3 1630 }
sahilmgandhi 18:6a4db94011d3 1631
sahilmgandhi 18:6a4db94011d3 1632 /**
sahilmgandhi 18:6a4db94011d3 1633 * @brief Tx and Rx Transfer completed callbacks
sahilmgandhi 18:6a4db94011d3 1634 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1635 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1636 * @retval None
sahilmgandhi 18:6a4db94011d3 1637 */
sahilmgandhi 18:6a4db94011d3 1638 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1639 {
sahilmgandhi 18:6a4db94011d3 1640 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1641 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 1642
sahilmgandhi 18:6a4db94011d3 1643 /* NOTE : This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1644 the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
sahilmgandhi 18:6a4db94011d3 1645 */
sahilmgandhi 18:6a4db94011d3 1646 }
sahilmgandhi 18:6a4db94011d3 1647
sahilmgandhi 18:6a4db94011d3 1648 /**
sahilmgandhi 18:6a4db94011d3 1649 * @brief SPI error callbacks
sahilmgandhi 18:6a4db94011d3 1650 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1651 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1652 * @retval None
sahilmgandhi 18:6a4db94011d3 1653 */
sahilmgandhi 18:6a4db94011d3 1654 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1655 {
sahilmgandhi 18:6a4db94011d3 1656 /* Prevent unused argument(s) compilation warning */
sahilmgandhi 18:6a4db94011d3 1657 UNUSED(hspi);
sahilmgandhi 18:6a4db94011d3 1658
sahilmgandhi 18:6a4db94011d3 1659 /* NOTE : - This function Should not be modified, when the callback is needed,
sahilmgandhi 18:6a4db94011d3 1660 the HAL_SPI_ErrorCallback() could be implenetd in the user file.
sahilmgandhi 18:6a4db94011d3 1661 - The ErrorCode parameter in the hspi handle is updated by the SPI processes
sahilmgandhi 18:6a4db94011d3 1662 and user can use HAL_SPI_GetError() API to check the latest error occurred.
sahilmgandhi 18:6a4db94011d3 1663 */
sahilmgandhi 18:6a4db94011d3 1664 }
sahilmgandhi 18:6a4db94011d3 1665
sahilmgandhi 18:6a4db94011d3 1666 /**
sahilmgandhi 18:6a4db94011d3 1667 * @}
sahilmgandhi 18:6a4db94011d3 1668 */
sahilmgandhi 18:6a4db94011d3 1669
sahilmgandhi 18:6a4db94011d3 1670 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
sahilmgandhi 18:6a4db94011d3 1671 * @brief SPI control functions
sahilmgandhi 18:6a4db94011d3 1672 *
sahilmgandhi 18:6a4db94011d3 1673 @verbatim
sahilmgandhi 18:6a4db94011d3 1674 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1675 ##### Peripheral State and Errors functions #####
sahilmgandhi 18:6a4db94011d3 1676 ===============================================================================
sahilmgandhi 18:6a4db94011d3 1677 [..]
sahilmgandhi 18:6a4db94011d3 1678 This subsection provides a set of functions allowing to control the SPI.
sahilmgandhi 18:6a4db94011d3 1679 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
sahilmgandhi 18:6a4db94011d3 1680 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
sahilmgandhi 18:6a4db94011d3 1681 @endverbatim
sahilmgandhi 18:6a4db94011d3 1682 * @{
sahilmgandhi 18:6a4db94011d3 1683 */
sahilmgandhi 18:6a4db94011d3 1684
sahilmgandhi 18:6a4db94011d3 1685 /**
sahilmgandhi 18:6a4db94011d3 1686 * @brief Return the SPI state
sahilmgandhi 18:6a4db94011d3 1687 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1688 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1689 * @retval HAL state
sahilmgandhi 18:6a4db94011d3 1690 */
sahilmgandhi 18:6a4db94011d3 1691 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1692 {
sahilmgandhi 18:6a4db94011d3 1693 return hspi->State;
sahilmgandhi 18:6a4db94011d3 1694 }
sahilmgandhi 18:6a4db94011d3 1695
sahilmgandhi 18:6a4db94011d3 1696 /**
sahilmgandhi 18:6a4db94011d3 1697 * @brief Return the SPI error code
sahilmgandhi 18:6a4db94011d3 1698 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1699 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1700 * @retval SPI Error Code
sahilmgandhi 18:6a4db94011d3 1701 */
sahilmgandhi 18:6a4db94011d3 1702 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1703 {
sahilmgandhi 18:6a4db94011d3 1704 return hspi->ErrorCode;
sahilmgandhi 18:6a4db94011d3 1705 }
sahilmgandhi 18:6a4db94011d3 1706
sahilmgandhi 18:6a4db94011d3 1707 /**
sahilmgandhi 18:6a4db94011d3 1708 * @}
sahilmgandhi 18:6a4db94011d3 1709 */
sahilmgandhi 18:6a4db94011d3 1710
sahilmgandhi 18:6a4db94011d3 1711 /**
sahilmgandhi 18:6a4db94011d3 1712 * @}
sahilmgandhi 18:6a4db94011d3 1713 */
sahilmgandhi 18:6a4db94011d3 1714
sahilmgandhi 18:6a4db94011d3 1715
sahilmgandhi 18:6a4db94011d3 1716
sahilmgandhi 18:6a4db94011d3 1717 /** @addtogroup SPI_Private_Functions
sahilmgandhi 18:6a4db94011d3 1718 * @{
sahilmgandhi 18:6a4db94011d3 1719 */
sahilmgandhi 18:6a4db94011d3 1720
sahilmgandhi 18:6a4db94011d3 1721 /**
sahilmgandhi 18:6a4db94011d3 1722 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 1723 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1724 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1725 * @retval None
sahilmgandhi 18:6a4db94011d3 1726 */
sahilmgandhi 18:6a4db94011d3 1727 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1728 {
sahilmgandhi 18:6a4db94011d3 1729 /* Receive data in 8bit mode */
sahilmgandhi 18:6a4db94011d3 1730 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
sahilmgandhi 18:6a4db94011d3 1731 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 1732
sahilmgandhi 18:6a4db94011d3 1733 /* check end of the reception */
sahilmgandhi 18:6a4db94011d3 1734 if(hspi->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1735 {
sahilmgandhi 18:6a4db94011d3 1736 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1737 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1738 {
sahilmgandhi 18:6a4db94011d3 1739 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
sahilmgandhi 18:6a4db94011d3 1740 return;
sahilmgandhi 18:6a4db94011d3 1741 }
sahilmgandhi 18:6a4db94011d3 1742 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1743
sahilmgandhi 18:6a4db94011d3 1744 /* Disable RXNE interrupt */
sahilmgandhi 18:6a4db94011d3 1745 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 1746
sahilmgandhi 18:6a4db94011d3 1747 if(hspi->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1748 {
sahilmgandhi 18:6a4db94011d3 1749 SPI_CloseRxTx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 1750 }
sahilmgandhi 18:6a4db94011d3 1751 }
sahilmgandhi 18:6a4db94011d3 1752 }
sahilmgandhi 18:6a4db94011d3 1753
sahilmgandhi 18:6a4db94011d3 1754 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1755 /**
sahilmgandhi 18:6a4db94011d3 1756 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 1757 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1758 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1759 * @retval None
sahilmgandhi 18:6a4db94011d3 1760 */
sahilmgandhi 18:6a4db94011d3 1761 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1762 {
sahilmgandhi 18:6a4db94011d3 1763 __IO uint8_t tmpreg = 0U;
sahilmgandhi 18:6a4db94011d3 1764
sahilmgandhi 18:6a4db94011d3 1765 /* Read data register to flush CRC */
sahilmgandhi 18:6a4db94011d3 1766 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
sahilmgandhi 18:6a4db94011d3 1767
sahilmgandhi 18:6a4db94011d3 1768 /* To avoid GCC warning */
sahilmgandhi 18:6a4db94011d3 1769
sahilmgandhi 18:6a4db94011d3 1770 UNUSED(tmpreg);
sahilmgandhi 18:6a4db94011d3 1771
sahilmgandhi 18:6a4db94011d3 1772 /* Disable RXNE interrupt */
sahilmgandhi 18:6a4db94011d3 1773 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 1774
sahilmgandhi 18:6a4db94011d3 1775 if(hspi->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1776 {
sahilmgandhi 18:6a4db94011d3 1777 SPI_CloseRxTx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 1778 }
sahilmgandhi 18:6a4db94011d3 1779 }
sahilmgandhi 18:6a4db94011d3 1780 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1781
sahilmgandhi 18:6a4db94011d3 1782 /**
sahilmgandhi 18:6a4db94011d3 1783 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 1784 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1785 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1786 * @retval None
sahilmgandhi 18:6a4db94011d3 1787 */
sahilmgandhi 18:6a4db94011d3 1788 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1789 {
sahilmgandhi 18:6a4db94011d3 1790 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 1791 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 1792
sahilmgandhi 18:6a4db94011d3 1793 /* check the end of the transmission */
sahilmgandhi 18:6a4db94011d3 1794 if(hspi->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1795 {
sahilmgandhi 18:6a4db94011d3 1796 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1797 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1798 {
sahilmgandhi 18:6a4db94011d3 1799 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 1800 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
sahilmgandhi 18:6a4db94011d3 1801 return;
sahilmgandhi 18:6a4db94011d3 1802 }
sahilmgandhi 18:6a4db94011d3 1803 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1804
sahilmgandhi 18:6a4db94011d3 1805 /* Disable TXE interrupt */
sahilmgandhi 18:6a4db94011d3 1806 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
sahilmgandhi 18:6a4db94011d3 1807
sahilmgandhi 18:6a4db94011d3 1808 if(hspi->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1809 {
sahilmgandhi 18:6a4db94011d3 1810 SPI_CloseRxTx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 1811 }
sahilmgandhi 18:6a4db94011d3 1812 }
sahilmgandhi 18:6a4db94011d3 1813 }
sahilmgandhi 18:6a4db94011d3 1814
sahilmgandhi 18:6a4db94011d3 1815 /**
sahilmgandhi 18:6a4db94011d3 1816 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 1817 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1818 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1819 * @retval None
sahilmgandhi 18:6a4db94011d3 1820 */
sahilmgandhi 18:6a4db94011d3 1821 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1822 {
sahilmgandhi 18:6a4db94011d3 1823 /* Receive data in 16 Bit mode */
sahilmgandhi 18:6a4db94011d3 1824 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 1825 hspi->pRxBuffPtr += sizeof(uint16_t);
sahilmgandhi 18:6a4db94011d3 1826 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 1827
sahilmgandhi 18:6a4db94011d3 1828 if(hspi->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1829 {
sahilmgandhi 18:6a4db94011d3 1830 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1831 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1832 {
sahilmgandhi 18:6a4db94011d3 1833 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
sahilmgandhi 18:6a4db94011d3 1834 return;
sahilmgandhi 18:6a4db94011d3 1835 }
sahilmgandhi 18:6a4db94011d3 1836 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1837
sahilmgandhi 18:6a4db94011d3 1838 /* Disable RXNE interrupt */
sahilmgandhi 18:6a4db94011d3 1839 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
sahilmgandhi 18:6a4db94011d3 1840
sahilmgandhi 18:6a4db94011d3 1841 if(hspi->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1842 {
sahilmgandhi 18:6a4db94011d3 1843 SPI_CloseRxTx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 1844 }
sahilmgandhi 18:6a4db94011d3 1845 }
sahilmgandhi 18:6a4db94011d3 1846 }
sahilmgandhi 18:6a4db94011d3 1847
sahilmgandhi 18:6a4db94011d3 1848 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1849 /**
sahilmgandhi 18:6a4db94011d3 1850 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 1851 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1852 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1853 * @retval None
sahilmgandhi 18:6a4db94011d3 1854 */
sahilmgandhi 18:6a4db94011d3 1855 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1856 {
sahilmgandhi 18:6a4db94011d3 1857 /* Receive data in 16 Bit mode */
sahilmgandhi 18:6a4db94011d3 1858 __IO uint16_t tmpreg = 0U;
sahilmgandhi 18:6a4db94011d3 1859
sahilmgandhi 18:6a4db94011d3 1860 /* Read data register to flush CRC */
sahilmgandhi 18:6a4db94011d3 1861 tmpreg = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 1862
sahilmgandhi 18:6a4db94011d3 1863 /* To avoid GCC warning */
sahilmgandhi 18:6a4db94011d3 1864 UNUSED(tmpreg);
sahilmgandhi 18:6a4db94011d3 1865
sahilmgandhi 18:6a4db94011d3 1866 /* Disable RXNE interrupt */
sahilmgandhi 18:6a4db94011d3 1867 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
sahilmgandhi 18:6a4db94011d3 1868
sahilmgandhi 18:6a4db94011d3 1869 SPI_CloseRxTx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 1870 }
sahilmgandhi 18:6a4db94011d3 1871 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1872
sahilmgandhi 18:6a4db94011d3 1873 /**
sahilmgandhi 18:6a4db94011d3 1874 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 1875 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1876 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1877 * @retval None
sahilmgandhi 18:6a4db94011d3 1878 */
sahilmgandhi 18:6a4db94011d3 1879 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1880 {
sahilmgandhi 18:6a4db94011d3 1881 /* Transmit data in 16 Bit mode */
sahilmgandhi 18:6a4db94011d3 1882 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
sahilmgandhi 18:6a4db94011d3 1883 hspi->pTxBuffPtr += sizeof(uint16_t);
sahilmgandhi 18:6a4db94011d3 1884 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 1885
sahilmgandhi 18:6a4db94011d3 1886 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 1887 if(hspi->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1888 {
sahilmgandhi 18:6a4db94011d3 1889 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1890 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1891 {
sahilmgandhi 18:6a4db94011d3 1892 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 1893 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
sahilmgandhi 18:6a4db94011d3 1894 return;
sahilmgandhi 18:6a4db94011d3 1895 }
sahilmgandhi 18:6a4db94011d3 1896 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1897
sahilmgandhi 18:6a4db94011d3 1898 /* Disable TXE interrupt */
sahilmgandhi 18:6a4db94011d3 1899 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
sahilmgandhi 18:6a4db94011d3 1900
sahilmgandhi 18:6a4db94011d3 1901 if(hspi->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1902 {
sahilmgandhi 18:6a4db94011d3 1903 SPI_CloseRxTx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 1904 }
sahilmgandhi 18:6a4db94011d3 1905 }
sahilmgandhi 18:6a4db94011d3 1906 }
sahilmgandhi 18:6a4db94011d3 1907
sahilmgandhi 18:6a4db94011d3 1908 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1909 /**
sahilmgandhi 18:6a4db94011d3 1910 * @brief Manage the CRC 8-bit receive in Interrupt context.
sahilmgandhi 18:6a4db94011d3 1911 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1912 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1913 * @retval None
sahilmgandhi 18:6a4db94011d3 1914 */
sahilmgandhi 18:6a4db94011d3 1915 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1916 {
sahilmgandhi 18:6a4db94011d3 1917 __IO uint8_t tmpreg = 0U;
sahilmgandhi 18:6a4db94011d3 1918
sahilmgandhi 18:6a4db94011d3 1919 /* Read data register to flush CRC */
sahilmgandhi 18:6a4db94011d3 1920 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
sahilmgandhi 18:6a4db94011d3 1921
sahilmgandhi 18:6a4db94011d3 1922 /* To avoid GCC warning */
sahilmgandhi 18:6a4db94011d3 1923 UNUSED(tmpreg);
sahilmgandhi 18:6a4db94011d3 1924
sahilmgandhi 18:6a4db94011d3 1925 SPI_CloseRx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 1926 }
sahilmgandhi 18:6a4db94011d3 1927 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1928
sahilmgandhi 18:6a4db94011d3 1929 /**
sahilmgandhi 18:6a4db94011d3 1930 * @brief Manage the receive 8-bit in Interrupt context.
sahilmgandhi 18:6a4db94011d3 1931 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1932 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1933 * @retval None
sahilmgandhi 18:6a4db94011d3 1934 */
sahilmgandhi 18:6a4db94011d3 1935 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1936 {
sahilmgandhi 18:6a4db94011d3 1937 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
sahilmgandhi 18:6a4db94011d3 1938 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 1939
sahilmgandhi 18:6a4db94011d3 1940 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1941 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 1942 if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
sahilmgandhi 18:6a4db94011d3 1943 {
sahilmgandhi 18:6a4db94011d3 1944 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 1945 }
sahilmgandhi 18:6a4db94011d3 1946 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1947
sahilmgandhi 18:6a4db94011d3 1948 if(hspi->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 1949 {
sahilmgandhi 18:6a4db94011d3 1950 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1951 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 1952 {
sahilmgandhi 18:6a4db94011d3 1953 hspi->RxISR = SPI_RxISR_8BITCRC;
sahilmgandhi 18:6a4db94011d3 1954 return;
sahilmgandhi 18:6a4db94011d3 1955 }
sahilmgandhi 18:6a4db94011d3 1956 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1957 SPI_CloseRx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 1958 }
sahilmgandhi 18:6a4db94011d3 1959 }
sahilmgandhi 18:6a4db94011d3 1960
sahilmgandhi 18:6a4db94011d3 1961 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1962 /**
sahilmgandhi 18:6a4db94011d3 1963 * @brief Manage the CRC 16-bit receive in Interrupt context.
sahilmgandhi 18:6a4db94011d3 1964 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1965 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1966 * @retval None
sahilmgandhi 18:6a4db94011d3 1967 */
sahilmgandhi 18:6a4db94011d3 1968 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1969 {
sahilmgandhi 18:6a4db94011d3 1970 __IO uint16_t tmpreg = 0U;
sahilmgandhi 18:6a4db94011d3 1971
sahilmgandhi 18:6a4db94011d3 1972 /* Read data register to flush CRC */
sahilmgandhi 18:6a4db94011d3 1973 tmpreg = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 1974
sahilmgandhi 18:6a4db94011d3 1975 /* To avoid GCC warning */
sahilmgandhi 18:6a4db94011d3 1976 UNUSED(tmpreg);
sahilmgandhi 18:6a4db94011d3 1977
sahilmgandhi 18:6a4db94011d3 1978 /* Disable RXNE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 1979 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 1980
sahilmgandhi 18:6a4db94011d3 1981 SPI_CloseRx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 1982 }
sahilmgandhi 18:6a4db94011d3 1983 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 1984
sahilmgandhi 18:6a4db94011d3 1985 /**
sahilmgandhi 18:6a4db94011d3 1986 * @brief Manage the 16-bit receive in Interrupt context.
sahilmgandhi 18:6a4db94011d3 1987 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 1988 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 1989 * @retval None
sahilmgandhi 18:6a4db94011d3 1990 */
sahilmgandhi 18:6a4db94011d3 1991 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 1992 {
sahilmgandhi 18:6a4db94011d3 1993 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 1994 hspi->pRxBuffPtr += sizeof(uint16_t);
sahilmgandhi 18:6a4db94011d3 1995 hspi->RxXferCount--;
sahilmgandhi 18:6a4db94011d3 1996
sahilmgandhi 18:6a4db94011d3 1997 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 1998 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 1999 if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
sahilmgandhi 18:6a4db94011d3 2000 {
sahilmgandhi 18:6a4db94011d3 2001 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 2002 }
sahilmgandhi 18:6a4db94011d3 2003 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 2004
sahilmgandhi 18:6a4db94011d3 2005 if(hspi->RxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 2006 {
sahilmgandhi 18:6a4db94011d3 2007 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 2008 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 2009 {
sahilmgandhi 18:6a4db94011d3 2010 hspi->RxISR = SPI_RxISR_16BITCRC;
sahilmgandhi 18:6a4db94011d3 2011 return;
sahilmgandhi 18:6a4db94011d3 2012 }
sahilmgandhi 18:6a4db94011d3 2013 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 2014 SPI_CloseRx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 2015 }
sahilmgandhi 18:6a4db94011d3 2016 }
sahilmgandhi 18:6a4db94011d3 2017
sahilmgandhi 18:6a4db94011d3 2018 /**
sahilmgandhi 18:6a4db94011d3 2019 * @brief Handle the data 8-bit transmit in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 2020 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2021 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 2022 * @retval None
sahilmgandhi 18:6a4db94011d3 2023 */
sahilmgandhi 18:6a4db94011d3 2024 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 2025 {
sahilmgandhi 18:6a4db94011d3 2026 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
sahilmgandhi 18:6a4db94011d3 2027 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 2028
sahilmgandhi 18:6a4db94011d3 2029 if(hspi->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 2030 {
sahilmgandhi 18:6a4db94011d3 2031 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 2032 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 2033 {
sahilmgandhi 18:6a4db94011d3 2034 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 2035 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 2036 }
sahilmgandhi 18:6a4db94011d3 2037 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 2038 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
sahilmgandhi 18:6a4db94011d3 2039 SPI_CloseTx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 2040 }
sahilmgandhi 18:6a4db94011d3 2041 }
sahilmgandhi 18:6a4db94011d3 2042
sahilmgandhi 18:6a4db94011d3 2043 /**
sahilmgandhi 18:6a4db94011d3 2044 * @brief Handle the data 16-bit transmit in Interrupt mode.
sahilmgandhi 18:6a4db94011d3 2045 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2046 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 2047 * @retval None
sahilmgandhi 18:6a4db94011d3 2048 */
sahilmgandhi 18:6a4db94011d3 2049 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 2050 {
sahilmgandhi 18:6a4db94011d3 2051 /* Transmit data in 16 Bit mode */
sahilmgandhi 18:6a4db94011d3 2052 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
sahilmgandhi 18:6a4db94011d3 2053 hspi->pTxBuffPtr += sizeof(uint16_t);
sahilmgandhi 18:6a4db94011d3 2054 hspi->TxXferCount--;
sahilmgandhi 18:6a4db94011d3 2055
sahilmgandhi 18:6a4db94011d3 2056 if(hspi->TxXferCount == 0U)
sahilmgandhi 18:6a4db94011d3 2057 {
sahilmgandhi 18:6a4db94011d3 2058 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 2059 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 2060 {
sahilmgandhi 18:6a4db94011d3 2061 /* Enable CRC Transmission */
sahilmgandhi 18:6a4db94011d3 2062 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
sahilmgandhi 18:6a4db94011d3 2063 }
sahilmgandhi 18:6a4db94011d3 2064 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 2065 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
sahilmgandhi 18:6a4db94011d3 2066 SPI_CloseTx_ISR(hspi);
sahilmgandhi 18:6a4db94011d3 2067 }
sahilmgandhi 18:6a4db94011d3 2068 }
sahilmgandhi 18:6a4db94011d3 2069
sahilmgandhi 18:6a4db94011d3 2070 /**
sahilmgandhi 18:6a4db94011d3 2071 * @brief Handle SPI Communication Timeout.
sahilmgandhi 18:6a4db94011d3 2072 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2073 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 2074 * @param Flag: SPI flag to check
sahilmgandhi 18:6a4db94011d3 2075 * @param State: flag state to check
sahilmgandhi 18:6a4db94011d3 2076 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 2077 * @param Tickstart: tick start value
sahilmgandhi 18:6a4db94011d3 2078 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 2079 */
sahilmgandhi 18:6a4db94011d3 2080 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
sahilmgandhi 18:6a4db94011d3 2081 {
sahilmgandhi 18:6a4db94011d3 2082 while((hspi->Instance->SR & Flag) != State)
sahilmgandhi 18:6a4db94011d3 2083 {
sahilmgandhi 18:6a4db94011d3 2084 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 2085 {
sahilmgandhi 18:6a4db94011d3 2086 if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
sahilmgandhi 18:6a4db94011d3 2087 {
sahilmgandhi 18:6a4db94011d3 2088 /* Disable the SPI and reset the CRC: the CRC value should be cleared
sahilmgandhi 18:6a4db94011d3 2089 on both master and slave sides in order to resynchronize the master
sahilmgandhi 18:6a4db94011d3 2090 and slave for their respective CRC calculation */
sahilmgandhi 18:6a4db94011d3 2091
sahilmgandhi 18:6a4db94011d3 2092 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
sahilmgandhi 18:6a4db94011d3 2093 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 2094
sahilmgandhi 18:6a4db94011d3 2095 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
sahilmgandhi 18:6a4db94011d3 2096 {
sahilmgandhi 18:6a4db94011d3 2097 /* Disable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 2098 __HAL_SPI_DISABLE(hspi);
sahilmgandhi 18:6a4db94011d3 2099 }
sahilmgandhi 18:6a4db94011d3 2100
sahilmgandhi 18:6a4db94011d3 2101 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 2102 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 2103 {
sahilmgandhi 18:6a4db94011d3 2104 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 2105 }
sahilmgandhi 18:6a4db94011d3 2106
sahilmgandhi 18:6a4db94011d3 2107 hspi->State= HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2108
sahilmgandhi 18:6a4db94011d3 2109 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 2110 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 2111
sahilmgandhi 18:6a4db94011d3 2112 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 2113 }
sahilmgandhi 18:6a4db94011d3 2114 }
sahilmgandhi 18:6a4db94011d3 2115 }
sahilmgandhi 18:6a4db94011d3 2116
sahilmgandhi 18:6a4db94011d3 2117 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 2118 }
sahilmgandhi 18:6a4db94011d3 2119
sahilmgandhi 18:6a4db94011d3 2120 /**
sahilmgandhi 18:6a4db94011d3 2121 * @brief DMA SPI transmit process complete callback
sahilmgandhi 18:6a4db94011d3 2122 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2123 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 2124 * @retval None
sahilmgandhi 18:6a4db94011d3 2125 */
sahilmgandhi 18:6a4db94011d3 2126 static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2127 {
sahilmgandhi 18:6a4db94011d3 2128 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2129
sahilmgandhi 18:6a4db94011d3 2130 /* DMA Normal Mode */
sahilmgandhi 18:6a4db94011d3 2131 if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
sahilmgandhi 18:6a4db94011d3 2132 {
sahilmgandhi 18:6a4db94011d3 2133 /* Wait until TXE flag is set to send data */
sahilmgandhi 18:6a4db94011d3 2134 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 2135 {
sahilmgandhi 18:6a4db94011d3 2136 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2137 }
sahilmgandhi 18:6a4db94011d3 2138
sahilmgandhi 18:6a4db94011d3 2139 /* Disable Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 2140 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 2141
sahilmgandhi 18:6a4db94011d3 2142 /* Wait until Busy flag is reset before disabling SPI */
sahilmgandhi 18:6a4db94011d3 2143 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 2144 {
sahilmgandhi 18:6a4db94011d3 2145 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2146 }
sahilmgandhi 18:6a4db94011d3 2147
sahilmgandhi 18:6a4db94011d3 2148 hspi->TxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2149 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2150 }
sahilmgandhi 18:6a4db94011d3 2151
sahilmgandhi 18:6a4db94011d3 2152 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
sahilmgandhi 18:6a4db94011d3 2153 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi 18:6a4db94011d3 2154 {
sahilmgandhi 18:6a4db94011d3 2155 __HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 2156 }
sahilmgandhi 18:6a4db94011d3 2157
sahilmgandhi 18:6a4db94011d3 2158 /* Check if Errors has been detected during transfer */
sahilmgandhi 18:6a4db94011d3 2159 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 2160 {
sahilmgandhi 18:6a4db94011d3 2161 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2162 }
sahilmgandhi 18:6a4db94011d3 2163 else
sahilmgandhi 18:6a4db94011d3 2164 {
sahilmgandhi 18:6a4db94011d3 2165 HAL_SPI_TxCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2166 }
sahilmgandhi 18:6a4db94011d3 2167 }
sahilmgandhi 18:6a4db94011d3 2168
sahilmgandhi 18:6a4db94011d3 2169 /**
sahilmgandhi 18:6a4db94011d3 2170 * @brief DMA SPI receive process complete callback
sahilmgandhi 18:6a4db94011d3 2171 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2172 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 2173 * @retval None
sahilmgandhi 18:6a4db94011d3 2174 */
sahilmgandhi 18:6a4db94011d3 2175 static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2176 {
sahilmgandhi 18:6a4db94011d3 2177 __IO uint16_t tmpreg = 0;
sahilmgandhi 18:6a4db94011d3 2178
sahilmgandhi 18:6a4db94011d3 2179 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2180
sahilmgandhi 18:6a4db94011d3 2181 /* DMA Normal mode */
sahilmgandhi 18:6a4db94011d3 2182 if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
sahilmgandhi 18:6a4db94011d3 2183 {
sahilmgandhi 18:6a4db94011d3 2184 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
sahilmgandhi 18:6a4db94011d3 2185 {
sahilmgandhi 18:6a4db94011d3 2186 /* Disable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 2187 __HAL_SPI_DISABLE(hspi);
sahilmgandhi 18:6a4db94011d3 2188 }
sahilmgandhi 18:6a4db94011d3 2189
sahilmgandhi 18:6a4db94011d3 2190 /* Disable Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 2191 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 2192
sahilmgandhi 18:6a4db94011d3 2193 /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
sahilmgandhi 18:6a4db94011d3 2194 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 2195
sahilmgandhi 18:6a4db94011d3 2196 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 2197 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 2198 {
sahilmgandhi 18:6a4db94011d3 2199 /* Wait until RXNE flag is set to send data */
sahilmgandhi 18:6a4db94011d3 2200 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 2201 {
sahilmgandhi 18:6a4db94011d3 2202 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2203 }
sahilmgandhi 18:6a4db94011d3 2204
sahilmgandhi 18:6a4db94011d3 2205 /* Read CRC */
sahilmgandhi 18:6a4db94011d3 2206 tmpreg = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 2207 UNUSED(tmpreg);
sahilmgandhi 18:6a4db94011d3 2208
sahilmgandhi 18:6a4db94011d3 2209 /* Wait until RXNE flag is set */
sahilmgandhi 18:6a4db94011d3 2210 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 2211 {
sahilmgandhi 18:6a4db94011d3 2212 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2213 }
sahilmgandhi 18:6a4db94011d3 2214
sahilmgandhi 18:6a4db94011d3 2215 /* Check if CRC error occurred */
sahilmgandhi 18:6a4db94011d3 2216 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
sahilmgandhi 18:6a4db94011d3 2217 {
sahilmgandhi 18:6a4db94011d3 2218 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi 18:6a4db94011d3 2219 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 2220 }
sahilmgandhi 18:6a4db94011d3 2221 }
sahilmgandhi 18:6a4db94011d3 2222
sahilmgandhi 18:6a4db94011d3 2223 hspi->RxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2224 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2225
sahilmgandhi 18:6a4db94011d3 2226 /* Check if Errors has been detected during transfer */
sahilmgandhi 18:6a4db94011d3 2227 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 2228 {
sahilmgandhi 18:6a4db94011d3 2229 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2230 }
sahilmgandhi 18:6a4db94011d3 2231 else
sahilmgandhi 18:6a4db94011d3 2232 {
sahilmgandhi 18:6a4db94011d3 2233 HAL_SPI_RxCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2234 }
sahilmgandhi 18:6a4db94011d3 2235 }
sahilmgandhi 18:6a4db94011d3 2236 else
sahilmgandhi 18:6a4db94011d3 2237 {
sahilmgandhi 18:6a4db94011d3 2238 HAL_SPI_RxCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2239 }
sahilmgandhi 18:6a4db94011d3 2240 }
sahilmgandhi 18:6a4db94011d3 2241
sahilmgandhi 18:6a4db94011d3 2242 /**
sahilmgandhi 18:6a4db94011d3 2243 * @brief DMA SPI transmit receive process complete callback
sahilmgandhi 18:6a4db94011d3 2244 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2245 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 2246 * @retval None
sahilmgandhi 18:6a4db94011d3 2247 */
sahilmgandhi 18:6a4db94011d3 2248 static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2249 {
sahilmgandhi 18:6a4db94011d3 2250 __IO uint16_t tmpreg = 0;
sahilmgandhi 18:6a4db94011d3 2251
sahilmgandhi 18:6a4db94011d3 2252 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2253
sahilmgandhi 18:6a4db94011d3 2254 if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
sahilmgandhi 18:6a4db94011d3 2255 {
sahilmgandhi 18:6a4db94011d3 2256 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 2257 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 2258 {
sahilmgandhi 18:6a4db94011d3 2259 /* Check if CRC is done on going (RXNE flag set) */
sahilmgandhi 18:6a4db94011d3 2260 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
sahilmgandhi 18:6a4db94011d3 2261 {
sahilmgandhi 18:6a4db94011d3 2262 /* Wait until RXNE flag is set to send data */
sahilmgandhi 18:6a4db94011d3 2263 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 2264 {
sahilmgandhi 18:6a4db94011d3 2265 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2266 }
sahilmgandhi 18:6a4db94011d3 2267 }
sahilmgandhi 18:6a4db94011d3 2268 /* Read CRC */
sahilmgandhi 18:6a4db94011d3 2269 tmpreg = hspi->Instance->DR;
sahilmgandhi 18:6a4db94011d3 2270 UNUSED(tmpreg);
sahilmgandhi 18:6a4db94011d3 2271
sahilmgandhi 18:6a4db94011d3 2272 /* Check if CRC error occurred */
sahilmgandhi 18:6a4db94011d3 2273 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
sahilmgandhi 18:6a4db94011d3 2274 {
sahilmgandhi 18:6a4db94011d3 2275 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi 18:6a4db94011d3 2276 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 2277 }
sahilmgandhi 18:6a4db94011d3 2278 }
sahilmgandhi 18:6a4db94011d3 2279
sahilmgandhi 18:6a4db94011d3 2280 /* Wait until TXE flag is set to send data */
sahilmgandhi 18:6a4db94011d3 2281 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 2282 {
sahilmgandhi 18:6a4db94011d3 2283 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2284 }
sahilmgandhi 18:6a4db94011d3 2285
sahilmgandhi 18:6a4db94011d3 2286 /* Disable Tx DMA Request */
sahilmgandhi 18:6a4db94011d3 2287 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
sahilmgandhi 18:6a4db94011d3 2288
sahilmgandhi 18:6a4db94011d3 2289 /* Wait until Busy flag is reset before disabling SPI */
sahilmgandhi 18:6a4db94011d3 2290 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 2291 {
sahilmgandhi 18:6a4db94011d3 2292 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2293 }
sahilmgandhi 18:6a4db94011d3 2294
sahilmgandhi 18:6a4db94011d3 2295 /* Disable Rx DMA Request */
sahilmgandhi 18:6a4db94011d3 2296 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
sahilmgandhi 18:6a4db94011d3 2297
sahilmgandhi 18:6a4db94011d3 2298 hspi->TxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2299 hspi->RxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2300
sahilmgandhi 18:6a4db94011d3 2301 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2302
sahilmgandhi 18:6a4db94011d3 2303 /* Check if Errors has been detected during transfer */
sahilmgandhi 18:6a4db94011d3 2304 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 2305 {
sahilmgandhi 18:6a4db94011d3 2306 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2307 }
sahilmgandhi 18:6a4db94011d3 2308 else
sahilmgandhi 18:6a4db94011d3 2309 {
sahilmgandhi 18:6a4db94011d3 2310 HAL_SPI_TxRxCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2311 }
sahilmgandhi 18:6a4db94011d3 2312 }
sahilmgandhi 18:6a4db94011d3 2313 else
sahilmgandhi 18:6a4db94011d3 2314 {
sahilmgandhi 18:6a4db94011d3 2315 HAL_SPI_TxRxCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2316 }
sahilmgandhi 18:6a4db94011d3 2317 }
sahilmgandhi 18:6a4db94011d3 2318
sahilmgandhi 18:6a4db94011d3 2319 /**
sahilmgandhi 18:6a4db94011d3 2320 * @brief DMA SPI half transmit process complete callback
sahilmgandhi 18:6a4db94011d3 2321 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2322 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 2323 * @retval None
sahilmgandhi 18:6a4db94011d3 2324 */
sahilmgandhi 18:6a4db94011d3 2325 static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2326 {
sahilmgandhi 18:6a4db94011d3 2327 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2328
sahilmgandhi 18:6a4db94011d3 2329 HAL_SPI_TxHalfCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2330 }
sahilmgandhi 18:6a4db94011d3 2331
sahilmgandhi 18:6a4db94011d3 2332 /**
sahilmgandhi 18:6a4db94011d3 2333 * @brief DMA SPI half receive process complete callback
sahilmgandhi 18:6a4db94011d3 2334 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2335 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 2336 * @retval None
sahilmgandhi 18:6a4db94011d3 2337 */
sahilmgandhi 18:6a4db94011d3 2338 static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2339 {
sahilmgandhi 18:6a4db94011d3 2340 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2341
sahilmgandhi 18:6a4db94011d3 2342 HAL_SPI_RxHalfCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2343 }
sahilmgandhi 18:6a4db94011d3 2344
sahilmgandhi 18:6a4db94011d3 2345 /**
sahilmgandhi 18:6a4db94011d3 2346 * @brief DMA SPI Half transmit receive process complete callback
sahilmgandhi 18:6a4db94011d3 2347 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2348 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 2349 * @retval None
sahilmgandhi 18:6a4db94011d3 2350 */
sahilmgandhi 18:6a4db94011d3 2351 static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2352 {
sahilmgandhi 18:6a4db94011d3 2353 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2354
sahilmgandhi 18:6a4db94011d3 2355 HAL_SPI_TxRxHalfCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2356 }
sahilmgandhi 18:6a4db94011d3 2357
sahilmgandhi 18:6a4db94011d3 2358 /**
sahilmgandhi 18:6a4db94011d3 2359 * @brief DMA SPI communication error callback
sahilmgandhi 18:6a4db94011d3 2360 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2361 * the configuration information for the specified DMA module.
sahilmgandhi 18:6a4db94011d3 2362 * @retval None
sahilmgandhi 18:6a4db94011d3 2363 */
sahilmgandhi 18:6a4db94011d3 2364 static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma)
sahilmgandhi 18:6a4db94011d3 2365 {
sahilmgandhi 18:6a4db94011d3 2366 SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
sahilmgandhi 18:6a4db94011d3 2367 hspi->TxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2368 hspi->RxXferCount = 0;
sahilmgandhi 18:6a4db94011d3 2369 hspi->State= HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2370 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
sahilmgandhi 18:6a4db94011d3 2371 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2372 }
sahilmgandhi 18:6a4db94011d3 2373
sahilmgandhi 18:6a4db94011d3 2374 /**
sahilmgandhi 18:6a4db94011d3 2375 * @brief This function handles SPI Communication Timeout.
sahilmgandhi 18:6a4db94011d3 2376 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2377 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 2378 * @param Flag: SPI flag to check
sahilmgandhi 18:6a4db94011d3 2379 * @param Status: Flag status to check: RESET or set
sahilmgandhi 18:6a4db94011d3 2380 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 2381 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 2382 */
sahilmgandhi 18:6a4db94011d3 2383 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
sahilmgandhi 18:6a4db94011d3 2384 {
sahilmgandhi 18:6a4db94011d3 2385 uint32_t tickstart = 0;
sahilmgandhi 18:6a4db94011d3 2386
sahilmgandhi 18:6a4db94011d3 2387 /* Get tick */
sahilmgandhi 18:6a4db94011d3 2388 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 2389
sahilmgandhi 18:6a4db94011d3 2390 /* Wait until flag is set */
sahilmgandhi 18:6a4db94011d3 2391 if(Status == RESET)
sahilmgandhi 18:6a4db94011d3 2392 {
sahilmgandhi 18:6a4db94011d3 2393 while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
sahilmgandhi 18:6a4db94011d3 2394 {
sahilmgandhi 18:6a4db94011d3 2395 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 2396 {
sahilmgandhi 18:6a4db94011d3 2397 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 2398 {
sahilmgandhi 18:6a4db94011d3 2399 /* Disable the SPI and reset the CRC: the CRC value should be cleared
sahilmgandhi 18:6a4db94011d3 2400 on both master and slave sides in order to resynchronize the master
sahilmgandhi 18:6a4db94011d3 2401 and slave for their respective CRC calculation */
sahilmgandhi 18:6a4db94011d3 2402
sahilmgandhi 18:6a4db94011d3 2403 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
sahilmgandhi 18:6a4db94011d3 2404 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 2405
sahilmgandhi 18:6a4db94011d3 2406 /* Disable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 2407 __HAL_SPI_DISABLE(hspi);
sahilmgandhi 18:6a4db94011d3 2408
sahilmgandhi 18:6a4db94011d3 2409 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 2410 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 2411 {
sahilmgandhi 18:6a4db94011d3 2412 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 2413 }
sahilmgandhi 18:6a4db94011d3 2414
sahilmgandhi 18:6a4db94011d3 2415 hspi->State= HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2416
sahilmgandhi 18:6a4db94011d3 2417 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 2418 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 2419
sahilmgandhi 18:6a4db94011d3 2420 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 2421 }
sahilmgandhi 18:6a4db94011d3 2422 }
sahilmgandhi 18:6a4db94011d3 2423 }
sahilmgandhi 18:6a4db94011d3 2424 }
sahilmgandhi 18:6a4db94011d3 2425 else
sahilmgandhi 18:6a4db94011d3 2426 {
sahilmgandhi 18:6a4db94011d3 2427 while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
sahilmgandhi 18:6a4db94011d3 2428 {
sahilmgandhi 18:6a4db94011d3 2429 if(Timeout != HAL_MAX_DELAY)
sahilmgandhi 18:6a4db94011d3 2430 {
sahilmgandhi 18:6a4db94011d3 2431 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
sahilmgandhi 18:6a4db94011d3 2432 {
sahilmgandhi 18:6a4db94011d3 2433 /* Disable the SPI and reset the CRC: the CRC value should be cleared
sahilmgandhi 18:6a4db94011d3 2434 on both master and slave sides in order to resynchronize the master
sahilmgandhi 18:6a4db94011d3 2435 and slave for their respective CRC calculation */
sahilmgandhi 18:6a4db94011d3 2436
sahilmgandhi 18:6a4db94011d3 2437 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
sahilmgandhi 18:6a4db94011d3 2438 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 2439
sahilmgandhi 18:6a4db94011d3 2440 /* Disable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 2441 __HAL_SPI_DISABLE(hspi);
sahilmgandhi 18:6a4db94011d3 2442
sahilmgandhi 18:6a4db94011d3 2443 /* Reset CRC Calculation */
sahilmgandhi 18:6a4db94011d3 2444 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
sahilmgandhi 18:6a4db94011d3 2445 {
sahilmgandhi 18:6a4db94011d3 2446 SPI_RESET_CRC(hspi);
sahilmgandhi 18:6a4db94011d3 2447 }
sahilmgandhi 18:6a4db94011d3 2448
sahilmgandhi 18:6a4db94011d3 2449 hspi->State= HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2450
sahilmgandhi 18:6a4db94011d3 2451 /* Process Unlocked */
sahilmgandhi 18:6a4db94011d3 2452 __HAL_UNLOCK(hspi);
sahilmgandhi 18:6a4db94011d3 2453
sahilmgandhi 18:6a4db94011d3 2454 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 2455 }
sahilmgandhi 18:6a4db94011d3 2456 }
sahilmgandhi 18:6a4db94011d3 2457 }
sahilmgandhi 18:6a4db94011d3 2458 }
sahilmgandhi 18:6a4db94011d3 2459 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 2460 }
sahilmgandhi 18:6a4db94011d3 2461 /**
sahilmgandhi 18:6a4db94011d3 2462 * @}
sahilmgandhi 18:6a4db94011d3 2463 */
sahilmgandhi 18:6a4db94011d3 2464
sahilmgandhi 18:6a4db94011d3 2465 /**
sahilmgandhi 18:6a4db94011d3 2466 * @brief Handle to check BSY flag before start a new transaction.
sahilmgandhi 18:6a4db94011d3 2467 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2468 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 2469 * @param Timeout: Timeout duration
sahilmgandhi 18:6a4db94011d3 2470 * @param Tickstart: tick start value
sahilmgandhi 18:6a4db94011d3 2471 * @retval HAL status
sahilmgandhi 18:6a4db94011d3 2472 */
sahilmgandhi 18:6a4db94011d3 2473 static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
sahilmgandhi 18:6a4db94011d3 2474 {
sahilmgandhi 18:6a4db94011d3 2475 /* Control the BSY flag */
sahilmgandhi 18:6a4db94011d3 2476 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 2477 {
sahilmgandhi 18:6a4db94011d3 2478 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2479 return HAL_TIMEOUT;
sahilmgandhi 18:6a4db94011d3 2480 }
sahilmgandhi 18:6a4db94011d3 2481 return HAL_OK;
sahilmgandhi 18:6a4db94011d3 2482 }
sahilmgandhi 18:6a4db94011d3 2483
sahilmgandhi 18:6a4db94011d3 2484 /**
sahilmgandhi 18:6a4db94011d3 2485 * @brief Handle the end of the RXTX transaction.
sahilmgandhi 18:6a4db94011d3 2486 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2487 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 2488 * @retval None
sahilmgandhi 18:6a4db94011d3 2489 */
sahilmgandhi 18:6a4db94011d3 2490 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 2491 {
sahilmgandhi 18:6a4db94011d3 2492 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 2493 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
sahilmgandhi 18:6a4db94011d3 2494 /* Init tickstart for timeout managment*/
sahilmgandhi 18:6a4db94011d3 2495 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 2496
sahilmgandhi 18:6a4db94011d3 2497 /* Disable ERR interrupt */
sahilmgandhi 18:6a4db94011d3 2498 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
sahilmgandhi 18:6a4db94011d3 2499
sahilmgandhi 18:6a4db94011d3 2500 /* Wait until TXE flag is set */
sahilmgandhi 18:6a4db94011d3 2501 do
sahilmgandhi 18:6a4db94011d3 2502 {
sahilmgandhi 18:6a4db94011d3 2503 if(count-- == 0)
sahilmgandhi 18:6a4db94011d3 2504 {
sahilmgandhi 18:6a4db94011d3 2505 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2506 break;
sahilmgandhi 18:6a4db94011d3 2507 }
sahilmgandhi 18:6a4db94011d3 2508 }
sahilmgandhi 18:6a4db94011d3 2509 while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
sahilmgandhi 18:6a4db94011d3 2510
sahilmgandhi 18:6a4db94011d3 2511 /* Check the end of the transaction */
sahilmgandhi 18:6a4db94011d3 2512 if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
sahilmgandhi 18:6a4db94011d3 2513 {
sahilmgandhi 18:6a4db94011d3 2514 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2515 }
sahilmgandhi 18:6a4db94011d3 2516
sahilmgandhi 18:6a4db94011d3 2517 /* Clear overrun flag in 2 Lines communication mode because received is not read */
sahilmgandhi 18:6a4db94011d3 2518 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi 18:6a4db94011d3 2519 {
sahilmgandhi 18:6a4db94011d3 2520 __HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 2521 }
sahilmgandhi 18:6a4db94011d3 2522
sahilmgandhi 18:6a4db94011d3 2523 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 2524 /* Check if CRC error occurred */
sahilmgandhi 18:6a4db94011d3 2525 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
sahilmgandhi 18:6a4db94011d3 2526 {
sahilmgandhi 18:6a4db94011d3 2527 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2528 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi 18:6a4db94011d3 2529 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 2530 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2531 }
sahilmgandhi 18:6a4db94011d3 2532 else
sahilmgandhi 18:6a4db94011d3 2533 {
sahilmgandhi 18:6a4db94011d3 2534 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 2535 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 2536 {
sahilmgandhi 18:6a4db94011d3 2537 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
sahilmgandhi 18:6a4db94011d3 2538 {
sahilmgandhi 18:6a4db94011d3 2539 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2540 HAL_SPI_RxCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2541 }
sahilmgandhi 18:6a4db94011d3 2542 else
sahilmgandhi 18:6a4db94011d3 2543 {
sahilmgandhi 18:6a4db94011d3 2544 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2545 HAL_SPI_TxRxCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2546 }
sahilmgandhi 18:6a4db94011d3 2547 }
sahilmgandhi 18:6a4db94011d3 2548 else
sahilmgandhi 18:6a4db94011d3 2549 {
sahilmgandhi 18:6a4db94011d3 2550 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2551 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2552 }
sahilmgandhi 18:6a4db94011d3 2553 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 2554 }
sahilmgandhi 18:6a4db94011d3 2555 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 2556 }
sahilmgandhi 18:6a4db94011d3 2557
sahilmgandhi 18:6a4db94011d3 2558 /**
sahilmgandhi 18:6a4db94011d3 2559 * @brief Handle the end of the RX transaction.
sahilmgandhi 18:6a4db94011d3 2560 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2561 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 2562 * @retval None
sahilmgandhi 18:6a4db94011d3 2563 */
sahilmgandhi 18:6a4db94011d3 2564 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 2565 {
sahilmgandhi 18:6a4db94011d3 2566 /* Disable RXNE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 2567 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 2568
sahilmgandhi 18:6a4db94011d3 2569 /* Check the end of the transaction */
sahilmgandhi 18:6a4db94011d3 2570 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
sahilmgandhi 18:6a4db94011d3 2571 {
sahilmgandhi 18:6a4db94011d3 2572 /* Disable SPI peripheral */
sahilmgandhi 18:6a4db94011d3 2573 __HAL_SPI_DISABLE(hspi);
sahilmgandhi 18:6a4db94011d3 2574 }
sahilmgandhi 18:6a4db94011d3 2575
sahilmgandhi 18:6a4db94011d3 2576 /* Clear overrun flag in 2 Lines communication mode because received is not read */
sahilmgandhi 18:6a4db94011d3 2577 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi 18:6a4db94011d3 2578 {
sahilmgandhi 18:6a4db94011d3 2579 __HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 2580 }
sahilmgandhi 18:6a4db94011d3 2581 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2582
sahilmgandhi 18:6a4db94011d3 2583 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 2584 /* Check if CRC error occurred */
sahilmgandhi 18:6a4db94011d3 2585 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
sahilmgandhi 18:6a4db94011d3 2586 {
sahilmgandhi 18:6a4db94011d3 2587 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
sahilmgandhi 18:6a4db94011d3 2588 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 2589 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2590 }
sahilmgandhi 18:6a4db94011d3 2591 else
sahilmgandhi 18:6a4db94011d3 2592 {
sahilmgandhi 18:6a4db94011d3 2593 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 2594 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 2595 {
sahilmgandhi 18:6a4db94011d3 2596 HAL_SPI_RxCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2597 }
sahilmgandhi 18:6a4db94011d3 2598 else
sahilmgandhi 18:6a4db94011d3 2599 {
sahilmgandhi 18:6a4db94011d3 2600 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2601 }
sahilmgandhi 18:6a4db94011d3 2602 #if (USE_SPI_CRC != 0U)
sahilmgandhi 18:6a4db94011d3 2603 }
sahilmgandhi 18:6a4db94011d3 2604 #endif /* USE_SPI_CRC */
sahilmgandhi 18:6a4db94011d3 2605 }
sahilmgandhi 18:6a4db94011d3 2606
sahilmgandhi 18:6a4db94011d3 2607 /**
sahilmgandhi 18:6a4db94011d3 2608 * @brief Handle the end of the TX transaction.
sahilmgandhi 18:6a4db94011d3 2609 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
sahilmgandhi 18:6a4db94011d3 2610 * the configuration information for SPI module.
sahilmgandhi 18:6a4db94011d3 2611 * @retval None
sahilmgandhi 18:6a4db94011d3 2612 */
sahilmgandhi 18:6a4db94011d3 2613 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
sahilmgandhi 18:6a4db94011d3 2614 {
sahilmgandhi 18:6a4db94011d3 2615 uint32_t tickstart = 0U;
sahilmgandhi 18:6a4db94011d3 2616 __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000);
sahilmgandhi 18:6a4db94011d3 2617
sahilmgandhi 18:6a4db94011d3 2618 /* Init tickstart for timeout management*/
sahilmgandhi 18:6a4db94011d3 2619 tickstart = HAL_GetTick();
sahilmgandhi 18:6a4db94011d3 2620
sahilmgandhi 18:6a4db94011d3 2621 /* Wait until TXE flag is set */
sahilmgandhi 18:6a4db94011d3 2622 do
sahilmgandhi 18:6a4db94011d3 2623 {
sahilmgandhi 18:6a4db94011d3 2624 if(count-- == 0)
sahilmgandhi 18:6a4db94011d3 2625 {
sahilmgandhi 18:6a4db94011d3 2626 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2627 break;
sahilmgandhi 18:6a4db94011d3 2628 }
sahilmgandhi 18:6a4db94011d3 2629 }
sahilmgandhi 18:6a4db94011d3 2630 while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
sahilmgandhi 18:6a4db94011d3 2631
sahilmgandhi 18:6a4db94011d3 2632 /* Disable TXE and ERR interrupt */
sahilmgandhi 18:6a4db94011d3 2633 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
sahilmgandhi 18:6a4db94011d3 2634
sahilmgandhi 18:6a4db94011d3 2635 /* Check Busy flag */
sahilmgandhi 18:6a4db94011d3 2636 if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
sahilmgandhi 18:6a4db94011d3 2637 {
sahilmgandhi 18:6a4db94011d3 2638 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
sahilmgandhi 18:6a4db94011d3 2639 }
sahilmgandhi 18:6a4db94011d3 2640
sahilmgandhi 18:6a4db94011d3 2641 /* Clear overrun flag in 2 Lines communication mode because received is not read */
sahilmgandhi 18:6a4db94011d3 2642 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
sahilmgandhi 18:6a4db94011d3 2643 {
sahilmgandhi 18:6a4db94011d3 2644 __HAL_SPI_CLEAR_OVRFLAG(hspi);
sahilmgandhi 18:6a4db94011d3 2645 }
sahilmgandhi 18:6a4db94011d3 2646
sahilmgandhi 18:6a4db94011d3 2647 hspi->State = HAL_SPI_STATE_READY;
sahilmgandhi 18:6a4db94011d3 2648 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
sahilmgandhi 18:6a4db94011d3 2649 {
sahilmgandhi 18:6a4db94011d3 2650 HAL_SPI_ErrorCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2651 }
sahilmgandhi 18:6a4db94011d3 2652 else
sahilmgandhi 18:6a4db94011d3 2653 {
sahilmgandhi 18:6a4db94011d3 2654 HAL_SPI_TxCpltCallback(hspi);
sahilmgandhi 18:6a4db94011d3 2655 }
sahilmgandhi 18:6a4db94011d3 2656 }
sahilmgandhi 18:6a4db94011d3 2657
sahilmgandhi 18:6a4db94011d3 2658 /**
sahilmgandhi 18:6a4db94011d3 2659 * @}
sahilmgandhi 18:6a4db94011d3 2660 */
sahilmgandhi 18:6a4db94011d3 2661
sahilmgandhi 18:6a4db94011d3 2662
sahilmgandhi 18:6a4db94011d3 2663 #endif /* HAL_SPI_MODULE_ENABLED */
sahilmgandhi 18:6a4db94011d3 2664 /**
sahilmgandhi 18:6a4db94011d3 2665 * @}
sahilmgandhi 18:6a4db94011d3 2666 */
sahilmgandhi 18:6a4db94011d3 2667
sahilmgandhi 18:6a4db94011d3 2668 /**
sahilmgandhi 18:6a4db94011d3 2669 * @}
sahilmgandhi 18:6a4db94011d3 2670 */
sahilmgandhi 18:6a4db94011d3 2671
sahilmgandhi 18:6a4db94011d3 2672 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/