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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32620/spi_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
sahilmgandhi 18:6a4db94011d3 5 * copy of this software and associated documentation files (the "Software"),
sahilmgandhi 18:6a4db94011d3 6 * to deal in the Software without restriction, including without limitation
sahilmgandhi 18:6a4db94011d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
sahilmgandhi 18:6a4db94011d3 8 * and/or sell copies of the Software, and to permit persons to whom the
sahilmgandhi 18:6a4db94011d3 9 * Software is furnished to do so, subject to the following conditions:
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * The above copyright notice and this permission notice shall be included
sahilmgandhi 18:6a4db94011d3 12 * in all copies or substantial portions of the Software.
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
sahilmgandhi 18:6a4db94011d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
sahilmgandhi 18:6a4db94011d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
sahilmgandhi 18:6a4db94011d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
sahilmgandhi 18:6a4db94011d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
sahilmgandhi 18:6a4db94011d3 20 * OTHER DEALINGS IN THE SOFTWARE.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * Except as contained in this notice, the name of Maxim Integrated
sahilmgandhi 18:6a4db94011d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
sahilmgandhi 18:6a4db94011d3 24 * Products, Inc. Branding Policy.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * The mere transfer of this software does not imply any licenses
sahilmgandhi 18:6a4db94011d3 27 * of trade secrets, proprietary technology, copyrights, patents,
sahilmgandhi 18:6a4db94011d3 28 * trademarks, maskwork rights, or any other form of intellectual
sahilmgandhi 18:6a4db94011d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
sahilmgandhi 18:6a4db94011d3 30 * ownership rights.
sahilmgandhi 18:6a4db94011d3 31 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #include <string.h>
sahilmgandhi 18:6a4db94011d3 35 #include "mbed_assert.h"
sahilmgandhi 18:6a4db94011d3 36 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 37 #include "spi_api.h"
sahilmgandhi 18:6a4db94011d3 38 #include "spi_multi_api.h"
sahilmgandhi 18:6a4db94011d3 39 #include "pinmap.h"
sahilmgandhi 18:6a4db94011d3 40 #include "ioman_regs.h"
sahilmgandhi 18:6a4db94011d3 41 #include "clkman_regs.h"
sahilmgandhi 18:6a4db94011d3 42 #include "PeripheralPins.h"
sahilmgandhi 18:6a4db94011d3 43
sahilmgandhi 18:6a4db94011d3 44 #define DEFAULT_CHAR 8
sahilmgandhi 18:6a4db94011d3 45 #define DEFAULT_MODE 0
sahilmgandhi 18:6a4db94011d3 46 #define DEFAULT_FREQ 1000000
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 // BYTE maximums for FIFO and page writes; FIFO depth spec'd as 16-bit words
sahilmgandhi 18:6a4db94011d3 49 #define SPI_MAX_BYTE_LEN (MXC_CFG_SPI_FIFO_DEPTH * 2)
sahilmgandhi 18:6a4db94011d3 50 #define SPI_MAX_PAGE_LEN (MXC_CFG_SPI_FIFO_DEPTH * 2)
sahilmgandhi 18:6a4db94011d3 51
sahilmgandhi 18:6a4db94011d3 52 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 53 // Instance references for async transactions
sahilmgandhi 18:6a4db94011d3 54 static struct spi_s *state[MXC_CFG_SPI_INSTANCES] = {NULL};
sahilmgandhi 18:6a4db94011d3 55 #endif
sahilmgandhi 18:6a4db94011d3 56
sahilmgandhi 18:6a4db94011d3 57 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 58 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
sahilmgandhi 18:6a4db94011d3 59 {
sahilmgandhi 18:6a4db94011d3 60 // Make sure pins are pointing to the same SPI instance
sahilmgandhi 18:6a4db94011d3 61 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 62 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 63 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 64 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 65
sahilmgandhi 18:6a4db94011d3 66 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
sahilmgandhi 18:6a4db94011d3 67 SPIName spi_cntl;
sahilmgandhi 18:6a4db94011d3 68
sahilmgandhi 18:6a4db94011d3 69 // Give the application the option to manually control Slave Select
sahilmgandhi 18:6a4db94011d3 70 if ((SPIName)spi_ssel != (SPIName)NC) {
sahilmgandhi 18:6a4db94011d3 71 spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
sahilmgandhi 18:6a4db94011d3 72 // Slave select is currently limited to slave select zero. If others are
sahilmgandhi 18:6a4db94011d3 73 // to be supported a function to map PinName to a value suitable for use
sahilmgandhi 18:6a4db94011d3 74 // in mstr_cfg.slave_sel will be required.
sahilmgandhi 18:6a4db94011d3 75 obj->spi.ssel = 0;
sahilmgandhi 18:6a4db94011d3 76 } else {
sahilmgandhi 18:6a4db94011d3 77 spi_cntl = spi_sclk;
sahilmgandhi 18:6a4db94011d3 78 obj->spi.ssel = -1;
sahilmgandhi 18:6a4db94011d3 79 }
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 MBED_ASSERT((SPIName)spi != (SPIName)NC);
sahilmgandhi 18:6a4db94011d3 84
sahilmgandhi 18:6a4db94011d3 85 // Set the obj pointer to the proper SPI Instance
sahilmgandhi 18:6a4db94011d3 86 obj->spi.spi = (mxc_spi_regs_t*)spi;
sahilmgandhi 18:6a4db94011d3 87
sahilmgandhi 18:6a4db94011d3 88 // Set the SPI index and FIFOs
sahilmgandhi 18:6a4db94011d3 89 obj->spi.index = MXC_SPI_GET_IDX(obj->spi.spi);
sahilmgandhi 18:6a4db94011d3 90 obj->spi.fifo = MXC_SPI_GET_SPI_FIFO(obj->spi.index);
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 // Configure the pins
sahilmgandhi 18:6a4db94011d3 93 pinmap_pinout(mosi, PinMap_SPI_MOSI);
sahilmgandhi 18:6a4db94011d3 94 pinmap_pinout(miso, PinMap_SPI_MISO);
sahilmgandhi 18:6a4db94011d3 95 pinmap_pinout(sclk, PinMap_SPI_SCLK);
sahilmgandhi 18:6a4db94011d3 96 pinmap_pinout(ssel, PinMap_SPI_SSEL);
sahilmgandhi 18:6a4db94011d3 97
sahilmgandhi 18:6a4db94011d3 98 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 99 // Configure default page size; size is known to async interface
sahilmgandhi 18:6a4db94011d3 100 obj->spi.spi->mstr_cfg = (obj->spi.spi->mstr_cfg & ~MXC_F_SPI_MSTR_CFG_PAGE_SIZE) | MXC_S_SPI_MSTR_CFG_PAGE_32B;
sahilmgandhi 18:6a4db94011d3 101 #endif
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 // Enable SPI and FIFOs
sahilmgandhi 18:6a4db94011d3 104 obj->spi.spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN |
sahilmgandhi 18:6a4db94011d3 105 MXC_F_SPI_GEN_CTRL_TX_FIFO_EN |
sahilmgandhi 18:6a4db94011d3 106 MXC_F_SPI_GEN_CTRL_RX_FIFO_EN );
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 obj->spi.sclk = sclk; // save the sclk PinName in the object as a key for Quad SPI pin mapping lookup
sahilmgandhi 18:6a4db94011d3 109 spi_master_width(obj, 0); // default this for Single SPI communications
sahilmgandhi 18:6a4db94011d3 110 }
sahilmgandhi 18:6a4db94011d3 111
sahilmgandhi 18:6a4db94011d3 112 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 113 void spi_format(spi_t *obj, int bits, int mode, int slave)
sahilmgandhi 18:6a4db94011d3 114 {
sahilmgandhi 18:6a4db94011d3 115 // Check the validity of the inputs
sahilmgandhi 18:6a4db94011d3 116 MBED_ASSERT(((bits >= 1) && (bits <= 32)) && ((mode >= 0) && (mode <= 3)));
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 // Only supports master mode
sahilmgandhi 18:6a4db94011d3 119 MBED_ASSERT(!slave);
sahilmgandhi 18:6a4db94011d3 120
sahilmgandhi 18:6a4db94011d3 121 // Save formatting data
sahilmgandhi 18:6a4db94011d3 122 obj->spi.bits = bits;
sahilmgandhi 18:6a4db94011d3 123
sahilmgandhi 18:6a4db94011d3 124 // Set the mode
sahilmgandhi 18:6a4db94011d3 125 MXC_SET_FIELD(&obj->spi.spi->mstr_cfg, MXC_F_SPI_MSTR_CFG_SPI_MODE, mode << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS);
sahilmgandhi 18:6a4db94011d3 126 }
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 129 void spi_frequency(spi_t *obj, int hz)
sahilmgandhi 18:6a4db94011d3 130 {
sahilmgandhi 18:6a4db94011d3 131 // Maximum frequency is half the system frequency
sahilmgandhi 18:6a4db94011d3 132 MBED_ASSERT((unsigned int)hz <= (SystemCoreClock / 2));
sahilmgandhi 18:6a4db94011d3 133 unsigned clocks = ((SystemCoreClock / 2) / hz);
sahilmgandhi 18:6a4db94011d3 134
sahilmgandhi 18:6a4db94011d3 135 // Figure out the divider ratio
sahilmgandhi 18:6a4db94011d3 136 int clk_div = 1;
sahilmgandhi 18:6a4db94011d3 137 while (clk_div < 10) {
sahilmgandhi 18:6a4db94011d3 138 if (clocks < 0x10) {
sahilmgandhi 18:6a4db94011d3 139 break;
sahilmgandhi 18:6a4db94011d3 140 }
sahilmgandhi 18:6a4db94011d3 141 clk_div++;
sahilmgandhi 18:6a4db94011d3 142 clocks = clocks >> 1;
sahilmgandhi 18:6a4db94011d3 143 }
sahilmgandhi 18:6a4db94011d3 144
sahilmgandhi 18:6a4db94011d3 145 // Turn on the SPI clock
sahilmgandhi 18:6a4db94011d3 146 if (obj->spi.index == 0) {
sahilmgandhi 18:6a4db94011d3 147 MXC_CLKMAN->sys_clk_ctrl_11_spi0 = clk_div;
sahilmgandhi 18:6a4db94011d3 148 } else if (obj->spi.index == 1) {
sahilmgandhi 18:6a4db94011d3 149 MXC_CLKMAN->sys_clk_ctrl_12_spi1 = clk_div;
sahilmgandhi 18:6a4db94011d3 150 } else if (obj->spi.index == 2) {
sahilmgandhi 18:6a4db94011d3 151 MXC_CLKMAN->sys_clk_ctrl_13_spi2 = clk_div;
sahilmgandhi 18:6a4db94011d3 152 } else {
sahilmgandhi 18:6a4db94011d3 153 MBED_ASSERT(0);
sahilmgandhi 18:6a4db94011d3 154 }
sahilmgandhi 18:6a4db94011d3 155
sahilmgandhi 18:6a4db94011d3 156 // Set the number of clocks to hold sclk high and low
sahilmgandhi 18:6a4db94011d3 157 MXC_SET_FIELD(&obj->spi.spi->mstr_cfg, (MXC_F_SPI_MSTR_CFG_SCK_HI_CLK | MXC_F_SPI_MSTR_CFG_SCK_LO_CLK),
sahilmgandhi 18:6a4db94011d3 158 ((clocks << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS)));
sahilmgandhi 18:6a4db94011d3 159 }
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 162 void spi_master_width(spi_t *obj, SpiWidth width)
sahilmgandhi 18:6a4db94011d3 163 {
sahilmgandhi 18:6a4db94011d3 164 // Save the width to be used in the SPI header
sahilmgandhi 18:6a4db94011d3 165 switch (width) {
sahilmgandhi 18:6a4db94011d3 166 case WidthSingle:
sahilmgandhi 18:6a4db94011d3 167 obj->spi.width = MXC_S_SPI_FIFO_WIDTH_SINGLE;
sahilmgandhi 18:6a4db94011d3 168 break;
sahilmgandhi 18:6a4db94011d3 169 case WidthDual:
sahilmgandhi 18:6a4db94011d3 170 obj->spi.width = MXC_S_SPI_FIFO_WIDTH_DUAL;
sahilmgandhi 18:6a4db94011d3 171 break;
sahilmgandhi 18:6a4db94011d3 172 case WidthQuad:
sahilmgandhi 18:6a4db94011d3 173 obj->spi.width = MXC_S_SPI_FIFO_WIDTH_QUAD;
sahilmgandhi 18:6a4db94011d3 174 // do pin mapping for SDIO[2] and SDIO[3] if Quad SPI is selected
sahilmgandhi 18:6a4db94011d3 175 pinmap_pinout(obj->spi.sclk, PinMap_SPI_QUAD);
sahilmgandhi 18:6a4db94011d3 176 break;
sahilmgandhi 18:6a4db94011d3 177 default:
sahilmgandhi 18:6a4db94011d3 178 MBED_ASSERT(0);
sahilmgandhi 18:6a4db94011d3 179 }
sahilmgandhi 18:6a4db94011d3 180 }
sahilmgandhi 18:6a4db94011d3 181
sahilmgandhi 18:6a4db94011d3 182 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 183 /** Performs a master write or read transaction
sahilmgandhi 18:6a4db94011d3 184 *
sahilmgandhi 18:6a4db94011d3 185 * @param[in] obj The SPI peripheral to use for sending
sahilmgandhi 18:6a4db94011d3 186 * @param[in] value The value to send
sahilmgandhi 18:6a4db94011d3 187 * @param[in] direction Direction of the transaction, TX, RX or both
sahilmgandhi 18:6a4db94011d3 188 * @return Returns the value received during send
sahilmgandhi 18:6a4db94011d3 189 */
sahilmgandhi 18:6a4db94011d3 190 static int spi_master_transaction(spi_t *obj, int value, uint32_t direction)
sahilmgandhi 18:6a4db94011d3 191 {
sahilmgandhi 18:6a4db94011d3 192 int bits;
sahilmgandhi 18:6a4db94011d3 193
sahilmgandhi 18:6a4db94011d3 194 // Create the header
sahilmgandhi 18:6a4db94011d3 195 uint16_t header = (direction | // direction based on SPI object
sahilmgandhi 18:6a4db94011d3 196 MXC_S_SPI_FIFO_UNIT_BITS | // unit size
sahilmgandhi 18:6a4db94011d3 197 ((obj->spi.bits == 32) ? 0 : obj->spi.bits << MXC_F_SPI_FIFO_SIZE_POS) | // Number of units
sahilmgandhi 18:6a4db94011d3 198 obj->spi.width | // I/O width
sahilmgandhi 18:6a4db94011d3 199 ((obj->spi.ssel == -1) ? 0 : 1 << MXC_F_SPI_FIFO_DASS_POS));
sahilmgandhi 18:6a4db94011d3 200
sahilmgandhi 18:6a4db94011d3 201 // Send the message header
sahilmgandhi 18:6a4db94011d3 202 *obj->spi.fifo->trans_16 = header;
sahilmgandhi 18:6a4db94011d3 203
sahilmgandhi 18:6a4db94011d3 204 // Send the data
sahilmgandhi 18:6a4db94011d3 205 if (obj->spi.bits < 17) {
sahilmgandhi 18:6a4db94011d3 206 *obj->spi.fifo->trans_16 = (uint16_t)value;
sahilmgandhi 18:6a4db94011d3 207 } else {
sahilmgandhi 18:6a4db94011d3 208 *obj->spi.fifo->trans_32 = (uint32_t)value;
sahilmgandhi 18:6a4db94011d3 209 }
sahilmgandhi 18:6a4db94011d3 210
sahilmgandhi 18:6a4db94011d3 211 // Get the data
sahilmgandhi 18:6a4db94011d3 212 bits = obj->spi.bits;
sahilmgandhi 18:6a4db94011d3 213 int result = 0;
sahilmgandhi 18:6a4db94011d3 214 int i = 0;
sahilmgandhi 18:6a4db94011d3 215 while (bits > 0) {
sahilmgandhi 18:6a4db94011d3 216 // Wait for data
sahilmgandhi 18:6a4db94011d3 217 while (((obj->spi.spi->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED)
sahilmgandhi 18:6a4db94011d3 218 >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS) < 1);
sahilmgandhi 18:6a4db94011d3 219
sahilmgandhi 18:6a4db94011d3 220 result |= (*obj->spi.fifo->rslts_8 << (i++*8));
sahilmgandhi 18:6a4db94011d3 221 bits-=8;
sahilmgandhi 18:6a4db94011d3 222 }
sahilmgandhi 18:6a4db94011d3 223
sahilmgandhi 18:6a4db94011d3 224 return result;
sahilmgandhi 18:6a4db94011d3 225 }
sahilmgandhi 18:6a4db94011d3 226
sahilmgandhi 18:6a4db94011d3 227 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 228 int spi_master_write(spi_t *obj, int value)
sahilmgandhi 18:6a4db94011d3 229 {
sahilmgandhi 18:6a4db94011d3 230 // set the fifo direction for full duplex, TX and RX simultaneously
sahilmgandhi 18:6a4db94011d3 231 return spi_master_transaction(obj, value, MXC_S_SPI_FIFO_DIR_BOTH);
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 235 int spi_master_read(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 236 {
sahilmgandhi 18:6a4db94011d3 237 return spi_master_transaction(obj, 0xFF, MXC_S_SPI_FIFO_DIR_RX);
sahilmgandhi 18:6a4db94011d3 238 }
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 241 // spi_busy() is part of the synchronous API, it is not used by the asynchronous API.
sahilmgandhi 18:6a4db94011d3 242 int spi_busy(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 243 {
sahilmgandhi 18:6a4db94011d3 244 return !(obj->spi.spi->intfl & MXC_F_SPI_INTFL_TX_READY);
sahilmgandhi 18:6a4db94011d3 245 }
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 #if DEVICE_SPI_ASYNCH
sahilmgandhi 18:6a4db94011d3 248 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 249 static uint32_t spi_master_read_rxfifo(mxc_spi_regs_t *spim, mxc_spi_fifo_regs_t *fifo, uint8_t *data, uint32_t len)
sahilmgandhi 18:6a4db94011d3 250 {
sahilmgandhi 18:6a4db94011d3 251 uint32_t num = 0;
sahilmgandhi 18:6a4db94011d3 252 uint32_t avail = ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS);
sahilmgandhi 18:6a4db94011d3 253
sahilmgandhi 18:6a4db94011d3 254 // Get data from the RXFIFO
sahilmgandhi 18:6a4db94011d3 255 while (avail && (len - num)) {
sahilmgandhi 18:6a4db94011d3 256 // Save data from the RXFIFO
sahilmgandhi 18:6a4db94011d3 257 if ((avail >= 4) && ((len - num) >= 4)) {
sahilmgandhi 18:6a4db94011d3 258 uint32_t temp = *fifo->rslts_32;
sahilmgandhi 18:6a4db94011d3 259 data[num++] = temp;
sahilmgandhi 18:6a4db94011d3 260 data[num++] = temp >> 8;
sahilmgandhi 18:6a4db94011d3 261 data[num++] = temp >> 16;
sahilmgandhi 18:6a4db94011d3 262 data[num++] = temp >> 24;
sahilmgandhi 18:6a4db94011d3 263 avail -= 4;
sahilmgandhi 18:6a4db94011d3 264 } else if ((avail >= 2) && ((len - num) >= 2)) {
sahilmgandhi 18:6a4db94011d3 265 uint16_t temp = *fifo->rslts_16;
sahilmgandhi 18:6a4db94011d3 266 data[num++] = temp;
sahilmgandhi 18:6a4db94011d3 267 data[num++] = temp >> 8;
sahilmgandhi 18:6a4db94011d3 268 avail -= 2;
sahilmgandhi 18:6a4db94011d3 269 } else {
sahilmgandhi 18:6a4db94011d3 270 data[num++] = *fifo->rslts_8;
sahilmgandhi 18:6a4db94011d3 271 avail--;
sahilmgandhi 18:6a4db94011d3 272 }
sahilmgandhi 18:6a4db94011d3 273
sahilmgandhi 18:6a4db94011d3 274 // Check to see if there is more data in the FIFO
sahilmgandhi 18:6a4db94011d3 275 if (avail == 0) {
sahilmgandhi 18:6a4db94011d3 276 avail = ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS);
sahilmgandhi 18:6a4db94011d3 277 }
sahilmgandhi 18:6a4db94011d3 278 }
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 return num;
sahilmgandhi 18:6a4db94011d3 281 }
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 284 static uint32_t spi_master_transfer_handler(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 285 {
sahilmgandhi 18:6a4db94011d3 286 uint8_t read;
sahilmgandhi 18:6a4db94011d3 287 uint8_t write;
sahilmgandhi 18:6a4db94011d3 288 uint16_t header;
sahilmgandhi 18:6a4db94011d3 289 uint32_t pages;
sahilmgandhi 18:6a4db94011d3 290 uint32_t bytes;
sahilmgandhi 18:6a4db94011d3 291 uint32_t inten;
sahilmgandhi 18:6a4db94011d3 292 unsigned remain;
sahilmgandhi 18:6a4db94011d3 293 unsigned bytes_read;
sahilmgandhi 18:6a4db94011d3 294 unsigned head_rem_temp;
sahilmgandhi 18:6a4db94011d3 295 unsigned avail;
sahilmgandhi 18:6a4db94011d3 296 struct spi_s *req = &obj->spi;
sahilmgandhi 18:6a4db94011d3 297 mxc_spi_regs_t *spim = obj->spi.spi;
sahilmgandhi 18:6a4db94011d3 298 mxc_spi_fifo_regs_t *fifo = obj->spi.fifo;
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 inten = 0;
sahilmgandhi 18:6a4db94011d3 301
sahilmgandhi 18:6a4db94011d3 302 // Figure out if we're reading
sahilmgandhi 18:6a4db94011d3 303 read = (req->rx_data != NULL) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 304
sahilmgandhi 18:6a4db94011d3 305 // Figure out if we're writing
sahilmgandhi 18:6a4db94011d3 306 write = (req->tx_data != NULL) ? 1 : 0;
sahilmgandhi 18:6a4db94011d3 307
sahilmgandhi 18:6a4db94011d3 308 // Read byte from the FIFO if we are reading
sahilmgandhi 18:6a4db94011d3 309 if (read) {
sahilmgandhi 18:6a4db94011d3 310
sahilmgandhi 18:6a4db94011d3 311 // Read all of the data in the RXFIFO, or until we don't need anymore
sahilmgandhi 18:6a4db94011d3 312 bytes_read = spi_master_read_rxfifo(spim, fifo, &req->rx_data[req->read_num], (req->len - req->read_num));
sahilmgandhi 18:6a4db94011d3 313
sahilmgandhi 18:6a4db94011d3 314 req->read_num += bytes_read;
sahilmgandhi 18:6a4db94011d3 315
sahilmgandhi 18:6a4db94011d3 316 // Adjust head_rem if we are only reading
sahilmgandhi 18:6a4db94011d3 317 if (!write && (req->head_rem > 0)) {
sahilmgandhi 18:6a4db94011d3 318 req->head_rem -= bytes_read;
sahilmgandhi 18:6a4db94011d3 319 }
sahilmgandhi 18:6a4db94011d3 320
sahilmgandhi 18:6a4db94011d3 321 // Figure out how many bytes we have left to read
sahilmgandhi 18:6a4db94011d3 322 if (req->head_rem > 0) {
sahilmgandhi 18:6a4db94011d3 323 remain = req->head_rem;
sahilmgandhi 18:6a4db94011d3 324 } else {
sahilmgandhi 18:6a4db94011d3 325 remain = req->len - req->read_num;
sahilmgandhi 18:6a4db94011d3 326 }
sahilmgandhi 18:6a4db94011d3 327
sahilmgandhi 18:6a4db94011d3 328 if (remain) {
sahilmgandhi 18:6a4db94011d3 329
sahilmgandhi 18:6a4db94011d3 330 // Set the RX interrupts
sahilmgandhi 18:6a4db94011d3 331 if (remain > MXC_CFG_SPI_FIFO_DEPTH) {
sahilmgandhi 18:6a4db94011d3 332 spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL) |
sahilmgandhi 18:6a4db94011d3 333 ((MXC_CFG_SPI_FIFO_DEPTH - 2) << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS));
sahilmgandhi 18:6a4db94011d3 334 } else {
sahilmgandhi 18:6a4db94011d3 335 spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL) |
sahilmgandhi 18:6a4db94011d3 336 ((remain - 1) << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS));
sahilmgandhi 18:6a4db94011d3 337 }
sahilmgandhi 18:6a4db94011d3 338
sahilmgandhi 18:6a4db94011d3 339 inten |= MXC_F_SPI_INTEN_RX_FIFO_AF;
sahilmgandhi 18:6a4db94011d3 340 }
sahilmgandhi 18:6a4db94011d3 341 }
sahilmgandhi 18:6a4db94011d3 342
sahilmgandhi 18:6a4db94011d3 343 // Figure out how many bytes we have left to send headers for
sahilmgandhi 18:6a4db94011d3 344 if (write) {
sahilmgandhi 18:6a4db94011d3 345 remain = req->len - req->write_num;
sahilmgandhi 18:6a4db94011d3 346 } else {
sahilmgandhi 18:6a4db94011d3 347 remain = req->len - req->read_num;
sahilmgandhi 18:6a4db94011d3 348 }
sahilmgandhi 18:6a4db94011d3 349
sahilmgandhi 18:6a4db94011d3 350 // See if we need to send a new header
sahilmgandhi 18:6a4db94011d3 351 if ((req->head_rem <= 0) && remain) {
sahilmgandhi 18:6a4db94011d3 352
sahilmgandhi 18:6a4db94011d3 353 // Set the transaction configuration in the header
sahilmgandhi 18:6a4db94011d3 354 header = ((write | (read << 1)) << MXC_F_SPI_FIFO_DIR_POS) | (req->width << MXC_F_SPI_FIFO_WIDTH_POS);
sahilmgandhi 18:6a4db94011d3 355
sahilmgandhi 18:6a4db94011d3 356 if (remain >= SPI_MAX_BYTE_LEN) {
sahilmgandhi 18:6a4db94011d3 357
sahilmgandhi 18:6a4db94011d3 358 // Send a 32 byte header
sahilmgandhi 18:6a4db94011d3 359 if (remain == SPI_MAX_BYTE_LEN) {
sahilmgandhi 18:6a4db94011d3 360
sahilmgandhi 18:6a4db94011d3 361 header |= (MXC_S_SPI_FIFO_UNIT_BYTES | MXC_F_SPI_FIFO_DASS);
sahilmgandhi 18:6a4db94011d3 362
sahilmgandhi 18:6a4db94011d3 363 // Save the number of bytes we need to write to the FIFO
sahilmgandhi 18:6a4db94011d3 364 bytes = SPI_MAX_BYTE_LEN;
sahilmgandhi 18:6a4db94011d3 365
sahilmgandhi 18:6a4db94011d3 366 } else {
sahilmgandhi 18:6a4db94011d3 367 // Send in increments of 32 byte pages
sahilmgandhi 18:6a4db94011d3 368 header |= MXC_S_SPI_FIFO_UNIT_PAGES;
sahilmgandhi 18:6a4db94011d3 369 pages = remain / SPI_MAX_PAGE_LEN;
sahilmgandhi 18:6a4db94011d3 370
sahilmgandhi 18:6a4db94011d3 371 if (pages >= 32) {
sahilmgandhi 18:6a4db94011d3 372 // 0 maps to 32 in the header
sahilmgandhi 18:6a4db94011d3 373 bytes = 32 * SPI_MAX_PAGE_LEN;
sahilmgandhi 18:6a4db94011d3 374 } else {
sahilmgandhi 18:6a4db94011d3 375 header |= (pages << MXC_F_SPI_FIFO_SIZE_POS);
sahilmgandhi 18:6a4db94011d3 376 bytes = pages * SPI_MAX_PAGE_LEN;
sahilmgandhi 18:6a4db94011d3 377 }
sahilmgandhi 18:6a4db94011d3 378
sahilmgandhi 18:6a4db94011d3 379 // Check if this is the last header we will send
sahilmgandhi 18:6a4db94011d3 380 if ((remain - bytes) == 0) {
sahilmgandhi 18:6a4db94011d3 381 header |= MXC_F_SPI_FIFO_DASS;
sahilmgandhi 18:6a4db94011d3 382 }
sahilmgandhi 18:6a4db94011d3 383 }
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 fifo->trans_16[0] = header;
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 // Save the number of bytes we need to write to the FIFO
sahilmgandhi 18:6a4db94011d3 388 req->head_rem = bytes;
sahilmgandhi 18:6a4db94011d3 389
sahilmgandhi 18:6a4db94011d3 390 } else {
sahilmgandhi 18:6a4db94011d3 391 // Send final header with the number of bytes remaining and de-assert the SS at the end of the transaction
sahilmgandhi 18:6a4db94011d3 392 header |= (MXC_S_SPI_FIFO_UNIT_BYTES | (remain << MXC_F_SPI_FIFO_SIZE_POS) | MXC_F_SPI_FIFO_DASS);
sahilmgandhi 18:6a4db94011d3 393 fifo->trans_16[0] = header;
sahilmgandhi 18:6a4db94011d3 394 req->head_rem = remain;
sahilmgandhi 18:6a4db94011d3 395 }
sahilmgandhi 18:6a4db94011d3 396 }
sahilmgandhi 18:6a4db94011d3 397
sahilmgandhi 18:6a4db94011d3 398 // Put data into the FIFO if we are writing
sahilmgandhi 18:6a4db94011d3 399 remain = req->len - req->write_num;
sahilmgandhi 18:6a4db94011d3 400 head_rem_temp = req->head_rem;
sahilmgandhi 18:6a4db94011d3 401 if (write && head_rem_temp) {
sahilmgandhi 18:6a4db94011d3 402
sahilmgandhi 18:6a4db94011d3 403 // Fill the FIFO
sahilmgandhi 18:6a4db94011d3 404 avail = (MXC_CFG_SPI_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS));
sahilmgandhi 18:6a4db94011d3 405
sahilmgandhi 18:6a4db94011d3 406 // Use memcpy for everything except the last byte in odd length transactions
sahilmgandhi 18:6a4db94011d3 407 while ((avail >= 2) && (head_rem_temp >= 2)) {
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 unsigned length;
sahilmgandhi 18:6a4db94011d3 410 if (head_rem_temp < avail) {
sahilmgandhi 18:6a4db94011d3 411 length = head_rem_temp;
sahilmgandhi 18:6a4db94011d3 412 } else {
sahilmgandhi 18:6a4db94011d3 413 length = avail;
sahilmgandhi 18:6a4db94011d3 414 }
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 // Only memcpy even numbers
sahilmgandhi 18:6a4db94011d3 417 length = ((length / 2) * 2);
sahilmgandhi 18:6a4db94011d3 418
sahilmgandhi 18:6a4db94011d3 419 memcpy((void*)fifo->trans_32, &(req->tx_data[req->write_num]), length);
sahilmgandhi 18:6a4db94011d3 420
sahilmgandhi 18:6a4db94011d3 421 head_rem_temp -= length;
sahilmgandhi 18:6a4db94011d3 422 req->write_num += length;
sahilmgandhi 18:6a4db94011d3 423
sahilmgandhi 18:6a4db94011d3 424 avail = (MXC_CFG_SPI_FIFO_DEPTH - ((spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED) >> MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS));
sahilmgandhi 18:6a4db94011d3 425 }
sahilmgandhi 18:6a4db94011d3 426
sahilmgandhi 18:6a4db94011d3 427 // Copy the last byte and pad with 0xF0 to not get confused as header
sahilmgandhi 18:6a4db94011d3 428 if ((avail >= 1) && (head_rem_temp == 1)) {
sahilmgandhi 18:6a4db94011d3 429
sahilmgandhi 18:6a4db94011d3 430 // Write the last byte
sahilmgandhi 18:6a4db94011d3 431 fifo->trans_16[0] = (0xF000 | req->tx_data[req->write_num]);
sahilmgandhi 18:6a4db94011d3 432
sahilmgandhi 18:6a4db94011d3 433 avail -= 1;
sahilmgandhi 18:6a4db94011d3 434 req->write_num += 1;
sahilmgandhi 18:6a4db94011d3 435 head_rem_temp -= 1;
sahilmgandhi 18:6a4db94011d3 436 }
sahilmgandhi 18:6a4db94011d3 437
sahilmgandhi 18:6a4db94011d3 438 req->head_rem = head_rem_temp;
sahilmgandhi 18:6a4db94011d3 439 remain = req->len - req->write_num;
sahilmgandhi 18:6a4db94011d3 440
sahilmgandhi 18:6a4db94011d3 441 // Set the TX interrupts
sahilmgandhi 18:6a4db94011d3 442 if (remain) {
sahilmgandhi 18:6a4db94011d3 443
sahilmgandhi 18:6a4db94011d3 444 // Set the TX FIFO almost empty interrupt if we have to refill
sahilmgandhi 18:6a4db94011d3 445 spim->fifo_ctrl = ((spim->fifo_ctrl & ~MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL) |
sahilmgandhi 18:6a4db94011d3 446 ((MXC_CFG_SPI_FIFO_DEPTH - 2) << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS));
sahilmgandhi 18:6a4db94011d3 447
sahilmgandhi 18:6a4db94011d3 448 inten |= MXC_F_SPI_INTEN_TX_FIFO_AE;
sahilmgandhi 18:6a4db94011d3 449 }
sahilmgandhi 18:6a4db94011d3 450 }
sahilmgandhi 18:6a4db94011d3 451
sahilmgandhi 18:6a4db94011d3 452 // Check to see if we've finished reading and writing
sahilmgandhi 18:6a4db94011d3 453 if (((read && (req->read_num == req->len)) || !read) &&
sahilmgandhi 18:6a4db94011d3 454 ((req->write_num == req->len) || !write)) {
sahilmgandhi 18:6a4db94011d3 455
sahilmgandhi 18:6a4db94011d3 456 // Disable interrupts
sahilmgandhi 18:6a4db94011d3 457 spim->inten = 0;
sahilmgandhi 18:6a4db94011d3 458 }
sahilmgandhi 18:6a4db94011d3 459
sahilmgandhi 18:6a4db94011d3 460 // Enable the SPIM interrupts
sahilmgandhi 18:6a4db94011d3 461 return inten;
sahilmgandhi 18:6a4db94011d3 462 }
sahilmgandhi 18:6a4db94011d3 463
sahilmgandhi 18:6a4db94011d3 464 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 465 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
sahilmgandhi 18:6a4db94011d3 466 {
sahilmgandhi 18:6a4db94011d3 467 MBED_ASSERT(tx_length == rx_length);
sahilmgandhi 18:6a4db94011d3 468 MBED_ASSERT(bit_width == obj->spi.bits);
sahilmgandhi 18:6a4db94011d3 469
sahilmgandhi 18:6a4db94011d3 470 // Save object reference for callback
sahilmgandhi 18:6a4db94011d3 471 state[obj->spi.index] = &obj->spi;
sahilmgandhi 18:6a4db94011d3 472
sahilmgandhi 18:6a4db94011d3 473 // Initialize request info
sahilmgandhi 18:6a4db94011d3 474 obj->spi.tx_data = tx;
sahilmgandhi 18:6a4db94011d3 475 obj->spi.rx_data = rx;
sahilmgandhi 18:6a4db94011d3 476 obj->spi.len = tx_length;
sahilmgandhi 18:6a4db94011d3 477 obj->spi.callback = (void(*)())handler;
sahilmgandhi 18:6a4db94011d3 478 obj->spi.event = event;
sahilmgandhi 18:6a4db94011d3 479 // Clear transfer state
sahilmgandhi 18:6a4db94011d3 480 obj->spi.read_num = 0;
sahilmgandhi 18:6a4db94011d3 481 obj->spi.write_num = 0;
sahilmgandhi 18:6a4db94011d3 482 obj->spi.head_rem = 0;
sahilmgandhi 18:6a4db94011d3 483
sahilmgandhi 18:6a4db94011d3 484 NVIC_EnableIRQ(MXC_SPI_GET_IRQ(obj->spi.index));
sahilmgandhi 18:6a4db94011d3 485
sahilmgandhi 18:6a4db94011d3 486 obj->spi.spi->inten = spi_master_transfer_handler(obj);
sahilmgandhi 18:6a4db94011d3 487 }
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 490 uint32_t spi_irq_handler_asynch(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 491 {
sahilmgandhi 18:6a4db94011d3 492 mxc_spi_regs_t *spim = obj->spi.spi;
sahilmgandhi 18:6a4db94011d3 493 uint32_t flags;
sahilmgandhi 18:6a4db94011d3 494
sahilmgandhi 18:6a4db94011d3 495 // Clear the interrupt flags
sahilmgandhi 18:6a4db94011d3 496 spim->inten = 0;
sahilmgandhi 18:6a4db94011d3 497 flags = spim->intfl;
sahilmgandhi 18:6a4db94011d3 498 spim->intfl = flags;
sahilmgandhi 18:6a4db94011d3 499
sahilmgandhi 18:6a4db94011d3 500 // Figure out if this SPIM has an active request
sahilmgandhi 18:6a4db94011d3 501 if (flags) {
sahilmgandhi 18:6a4db94011d3 502 if ((spim->inten = spi_master_transfer_handler(obj)) != 0) {
sahilmgandhi 18:6a4db94011d3 503 return 0;
sahilmgandhi 18:6a4db94011d3 504 }
sahilmgandhi 18:6a4db94011d3 505 }
sahilmgandhi 18:6a4db94011d3 506
sahilmgandhi 18:6a4db94011d3 507 state[obj->spi.index] = NULL;
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 return SPI_EVENT_COMPLETE;
sahilmgandhi 18:6a4db94011d3 510 }
sahilmgandhi 18:6a4db94011d3 511
sahilmgandhi 18:6a4db94011d3 512 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 513 uint8_t spi_active(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 514 {
sahilmgandhi 18:6a4db94011d3 515 mxc_spi_regs_t *spim = obj->spi.spi;
sahilmgandhi 18:6a4db94011d3 516
sahilmgandhi 18:6a4db94011d3 517 // Check to see if there are any ongoing transactions
sahilmgandhi 18:6a4db94011d3 518 if ((state[obj->spi.index] == NULL) &&
sahilmgandhi 18:6a4db94011d3 519 !(spim->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED)) {
sahilmgandhi 18:6a4db94011d3 520 return 0;
sahilmgandhi 18:6a4db94011d3 521 }
sahilmgandhi 18:6a4db94011d3 522
sahilmgandhi 18:6a4db94011d3 523 return 1;
sahilmgandhi 18:6a4db94011d3 524 }
sahilmgandhi 18:6a4db94011d3 525
sahilmgandhi 18:6a4db94011d3 526 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 527 void spi_abort_asynch(spi_t *obj)
sahilmgandhi 18:6a4db94011d3 528 {
sahilmgandhi 18:6a4db94011d3 529 mxc_spi_regs_t *spim = obj->spi.spi;
sahilmgandhi 18:6a4db94011d3 530
sahilmgandhi 18:6a4db94011d3 531 // Disable interrupts, clear the flags
sahilmgandhi 18:6a4db94011d3 532 spim->inten = 0;
sahilmgandhi 18:6a4db94011d3 533 spim->intfl = spim->intfl;
sahilmgandhi 18:6a4db94011d3 534
sahilmgandhi 18:6a4db94011d3 535 // Reset the SPIM to cancel the on ongoing transaction
sahilmgandhi 18:6a4db94011d3 536 spim->gen_ctrl &= ~(MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN);
sahilmgandhi 18:6a4db94011d3 537 spim->gen_ctrl |= (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN);
sahilmgandhi 18:6a4db94011d3 538
sahilmgandhi 18:6a4db94011d3 539 state[obj->spi.index] = NULL;
sahilmgandhi 18:6a4db94011d3 540 }
sahilmgandhi 18:6a4db94011d3 541
sahilmgandhi 18:6a4db94011d3 542 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 543 static void SPI_IRQHandler(int spim_num)
sahilmgandhi 18:6a4db94011d3 544 {
sahilmgandhi 18:6a4db94011d3 545 if (state[spim_num] != NULL) {
sahilmgandhi 18:6a4db94011d3 546 if (state[spim_num]->callback != NULL) {
sahilmgandhi 18:6a4db94011d3 547 state[spim_num]->callback();
sahilmgandhi 18:6a4db94011d3 548 return;
sahilmgandhi 18:6a4db94011d3 549 }
sahilmgandhi 18:6a4db94011d3 550 }
sahilmgandhi 18:6a4db94011d3 551 mxc_spi_regs_t *spim = MXC_SPI_GET_SPI(spim_num);
sahilmgandhi 18:6a4db94011d3 552 spim->inten = 0;
sahilmgandhi 18:6a4db94011d3 553 }
sahilmgandhi 18:6a4db94011d3 554
sahilmgandhi 18:6a4db94011d3 555 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 556 void SPI0_IRQHandler(void) { SPI_IRQHandler(0); }
sahilmgandhi 18:6a4db94011d3 557 void SPI1_IRQHandler(void) { SPI_IRQHandler(1); }
sahilmgandhi 18:6a4db94011d3 558 void SPI2_IRQHandler(void) { SPI_IRQHandler(2); }
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 #endif