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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Maxim/TARGET_MAX32620/rtc_api.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
sahilmgandhi 18:6a4db94011d3 3 *
sahilmgandhi 18:6a4db94011d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
sahilmgandhi 18:6a4db94011d3 5 * copy of this software and associated documentation files (the "Software"),
sahilmgandhi 18:6a4db94011d3 6 * to deal in the Software without restriction, including without limitation
sahilmgandhi 18:6a4db94011d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
sahilmgandhi 18:6a4db94011d3 8 * and/or sell copies of the Software, and to permit persons to whom the
sahilmgandhi 18:6a4db94011d3 9 * Software is furnished to do so, subject to the following conditions:
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * The above copyright notice and this permission notice shall be included
sahilmgandhi 18:6a4db94011d3 12 * in all copies or substantial portions of the Software.
sahilmgandhi 18:6a4db94011d3 13 *
sahilmgandhi 18:6a4db94011d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
sahilmgandhi 18:6a4db94011d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
sahilmgandhi 18:6a4db94011d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
sahilmgandhi 18:6a4db94011d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
sahilmgandhi 18:6a4db94011d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
sahilmgandhi 18:6a4db94011d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
sahilmgandhi 18:6a4db94011d3 20 * OTHER DEALINGS IN THE SOFTWARE.
sahilmgandhi 18:6a4db94011d3 21 *
sahilmgandhi 18:6a4db94011d3 22 * Except as contained in this notice, the name of Maxim Integrated
sahilmgandhi 18:6a4db94011d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
sahilmgandhi 18:6a4db94011d3 24 * Products, Inc. Branding Policy.
sahilmgandhi 18:6a4db94011d3 25 *
sahilmgandhi 18:6a4db94011d3 26 * The mere transfer of this software does not imply any licenses
sahilmgandhi 18:6a4db94011d3 27 * of trade secrets, proprietary technology, copyrights, patents,
sahilmgandhi 18:6a4db94011d3 28 * trademarks, maskwork rights, or any other form of intellectual
sahilmgandhi 18:6a4db94011d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
sahilmgandhi 18:6a4db94011d3 30 * ownership rights.
sahilmgandhi 18:6a4db94011d3 31 *******************************************************************************
sahilmgandhi 18:6a4db94011d3 32 */
sahilmgandhi 18:6a4db94011d3 33
sahilmgandhi 18:6a4db94011d3 34 #include "rtc_api.h"
sahilmgandhi 18:6a4db94011d3 35 #include "lp_ticker_api.h"
sahilmgandhi 18:6a4db94011d3 36 #include "cmsis.h"
sahilmgandhi 18:6a4db94011d3 37 #include "rtc_regs.h"
sahilmgandhi 18:6a4db94011d3 38 #include "pwrseq_regs.h"
sahilmgandhi 18:6a4db94011d3 39 #include "clkman_regs.h"
sahilmgandhi 18:6a4db94011d3 40
sahilmgandhi 18:6a4db94011d3 41 /**
sahilmgandhi 18:6a4db94011d3 42 * Defines clock divider for 4096Hz input clock.
sahilmgandhi 18:6a4db94011d3 43 */
sahilmgandhi 18:6a4db94011d3 44 typedef enum {
sahilmgandhi 18:6a4db94011d3 45 /** (4kHz) divide input clock by 2^0 = 1 */
sahilmgandhi 18:6a4db94011d3 46 MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
sahilmgandhi 18:6a4db94011d3 47 /** (2kHz) divide input clock by 2^1 = 2 */
sahilmgandhi 18:6a4db94011d3 48 MXC_E_RTC_PRESCALE_DIV_2_1,
sahilmgandhi 18:6a4db94011d3 49 /** (1kHz) divide input clock by 2^2 = 4 */
sahilmgandhi 18:6a4db94011d3 50 MXC_E_RTC_PRESCALE_DIV_2_2,
sahilmgandhi 18:6a4db94011d3 51 /** (512Hz) divide input clock by 2^3 = 8 */
sahilmgandhi 18:6a4db94011d3 52 MXC_E_RTC_PRESCALE_DIV_2_3,
sahilmgandhi 18:6a4db94011d3 53 /** (256Hz) divide input clock by 2^4 = 16 */
sahilmgandhi 18:6a4db94011d3 54 MXC_E_RTC_PRESCALE_DIV_2_4,
sahilmgandhi 18:6a4db94011d3 55 /** (128Hz) divide input clock by 2^5 = 32 */
sahilmgandhi 18:6a4db94011d3 56 MXC_E_RTC_PRESCALE_DIV_2_5,
sahilmgandhi 18:6a4db94011d3 57 /** (64Hz) divide input clock by 2^6 = 64 */
sahilmgandhi 18:6a4db94011d3 58 MXC_E_RTC_PRESCALE_DIV_2_6,
sahilmgandhi 18:6a4db94011d3 59 /** (32Hz) divide input clock by 2^7 = 128 */
sahilmgandhi 18:6a4db94011d3 60 MXC_E_RTC_PRESCALE_DIV_2_7,
sahilmgandhi 18:6a4db94011d3 61 /** (16Hz) divide input clock by 2^8 = 256 */
sahilmgandhi 18:6a4db94011d3 62 MXC_E_RTC_PRESCALE_DIV_2_8,
sahilmgandhi 18:6a4db94011d3 63 /** (8Hz) divide input clock by 2^9 = 512 */
sahilmgandhi 18:6a4db94011d3 64 MXC_E_RTC_PRESCALE_DIV_2_9,
sahilmgandhi 18:6a4db94011d3 65 /** (4Hz) divide input clock by 2^10 = 1024 */
sahilmgandhi 18:6a4db94011d3 66 MXC_E_RTC_PRESCALE_DIV_2_10,
sahilmgandhi 18:6a4db94011d3 67 /** (2Hz) divide input clock by 2^11 = 2048 */
sahilmgandhi 18:6a4db94011d3 68 MXC_E_RTC_PRESCALE_DIV_2_11,
sahilmgandhi 18:6a4db94011d3 69 /** (1Hz) divide input clock by 2^12 = 4096 */
sahilmgandhi 18:6a4db94011d3 70 MXC_E_RTC_PRESCALE_DIV_2_12,
sahilmgandhi 18:6a4db94011d3 71 } mxc_rtc_prescale_t;
sahilmgandhi 18:6a4db94011d3 72
sahilmgandhi 18:6a4db94011d3 73 #define PRESCALE_VAL MXC_E_RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
sahilmgandhi 18:6a4db94011d3 74 #define SHIFT_AMT (MXC_E_RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
sahilmgandhi 18:6a4db94011d3 75
sahilmgandhi 18:6a4db94011d3 76 #define WINDOW 1000
sahilmgandhi 18:6a4db94011d3 77
sahilmgandhi 18:6a4db94011d3 78 static int rtc_inited = 0;
sahilmgandhi 18:6a4db94011d3 79 static volatile uint32_t overflow_cnt = 0;
sahilmgandhi 18:6a4db94011d3 80
sahilmgandhi 18:6a4db94011d3 81 static uint64_t rtc_read64(void);
sahilmgandhi 18:6a4db94011d3 82
sahilmgandhi 18:6a4db94011d3 83 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 84 static void overflow_handler(void)
sahilmgandhi 18:6a4db94011d3 85 {
sahilmgandhi 18:6a4db94011d3 86 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
sahilmgandhi 18:6a4db94011d3 87 overflow_cnt++;
sahilmgandhi 18:6a4db94011d3 88
sahilmgandhi 18:6a4db94011d3 89 // Wait for pending transactions
sahilmgandhi 18:6a4db94011d3 90 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
sahilmgandhi 18:6a4db94011d3 91 }
sahilmgandhi 18:6a4db94011d3 92
sahilmgandhi 18:6a4db94011d3 93 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 94 void rtc_init(void)
sahilmgandhi 18:6a4db94011d3 95 {
sahilmgandhi 18:6a4db94011d3 96 if (rtc_inited) {
sahilmgandhi 18:6a4db94011d3 97 return;
sahilmgandhi 18:6a4db94011d3 98 }
sahilmgandhi 18:6a4db94011d3 99 rtc_inited = 1;
sahilmgandhi 18:6a4db94011d3 100
sahilmgandhi 18:6a4db94011d3 101 overflow_cnt = 0;
sahilmgandhi 18:6a4db94011d3 102
sahilmgandhi 18:6a4db94011d3 103 // Enable the clock to the synchronizer
sahilmgandhi 18:6a4db94011d3 104 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
sahilmgandhi 18:6a4db94011d3 105
sahilmgandhi 18:6a4db94011d3 106 // Enable the clock to the RTC
sahilmgandhi 18:6a4db94011d3 107 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
sahilmgandhi 18:6a4db94011d3 108
sahilmgandhi 18:6a4db94011d3 109 // Prepare interrupt handlers
sahilmgandhi 18:6a4db94011d3 110 NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
sahilmgandhi 18:6a4db94011d3 111 NVIC_EnableIRQ(RTC0_IRQn);
sahilmgandhi 18:6a4db94011d3 112 NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
sahilmgandhi 18:6a4db94011d3 113 NVIC_EnableIRQ(RTC3_IRQn);
sahilmgandhi 18:6a4db94011d3 114
sahilmgandhi 18:6a4db94011d3 115 // Enable wakeup on RTC rollover
sahilmgandhi 18:6a4db94011d3 116 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
sahilmgandhi 18:6a4db94011d3 117
sahilmgandhi 18:6a4db94011d3 118 /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
sahilmgandhi 18:6a4db94011d3 119 * if it is already running.
sahilmgandhi 18:6a4db94011d3 120 */
sahilmgandhi 18:6a4db94011d3 121 if (!(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)) {
sahilmgandhi 18:6a4db94011d3 122 // Set the clock divider
sahilmgandhi 18:6a4db94011d3 123 MXC_RTCTMR->prescale = PRESCALE_VAL;
sahilmgandhi 18:6a4db94011d3 124
sahilmgandhi 18:6a4db94011d3 125 // Enable the overflow interrupt
sahilmgandhi 18:6a4db94011d3 126 MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
sahilmgandhi 18:6a4db94011d3 127
sahilmgandhi 18:6a4db94011d3 128 // Restart the timer from 0
sahilmgandhi 18:6a4db94011d3 129 MXC_RTCTMR->timer = 0;
sahilmgandhi 18:6a4db94011d3 130
sahilmgandhi 18:6a4db94011d3 131 // Enable the RTC
sahilmgandhi 18:6a4db94011d3 132 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
sahilmgandhi 18:6a4db94011d3 133 }
sahilmgandhi 18:6a4db94011d3 134 }
sahilmgandhi 18:6a4db94011d3 135
sahilmgandhi 18:6a4db94011d3 136 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 137 void lp_ticker_init(void)
sahilmgandhi 18:6a4db94011d3 138 {
sahilmgandhi 18:6a4db94011d3 139 rtc_init();
sahilmgandhi 18:6a4db94011d3 140 }
sahilmgandhi 18:6a4db94011d3 141
sahilmgandhi 18:6a4db94011d3 142 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 143 void rtc_free(void)
sahilmgandhi 18:6a4db94011d3 144 {
sahilmgandhi 18:6a4db94011d3 145 if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
sahilmgandhi 18:6a4db94011d3 146 // Clear and disable RTC
sahilmgandhi 18:6a4db94011d3 147 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
sahilmgandhi 18:6a4db94011d3 148 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
sahilmgandhi 18:6a4db94011d3 149
sahilmgandhi 18:6a4db94011d3 150 // Wait for pending transactions
sahilmgandhi 18:6a4db94011d3 151 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
sahilmgandhi 18:6a4db94011d3 152 }
sahilmgandhi 18:6a4db94011d3 153
sahilmgandhi 18:6a4db94011d3 154 // Disable the clock to the RTC
sahilmgandhi 18:6a4db94011d3 155 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
sahilmgandhi 18:6a4db94011d3 156
sahilmgandhi 18:6a4db94011d3 157 // Disable the clock to the synchronizer
sahilmgandhi 18:6a4db94011d3 158 MXC_CLKMAN->sys_clk_ctrl_1_sync = MXC_S_CLKMAN_CLK_SCALE_DISABLED;
sahilmgandhi 18:6a4db94011d3 159 }
sahilmgandhi 18:6a4db94011d3 160
sahilmgandhi 18:6a4db94011d3 161 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 162 int rtc_isenabled(void)
sahilmgandhi 18:6a4db94011d3 163 {
sahilmgandhi 18:6a4db94011d3 164 return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
sahilmgandhi 18:6a4db94011d3 165 }
sahilmgandhi 18:6a4db94011d3 166
sahilmgandhi 18:6a4db94011d3 167 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 168 time_t rtc_read(void)
sahilmgandhi 18:6a4db94011d3 169 {
sahilmgandhi 18:6a4db94011d3 170 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
sahilmgandhi 18:6a4db94011d3 171 uint32_t ovf1, ovf2;
sahilmgandhi 18:6a4db94011d3 172
sahilmgandhi 18:6a4db94011d3 173 // Make sure RTC is setup before trying to read
sahilmgandhi 18:6a4db94011d3 174 if (!rtc_inited) {
sahilmgandhi 18:6a4db94011d3 175 rtc_init();
sahilmgandhi 18:6a4db94011d3 176 }
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 // Ensure coherency between overflow_cnt and timer
sahilmgandhi 18:6a4db94011d3 179 do {
sahilmgandhi 18:6a4db94011d3 180 ovf_cnt_1 = overflow_cnt;
sahilmgandhi 18:6a4db94011d3 181 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
sahilmgandhi 18:6a4db94011d3 182 timer_cnt = MXC_RTCTMR->timer;
sahilmgandhi 18:6a4db94011d3 183 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
sahilmgandhi 18:6a4db94011d3 184 ovf_cnt_2 = overflow_cnt;
sahilmgandhi 18:6a4db94011d3 185 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
sahilmgandhi 18:6a4db94011d3 186
sahilmgandhi 18:6a4db94011d3 187 // Account for an unserviced interrupt
sahilmgandhi 18:6a4db94011d3 188 if (ovf1) {
sahilmgandhi 18:6a4db94011d3 189 ovf_cnt_1++;
sahilmgandhi 18:6a4db94011d3 190 }
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
sahilmgandhi 18:6a4db94011d3 193 }
sahilmgandhi 18:6a4db94011d3 194
sahilmgandhi 18:6a4db94011d3 195 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 196 static uint64_t rtc_read64(void)
sahilmgandhi 18:6a4db94011d3 197 {
sahilmgandhi 18:6a4db94011d3 198 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
sahilmgandhi 18:6a4db94011d3 199 uint32_t ovf1, ovf2;
sahilmgandhi 18:6a4db94011d3 200 uint64_t current_us;
sahilmgandhi 18:6a4db94011d3 201
sahilmgandhi 18:6a4db94011d3 202 // Make sure RTC is setup before trying to read
sahilmgandhi 18:6a4db94011d3 203 if (!rtc_inited) {
sahilmgandhi 18:6a4db94011d3 204 rtc_init();
sahilmgandhi 18:6a4db94011d3 205 }
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 // Ensure coherency between overflow_cnt and timer
sahilmgandhi 18:6a4db94011d3 208 do {
sahilmgandhi 18:6a4db94011d3 209 ovf_cnt_1 = overflow_cnt;
sahilmgandhi 18:6a4db94011d3 210 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
sahilmgandhi 18:6a4db94011d3 211 timer_cnt = MXC_RTCTMR->timer;
sahilmgandhi 18:6a4db94011d3 212 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
sahilmgandhi 18:6a4db94011d3 213 ovf_cnt_2 = overflow_cnt;
sahilmgandhi 18:6a4db94011d3 214 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
sahilmgandhi 18:6a4db94011d3 215
sahilmgandhi 18:6a4db94011d3 216 // Account for an unserviced interrupt
sahilmgandhi 18:6a4db94011d3 217 if (ovf1) {
sahilmgandhi 18:6a4db94011d3 218 ovf_cnt_1++;
sahilmgandhi 18:6a4db94011d3 219 }
sahilmgandhi 18:6a4db94011d3 220
sahilmgandhi 18:6a4db94011d3 221 current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 return current_us;
sahilmgandhi 18:6a4db94011d3 224 }
sahilmgandhi 18:6a4db94011d3 225
sahilmgandhi 18:6a4db94011d3 226 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 227 void rtc_write(time_t t)
sahilmgandhi 18:6a4db94011d3 228 {
sahilmgandhi 18:6a4db94011d3 229 // Make sure RTC is setup before accessing
sahilmgandhi 18:6a4db94011d3 230 if (!rtc_inited) {
sahilmgandhi 18:6a4db94011d3 231 rtc_init();
sahilmgandhi 18:6a4db94011d3 232 }
sahilmgandhi 18:6a4db94011d3 233
sahilmgandhi 18:6a4db94011d3 234 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
sahilmgandhi 18:6a4db94011d3 235 MXC_RTCTMR->timer = t << SHIFT_AMT;
sahilmgandhi 18:6a4db94011d3 236 overflow_cnt = t >> (32 - SHIFT_AMT);
sahilmgandhi 18:6a4db94011d3 237 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating
sahilmgandhi 18:6a4db94011d3 238 }
sahilmgandhi 18:6a4db94011d3 239
sahilmgandhi 18:6a4db94011d3 240 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 241 void lp_ticker_set_interrupt(timestamp_t timestamp)
sahilmgandhi 18:6a4db94011d3 242 {
sahilmgandhi 18:6a4db94011d3 243 uint32_t comp_value;
sahilmgandhi 18:6a4db94011d3 244 uint64_t curr_ts64;
sahilmgandhi 18:6a4db94011d3 245 uint64_t ts64;
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 // Note: interrupts are disabled before this function is called.
sahilmgandhi 18:6a4db94011d3 248
sahilmgandhi 18:6a4db94011d3 249 // Disable the alarm while it is prepared
sahilmgandhi 18:6a4db94011d3 250 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
sahilmgandhi 18:6a4db94011d3 251
sahilmgandhi 18:6a4db94011d3 252 curr_ts64 = rtc_read64();
sahilmgandhi 18:6a4db94011d3 253 ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 // If this event is older than a recent window, it must be in the future
sahilmgandhi 18:6a4db94011d3 256 if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
sahilmgandhi 18:6a4db94011d3 257 ts64 += 0x100000000ULL;
sahilmgandhi 18:6a4db94011d3 258 }
sahilmgandhi 18:6a4db94011d3 259
sahilmgandhi 18:6a4db94011d3 260 uint32_t timer = MXC_RTCTMR->timer;
sahilmgandhi 18:6a4db94011d3 261 if (ts64 <= curr_ts64) {
sahilmgandhi 18:6a4db94011d3 262 // This event has already occurred. Set the alarm to expire immediately.
sahilmgandhi 18:6a4db94011d3 263 comp_value = timer + 1;
sahilmgandhi 18:6a4db94011d3 264 } else {
sahilmgandhi 18:6a4db94011d3 265 comp_value = (ts64 << SHIFT_AMT) / 1000000;
sahilmgandhi 18:6a4db94011d3 266 }
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
sahilmgandhi 18:6a4db94011d3 269 if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
sahilmgandhi 18:6a4db94011d3 270 comp_value = timer + 2;
sahilmgandhi 18:6a4db94011d3 271 }
sahilmgandhi 18:6a4db94011d3 272
sahilmgandhi 18:6a4db94011d3 273 MXC_RTCTMR->comp[0] = comp_value;
sahilmgandhi 18:6a4db94011d3 274 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
sahilmgandhi 18:6a4db94011d3 275 MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
sahilmgandhi 18:6a4db94011d3 276
sahilmgandhi 18:6a4db94011d3 277 // Enable wakeup from RTC
sahilmgandhi 18:6a4db94011d3 278 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 // Wait for pending transactions
sahilmgandhi 18:6a4db94011d3 281 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
sahilmgandhi 18:6a4db94011d3 282 }
sahilmgandhi 18:6a4db94011d3 283
sahilmgandhi 18:6a4db94011d3 284 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 285 inline void lp_ticker_disable_interrupt(void)
sahilmgandhi 18:6a4db94011d3 286 {
sahilmgandhi 18:6a4db94011d3 287 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
sahilmgandhi 18:6a4db94011d3 288 }
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 291 inline void lp_ticker_clear_interrupt(void)
sahilmgandhi 18:6a4db94011d3 292 {
sahilmgandhi 18:6a4db94011d3 293 MXC_RTCTMR->flags |= MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 // Wait for pending transactions
sahilmgandhi 18:6a4db94011d3 296 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
sahilmgandhi 18:6a4db94011d3 297 }
sahilmgandhi 18:6a4db94011d3 298
sahilmgandhi 18:6a4db94011d3 299 //******************************************************************************
sahilmgandhi 18:6a4db94011d3 300 inline uint32_t lp_ticker_read(void)
sahilmgandhi 18:6a4db94011d3 301 {
sahilmgandhi 18:6a4db94011d3 302 return rtc_read64();
sahilmgandhi 18:6a4db94011d3 303 }