MacroRat / MouseCode

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Dependencies:   ITG3200 QEI

mbed-dev/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_uart.c@18:6a4db94011d3, 2017-05-14 (annotated)

Committer:
sahilmgandhi
Date:
Sun May 14 23:18:57 2017 +0000
Revision:
18:6a4db94011d3
Publishing again

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sahilmgandhi 18:6a4db94011d3 1 /*
sahilmgandhi 18:6a4db94011d3 2 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
sahilmgandhi 18:6a4db94011d3 3 * All rights reserved.
sahilmgandhi 18:6a4db94011d3 4 *
sahilmgandhi 18:6a4db94011d3 5 * Redistribution and use in source and binary forms, with or without modification,
sahilmgandhi 18:6a4db94011d3 6 * are permitted provided that the following conditions are met:
sahilmgandhi 18:6a4db94011d3 7 *
sahilmgandhi 18:6a4db94011d3 8 * o Redistributions of source code must retain the above copyright notice, this list
sahilmgandhi 18:6a4db94011d3 9 * of conditions and the following disclaimer.
sahilmgandhi 18:6a4db94011d3 10 *
sahilmgandhi 18:6a4db94011d3 11 * o Redistributions in binary form must reproduce the above copyright notice, this
sahilmgandhi 18:6a4db94011d3 12 * list of conditions and the following disclaimer in the documentation and/or
sahilmgandhi 18:6a4db94011d3 13 * other materials provided with the distribution.
sahilmgandhi 18:6a4db94011d3 14 *
sahilmgandhi 18:6a4db94011d3 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
sahilmgandhi 18:6a4db94011d3 16 * contributors may be used to endorse or promote products derived from this
sahilmgandhi 18:6a4db94011d3 17 * software without specific prior written permission.
sahilmgandhi 18:6a4db94011d3 18 *
sahilmgandhi 18:6a4db94011d3 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
sahilmgandhi 18:6a4db94011d3 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
sahilmgandhi 18:6a4db94011d3 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sahilmgandhi 18:6a4db94011d3 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
sahilmgandhi 18:6a4db94011d3 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
sahilmgandhi 18:6a4db94011d3 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
sahilmgandhi 18:6a4db94011d3 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
sahilmgandhi 18:6a4db94011d3 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
sahilmgandhi 18:6a4db94011d3 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
sahilmgandhi 18:6a4db94011d3 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sahilmgandhi 18:6a4db94011d3 29 */
sahilmgandhi 18:6a4db94011d3 30
sahilmgandhi 18:6a4db94011d3 31 #include "fsl_uart.h"
sahilmgandhi 18:6a4db94011d3 32
sahilmgandhi 18:6a4db94011d3 33 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 34 * Definitions
sahilmgandhi 18:6a4db94011d3 35 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 36
sahilmgandhi 18:6a4db94011d3 37 /* UART transfer state. */
sahilmgandhi 18:6a4db94011d3 38 enum _uart_tansfer_states
sahilmgandhi 18:6a4db94011d3 39 {
sahilmgandhi 18:6a4db94011d3 40 kUART_TxIdle, /* TX idle. */
sahilmgandhi 18:6a4db94011d3 41 kUART_TxBusy, /* TX busy. */
sahilmgandhi 18:6a4db94011d3 42 kUART_RxIdle, /* RX idle. */
sahilmgandhi 18:6a4db94011d3 43 kUART_RxBusy, /* RX busy. */
sahilmgandhi 18:6a4db94011d3 44 kUART_RxFramingError, /* Rx framing error */
sahilmgandhi 18:6a4db94011d3 45 kUART_RxParityError /* Rx parity error */
sahilmgandhi 18:6a4db94011d3 46 };
sahilmgandhi 18:6a4db94011d3 47
sahilmgandhi 18:6a4db94011d3 48 /* Typedef for interrupt handler. */
sahilmgandhi 18:6a4db94011d3 49 typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle);
sahilmgandhi 18:6a4db94011d3 50
sahilmgandhi 18:6a4db94011d3 51 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 52 * Prototypes
sahilmgandhi 18:6a4db94011d3 53 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 54
sahilmgandhi 18:6a4db94011d3 55 /*!
sahilmgandhi 18:6a4db94011d3 56 * @brief Get the UART instance from peripheral base address.
sahilmgandhi 18:6a4db94011d3 57 *
sahilmgandhi 18:6a4db94011d3 58 * @param base UART peripheral base address.
sahilmgandhi 18:6a4db94011d3 59 * @return UART instance.
sahilmgandhi 18:6a4db94011d3 60 */
sahilmgandhi 18:6a4db94011d3 61 uint32_t UART_GetInstance(UART_Type *base);
sahilmgandhi 18:6a4db94011d3 62
sahilmgandhi 18:6a4db94011d3 63 /*!
sahilmgandhi 18:6a4db94011d3 64 * @brief Get the length of received data in RX ring buffer.
sahilmgandhi 18:6a4db94011d3 65 *
sahilmgandhi 18:6a4db94011d3 66 * @param handle UART handle pointer.
sahilmgandhi 18:6a4db94011d3 67 * @return Length of received data in RX ring buffer.
sahilmgandhi 18:6a4db94011d3 68 */
sahilmgandhi 18:6a4db94011d3 69 static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle);
sahilmgandhi 18:6a4db94011d3 70
sahilmgandhi 18:6a4db94011d3 71 /*!
sahilmgandhi 18:6a4db94011d3 72 * @brief Check whether the RX ring buffer is full.
sahilmgandhi 18:6a4db94011d3 73 *
sahilmgandhi 18:6a4db94011d3 74 * @param handle UART handle pointer.
sahilmgandhi 18:6a4db94011d3 75 * @retval true RX ring buffer is full.
sahilmgandhi 18:6a4db94011d3 76 * @retval false RX ring buffer is not full.
sahilmgandhi 18:6a4db94011d3 77 */
sahilmgandhi 18:6a4db94011d3 78 static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle);
sahilmgandhi 18:6a4db94011d3 79
sahilmgandhi 18:6a4db94011d3 80 /*!
sahilmgandhi 18:6a4db94011d3 81 * @brief Read RX register using non-blocking method.
sahilmgandhi 18:6a4db94011d3 82 *
sahilmgandhi 18:6a4db94011d3 83 * This function reads data from the TX register directly, upper layer must make
sahilmgandhi 18:6a4db94011d3 84 * sure the RX register is full or TX FIFO has data before calling this function.
sahilmgandhi 18:6a4db94011d3 85 *
sahilmgandhi 18:6a4db94011d3 86 * @param base UART peripheral base address.
sahilmgandhi 18:6a4db94011d3 87 * @param data Start addresss of the buffer to store the received data.
sahilmgandhi 18:6a4db94011d3 88 * @param length Size of the buffer.
sahilmgandhi 18:6a4db94011d3 89 */
sahilmgandhi 18:6a4db94011d3 90 static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length);
sahilmgandhi 18:6a4db94011d3 91
sahilmgandhi 18:6a4db94011d3 92 /*!
sahilmgandhi 18:6a4db94011d3 93 * @brief Write to TX register using non-blocking method.
sahilmgandhi 18:6a4db94011d3 94 *
sahilmgandhi 18:6a4db94011d3 95 * This function writes data to the TX register directly, upper layer must make
sahilmgandhi 18:6a4db94011d3 96 * sure the TX register is empty or TX FIFO has empty room before calling this function.
sahilmgandhi 18:6a4db94011d3 97 *
sahilmgandhi 18:6a4db94011d3 98 * @note This function does not check whether all the data has been sent out to bus,
sahilmgandhi 18:6a4db94011d3 99 * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is
sahilmgandhi 18:6a4db94011d3 100 * finished.
sahilmgandhi 18:6a4db94011d3 101 *
sahilmgandhi 18:6a4db94011d3 102 * @param base UART peripheral base address.
sahilmgandhi 18:6a4db94011d3 103 * @param data Start addresss of the data to write.
sahilmgandhi 18:6a4db94011d3 104 * @param length Size of the buffer to be sent.
sahilmgandhi 18:6a4db94011d3 105 */
sahilmgandhi 18:6a4db94011d3 106 static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length);
sahilmgandhi 18:6a4db94011d3 107
sahilmgandhi 18:6a4db94011d3 108 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 109 * Variables
sahilmgandhi 18:6a4db94011d3 110 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 111 /* Array of UART handle. */
sahilmgandhi 18:6a4db94011d3 112 #if (defined(UART5))
sahilmgandhi 18:6a4db94011d3 113 #define UART_HANDLE_ARRAY_SIZE 6
sahilmgandhi 18:6a4db94011d3 114 #else /* UART5 */
sahilmgandhi 18:6a4db94011d3 115 #if (defined(UART4))
sahilmgandhi 18:6a4db94011d3 116 #define UART_HANDLE_ARRAY_SIZE 5
sahilmgandhi 18:6a4db94011d3 117 #else /* UART4 */
sahilmgandhi 18:6a4db94011d3 118 #if (defined(UART3))
sahilmgandhi 18:6a4db94011d3 119 #define UART_HANDLE_ARRAY_SIZE 4
sahilmgandhi 18:6a4db94011d3 120 #else /* UART3 */
sahilmgandhi 18:6a4db94011d3 121 #if (defined(UART2))
sahilmgandhi 18:6a4db94011d3 122 #define UART_HANDLE_ARRAY_SIZE 3
sahilmgandhi 18:6a4db94011d3 123 #else /* UART2 */
sahilmgandhi 18:6a4db94011d3 124 #if (defined(UART1))
sahilmgandhi 18:6a4db94011d3 125 #define UART_HANDLE_ARRAY_SIZE 2
sahilmgandhi 18:6a4db94011d3 126 #else /* UART1 */
sahilmgandhi 18:6a4db94011d3 127 #if (defined(UART0))
sahilmgandhi 18:6a4db94011d3 128 #define UART_HANDLE_ARRAY_SIZE 1
sahilmgandhi 18:6a4db94011d3 129 #else /* UART0 */
sahilmgandhi 18:6a4db94011d3 130 #error No UART instance.
sahilmgandhi 18:6a4db94011d3 131 #endif /* UART 0 */
sahilmgandhi 18:6a4db94011d3 132 #endif /* UART 1 */
sahilmgandhi 18:6a4db94011d3 133 #endif /* UART 2 */
sahilmgandhi 18:6a4db94011d3 134 #endif /* UART 3 */
sahilmgandhi 18:6a4db94011d3 135 #endif /* UART 4 */
sahilmgandhi 18:6a4db94011d3 136 #endif /* UART 5 */
sahilmgandhi 18:6a4db94011d3 137 static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE];
sahilmgandhi 18:6a4db94011d3 138 /* Array of UART peripheral base address. */
sahilmgandhi 18:6a4db94011d3 139 static UART_Type *const s_uartBases[] = UART_BASE_PTRS;
sahilmgandhi 18:6a4db94011d3 140
sahilmgandhi 18:6a4db94011d3 141 /* Array of UART IRQ number. */
sahilmgandhi 18:6a4db94011d3 142 static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS;
sahilmgandhi 18:6a4db94011d3 143 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
sahilmgandhi 18:6a4db94011d3 144 /* Array of UART clock name. */
sahilmgandhi 18:6a4db94011d3 145 static const clock_ip_name_t s_uartClock[] = UART_CLOCKS;
sahilmgandhi 18:6a4db94011d3 146 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
sahilmgandhi 18:6a4db94011d3 147
sahilmgandhi 18:6a4db94011d3 148 /* UART ISR for transactional APIs. */
sahilmgandhi 18:6a4db94011d3 149 static uart_isr_t s_uartIsr;
sahilmgandhi 18:6a4db94011d3 150
sahilmgandhi 18:6a4db94011d3 151 /*******************************************************************************
sahilmgandhi 18:6a4db94011d3 152 * Code
sahilmgandhi 18:6a4db94011d3 153 ******************************************************************************/
sahilmgandhi 18:6a4db94011d3 154
sahilmgandhi 18:6a4db94011d3 155 uint32_t UART_GetInstance(UART_Type *base)
sahilmgandhi 18:6a4db94011d3 156 {
sahilmgandhi 18:6a4db94011d3 157 uint32_t instance;
sahilmgandhi 18:6a4db94011d3 158 uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0]));
sahilmgandhi 18:6a4db94011d3 159
sahilmgandhi 18:6a4db94011d3 160 /* Find the instance index from base address mappings. */
sahilmgandhi 18:6a4db94011d3 161 for (instance = 0; instance < uartArrayCount; instance++)
sahilmgandhi 18:6a4db94011d3 162 {
sahilmgandhi 18:6a4db94011d3 163 if (s_uartBases[instance] == base)
sahilmgandhi 18:6a4db94011d3 164 {
sahilmgandhi 18:6a4db94011d3 165 break;
sahilmgandhi 18:6a4db94011d3 166 }
sahilmgandhi 18:6a4db94011d3 167 }
sahilmgandhi 18:6a4db94011d3 168
sahilmgandhi 18:6a4db94011d3 169 assert(instance < uartArrayCount);
sahilmgandhi 18:6a4db94011d3 170
sahilmgandhi 18:6a4db94011d3 171 return instance;
sahilmgandhi 18:6a4db94011d3 172 }
sahilmgandhi 18:6a4db94011d3 173
sahilmgandhi 18:6a4db94011d3 174 static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle)
sahilmgandhi 18:6a4db94011d3 175 {
sahilmgandhi 18:6a4db94011d3 176 assert(handle);
sahilmgandhi 18:6a4db94011d3 177
sahilmgandhi 18:6a4db94011d3 178 size_t size;
sahilmgandhi 18:6a4db94011d3 179
sahilmgandhi 18:6a4db94011d3 180 if (handle->rxRingBufferTail > handle->rxRingBufferHead)
sahilmgandhi 18:6a4db94011d3 181 {
sahilmgandhi 18:6a4db94011d3 182 size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);
sahilmgandhi 18:6a4db94011d3 183 }
sahilmgandhi 18:6a4db94011d3 184 else
sahilmgandhi 18:6a4db94011d3 185 {
sahilmgandhi 18:6a4db94011d3 186 size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);
sahilmgandhi 18:6a4db94011d3 187 }
sahilmgandhi 18:6a4db94011d3 188
sahilmgandhi 18:6a4db94011d3 189 return size;
sahilmgandhi 18:6a4db94011d3 190 }
sahilmgandhi 18:6a4db94011d3 191
sahilmgandhi 18:6a4db94011d3 192 static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle)
sahilmgandhi 18:6a4db94011d3 193 {
sahilmgandhi 18:6a4db94011d3 194 assert(handle);
sahilmgandhi 18:6a4db94011d3 195
sahilmgandhi 18:6a4db94011d3 196 bool full;
sahilmgandhi 18:6a4db94011d3 197
sahilmgandhi 18:6a4db94011d3 198 if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
sahilmgandhi 18:6a4db94011d3 199 {
sahilmgandhi 18:6a4db94011d3 200 full = true;
sahilmgandhi 18:6a4db94011d3 201 }
sahilmgandhi 18:6a4db94011d3 202 else
sahilmgandhi 18:6a4db94011d3 203 {
sahilmgandhi 18:6a4db94011d3 204 full = false;
sahilmgandhi 18:6a4db94011d3 205 }
sahilmgandhi 18:6a4db94011d3 206
sahilmgandhi 18:6a4db94011d3 207 return full;
sahilmgandhi 18:6a4db94011d3 208 }
sahilmgandhi 18:6a4db94011d3 209
sahilmgandhi 18:6a4db94011d3 210 status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
sahilmgandhi 18:6a4db94011d3 211 {
sahilmgandhi 18:6a4db94011d3 212 assert(config);
sahilmgandhi 18:6a4db94011d3 213 assert(config->baudRate_Bps);
sahilmgandhi 18:6a4db94011d3 214 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 215 assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark);
sahilmgandhi 18:6a4db94011d3 216 assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark);
sahilmgandhi 18:6a4db94011d3 217 #endif
sahilmgandhi 18:6a4db94011d3 218
sahilmgandhi 18:6a4db94011d3 219 uint16_t sbr = 0;
sahilmgandhi 18:6a4db94011d3 220 uint8_t temp = 0;
sahilmgandhi 18:6a4db94011d3 221 uint32_t baudDiff = 0;
sahilmgandhi 18:6a4db94011d3 222
sahilmgandhi 18:6a4db94011d3 223 /* Calculate the baud rate modulo divisor, sbr*/
sahilmgandhi 18:6a4db94011d3 224 sbr = srcClock_Hz / (config->baudRate_Bps * 16);
sahilmgandhi 18:6a4db94011d3 225 /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
sahilmgandhi 18:6a4db94011d3 226 if (sbr == 0)
sahilmgandhi 18:6a4db94011d3 227 {
sahilmgandhi 18:6a4db94011d3 228 sbr = 1;
sahilmgandhi 18:6a4db94011d3 229 }
sahilmgandhi 18:6a4db94011d3 230 #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
sahilmgandhi 18:6a4db94011d3 231 /* Determine if a fractional divider is needed to fine tune closer to the
sahilmgandhi 18:6a4db94011d3 232 * desired baud, each value of brfa is in 1/32 increments,
sahilmgandhi 18:6a4db94011d3 233 * hence the multiply-by-32. */
sahilmgandhi 18:6a4db94011d3 234 uint32_t tempBaud = 0;
sahilmgandhi 18:6a4db94011d3 235
sahilmgandhi 18:6a4db94011d3 236 uint16_t brfa = (2 * srcClock_Hz / (config->baudRate_Bps)) - 32 * sbr;
sahilmgandhi 18:6a4db94011d3 237
sahilmgandhi 18:6a4db94011d3 238 /* Calculate the baud rate based on the temporary SBR values and BRFA */
sahilmgandhi 18:6a4db94011d3 239 tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
sahilmgandhi 18:6a4db94011d3 240 baudDiff =
sahilmgandhi 18:6a4db94011d3 241 (tempBaud > config->baudRate_Bps) ? (tempBaud - config->baudRate_Bps) : (config->baudRate_Bps - tempBaud);
sahilmgandhi 18:6a4db94011d3 242
sahilmgandhi 18:6a4db94011d3 243 #else
sahilmgandhi 18:6a4db94011d3 244 /* Calculate the baud rate based on the temporary SBR values */
sahilmgandhi 18:6a4db94011d3 245 baudDiff = (srcClock_Hz / (sbr * 16)) - config->baudRate_Bps;
sahilmgandhi 18:6a4db94011d3 246
sahilmgandhi 18:6a4db94011d3 247 /* Select the better value between sbr and (sbr + 1) */
sahilmgandhi 18:6a4db94011d3 248 if (baudDiff > (config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
sahilmgandhi 18:6a4db94011d3 249 {
sahilmgandhi 18:6a4db94011d3 250 baudDiff = config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
sahilmgandhi 18:6a4db94011d3 251 sbr++;
sahilmgandhi 18:6a4db94011d3 252 }
sahilmgandhi 18:6a4db94011d3 253 #endif
sahilmgandhi 18:6a4db94011d3 254
sahilmgandhi 18:6a4db94011d3 255 /* next, check to see if actual baud rate is within 3% of desired baud rate
sahilmgandhi 18:6a4db94011d3 256 * based on the calculate SBR value */
sahilmgandhi 18:6a4db94011d3 257 if (baudDiff > ((config->baudRate_Bps / 100) * 3))
sahilmgandhi 18:6a4db94011d3 258 {
sahilmgandhi 18:6a4db94011d3 259 /* Unacceptable baud rate difference of more than 3%*/
sahilmgandhi 18:6a4db94011d3 260 return kStatus_UART_BaudrateNotSupport;
sahilmgandhi 18:6a4db94011d3 261 }
sahilmgandhi 18:6a4db94011d3 262
sahilmgandhi 18:6a4db94011d3 263 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
sahilmgandhi 18:6a4db94011d3 264 /* Enable uart clock */
sahilmgandhi 18:6a4db94011d3 265 CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]);
sahilmgandhi 18:6a4db94011d3 266 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
sahilmgandhi 18:6a4db94011d3 267
sahilmgandhi 18:6a4db94011d3 268 /* Disable UART TX RX before setting. */
sahilmgandhi 18:6a4db94011d3 269 base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
sahilmgandhi 18:6a4db94011d3 270
sahilmgandhi 18:6a4db94011d3 271 /* Write the sbr value to the BDH and BDL registers*/
sahilmgandhi 18:6a4db94011d3 272 base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
sahilmgandhi 18:6a4db94011d3 273 base->BDL = (uint8_t)sbr;
sahilmgandhi 18:6a4db94011d3 274
sahilmgandhi 18:6a4db94011d3 275 #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
sahilmgandhi 18:6a4db94011d3 276 /* Write the brfa value to the register*/
sahilmgandhi 18:6a4db94011d3 277 base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
sahilmgandhi 18:6a4db94011d3 278 #endif
sahilmgandhi 18:6a4db94011d3 279
sahilmgandhi 18:6a4db94011d3 280 /* Set bit count and parity mode. */
sahilmgandhi 18:6a4db94011d3 281 temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK);
sahilmgandhi 18:6a4db94011d3 282
sahilmgandhi 18:6a4db94011d3 283 if (kUART_ParityDisabled != config->parityMode)
sahilmgandhi 18:6a4db94011d3 284 {
sahilmgandhi 18:6a4db94011d3 285 temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode);
sahilmgandhi 18:6a4db94011d3 286 }
sahilmgandhi 18:6a4db94011d3 287
sahilmgandhi 18:6a4db94011d3 288 base->C1 = temp;
sahilmgandhi 18:6a4db94011d3 289
sahilmgandhi 18:6a4db94011d3 290 #if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
sahilmgandhi 18:6a4db94011d3 291 /* Set stop bit per char */
sahilmgandhi 18:6a4db94011d3 292 base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)config->stopBitCount);
sahilmgandhi 18:6a4db94011d3 293 #endif
sahilmgandhi 18:6a4db94011d3 294
sahilmgandhi 18:6a4db94011d3 295 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 296 /* Set tx/rx FIFO watermark */
sahilmgandhi 18:6a4db94011d3 297 base->TWFIFO = config->txFifoWatermark;
sahilmgandhi 18:6a4db94011d3 298 base->RWFIFO = config->rxFifoWatermark;
sahilmgandhi 18:6a4db94011d3 299
sahilmgandhi 18:6a4db94011d3 300 /* Enable tx/rx FIFO */
sahilmgandhi 18:6a4db94011d3 301 base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK);
sahilmgandhi 18:6a4db94011d3 302
sahilmgandhi 18:6a4db94011d3 303 /* Flush FIFO */
sahilmgandhi 18:6a4db94011d3 304 base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK);
sahilmgandhi 18:6a4db94011d3 305 #endif
sahilmgandhi 18:6a4db94011d3 306
sahilmgandhi 18:6a4db94011d3 307 /* Enable TX/RX base on configure structure. */
sahilmgandhi 18:6a4db94011d3 308 temp = base->C2;
sahilmgandhi 18:6a4db94011d3 309
sahilmgandhi 18:6a4db94011d3 310 if (config->enableTx)
sahilmgandhi 18:6a4db94011d3 311 {
sahilmgandhi 18:6a4db94011d3 312 temp |= UART_C2_TE_MASK;
sahilmgandhi 18:6a4db94011d3 313 }
sahilmgandhi 18:6a4db94011d3 314
sahilmgandhi 18:6a4db94011d3 315 if (config->enableRx)
sahilmgandhi 18:6a4db94011d3 316 {
sahilmgandhi 18:6a4db94011d3 317 temp |= UART_C2_RE_MASK;
sahilmgandhi 18:6a4db94011d3 318 }
sahilmgandhi 18:6a4db94011d3 319
sahilmgandhi 18:6a4db94011d3 320 base->C2 = temp;
sahilmgandhi 18:6a4db94011d3 321
sahilmgandhi 18:6a4db94011d3 322 return kStatus_Success;
sahilmgandhi 18:6a4db94011d3 323 }
sahilmgandhi 18:6a4db94011d3 324
sahilmgandhi 18:6a4db94011d3 325 void UART_Deinit(UART_Type *base)
sahilmgandhi 18:6a4db94011d3 326 {
sahilmgandhi 18:6a4db94011d3 327 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 328 /* Wait tx FIFO send out*/
sahilmgandhi 18:6a4db94011d3 329 while (0 != base->TCFIFO)
sahilmgandhi 18:6a4db94011d3 330 {
sahilmgandhi 18:6a4db94011d3 331 }
sahilmgandhi 18:6a4db94011d3 332 #endif
sahilmgandhi 18:6a4db94011d3 333 /* Wait last char shoft out */
sahilmgandhi 18:6a4db94011d3 334 while (0 == (base->S1 & UART_S1_TC_MASK))
sahilmgandhi 18:6a4db94011d3 335 {
sahilmgandhi 18:6a4db94011d3 336 }
sahilmgandhi 18:6a4db94011d3 337
sahilmgandhi 18:6a4db94011d3 338 /* Disable the module. */
sahilmgandhi 18:6a4db94011d3 339 base->C2 = 0;
sahilmgandhi 18:6a4db94011d3 340
sahilmgandhi 18:6a4db94011d3 341 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
sahilmgandhi 18:6a4db94011d3 342 /* Disable uart clock */
sahilmgandhi 18:6a4db94011d3 343 CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]);
sahilmgandhi 18:6a4db94011d3 344 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
sahilmgandhi 18:6a4db94011d3 345 }
sahilmgandhi 18:6a4db94011d3 346
sahilmgandhi 18:6a4db94011d3 347 void UART_GetDefaultConfig(uart_config_t *config)
sahilmgandhi 18:6a4db94011d3 348 {
sahilmgandhi 18:6a4db94011d3 349 assert(config);
sahilmgandhi 18:6a4db94011d3 350
sahilmgandhi 18:6a4db94011d3 351 config->baudRate_Bps = 115200U;
sahilmgandhi 18:6a4db94011d3 352 config->parityMode = kUART_ParityDisabled;
sahilmgandhi 18:6a4db94011d3 353 #if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
sahilmgandhi 18:6a4db94011d3 354 config->stopBitCount = kUART_OneStopBit;
sahilmgandhi 18:6a4db94011d3 355 #endif
sahilmgandhi 18:6a4db94011d3 356 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 357 config->txFifoWatermark = 0;
sahilmgandhi 18:6a4db94011d3 358 config->rxFifoWatermark = 1;
sahilmgandhi 18:6a4db94011d3 359 #endif
sahilmgandhi 18:6a4db94011d3 360 config->enableTx = false;
sahilmgandhi 18:6a4db94011d3 361 config->enableRx = false;
sahilmgandhi 18:6a4db94011d3 362 }
sahilmgandhi 18:6a4db94011d3 363
sahilmgandhi 18:6a4db94011d3 364 status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
sahilmgandhi 18:6a4db94011d3 365 {
sahilmgandhi 18:6a4db94011d3 366 assert(baudRate_Bps);
sahilmgandhi 18:6a4db94011d3 367
sahilmgandhi 18:6a4db94011d3 368 uint16_t sbr = 0;
sahilmgandhi 18:6a4db94011d3 369 uint32_t baudDiff = 0;
sahilmgandhi 18:6a4db94011d3 370 uint8_t oldCtrl;
sahilmgandhi 18:6a4db94011d3 371
sahilmgandhi 18:6a4db94011d3 372 /* Calculate the baud rate modulo divisor, sbr*/
sahilmgandhi 18:6a4db94011d3 373 sbr = srcClock_Hz / (baudRate_Bps * 16);
sahilmgandhi 18:6a4db94011d3 374 /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */
sahilmgandhi 18:6a4db94011d3 375 if (sbr == 0)
sahilmgandhi 18:6a4db94011d3 376 {
sahilmgandhi 18:6a4db94011d3 377 sbr = 1;
sahilmgandhi 18:6a4db94011d3 378 }
sahilmgandhi 18:6a4db94011d3 379 #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
sahilmgandhi 18:6a4db94011d3 380 /* Determine if a fractional divider is needed to fine tune closer to the
sahilmgandhi 18:6a4db94011d3 381 * desired baud, each value of brfa is in 1/32 increments,
sahilmgandhi 18:6a4db94011d3 382 * hence the multiply-by-32. */
sahilmgandhi 18:6a4db94011d3 383 uint32_t tempBaud = 0;
sahilmgandhi 18:6a4db94011d3 384
sahilmgandhi 18:6a4db94011d3 385 uint16_t brfa = (2 * srcClock_Hz / (baudRate_Bps)) - 32 * sbr;
sahilmgandhi 18:6a4db94011d3 386
sahilmgandhi 18:6a4db94011d3 387 /* Calculate the baud rate based on the temporary SBR values and BRFA */
sahilmgandhi 18:6a4db94011d3 388 tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa)));
sahilmgandhi 18:6a4db94011d3 389 baudDiff = (tempBaud > baudRate_Bps) ? (tempBaud - baudRate_Bps) : (baudRate_Bps - tempBaud);
sahilmgandhi 18:6a4db94011d3 390 #else
sahilmgandhi 18:6a4db94011d3 391 /* Calculate the baud rate based on the temporary SBR values */
sahilmgandhi 18:6a4db94011d3 392 baudDiff = (srcClock_Hz / (sbr * 16)) - baudRate_Bps;
sahilmgandhi 18:6a4db94011d3 393
sahilmgandhi 18:6a4db94011d3 394 /* Select the better value between sbr and (sbr + 1) */
sahilmgandhi 18:6a4db94011d3 395 if (baudDiff > (baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)))))
sahilmgandhi 18:6a4db94011d3 396 {
sahilmgandhi 18:6a4db94011d3 397 baudDiff = baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1)));
sahilmgandhi 18:6a4db94011d3 398 sbr++;
sahilmgandhi 18:6a4db94011d3 399 }
sahilmgandhi 18:6a4db94011d3 400 #endif
sahilmgandhi 18:6a4db94011d3 401
sahilmgandhi 18:6a4db94011d3 402 /* next, check to see if actual baud rate is within 3% of desired baud rate
sahilmgandhi 18:6a4db94011d3 403 * based on the calculate SBR value */
sahilmgandhi 18:6a4db94011d3 404 if (baudDiff < ((baudRate_Bps / 100) * 3))
sahilmgandhi 18:6a4db94011d3 405 {
sahilmgandhi 18:6a4db94011d3 406 /* Store C2 before disable Tx and Rx */
sahilmgandhi 18:6a4db94011d3 407 oldCtrl = base->C2;
sahilmgandhi 18:6a4db94011d3 408
sahilmgandhi 18:6a4db94011d3 409 /* Disable UART TX RX before setting. */
sahilmgandhi 18:6a4db94011d3 410 base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK);
sahilmgandhi 18:6a4db94011d3 411
sahilmgandhi 18:6a4db94011d3 412 /* Write the sbr value to the BDH and BDL registers*/
sahilmgandhi 18:6a4db94011d3 413 base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8);
sahilmgandhi 18:6a4db94011d3 414 base->BDL = (uint8_t)sbr;
sahilmgandhi 18:6a4db94011d3 415
sahilmgandhi 18:6a4db94011d3 416 #if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT
sahilmgandhi 18:6a4db94011d3 417 /* Write the brfa value to the register*/
sahilmgandhi 18:6a4db94011d3 418 base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK);
sahilmgandhi 18:6a4db94011d3 419 #endif
sahilmgandhi 18:6a4db94011d3 420 /* Restore C2. */
sahilmgandhi 18:6a4db94011d3 421 base->C2 = oldCtrl;
sahilmgandhi 18:6a4db94011d3 422
sahilmgandhi 18:6a4db94011d3 423 return kStatus_Success;
sahilmgandhi 18:6a4db94011d3 424 }
sahilmgandhi 18:6a4db94011d3 425 else
sahilmgandhi 18:6a4db94011d3 426 {
sahilmgandhi 18:6a4db94011d3 427 /* Unacceptable baud rate difference of more than 3%*/
sahilmgandhi 18:6a4db94011d3 428 return kStatus_UART_BaudrateNotSupport;
sahilmgandhi 18:6a4db94011d3 429 }
sahilmgandhi 18:6a4db94011d3 430 }
sahilmgandhi 18:6a4db94011d3 431
sahilmgandhi 18:6a4db94011d3 432 void UART_EnableInterrupts(UART_Type *base, uint32_t mask)
sahilmgandhi 18:6a4db94011d3 433 {
sahilmgandhi 18:6a4db94011d3 434 mask &= kUART_AllInterruptsEnable;
sahilmgandhi 18:6a4db94011d3 435
sahilmgandhi 18:6a4db94011d3 436 /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
sahilmgandhi 18:6a4db94011d3 437 */
sahilmgandhi 18:6a4db94011d3 438 base->BDH |= mask;
sahilmgandhi 18:6a4db94011d3 439 base->C2 |= (mask >> 8);
sahilmgandhi 18:6a4db94011d3 440 base->C3 |= (mask >> 16);
sahilmgandhi 18:6a4db94011d3 441
sahilmgandhi 18:6a4db94011d3 442 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 443 base->CFIFO |= (mask >> 24);
sahilmgandhi 18:6a4db94011d3 444 #endif
sahilmgandhi 18:6a4db94011d3 445 }
sahilmgandhi 18:6a4db94011d3 446
sahilmgandhi 18:6a4db94011d3 447 void UART_DisableInterrupts(UART_Type *base, uint32_t mask)
sahilmgandhi 18:6a4db94011d3 448 {
sahilmgandhi 18:6a4db94011d3 449 mask &= kUART_AllInterruptsEnable;
sahilmgandhi 18:6a4db94011d3 450
sahilmgandhi 18:6a4db94011d3 451 /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH))
sahilmgandhi 18:6a4db94011d3 452 */
sahilmgandhi 18:6a4db94011d3 453 base->BDH &= ~mask;
sahilmgandhi 18:6a4db94011d3 454 base->C2 &= ~(mask >> 8);
sahilmgandhi 18:6a4db94011d3 455 base->C3 &= ~(mask >> 16);
sahilmgandhi 18:6a4db94011d3 456
sahilmgandhi 18:6a4db94011d3 457 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 458 base->CFIFO &= ~(mask >> 24);
sahilmgandhi 18:6a4db94011d3 459 #endif
sahilmgandhi 18:6a4db94011d3 460 }
sahilmgandhi 18:6a4db94011d3 461
sahilmgandhi 18:6a4db94011d3 462 uint32_t UART_GetEnabledInterrupts(UART_Type *base)
sahilmgandhi 18:6a4db94011d3 463 {
sahilmgandhi 18:6a4db94011d3 464 uint32_t temp;
sahilmgandhi 18:6a4db94011d3 465
sahilmgandhi 18:6a4db94011d3 466 temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16);
sahilmgandhi 18:6a4db94011d3 467
sahilmgandhi 18:6a4db94011d3 468 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 469 temp |= ((uint32_t)(base->CFIFO) << 24);
sahilmgandhi 18:6a4db94011d3 470 #endif
sahilmgandhi 18:6a4db94011d3 471
sahilmgandhi 18:6a4db94011d3 472 return temp & kUART_AllInterruptsEnable;
sahilmgandhi 18:6a4db94011d3 473 }
sahilmgandhi 18:6a4db94011d3 474
sahilmgandhi 18:6a4db94011d3 475 uint32_t UART_GetStatusFlags(UART_Type *base)
sahilmgandhi 18:6a4db94011d3 476 {
sahilmgandhi 18:6a4db94011d3 477 uint32_t status_flag;
sahilmgandhi 18:6a4db94011d3 478
sahilmgandhi 18:6a4db94011d3 479 status_flag = base->S1 | ((uint32_t)(base->S2) << 8);
sahilmgandhi 18:6a4db94011d3 480
sahilmgandhi 18:6a4db94011d3 481 #if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS
sahilmgandhi 18:6a4db94011d3 482 status_flag |= ((uint32_t)(base->ED) << 16);
sahilmgandhi 18:6a4db94011d3 483 #endif
sahilmgandhi 18:6a4db94011d3 484
sahilmgandhi 18:6a4db94011d3 485 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 486 status_flag |= ((uint32_t)(base->SFIFO) << 24);
sahilmgandhi 18:6a4db94011d3 487 #endif
sahilmgandhi 18:6a4db94011d3 488
sahilmgandhi 18:6a4db94011d3 489 return status_flag;
sahilmgandhi 18:6a4db94011d3 490 }
sahilmgandhi 18:6a4db94011d3 491
sahilmgandhi 18:6a4db94011d3 492 status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask)
sahilmgandhi 18:6a4db94011d3 493 {
sahilmgandhi 18:6a4db94011d3 494 uint8_t reg = base->S2;
sahilmgandhi 18:6a4db94011d3 495 status_t status;
sahilmgandhi 18:6a4db94011d3 496
sahilmgandhi 18:6a4db94011d3 497 #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT
sahilmgandhi 18:6a4db94011d3 498 reg &= ~(UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK);
sahilmgandhi 18:6a4db94011d3 499 #else
sahilmgandhi 18:6a4db94011d3 500 reg &= ~UART_S2_RXEDGIF_MASK;
sahilmgandhi 18:6a4db94011d3 501 #endif
sahilmgandhi 18:6a4db94011d3 502
sahilmgandhi 18:6a4db94011d3 503 base->S2 = reg | (uint8_t)(mask >> 8);
sahilmgandhi 18:6a4db94011d3 504
sahilmgandhi 18:6a4db94011d3 505 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 506 base->SFIFO = (uint8_t)(mask >> 24);
sahilmgandhi 18:6a4db94011d3 507 #endif
sahilmgandhi 18:6a4db94011d3 508
sahilmgandhi 18:6a4db94011d3 509 if (mask & (kUART_IdleLineFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | kUART_ParityErrorFlag))
sahilmgandhi 18:6a4db94011d3 510 {
sahilmgandhi 18:6a4db94011d3 511 /* Read base->D to clear the flags. */
sahilmgandhi 18:6a4db94011d3 512 (void)base->S1;
sahilmgandhi 18:6a4db94011d3 513 (void)base->D;
sahilmgandhi 18:6a4db94011d3 514 }
sahilmgandhi 18:6a4db94011d3 515
sahilmgandhi 18:6a4db94011d3 516 if (mask & kUART_RxOverrunFlag)
sahilmgandhi 18:6a4db94011d3 517 {
sahilmgandhi 18:6a4db94011d3 518 /* Read base->D to clear the flags and Flush all data in FIFO. */
sahilmgandhi 18:6a4db94011d3 519 (void)base->S1;
sahilmgandhi 18:6a4db94011d3 520 (void)base->D;
sahilmgandhi 18:6a4db94011d3 521 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 522 /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
sahilmgandhi 18:6a4db94011d3 523 base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
sahilmgandhi 18:6a4db94011d3 524 #endif
sahilmgandhi 18:6a4db94011d3 525 }
sahilmgandhi 18:6a4db94011d3 526
sahilmgandhi 18:6a4db94011d3 527 /* If some flags still pending. */
sahilmgandhi 18:6a4db94011d3 528 if (mask & UART_GetStatusFlags(base))
sahilmgandhi 18:6a4db94011d3 529 {
sahilmgandhi 18:6a4db94011d3 530 /* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag,
sahilmgandhi 18:6a4db94011d3 531 kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag,
sahilmgandhi 18:6a4db94011d3 532 kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */
sahilmgandhi 18:6a4db94011d3 533 status = kStatus_UART_FlagCannotClearManually;
sahilmgandhi 18:6a4db94011d3 534 }
sahilmgandhi 18:6a4db94011d3 535 else
sahilmgandhi 18:6a4db94011d3 536 {
sahilmgandhi 18:6a4db94011d3 537 status = kStatus_Success;
sahilmgandhi 18:6a4db94011d3 538 }
sahilmgandhi 18:6a4db94011d3 539
sahilmgandhi 18:6a4db94011d3 540 return status;
sahilmgandhi 18:6a4db94011d3 541 }
sahilmgandhi 18:6a4db94011d3 542
sahilmgandhi 18:6a4db94011d3 543 void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length)
sahilmgandhi 18:6a4db94011d3 544 {
sahilmgandhi 18:6a4db94011d3 545 /* This API can only ensure that the data is written into the data buffer but can't
sahilmgandhi 18:6a4db94011d3 546 ensure all data in the data buffer are sent into the transmit shift buffer. */
sahilmgandhi 18:6a4db94011d3 547 while (length--)
sahilmgandhi 18:6a4db94011d3 548 {
sahilmgandhi 18:6a4db94011d3 549 while (!(base->S1 & UART_S1_TDRE_MASK))
sahilmgandhi 18:6a4db94011d3 550 {
sahilmgandhi 18:6a4db94011d3 551 }
sahilmgandhi 18:6a4db94011d3 552 base->D = *(data++);
sahilmgandhi 18:6a4db94011d3 553 }
sahilmgandhi 18:6a4db94011d3 554 }
sahilmgandhi 18:6a4db94011d3 555
sahilmgandhi 18:6a4db94011d3 556 static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length)
sahilmgandhi 18:6a4db94011d3 557 {
sahilmgandhi 18:6a4db94011d3 558 assert(data);
sahilmgandhi 18:6a4db94011d3 559
sahilmgandhi 18:6a4db94011d3 560 size_t i;
sahilmgandhi 18:6a4db94011d3 561
sahilmgandhi 18:6a4db94011d3 562 /* The Non Blocking write data API assume user have ensured there is enough space in
sahilmgandhi 18:6a4db94011d3 563 peripheral to write. */
sahilmgandhi 18:6a4db94011d3 564 for (i = 0; i < length; i++)
sahilmgandhi 18:6a4db94011d3 565 {
sahilmgandhi 18:6a4db94011d3 566 base->D = data[i];
sahilmgandhi 18:6a4db94011d3 567 }
sahilmgandhi 18:6a4db94011d3 568 }
sahilmgandhi 18:6a4db94011d3 569
sahilmgandhi 18:6a4db94011d3 570 status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length)
sahilmgandhi 18:6a4db94011d3 571 {
sahilmgandhi 18:6a4db94011d3 572 assert(data);
sahilmgandhi 18:6a4db94011d3 573
sahilmgandhi 18:6a4db94011d3 574 uint32_t statusFlag;
sahilmgandhi 18:6a4db94011d3 575
sahilmgandhi 18:6a4db94011d3 576 while (length--)
sahilmgandhi 18:6a4db94011d3 577 {
sahilmgandhi 18:6a4db94011d3 578 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 579 while (!base->RCFIFO)
sahilmgandhi 18:6a4db94011d3 580 #else
sahilmgandhi 18:6a4db94011d3 581 while (!(base->S1 & UART_S1_RDRF_MASK))
sahilmgandhi 18:6a4db94011d3 582 #endif
sahilmgandhi 18:6a4db94011d3 583 {
sahilmgandhi 18:6a4db94011d3 584 statusFlag = UART_GetStatusFlags(base);
sahilmgandhi 18:6a4db94011d3 585
sahilmgandhi 18:6a4db94011d3 586 if (statusFlag & kUART_RxOverrunFlag)
sahilmgandhi 18:6a4db94011d3 587 {
sahilmgandhi 18:6a4db94011d3 588 return kStatus_UART_RxHardwareOverrun;
sahilmgandhi 18:6a4db94011d3 589 }
sahilmgandhi 18:6a4db94011d3 590
sahilmgandhi 18:6a4db94011d3 591 if (statusFlag & kUART_NoiseErrorFlag)
sahilmgandhi 18:6a4db94011d3 592 {
sahilmgandhi 18:6a4db94011d3 593 return kStatus_UART_NoiseError;
sahilmgandhi 18:6a4db94011d3 594 }
sahilmgandhi 18:6a4db94011d3 595
sahilmgandhi 18:6a4db94011d3 596 if (statusFlag & kUART_FramingErrorFlag)
sahilmgandhi 18:6a4db94011d3 597 {
sahilmgandhi 18:6a4db94011d3 598 return kStatus_UART_FramingError;
sahilmgandhi 18:6a4db94011d3 599 }
sahilmgandhi 18:6a4db94011d3 600
sahilmgandhi 18:6a4db94011d3 601 if (statusFlag & kUART_ParityErrorFlag)
sahilmgandhi 18:6a4db94011d3 602 {
sahilmgandhi 18:6a4db94011d3 603 return kStatus_UART_ParityError;
sahilmgandhi 18:6a4db94011d3 604 }
sahilmgandhi 18:6a4db94011d3 605 }
sahilmgandhi 18:6a4db94011d3 606 *(data++) = base->D;
sahilmgandhi 18:6a4db94011d3 607 }
sahilmgandhi 18:6a4db94011d3 608
sahilmgandhi 18:6a4db94011d3 609 return kStatus_Success;
sahilmgandhi 18:6a4db94011d3 610 }
sahilmgandhi 18:6a4db94011d3 611
sahilmgandhi 18:6a4db94011d3 612 static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length)
sahilmgandhi 18:6a4db94011d3 613 {
sahilmgandhi 18:6a4db94011d3 614 assert(data);
sahilmgandhi 18:6a4db94011d3 615
sahilmgandhi 18:6a4db94011d3 616 size_t i;
sahilmgandhi 18:6a4db94011d3 617
sahilmgandhi 18:6a4db94011d3 618 /* The Non Blocking read data API assume user have ensured there is enough space in
sahilmgandhi 18:6a4db94011d3 619 peripheral to write. */
sahilmgandhi 18:6a4db94011d3 620 for (i = 0; i < length; i++)
sahilmgandhi 18:6a4db94011d3 621 {
sahilmgandhi 18:6a4db94011d3 622 data[i] = base->D;
sahilmgandhi 18:6a4db94011d3 623 }
sahilmgandhi 18:6a4db94011d3 624 }
sahilmgandhi 18:6a4db94011d3 625
sahilmgandhi 18:6a4db94011d3 626 void UART_TransferCreateHandle(UART_Type *base,
sahilmgandhi 18:6a4db94011d3 627 uart_handle_t *handle,
sahilmgandhi 18:6a4db94011d3 628 uart_transfer_callback_t callback,
sahilmgandhi 18:6a4db94011d3 629 void *userData)
sahilmgandhi 18:6a4db94011d3 630 {
sahilmgandhi 18:6a4db94011d3 631 assert(handle);
sahilmgandhi 18:6a4db94011d3 632
sahilmgandhi 18:6a4db94011d3 633 uint32_t instance;
sahilmgandhi 18:6a4db94011d3 634
sahilmgandhi 18:6a4db94011d3 635 /* Zero the handle. */
sahilmgandhi 18:6a4db94011d3 636 memset(handle, 0, sizeof(*handle));
sahilmgandhi 18:6a4db94011d3 637
sahilmgandhi 18:6a4db94011d3 638 /* Set the TX/RX state. */
sahilmgandhi 18:6a4db94011d3 639 handle->rxState = kUART_RxIdle;
sahilmgandhi 18:6a4db94011d3 640 handle->txState = kUART_TxIdle;
sahilmgandhi 18:6a4db94011d3 641
sahilmgandhi 18:6a4db94011d3 642 /* Set the callback and user data. */
sahilmgandhi 18:6a4db94011d3 643 handle->callback = callback;
sahilmgandhi 18:6a4db94011d3 644 handle->userData = userData;
sahilmgandhi 18:6a4db94011d3 645
sahilmgandhi 18:6a4db94011d3 646 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 647 /* Note:
sahilmgandhi 18:6a4db94011d3 648 Take care of the RX FIFO, RX interrupt request only assert when received bytes
sahilmgandhi 18:6a4db94011d3 649 equal or more than RX water mark, there is potential issue if RX water
sahilmgandhi 18:6a4db94011d3 650 mark larger than 1.
sahilmgandhi 18:6a4db94011d3 651 For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and
sahilmgandhi 18:6a4db94011d3 652 5 bytes are received. the last byte will be saved in FIFO but not trigger
sahilmgandhi 18:6a4db94011d3 653 RX interrupt because the water mark is 2.
sahilmgandhi 18:6a4db94011d3 654 */
sahilmgandhi 18:6a4db94011d3 655 base->RWFIFO = 1U;
sahilmgandhi 18:6a4db94011d3 656 #endif
sahilmgandhi 18:6a4db94011d3 657
sahilmgandhi 18:6a4db94011d3 658 /* Get instance from peripheral base address. */
sahilmgandhi 18:6a4db94011d3 659 instance = UART_GetInstance(base);
sahilmgandhi 18:6a4db94011d3 660
sahilmgandhi 18:6a4db94011d3 661 /* Save the handle in global variables to support the double weak mechanism. */
sahilmgandhi 18:6a4db94011d3 662 s_uartHandle[instance] = handle;
sahilmgandhi 18:6a4db94011d3 663
sahilmgandhi 18:6a4db94011d3 664 s_uartIsr = UART_TransferHandleIRQ;
sahilmgandhi 18:6a4db94011d3 665 /* Enable interrupt in NVIC. */
sahilmgandhi 18:6a4db94011d3 666 EnableIRQ(s_uartIRQ[instance]);
sahilmgandhi 18:6a4db94011d3 667 }
sahilmgandhi 18:6a4db94011d3 668
sahilmgandhi 18:6a4db94011d3 669 void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
sahilmgandhi 18:6a4db94011d3 670 {
sahilmgandhi 18:6a4db94011d3 671 assert(handle);
sahilmgandhi 18:6a4db94011d3 672 assert(ringBuffer);
sahilmgandhi 18:6a4db94011d3 673
sahilmgandhi 18:6a4db94011d3 674 /* Setup the ringbuffer address */
sahilmgandhi 18:6a4db94011d3 675 handle->rxRingBuffer = ringBuffer;
sahilmgandhi 18:6a4db94011d3 676 handle->rxRingBufferSize = ringBufferSize;
sahilmgandhi 18:6a4db94011d3 677 handle->rxRingBufferHead = 0U;
sahilmgandhi 18:6a4db94011d3 678 handle->rxRingBufferTail = 0U;
sahilmgandhi 18:6a4db94011d3 679
sahilmgandhi 18:6a4db94011d3 680 /* Enable the interrupt to accept the data when user need the ring buffer. */
sahilmgandhi 18:6a4db94011d3 681 UART_EnableInterrupts(
sahilmgandhi 18:6a4db94011d3 682 base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | kUART_FramingErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 683 /* Enable parity error interrupt when parity mode is enable*/
sahilmgandhi 18:6a4db94011d3 684 if (UART_C1_PE_MASK & base->C1)
sahilmgandhi 18:6a4db94011d3 685 {
sahilmgandhi 18:6a4db94011d3 686 UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 687 }
sahilmgandhi 18:6a4db94011d3 688 }
sahilmgandhi 18:6a4db94011d3 689
sahilmgandhi 18:6a4db94011d3 690 void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle)
sahilmgandhi 18:6a4db94011d3 691 {
sahilmgandhi 18:6a4db94011d3 692 assert(handle);
sahilmgandhi 18:6a4db94011d3 693
sahilmgandhi 18:6a4db94011d3 694 if (handle->rxState == kUART_RxIdle)
sahilmgandhi 18:6a4db94011d3 695 {
sahilmgandhi 18:6a4db94011d3 696 UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
sahilmgandhi 18:6a4db94011d3 697 kUART_FramingErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 698 /* Disable parity error interrupt when parity mode is enable*/
sahilmgandhi 18:6a4db94011d3 699 if (UART_C1_PE_MASK & base->C1)
sahilmgandhi 18:6a4db94011d3 700 {
sahilmgandhi 18:6a4db94011d3 701 UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 702 }
sahilmgandhi 18:6a4db94011d3 703 }
sahilmgandhi 18:6a4db94011d3 704
sahilmgandhi 18:6a4db94011d3 705 handle->rxRingBuffer = NULL;
sahilmgandhi 18:6a4db94011d3 706 handle->rxRingBufferSize = 0U;
sahilmgandhi 18:6a4db94011d3 707 handle->rxRingBufferHead = 0U;
sahilmgandhi 18:6a4db94011d3 708 handle->rxRingBufferTail = 0U;
sahilmgandhi 18:6a4db94011d3 709 }
sahilmgandhi 18:6a4db94011d3 710
sahilmgandhi 18:6a4db94011d3 711 status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer)
sahilmgandhi 18:6a4db94011d3 712 {
sahilmgandhi 18:6a4db94011d3 713 assert(handle);
sahilmgandhi 18:6a4db94011d3 714 assert(xfer);
sahilmgandhi 18:6a4db94011d3 715 assert(xfer->dataSize);
sahilmgandhi 18:6a4db94011d3 716 assert(xfer->data);
sahilmgandhi 18:6a4db94011d3 717
sahilmgandhi 18:6a4db94011d3 718 status_t status;
sahilmgandhi 18:6a4db94011d3 719
sahilmgandhi 18:6a4db94011d3 720 /* Return error if current TX busy. */
sahilmgandhi 18:6a4db94011d3 721 if (kUART_TxBusy == handle->txState)
sahilmgandhi 18:6a4db94011d3 722 {
sahilmgandhi 18:6a4db94011d3 723 status = kStatus_UART_TxBusy;
sahilmgandhi 18:6a4db94011d3 724 }
sahilmgandhi 18:6a4db94011d3 725 else
sahilmgandhi 18:6a4db94011d3 726 {
sahilmgandhi 18:6a4db94011d3 727 handle->txData = xfer->data;
sahilmgandhi 18:6a4db94011d3 728 handle->txDataSize = xfer->dataSize;
sahilmgandhi 18:6a4db94011d3 729 handle->txDataSizeAll = xfer->dataSize;
sahilmgandhi 18:6a4db94011d3 730 handle->txState = kUART_TxBusy;
sahilmgandhi 18:6a4db94011d3 731
sahilmgandhi 18:6a4db94011d3 732 /* Enable transmiter interrupt. */
sahilmgandhi 18:6a4db94011d3 733 UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable);
sahilmgandhi 18:6a4db94011d3 734
sahilmgandhi 18:6a4db94011d3 735 status = kStatus_Success;
sahilmgandhi 18:6a4db94011d3 736 }
sahilmgandhi 18:6a4db94011d3 737
sahilmgandhi 18:6a4db94011d3 738 return status;
sahilmgandhi 18:6a4db94011d3 739 }
sahilmgandhi 18:6a4db94011d3 740
sahilmgandhi 18:6a4db94011d3 741 void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle)
sahilmgandhi 18:6a4db94011d3 742 {
sahilmgandhi 18:6a4db94011d3 743 assert(handle);
sahilmgandhi 18:6a4db94011d3 744
sahilmgandhi 18:6a4db94011d3 745 UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable);
sahilmgandhi 18:6a4db94011d3 746
sahilmgandhi 18:6a4db94011d3 747 handle->txDataSize = 0;
sahilmgandhi 18:6a4db94011d3 748 handle->txState = kUART_TxIdle;
sahilmgandhi 18:6a4db94011d3 749 }
sahilmgandhi 18:6a4db94011d3 750
sahilmgandhi 18:6a4db94011d3 751 status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
sahilmgandhi 18:6a4db94011d3 752 {
sahilmgandhi 18:6a4db94011d3 753 assert(handle);
sahilmgandhi 18:6a4db94011d3 754 assert(count);
sahilmgandhi 18:6a4db94011d3 755
sahilmgandhi 18:6a4db94011d3 756 if (kUART_TxIdle == handle->txState)
sahilmgandhi 18:6a4db94011d3 757 {
sahilmgandhi 18:6a4db94011d3 758 return kStatus_NoTransferInProgress;
sahilmgandhi 18:6a4db94011d3 759 }
sahilmgandhi 18:6a4db94011d3 760
sahilmgandhi 18:6a4db94011d3 761 *count = handle->txDataSizeAll - handle->txDataSize;
sahilmgandhi 18:6a4db94011d3 762
sahilmgandhi 18:6a4db94011d3 763 return kStatus_Success;
sahilmgandhi 18:6a4db94011d3 764 }
sahilmgandhi 18:6a4db94011d3 765
sahilmgandhi 18:6a4db94011d3 766 status_t UART_TransferReceiveNonBlocking(UART_Type *base,
sahilmgandhi 18:6a4db94011d3 767 uart_handle_t *handle,
sahilmgandhi 18:6a4db94011d3 768 uart_transfer_t *xfer,
sahilmgandhi 18:6a4db94011d3 769 size_t *receivedBytes)
sahilmgandhi 18:6a4db94011d3 770 {
sahilmgandhi 18:6a4db94011d3 771 assert(handle);
sahilmgandhi 18:6a4db94011d3 772 assert(xfer);
sahilmgandhi 18:6a4db94011d3 773 assert(xfer->data);
sahilmgandhi 18:6a4db94011d3 774 assert(xfer->dataSize);
sahilmgandhi 18:6a4db94011d3 775
sahilmgandhi 18:6a4db94011d3 776 uint32_t i;
sahilmgandhi 18:6a4db94011d3 777 status_t status;
sahilmgandhi 18:6a4db94011d3 778 /* How many bytes to copy from ring buffer to user memory. */
sahilmgandhi 18:6a4db94011d3 779 size_t bytesToCopy = 0U;
sahilmgandhi 18:6a4db94011d3 780 /* How many bytes to receive. */
sahilmgandhi 18:6a4db94011d3 781 size_t bytesToReceive;
sahilmgandhi 18:6a4db94011d3 782 /* How many bytes currently have received. */
sahilmgandhi 18:6a4db94011d3 783 size_t bytesCurrentReceived;
sahilmgandhi 18:6a4db94011d3 784
sahilmgandhi 18:6a4db94011d3 785 /* How to get data:
sahilmgandhi 18:6a4db94011d3 786 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
sahilmgandhi 18:6a4db94011d3 787 to uart handle, enable interrupt to store received data to xfer->data. When
sahilmgandhi 18:6a4db94011d3 788 all data received, trigger callback.
sahilmgandhi 18:6a4db94011d3 789 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
sahilmgandhi 18:6a4db94011d3 790 If there are enough data in ring buffer, copy them to xfer->data and return.
sahilmgandhi 18:6a4db94011d3 791 If there are not enough data in ring buffer, copy all of them to xfer->data,
sahilmgandhi 18:6a4db94011d3 792 save the xfer->data remained empty space to uart handle, receive data
sahilmgandhi 18:6a4db94011d3 793 to this empty space and trigger callback when finished. */
sahilmgandhi 18:6a4db94011d3 794
sahilmgandhi 18:6a4db94011d3 795 if (kUART_RxBusy == handle->rxState)
sahilmgandhi 18:6a4db94011d3 796 {
sahilmgandhi 18:6a4db94011d3 797 status = kStatus_UART_RxBusy;
sahilmgandhi 18:6a4db94011d3 798 }
sahilmgandhi 18:6a4db94011d3 799 else
sahilmgandhi 18:6a4db94011d3 800 {
sahilmgandhi 18:6a4db94011d3 801 bytesToReceive = xfer->dataSize;
sahilmgandhi 18:6a4db94011d3 802 bytesCurrentReceived = 0U;
sahilmgandhi 18:6a4db94011d3 803
sahilmgandhi 18:6a4db94011d3 804 /* If RX ring buffer is used. */
sahilmgandhi 18:6a4db94011d3 805 if (handle->rxRingBuffer)
sahilmgandhi 18:6a4db94011d3 806 {
sahilmgandhi 18:6a4db94011d3 807 /* Disable UART RX IRQ, protect ring buffer. */
sahilmgandhi 18:6a4db94011d3 808 UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
sahilmgandhi 18:6a4db94011d3 809
sahilmgandhi 18:6a4db94011d3 810 /* How many bytes in RX ring buffer currently. */
sahilmgandhi 18:6a4db94011d3 811 bytesToCopy = UART_TransferGetRxRingBufferLength(handle);
sahilmgandhi 18:6a4db94011d3 812
sahilmgandhi 18:6a4db94011d3 813 if (bytesToCopy)
sahilmgandhi 18:6a4db94011d3 814 {
sahilmgandhi 18:6a4db94011d3 815 bytesToCopy = MIN(bytesToReceive, bytesToCopy);
sahilmgandhi 18:6a4db94011d3 816
sahilmgandhi 18:6a4db94011d3 817 bytesToReceive -= bytesToCopy;
sahilmgandhi 18:6a4db94011d3 818
sahilmgandhi 18:6a4db94011d3 819 /* Copy data from ring buffer to user memory. */
sahilmgandhi 18:6a4db94011d3 820 for (i = 0U; i < bytesToCopy; i++)
sahilmgandhi 18:6a4db94011d3 821 {
sahilmgandhi 18:6a4db94011d3 822 xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
sahilmgandhi 18:6a4db94011d3 823
sahilmgandhi 18:6a4db94011d3 824 /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
sahilmgandhi 18:6a4db94011d3 825 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
sahilmgandhi 18:6a4db94011d3 826 {
sahilmgandhi 18:6a4db94011d3 827 handle->rxRingBufferTail = 0U;
sahilmgandhi 18:6a4db94011d3 828 }
sahilmgandhi 18:6a4db94011d3 829 else
sahilmgandhi 18:6a4db94011d3 830 {
sahilmgandhi 18:6a4db94011d3 831 handle->rxRingBufferTail++;
sahilmgandhi 18:6a4db94011d3 832 }
sahilmgandhi 18:6a4db94011d3 833 }
sahilmgandhi 18:6a4db94011d3 834 }
sahilmgandhi 18:6a4db94011d3 835
sahilmgandhi 18:6a4db94011d3 836 /* If ring buffer does not have enough data, still need to read more data. */
sahilmgandhi 18:6a4db94011d3 837 if (bytesToReceive)
sahilmgandhi 18:6a4db94011d3 838 {
sahilmgandhi 18:6a4db94011d3 839 /* No data in ring buffer, save the request to UART handle. */
sahilmgandhi 18:6a4db94011d3 840 handle->rxData = xfer->data + bytesCurrentReceived;
sahilmgandhi 18:6a4db94011d3 841 handle->rxDataSize = bytesToReceive;
sahilmgandhi 18:6a4db94011d3 842 handle->rxDataSizeAll = bytesToReceive;
sahilmgandhi 18:6a4db94011d3 843 handle->rxState = kUART_RxBusy;
sahilmgandhi 18:6a4db94011d3 844 }
sahilmgandhi 18:6a4db94011d3 845
sahilmgandhi 18:6a4db94011d3 846 /* Enable UART RX IRQ if previously enabled. */
sahilmgandhi 18:6a4db94011d3 847 UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable);
sahilmgandhi 18:6a4db94011d3 848
sahilmgandhi 18:6a4db94011d3 849 /* Call user callback since all data are received. */
sahilmgandhi 18:6a4db94011d3 850 if (0 == bytesToReceive)
sahilmgandhi 18:6a4db94011d3 851 {
sahilmgandhi 18:6a4db94011d3 852 if (handle->callback)
sahilmgandhi 18:6a4db94011d3 853 {
sahilmgandhi 18:6a4db94011d3 854 handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
sahilmgandhi 18:6a4db94011d3 855 }
sahilmgandhi 18:6a4db94011d3 856 }
sahilmgandhi 18:6a4db94011d3 857 }
sahilmgandhi 18:6a4db94011d3 858 /* Ring buffer not used. */
sahilmgandhi 18:6a4db94011d3 859 else
sahilmgandhi 18:6a4db94011d3 860 {
sahilmgandhi 18:6a4db94011d3 861 handle->rxData = xfer->data + bytesCurrentReceived;
sahilmgandhi 18:6a4db94011d3 862 handle->rxDataSize = bytesToReceive;
sahilmgandhi 18:6a4db94011d3 863 handle->rxDataSizeAll = bytesToReceive;
sahilmgandhi 18:6a4db94011d3 864 handle->rxState = kUART_RxBusy;
sahilmgandhi 18:6a4db94011d3 865
sahilmgandhi 18:6a4db94011d3 866 /* Enable RX/Rx overrun/framing error interrupt. */
sahilmgandhi 18:6a4db94011d3 867 UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
sahilmgandhi 18:6a4db94011d3 868 kUART_FramingErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 869 /* Enable parity error interrupt when parity mode is enable*/
sahilmgandhi 18:6a4db94011d3 870 if (UART_C1_PE_MASK & base->C1)
sahilmgandhi 18:6a4db94011d3 871 {
sahilmgandhi 18:6a4db94011d3 872 UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 873 }
sahilmgandhi 18:6a4db94011d3 874 }
sahilmgandhi 18:6a4db94011d3 875
sahilmgandhi 18:6a4db94011d3 876 /* Return the how many bytes have read. */
sahilmgandhi 18:6a4db94011d3 877 if (receivedBytes)
sahilmgandhi 18:6a4db94011d3 878 {
sahilmgandhi 18:6a4db94011d3 879 *receivedBytes = bytesCurrentReceived;
sahilmgandhi 18:6a4db94011d3 880 }
sahilmgandhi 18:6a4db94011d3 881
sahilmgandhi 18:6a4db94011d3 882 status = kStatus_Success;
sahilmgandhi 18:6a4db94011d3 883 }
sahilmgandhi 18:6a4db94011d3 884
sahilmgandhi 18:6a4db94011d3 885 return status;
sahilmgandhi 18:6a4db94011d3 886 }
sahilmgandhi 18:6a4db94011d3 887
sahilmgandhi 18:6a4db94011d3 888 void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle)
sahilmgandhi 18:6a4db94011d3 889 {
sahilmgandhi 18:6a4db94011d3 890 assert(handle);
sahilmgandhi 18:6a4db94011d3 891
sahilmgandhi 18:6a4db94011d3 892 /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
sahilmgandhi 18:6a4db94011d3 893 if (!handle->rxRingBuffer)
sahilmgandhi 18:6a4db94011d3 894 {
sahilmgandhi 18:6a4db94011d3 895 /* Disable RX interrupt. */
sahilmgandhi 18:6a4db94011d3 896 UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
sahilmgandhi 18:6a4db94011d3 897 kUART_FramingErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 898 /* Disable parity error interrupt when parity mode is enable*/
sahilmgandhi 18:6a4db94011d3 899 if (UART_C1_PE_MASK & base->C1)
sahilmgandhi 18:6a4db94011d3 900 {
sahilmgandhi 18:6a4db94011d3 901 UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 902 }
sahilmgandhi 18:6a4db94011d3 903 }
sahilmgandhi 18:6a4db94011d3 904
sahilmgandhi 18:6a4db94011d3 905 handle->rxDataSize = 0U;
sahilmgandhi 18:6a4db94011d3 906 handle->rxState = kUART_RxIdle;
sahilmgandhi 18:6a4db94011d3 907 }
sahilmgandhi 18:6a4db94011d3 908
sahilmgandhi 18:6a4db94011d3 909 status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
sahilmgandhi 18:6a4db94011d3 910 {
sahilmgandhi 18:6a4db94011d3 911 assert(handle);
sahilmgandhi 18:6a4db94011d3 912 assert(count);
sahilmgandhi 18:6a4db94011d3 913
sahilmgandhi 18:6a4db94011d3 914 if (kUART_RxIdle == handle->rxState)
sahilmgandhi 18:6a4db94011d3 915 {
sahilmgandhi 18:6a4db94011d3 916 return kStatus_NoTransferInProgress;
sahilmgandhi 18:6a4db94011d3 917 }
sahilmgandhi 18:6a4db94011d3 918
sahilmgandhi 18:6a4db94011d3 919 if (!count)
sahilmgandhi 18:6a4db94011d3 920 {
sahilmgandhi 18:6a4db94011d3 921 return kStatus_InvalidArgument;
sahilmgandhi 18:6a4db94011d3 922 }
sahilmgandhi 18:6a4db94011d3 923
sahilmgandhi 18:6a4db94011d3 924 *count = handle->rxDataSizeAll - handle->rxDataSize;
sahilmgandhi 18:6a4db94011d3 925
sahilmgandhi 18:6a4db94011d3 926 return kStatus_Success;
sahilmgandhi 18:6a4db94011d3 927 }
sahilmgandhi 18:6a4db94011d3 928
sahilmgandhi 18:6a4db94011d3 929 void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle)
sahilmgandhi 18:6a4db94011d3 930 {
sahilmgandhi 18:6a4db94011d3 931 assert(handle);
sahilmgandhi 18:6a4db94011d3 932
sahilmgandhi 18:6a4db94011d3 933 uint8_t count;
sahilmgandhi 18:6a4db94011d3 934 uint8_t tempCount;
sahilmgandhi 18:6a4db94011d3 935
sahilmgandhi 18:6a4db94011d3 936 /* If RX framing error */
sahilmgandhi 18:6a4db94011d3 937 if (UART_S1_FE_MASK & base->S1)
sahilmgandhi 18:6a4db94011d3 938 {
sahilmgandhi 18:6a4db94011d3 939 /* Read base->D to clear framing error flag, otherwise the RX does not work. */
sahilmgandhi 18:6a4db94011d3 940 while (base->S1 & UART_S1_RDRF_MASK)
sahilmgandhi 18:6a4db94011d3 941 {
sahilmgandhi 18:6a4db94011d3 942 (void)base->D;
sahilmgandhi 18:6a4db94011d3 943 }
sahilmgandhi 18:6a4db94011d3 944 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 945 /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
sahilmgandhi 18:6a4db94011d3 946 base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
sahilmgandhi 18:6a4db94011d3 947 #endif
sahilmgandhi 18:6a4db94011d3 948
sahilmgandhi 18:6a4db94011d3 949 handle->rxState = kUART_RxFramingError;
sahilmgandhi 18:6a4db94011d3 950 handle->rxDataSize = 0U;
sahilmgandhi 18:6a4db94011d3 951 /* Trigger callback. */
sahilmgandhi 18:6a4db94011d3 952 if (handle->callback)
sahilmgandhi 18:6a4db94011d3 953 {
sahilmgandhi 18:6a4db94011d3 954 handle->callback(base, handle, kStatus_UART_FramingError, handle->userData);
sahilmgandhi 18:6a4db94011d3 955 }
sahilmgandhi 18:6a4db94011d3 956 }
sahilmgandhi 18:6a4db94011d3 957
sahilmgandhi 18:6a4db94011d3 958 /* If RX parity error */
sahilmgandhi 18:6a4db94011d3 959 if (UART_S1_PF_MASK & base->S1)
sahilmgandhi 18:6a4db94011d3 960 {
sahilmgandhi 18:6a4db94011d3 961 /* Read base->D to clear parity error flag, otherwise the RX does not work. */
sahilmgandhi 18:6a4db94011d3 962 while (base->S1 & UART_S1_RDRF_MASK)
sahilmgandhi 18:6a4db94011d3 963 {
sahilmgandhi 18:6a4db94011d3 964 (void)base->D;
sahilmgandhi 18:6a4db94011d3 965 }
sahilmgandhi 18:6a4db94011d3 966 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 967 /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
sahilmgandhi 18:6a4db94011d3 968 base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
sahilmgandhi 18:6a4db94011d3 969 #endif
sahilmgandhi 18:6a4db94011d3 970
sahilmgandhi 18:6a4db94011d3 971 handle->rxState = kUART_RxParityError;
sahilmgandhi 18:6a4db94011d3 972 handle->rxDataSize = 0U;
sahilmgandhi 18:6a4db94011d3 973 /* Trigger callback. */
sahilmgandhi 18:6a4db94011d3 974 if (handle->callback)
sahilmgandhi 18:6a4db94011d3 975 {
sahilmgandhi 18:6a4db94011d3 976 handle->callback(base, handle, kStatus_UART_ParityError, handle->userData);
sahilmgandhi 18:6a4db94011d3 977 }
sahilmgandhi 18:6a4db94011d3 978 }
sahilmgandhi 18:6a4db94011d3 979
sahilmgandhi 18:6a4db94011d3 980 /* If RX overrun. */
sahilmgandhi 18:6a4db94011d3 981 if (UART_S1_OR_MASK & base->S1)
sahilmgandhi 18:6a4db94011d3 982 {
sahilmgandhi 18:6a4db94011d3 983 /* Read base->D to clear overrun flag, otherwise the RX does not work. */
sahilmgandhi 18:6a4db94011d3 984 while (base->S1 & UART_S1_RDRF_MASK)
sahilmgandhi 18:6a4db94011d3 985 {
sahilmgandhi 18:6a4db94011d3 986 (void)base->D;
sahilmgandhi 18:6a4db94011d3 987 }
sahilmgandhi 18:6a4db94011d3 988 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 989 /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */
sahilmgandhi 18:6a4db94011d3 990 base->CFIFO |= UART_CFIFO_RXFLUSH_MASK;
sahilmgandhi 18:6a4db94011d3 991 #endif
sahilmgandhi 18:6a4db94011d3 992 /* Trigger callback. */
sahilmgandhi 18:6a4db94011d3 993 if (handle->callback)
sahilmgandhi 18:6a4db94011d3 994 {
sahilmgandhi 18:6a4db94011d3 995 handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData);
sahilmgandhi 18:6a4db94011d3 996 }
sahilmgandhi 18:6a4db94011d3 997 }
sahilmgandhi 18:6a4db94011d3 998
sahilmgandhi 18:6a4db94011d3 999 /* Receive data register full */
sahilmgandhi 18:6a4db94011d3 1000 if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2))
sahilmgandhi 18:6a4db94011d3 1001 {
sahilmgandhi 18:6a4db94011d3 1002 /* Get the size that can be stored into buffer for this interrupt. */
sahilmgandhi 18:6a4db94011d3 1003 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 1004 count = base->RCFIFO;
sahilmgandhi 18:6a4db94011d3 1005 #else
sahilmgandhi 18:6a4db94011d3 1006 count = 1;
sahilmgandhi 18:6a4db94011d3 1007 #endif
sahilmgandhi 18:6a4db94011d3 1008
sahilmgandhi 18:6a4db94011d3 1009 /* If handle->rxDataSize is not 0, first save data to handle->rxData. */
sahilmgandhi 18:6a4db94011d3 1010 while ((count) && (handle->rxDataSize))
sahilmgandhi 18:6a4db94011d3 1011 {
sahilmgandhi 18:6a4db94011d3 1012 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 1013 tempCount = MIN(handle->rxDataSize, count);
sahilmgandhi 18:6a4db94011d3 1014 #else
sahilmgandhi 18:6a4db94011d3 1015 tempCount = 1;
sahilmgandhi 18:6a4db94011d3 1016 #endif
sahilmgandhi 18:6a4db94011d3 1017
sahilmgandhi 18:6a4db94011d3 1018 /* Using non block API to read the data from the registers. */
sahilmgandhi 18:6a4db94011d3 1019 UART_ReadNonBlocking(base, handle->rxData, tempCount);
sahilmgandhi 18:6a4db94011d3 1020 handle->rxData += tempCount;
sahilmgandhi 18:6a4db94011d3 1021 handle->rxDataSize -= tempCount;
sahilmgandhi 18:6a4db94011d3 1022 count -= tempCount;
sahilmgandhi 18:6a4db94011d3 1023
sahilmgandhi 18:6a4db94011d3 1024 /* If all the data required for upper layer is ready, trigger callback. */
sahilmgandhi 18:6a4db94011d3 1025 if (!handle->rxDataSize)
sahilmgandhi 18:6a4db94011d3 1026 {
sahilmgandhi 18:6a4db94011d3 1027 handle->rxState = kUART_RxIdle;
sahilmgandhi 18:6a4db94011d3 1028
sahilmgandhi 18:6a4db94011d3 1029 if (handle->callback)
sahilmgandhi 18:6a4db94011d3 1030 {
sahilmgandhi 18:6a4db94011d3 1031 handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
sahilmgandhi 18:6a4db94011d3 1032 }
sahilmgandhi 18:6a4db94011d3 1033 }
sahilmgandhi 18:6a4db94011d3 1034 }
sahilmgandhi 18:6a4db94011d3 1035
sahilmgandhi 18:6a4db94011d3 1036 /* If use RX ring buffer, receive data to ring buffer. */
sahilmgandhi 18:6a4db94011d3 1037 if (handle->rxRingBuffer)
sahilmgandhi 18:6a4db94011d3 1038 {
sahilmgandhi 18:6a4db94011d3 1039 while (count--)
sahilmgandhi 18:6a4db94011d3 1040 {
sahilmgandhi 18:6a4db94011d3 1041 /* If RX ring buffer is full, trigger callback to notify over run. */
sahilmgandhi 18:6a4db94011d3 1042 if (UART_TransferIsRxRingBufferFull(handle))
sahilmgandhi 18:6a4db94011d3 1043 {
sahilmgandhi 18:6a4db94011d3 1044 if (handle->callback)
sahilmgandhi 18:6a4db94011d3 1045 {
sahilmgandhi 18:6a4db94011d3 1046 handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData);
sahilmgandhi 18:6a4db94011d3 1047 }
sahilmgandhi 18:6a4db94011d3 1048 }
sahilmgandhi 18:6a4db94011d3 1049
sahilmgandhi 18:6a4db94011d3 1050 /* If ring buffer is still full after callback function, the oldest data is overrided. */
sahilmgandhi 18:6a4db94011d3 1051 if (UART_TransferIsRxRingBufferFull(handle))
sahilmgandhi 18:6a4db94011d3 1052 {
sahilmgandhi 18:6a4db94011d3 1053 /* Increase handle->rxRingBufferTail to make room for new data. */
sahilmgandhi 18:6a4db94011d3 1054 if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
sahilmgandhi 18:6a4db94011d3 1055 {
sahilmgandhi 18:6a4db94011d3 1056 handle->rxRingBufferTail = 0U;
sahilmgandhi 18:6a4db94011d3 1057 }
sahilmgandhi 18:6a4db94011d3 1058 else
sahilmgandhi 18:6a4db94011d3 1059 {
sahilmgandhi 18:6a4db94011d3 1060 handle->rxRingBufferTail++;
sahilmgandhi 18:6a4db94011d3 1061 }
sahilmgandhi 18:6a4db94011d3 1062 }
sahilmgandhi 18:6a4db94011d3 1063
sahilmgandhi 18:6a4db94011d3 1064 /* Read data. */
sahilmgandhi 18:6a4db94011d3 1065 handle->rxRingBuffer[handle->rxRingBufferHead] = base->D;
sahilmgandhi 18:6a4db94011d3 1066
sahilmgandhi 18:6a4db94011d3 1067 /* Increase handle->rxRingBufferHead. */
sahilmgandhi 18:6a4db94011d3 1068 if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
sahilmgandhi 18:6a4db94011d3 1069 {
sahilmgandhi 18:6a4db94011d3 1070 handle->rxRingBufferHead = 0U;
sahilmgandhi 18:6a4db94011d3 1071 }
sahilmgandhi 18:6a4db94011d3 1072 else
sahilmgandhi 18:6a4db94011d3 1073 {
sahilmgandhi 18:6a4db94011d3 1074 handle->rxRingBufferHead++;
sahilmgandhi 18:6a4db94011d3 1075 }
sahilmgandhi 18:6a4db94011d3 1076 }
sahilmgandhi 18:6a4db94011d3 1077 }
sahilmgandhi 18:6a4db94011d3 1078
sahilmgandhi 18:6a4db94011d3 1079 else if (!handle->rxDataSize)
sahilmgandhi 18:6a4db94011d3 1080 {
sahilmgandhi 18:6a4db94011d3 1081 /* Disable RX interrupt/overrun interrupt/fram error interrupt */
sahilmgandhi 18:6a4db94011d3 1082 UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
sahilmgandhi 18:6a4db94011d3 1083 kUART_FramingErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 1084
sahilmgandhi 18:6a4db94011d3 1085 /* Disable parity error interrupt when parity mode is enable*/
sahilmgandhi 18:6a4db94011d3 1086 if (UART_C1_PE_MASK & base->C1)
sahilmgandhi 18:6a4db94011d3 1087 {
sahilmgandhi 18:6a4db94011d3 1088 UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 1089 }
sahilmgandhi 18:6a4db94011d3 1090 }
sahilmgandhi 18:6a4db94011d3 1091 else
sahilmgandhi 18:6a4db94011d3 1092 {
sahilmgandhi 18:6a4db94011d3 1093 }
sahilmgandhi 18:6a4db94011d3 1094 }
sahilmgandhi 18:6a4db94011d3 1095
sahilmgandhi 18:6a4db94011d3 1096 /* If framing error or parity error happened, stop the RX interrupt when ues no ring buffer */
sahilmgandhi 18:6a4db94011d3 1097 if (((handle->rxState == kUART_RxFramingError) || (handle->rxState == kUART_RxParityError)) &&
sahilmgandhi 18:6a4db94011d3 1098 (!handle->rxRingBuffer))
sahilmgandhi 18:6a4db94011d3 1099 {
sahilmgandhi 18:6a4db94011d3 1100 UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable |
sahilmgandhi 18:6a4db94011d3 1101 kUART_FramingErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 1102
sahilmgandhi 18:6a4db94011d3 1103 /* Disable parity error interrupt when parity mode is enable*/
sahilmgandhi 18:6a4db94011d3 1104 if (UART_C1_PE_MASK & base->C1)
sahilmgandhi 18:6a4db94011d3 1105 {
sahilmgandhi 18:6a4db94011d3 1106 UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable);
sahilmgandhi 18:6a4db94011d3 1107 }
sahilmgandhi 18:6a4db94011d3 1108 }
sahilmgandhi 18:6a4db94011d3 1109
sahilmgandhi 18:6a4db94011d3 1110 /* Send data register empty and the interrupt is enabled. */
sahilmgandhi 18:6a4db94011d3 1111 if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK))
sahilmgandhi 18:6a4db94011d3 1112 {
sahilmgandhi 18:6a4db94011d3 1113 /* Get the bytes that available at this moment. */
sahilmgandhi 18:6a4db94011d3 1114 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 1115 count = FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO;
sahilmgandhi 18:6a4db94011d3 1116 #else
sahilmgandhi 18:6a4db94011d3 1117 count = 1;
sahilmgandhi 18:6a4db94011d3 1118 #endif
sahilmgandhi 18:6a4db94011d3 1119
sahilmgandhi 18:6a4db94011d3 1120 while ((count) && (handle->txDataSize))
sahilmgandhi 18:6a4db94011d3 1121 {
sahilmgandhi 18:6a4db94011d3 1122 #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
sahilmgandhi 18:6a4db94011d3 1123 tempCount = MIN(handle->txDataSize, count);
sahilmgandhi 18:6a4db94011d3 1124 #else
sahilmgandhi 18:6a4db94011d3 1125 tempCount = 1;
sahilmgandhi 18:6a4db94011d3 1126 #endif
sahilmgandhi 18:6a4db94011d3 1127
sahilmgandhi 18:6a4db94011d3 1128 /* Using non block API to write the data to the registers. */
sahilmgandhi 18:6a4db94011d3 1129 UART_WriteNonBlocking(base, handle->txData, tempCount);
sahilmgandhi 18:6a4db94011d3 1130 handle->txData += tempCount;
sahilmgandhi 18:6a4db94011d3 1131 handle->txDataSize -= tempCount;
sahilmgandhi 18:6a4db94011d3 1132 count -= tempCount;
sahilmgandhi 18:6a4db94011d3 1133
sahilmgandhi 18:6a4db94011d3 1134 /* If all the data are written to data register, TX finished. */
sahilmgandhi 18:6a4db94011d3 1135 if (!handle->txDataSize)
sahilmgandhi 18:6a4db94011d3 1136 {
sahilmgandhi 18:6a4db94011d3 1137 handle->txState = kUART_TxIdle;
sahilmgandhi 18:6a4db94011d3 1138
sahilmgandhi 18:6a4db94011d3 1139 /* Disable TX register empty interrupt. */
sahilmgandhi 18:6a4db94011d3 1140 base->C2 = (base->C2 & ~UART_C2_TIE_MASK);
sahilmgandhi 18:6a4db94011d3 1141
sahilmgandhi 18:6a4db94011d3 1142 /* Trigger callback. */
sahilmgandhi 18:6a4db94011d3 1143 if (handle->callback)
sahilmgandhi 18:6a4db94011d3 1144 {
sahilmgandhi 18:6a4db94011d3 1145 handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData);
sahilmgandhi 18:6a4db94011d3 1146 }
sahilmgandhi 18:6a4db94011d3 1147 }
sahilmgandhi 18:6a4db94011d3 1148 }
sahilmgandhi 18:6a4db94011d3 1149 }
sahilmgandhi 18:6a4db94011d3 1150 }
sahilmgandhi 18:6a4db94011d3 1151
sahilmgandhi 18:6a4db94011d3 1152 void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle)
sahilmgandhi 18:6a4db94011d3 1153 {
sahilmgandhi 18:6a4db94011d3 1154 /* To be implemented by User. */
sahilmgandhi 18:6a4db94011d3 1155 }
sahilmgandhi 18:6a4db94011d3 1156
sahilmgandhi 18:6a4db94011d3 1157 #if defined(UART0)
sahilmgandhi 18:6a4db94011d3 1158 #if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \
sahilmgandhi 18:6a4db94011d3 1159 ((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0)))
sahilmgandhi 18:6a4db94011d3 1160 void UART0_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1161 {
sahilmgandhi 18:6a4db94011d3 1162 s_uartIsr(UART0, s_uartHandle[0]);
sahilmgandhi 18:6a4db94011d3 1163 }
sahilmgandhi 18:6a4db94011d3 1164
sahilmgandhi 18:6a4db94011d3 1165 void UART0_RX_TX_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1166 {
sahilmgandhi 18:6a4db94011d3 1167 UART0_DriverIRQHandler();
sahilmgandhi 18:6a4db94011d3 1168 }
sahilmgandhi 18:6a4db94011d3 1169 #endif
sahilmgandhi 18:6a4db94011d3 1170 #endif
sahilmgandhi 18:6a4db94011d3 1171
sahilmgandhi 18:6a4db94011d3 1172 #if defined(UART1)
sahilmgandhi 18:6a4db94011d3 1173 void UART1_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1174 {
sahilmgandhi 18:6a4db94011d3 1175 s_uartIsr(UART1, s_uartHandle[1]);
sahilmgandhi 18:6a4db94011d3 1176 }
sahilmgandhi 18:6a4db94011d3 1177
sahilmgandhi 18:6a4db94011d3 1178 void UART1_RX_TX_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1179 {
sahilmgandhi 18:6a4db94011d3 1180 UART1_DriverIRQHandler();
sahilmgandhi 18:6a4db94011d3 1181 }
sahilmgandhi 18:6a4db94011d3 1182 #endif
sahilmgandhi 18:6a4db94011d3 1183
sahilmgandhi 18:6a4db94011d3 1184 #if defined(UART2)
sahilmgandhi 18:6a4db94011d3 1185 void UART2_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1186 {
sahilmgandhi 18:6a4db94011d3 1187 s_uartIsr(UART2, s_uartHandle[2]);
sahilmgandhi 18:6a4db94011d3 1188 }
sahilmgandhi 18:6a4db94011d3 1189
sahilmgandhi 18:6a4db94011d3 1190 void UART2_RX_TX_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1191 {
sahilmgandhi 18:6a4db94011d3 1192 UART2_DriverIRQHandler();
sahilmgandhi 18:6a4db94011d3 1193 }
sahilmgandhi 18:6a4db94011d3 1194 #endif
sahilmgandhi 18:6a4db94011d3 1195
sahilmgandhi 18:6a4db94011d3 1196 #if defined(UART3)
sahilmgandhi 18:6a4db94011d3 1197 void UART3_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1198 {
sahilmgandhi 18:6a4db94011d3 1199 s_uartIsr(UART3, s_uartHandle[3]);
sahilmgandhi 18:6a4db94011d3 1200 }
sahilmgandhi 18:6a4db94011d3 1201
sahilmgandhi 18:6a4db94011d3 1202 void UART3_RX_TX_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1203 {
sahilmgandhi 18:6a4db94011d3 1204 UART3_DriverIRQHandler();
sahilmgandhi 18:6a4db94011d3 1205 }
sahilmgandhi 18:6a4db94011d3 1206 #endif
sahilmgandhi 18:6a4db94011d3 1207
sahilmgandhi 18:6a4db94011d3 1208 #if defined(UART4)
sahilmgandhi 18:6a4db94011d3 1209 void UART4_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1210 {
sahilmgandhi 18:6a4db94011d3 1211 s_uartIsr(UART4, s_uartHandle[4]);
sahilmgandhi 18:6a4db94011d3 1212 }
sahilmgandhi 18:6a4db94011d3 1213
sahilmgandhi 18:6a4db94011d3 1214 void UART4_RX_TX_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1215 {
sahilmgandhi 18:6a4db94011d3 1216 UART4_DriverIRQHandler();
sahilmgandhi 18:6a4db94011d3 1217 }
sahilmgandhi 18:6a4db94011d3 1218 #endif
sahilmgandhi 18:6a4db94011d3 1219
sahilmgandhi 18:6a4db94011d3 1220 #if defined(UART5)
sahilmgandhi 18:6a4db94011d3 1221 void UART5_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1222 {
sahilmgandhi 18:6a4db94011d3 1223 s_uartIsr(UART5, s_uartHandle[5]);
sahilmgandhi 18:6a4db94011d3 1224 }
sahilmgandhi 18:6a4db94011d3 1225
sahilmgandhi 18:6a4db94011d3 1226 void UART5_RX_TX_DriverIRQHandler(void)
sahilmgandhi 18:6a4db94011d3 1227 {
sahilmgandhi 18:6a4db94011d3 1228 UART5_DriverIRQHandler();
sahilmgandhi 18:6a4db94011d3 1229 }
sahilmgandhi 18:6a4db94011d3 1230 #endif